1 /* $OpenBSD: wdc.c,v 1.62 2003/07/06 08:25:16 grange Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 4 5 /* 6 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1998 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/conf.h> 74 #include <sys/buf.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/syslog.h> 78 #include <sys/proc.h> 79 #include <sys/pool.h> 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/intr.h> 83 #include <machine/bus.h> 84 85 #include <dev/ata/atavar.h> 86 #include <dev/ata/atareg.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 #include <dev/ic/wdcevent.h> 90 91 #include "atapiscsi.h" 92 93 #define WDCDELAY 100 /* 100 microseconds */ 94 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 95 #if 0 96 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 97 #define WDCNDELAY_DEBUG 50 98 #endif /* 0 */ 99 100 struct pool wdc_xfer_pool; 101 102 static void __wdcerror(struct channel_softc*, char *); 103 static int __wdcwait_reset(struct channel_softc *, int); 104 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *); 105 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *); 106 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int); 107 int wdprint(void *, const char *); 108 void wdc_kill_pending(struct channel_softc *); 109 110 #define DEBUG_INTR 0x01 111 #define DEBUG_XFERS 0x02 112 #define DEBUG_STATUS 0x04 113 #define DEBUG_FUNCS 0x08 114 #define DEBUG_PROBE 0x10 115 #define DEBUG_STATUSX 0x20 116 #define DEBUG_SDRIVE 0x40 117 #define DEBUG_DETACH 0x80 118 119 #ifdef WDCDEBUG 120 int wdcdebug_mask = 0; 121 int wdc_nxfer = 0; 122 #define WDCDEBUG_PRINT(args, level) do { \ 123 if ((wdcdebug_mask & (level)) != 0) \ 124 printf args; \ 125 } while (0) 126 #else 127 #define WDCDEBUG_PRINT(args, level) 128 #endif /* WDCDEBUG */ 129 130 int at_poll = AT_POLL; 131 132 u_int8_t wdc_default_read_reg(struct channel_softc *, enum wdc_regs); 133 void wdc_default_write_reg(struct channel_softc *, enum wdc_regs, u_int8_t); 134 void wdc_default_read_raw_multi_2(struct channel_softc *, 135 void *, unsigned int); 136 void wdc_default_write_raw_multi_2(struct channel_softc *, 137 void *, unsigned int); 138 void wdc_default_read_raw_multi_4(struct channel_softc *, 139 void *, unsigned int); 140 void wdc_default_write_raw_multi_4(struct channel_softc *, 141 void *, unsigned int); 142 143 int wdc_floating_bus(struct channel_softc *, int); 144 int wdc_preata_drive(struct channel_softc *, int); 145 int wdc_ata_present(struct channel_softc *, int); 146 147 struct channel_softc_vtbl wdc_default_vtbl = { 148 wdc_default_read_reg, 149 wdc_default_write_reg, 150 wdc_default_read_raw_multi_2, 151 wdc_default_write_raw_multi_2, 152 wdc_default_read_raw_multi_4, 153 wdc_default_write_raw_multi_4 154 }; 155 156 static char *wdc_log_buf = NULL; 157 static int wdc_tail = 0; 158 static int wdc_head = 0; 159 static int wdc_size = 16 * 1024; 160 static int chp_idx = 1; 161 162 void 163 wdc_log(struct channel_softc *chp, enum wdcevent_type type, 164 unsigned int size, char val[]) 165 { 166 unsigned int request_size; 167 int idx; 168 char *ptr; 169 int nbytes; 170 171 if (wdc_head < 0 || wdc_head > wdc_size || 172 wdc_tail < 0 || wdc_tail > wdc_size) { 173 printf ("wdc_log: wdc_head %x wdc_tail %x\n", wdc_head, wdc_tail); 174 return; 175 } 176 177 if (size > wdc_size / 2) { 178 printf ("wdc_log: type %d size %x\n", type, size); 179 } 180 181 if (wdc_log_buf == NULL) { 182 wdc_log_buf = malloc(wdc_size, M_DEVBUF, M_NOWAIT); 183 if (wdc_log_buf == NULL) 184 return; 185 } 186 if (chp->ch_log_idx == 0) 187 chp->ch_log_idx = chp_idx++; 188 189 request_size = size + 2; 190 191 /* Check how many bytes are left */ 192 nbytes = wdc_head - wdc_tail; 193 if (nbytes < 0) nbytes += wdc_size; 194 195 if (nbytes + request_size >= wdc_size) { 196 wdc_tail = (wdc_tail + request_size * 2) % wdc_size; 197 } 198 199 /* Avoid wrapping in the middle of a request */ 200 if (wdc_head + request_size >= wdc_size) { 201 memset(&wdc_log_buf[wdc_head], 0, wdc_size - wdc_head); 202 wdc_head = 0; 203 } 204 205 ptr = &wdc_log_buf[wdc_head]; 206 *ptr++ = type & 0xff; 207 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f); 208 209 idx = 0; 210 while (size--) { 211 *ptr++ = val[idx]; 212 idx++; 213 } 214 wdc_head += request_size; 215 } 216 217 char *wdc_get_log(unsigned int *, unsigned int *); 218 219 char * 220 wdc_get_log(unsigned int * size, unsigned int *left) 221 { 222 int bytes = (wdc_head - wdc_tail); 223 char *retbuf; 224 int ot, c1, c2; 225 226 if (left != NULL) 227 *left = 0; 228 229 if (bytes < 0) bytes += wdc_size; 230 if (bytes > *size) { 231 if (left != NULL) { 232 *left = bytes - *size; 233 } 234 bytes = *size; 235 } 236 237 if (wdc_log_buf == NULL) { 238 *size = 0; 239 *left = 0; 240 return (NULL); 241 } 242 243 if (wdc_head < 0 || wdc_head > wdc_size || 244 wdc_tail < 0 || wdc_tail > wdc_size) { 245 printf ("wdc_log: wdc_head %x wdc_tail %x\n", wdc_head, wdc_tail); 246 *size = 0; 247 *left = 0; 248 return (NULL); 249 } 250 251 retbuf = malloc(bytes, M_TEMP, M_NOWAIT); 252 if (retbuf == NULL) { 253 *size = 0; 254 *left = bytes; 255 return (NULL); 256 } 257 258 *size = bytes; 259 260 ot = wdc_tail; 261 wdc_tail += bytes; 262 if (wdc_tail > wdc_size) { 263 wdc_tail -= wdc_size; 264 c2 = wdc_tail; 265 c1 = bytes - wdc_tail; 266 } else { 267 c1 = bytes; 268 c2 = 0; 269 } 270 271 memcpy(retbuf, &wdc_log_buf[ot], c1); 272 memcpy(&retbuf[c1], &wdc_log_buf[0], c2); 273 274 return (retbuf); 275 } 276 277 278 u_int8_t 279 wdc_default_read_reg(chp, reg) 280 struct channel_softc *chp; 281 enum wdc_regs reg; 282 { 283 #ifdef DIAGNOSTIC 284 if (reg & _WDC_WRONLY) { 285 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 286 } 287 #endif /* DIAGNOSTIC */ 288 289 if (reg & _WDC_AUX) 290 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 291 reg & _WDC_REGMASK)); 292 else 293 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 294 reg & _WDC_REGMASK)); 295 } 296 297 void 298 wdc_default_write_reg(chp, reg, val) 299 struct channel_softc *chp; 300 enum wdc_regs reg; 301 u_int8_t val; 302 { 303 #ifdef DIAGNOSTIC 304 if (reg & _WDC_RDONLY) { 305 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 306 } 307 #endif /* DIAGNOSTIC */ 308 309 if (reg & _WDC_AUX) 310 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 311 reg & _WDC_REGMASK, val); 312 else 313 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 314 reg & _WDC_REGMASK, val); 315 } 316 317 318 void 319 wdc_default_read_raw_multi_2(chp, data, nbytes) 320 struct channel_softc *chp; 321 void *data; 322 unsigned int nbytes; 323 { 324 if (data == NULL) { 325 int i; 326 327 for (i = 0; i < nbytes; i += 2) { 328 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 329 } 330 331 return; 332 } 333 334 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 335 data, nbytes); 336 return; 337 } 338 339 340 void 341 wdc_default_write_raw_multi_2(chp, data, nbytes) 342 struct channel_softc *chp; 343 void *data; 344 unsigned int nbytes; 345 { 346 if (data == NULL) { 347 int i; 348 349 for (i = 0; i < nbytes; i += 2) { 350 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 351 } 352 353 return; 354 } 355 356 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 357 data, nbytes); 358 return; 359 } 360 361 362 void 363 wdc_default_write_raw_multi_4(chp, data, nbytes) 364 struct channel_softc *chp; 365 void *data; 366 unsigned int nbytes; 367 { 368 if (data == NULL) { 369 int i; 370 371 for (i = 0; i < nbytes; i += 4) { 372 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 373 } 374 375 return; 376 } 377 378 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 379 data, nbytes); 380 return; 381 } 382 383 384 void 385 wdc_default_read_raw_multi_4(chp, data, nbytes) 386 struct channel_softc *chp; 387 void *data; 388 unsigned int nbytes; 389 { 390 if (data == NULL) { 391 int i; 392 393 for (i = 0; i < nbytes; i += 4) { 394 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 395 } 396 397 return; 398 } 399 400 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 401 data, nbytes); 402 return; 403 } 404 405 406 int 407 wdprint(aux, pnp) 408 void *aux; 409 const char *pnp; 410 { 411 struct ata_atapi_attach *aa_link = aux; 412 if (pnp) 413 printf("drive at %s", pnp); 414 printf(" channel %d drive %d", aa_link->aa_channel, 415 aa_link->aa_drv_data->drive); 416 return (UNCONF); 417 } 418 419 int 420 atapi_print(aux, pnp) 421 void *aux; 422 const char *pnp; 423 { 424 struct ata_atapi_attach *aa_link = aux; 425 if (pnp) 426 printf("atapiscsi at %s", pnp); 427 printf(" channel %d", aa_link->aa_channel); 428 return (UNCONF); 429 } 430 431 void 432 wdc_disable_intr(chp) 433 struct channel_softc *chp; 434 { 435 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 436 } 437 438 void 439 wdc_enable_intr(chp) 440 struct channel_softc *chp; 441 { 442 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 443 } 444 445 void 446 wdc_set_drive(struct channel_softc *chp, int drive) 447 { 448 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM); 449 WDC_LOG_SET_DRIVE(chp, drive); 450 } 451 452 int 453 wdc_floating_bus(chp, drive) 454 struct channel_softc *chp; 455 int drive; 456 457 { 458 u_int8_t cumulative_status, status; 459 int iter; 460 461 wdc_set_drive(chp, drive); 462 delay(10); 463 464 /* Stolen from Phoenix BIOS Drive Autotyping document */ 465 cumulative_status = 0; 466 for (iter = 0; iter < 100; iter++) { 467 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 468 delay (1); 469 470 status = CHP_READ_REG(chp, wdr_status); 471 472 /* The other bits are meaningless if BSY is set */ 473 if (status & WDCS_BSY) 474 continue; 475 476 cumulative_status |= status; 477 478 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 479 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 480 return 1; 481 } 482 483 484 return 0; 485 } 486 487 488 int 489 wdc_preata_drive(chp, drive) 490 struct channel_softc *chp; 491 int drive; 492 493 { 494 if (wdc_floating_bus(chp, drive)) { 495 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 496 chp->wdc->sc_dev.dv_xname, 497 chp->channel, drive), DEBUG_PROBE); 498 return 0; 499 } 500 501 wdc_set_drive(chp, drive); 502 delay(100); 503 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 504 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 505 chp->wdc->sc_dev.dv_xname, 506 chp->channel, drive), DEBUG_PROBE); 507 return 0; 508 } 509 510 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 511 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL); 512 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 513 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 514 chp->wdc->sc_dev.dv_xname, 515 chp->channel, drive), DEBUG_PROBE); 516 return 0; 517 } 518 519 return 1; 520 } 521 522 int 523 wdc_ata_present(chp, drive) 524 struct channel_softc *chp; 525 int drive; 526 { 527 int time_to_done; 528 int retry_cnt = 0; 529 530 wdc_set_drive(chp, drive); 531 delay(10); 532 533 retry: 534 /* 535 You're actually supposed to wait up to 10 seconds 536 for DRDY. However, as a practical matter, most 537 drives assert DRDY very quickly after dropping BSY. 538 539 The 10 seconds wait is sub-optimal because, according 540 to the ATA standard, the master should reply with 00 541 for any reads to a non-existant slave. 542 */ 543 time_to_done = wdc_wait_for_status(chp, 544 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 545 (WDCS_DRDY | WDCS_DSC), 1000); 546 if (time_to_done == -1) { 547 if (retry_cnt == 0 && chp->ch_status == 0x00) { 548 /* At least one flash card needs to be kicked */ 549 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 550 retry_cnt++; 551 goto retry; 552 } 553 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 554 " %02x\n", 555 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 556 chp->channel, drive, chp->ch_status), 557 DEBUG_PROBE); 558 return 0; 559 } 560 561 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 562 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 563 " %02x\n", 564 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 565 chp->channel, drive, chp->ch_status), 566 DEBUG_PROBE); 567 568 return 0; 569 } 570 571 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 572 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 573 chp->channel, drive, time_to_done), DEBUG_PROBE); 574 575 /* 576 * Test register writability 577 */ 578 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 579 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 580 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 581 DELAY(10); 582 583 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 584 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 585 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 586 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 587 chp->channel, drive), DEBUG_PROBE); 588 return 0; 589 } 590 591 return 1; 592 } 593 594 595 /* 596 Test to see controller with at least one attached drive is there. 597 Returns a bit for each possible drive found (0x01 for drive 0, 598 0x02 for drive 1). 599 */ 600 601 int 602 wdcprobe(chp) 603 struct channel_softc *chp; 604 { 605 u_int8_t st0, st1, sc, sn, cl, ch; 606 u_int8_t ret_value = 0x03; 607 u_int8_t drive; 608 #ifdef WDCDEBUG 609 int savedmask = wdcdebug_mask; 610 #endif 611 612 if (chp->_vtbl == 0) { 613 int s = splbio(); 614 chp->_vtbl = &wdc_default_vtbl; 615 splx(s); 616 } 617 618 #ifdef WDCDEBUG 619 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 620 (chp->wdc && 621 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 622 wdcdebug_mask |= DEBUG_PROBE; 623 #endif /* WDCDEBUG */ 624 625 if (chp->wdc == NULL || 626 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 627 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 628 wdc_set_drive(chp, 0); 629 delay(10); 630 st0 = CHP_READ_REG(chp, wdr_status); 631 WDC_LOG_STATUS(chp, st0); 632 wdc_set_drive(chp, 1); 633 delay(10); 634 st1 = CHP_READ_REG(chp, wdr_status); 635 WDC_LOG_STATUS(chp, st1); 636 637 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 638 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 639 chp->channel, st0, st1), DEBUG_PROBE); 640 641 /* 642 If the status is 0x7f or 0xff, then it's 643 an empty channel with pull-up resistors. 644 */ 645 if ((st0 & 0x7f) == 0x7f) 646 ret_value &= ~0x01; 647 if ((st1 & 0x7f) == 0x7f) 648 ret_value &= ~0x02; 649 if (ret_value == 0) 650 return 0; 651 } 652 653 /* reset the channel */ 654 CHP_WRITE_REG(chp,wdr_ctlr, WDCTL_RST | WDCTL_4BIT); 655 delay(10); 656 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 657 delay(2000); 658 659 ret_value = __wdcwait_reset(chp, ret_value); 660 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 661 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 662 ret_value), DEBUG_PROBE); 663 664 if (ret_value == 0) 665 return 0; 666 667 /* 668 * Use signatures to find potential ATAPI drives 669 */ 670 for (drive = 0; drive < 2; drive++) { 671 if ((ret_value & (0x01 << drive)) == 0) 672 continue; 673 wdc_set_drive(chp, drive); 674 delay(10); 675 /* Save registers contents */ 676 st0 = CHP_READ_REG(chp, wdr_status); 677 sc = CHP_READ_REG(chp, wdr_seccnt); 678 sn = CHP_READ_REG(chp, wdr_sector); 679 cl = CHP_READ_REG(chp, wdr_cyl_lo); 680 ch = CHP_READ_REG(chp, wdr_cyl_hi); 681 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl); 682 683 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%x, sc=0x%x" 684 " sn=0x%x cl=0x%x ch=0x%x\n", 685 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 686 chp->channel, drive, st0, sc, sn, cl, ch), DEBUG_PROBE); 687 /* 688 * This is a simplification of the test in the ATAPI 689 * spec since not all drives seem to set the other regs 690 * correctly. 691 */ 692 if (cl == 0x14 && ch == 0xeb) 693 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 694 } 695 696 /* 697 * Detect ATA drives by poking around the registers 698 */ 699 for (drive = 0; drive < 2; drive++) { 700 if ((ret_value & (0x01 << drive)) == 0) 701 continue; 702 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 703 continue; 704 705 wdc_disable_intr(chp); 706 /* ATA detect */ 707 if (wdc_ata_present(chp, drive)) { 708 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 709 if (chp->wdc == NULL || 710 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 711 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 712 } else { 713 ret_value &= ~(1 << drive); 714 } 715 wdc_enable_intr(chp); 716 } 717 718 #ifdef WDCDEBUG 719 wdcdebug_mask = savedmask; 720 #endif 721 return (ret_value); 722 } 723 724 /* 725 * Call activate routine of underlying devices. 726 */ 727 int 728 wdcactivate(self, act) 729 struct device *self; 730 enum devact act; 731 { 732 int error = 0; 733 int s; 734 735 s = splbio(); 736 config_activate_children(self, act); 737 splx(s); 738 739 return (error); 740 } 741 742 void 743 wdcattach(chp) 744 struct channel_softc *chp; 745 { 746 int channel_flags, ctrl_flags, i; 747 #ifndef __OpenBSD__ 748 int error; 749 #endif 750 struct ata_atapi_attach aa_link; 751 static int inited = 0; 752 #ifdef WDCDEBUG 753 int savedmask = wdcdebug_mask; 754 #endif 755 756 if (!cold) 757 at_poll = AT_WAIT; 758 759 timeout_set(&chp->ch_timo, wdctimeout, chp); 760 761 #ifndef __OpenBSD__ 762 if ((error = wdc_addref(chp)) != 0) { 763 printf("%s: unable to enable controller\n", 764 chp->wdc->sc_dev.dv_xname); 765 return; 766 } 767 #endif /* __OpenBSD__ */ 768 if (!chp->_vtbl) 769 chp->_vtbl = &wdc_default_vtbl; 770 771 if (wdcprobe(chp) == 0) { 772 /* If no drives, abort attach here. */ 773 #ifndef __OpenBSD__ 774 wdc_delref(chp); 775 #endif 776 return; 777 } 778 779 /* ATAPI drives need settling time. Give them 250ms */ 780 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 781 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 782 delay(250 * 1000); 783 } 784 785 #ifdef WDCDEBUG 786 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 787 wdcdebug_mask |= DEBUG_PROBE; 788 789 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 790 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 791 wdcdebug_mask = DEBUG_PROBE; 792 } 793 #endif /* WDCDEBUG */ 794 795 /* initialise global data */ 796 if (inited == 0) { 797 /* Initialize the wdc_xfer pool. */ 798 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 799 0, 0, "wdcspl", NULL); 800 inited++; 801 } 802 TAILQ_INIT(&chp->ch_queue->sc_xfer); 803 804 for (i = 0; i < 2; i++) { 805 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 806 807 drvp->chnl_softc = chp; 808 drvp->drive = i; 809 /* If controller can't do 16bit flag the drives as 32bit */ 810 if ((chp->wdc->cap & 811 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 812 WDC_CAPABILITY_DATA32) 813 drvp->drive_flags |= DRIVE_CAP32; 814 815 if ((drvp->drive_flags & DRIVE) == 0) 816 continue; 817 818 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 819 chp->ch_flags |= WDCF_ONESLAVE; 820 /* 821 * Issue an IDENTIFY command in order to distinct ATA from OLD. 822 * This also kill ATAPI ghost. 823 */ 824 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 825 CMD_OK) { 826 /* If IDENTIFY succeded, this is not an OLD ctrl */ 827 drvp->drive_flags &= ~DRIVE_OLD; 828 } else { 829 drvp->drive_flags &= 830 ~(DRIVE_ATA | DRIVE_ATAPI); 831 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 832 chp->wdc->sc_dev.dv_xname, 833 chp->channel, i), DEBUG_PROBE); 834 835 if ((drvp->drive_flags & DRIVE_OLD) && 836 !wdc_preata_drive(chp, i)) 837 drvp->drive_flags &= ~DRIVE_OLD; 838 } 839 } 840 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 841 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 842 843 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 844 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 845 DEBUG_PROBE); 846 847 /* If no drives, abort here */ 848 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 849 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 850 goto exit; 851 852 for (i = 0; i < 2; i++) { 853 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 854 continue; 855 } 856 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 857 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 858 aa_link.aa_type = T_ATAPI; 859 else 860 aa_link.aa_type = T_ATA; 861 aa_link.aa_channel = chp->channel; 862 aa_link.aa_openings = 1; 863 aa_link.aa_drv_data = &chp->ch_drive[i]; 864 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 865 } 866 867 /* 868 * reset drive_flags for unnatached devices, reset state for attached 869 * ones 870 */ 871 for (i = 0; i < 2; i++) { 872 if (chp->ch_drive[i].drive_name[0] == 0) 873 chp->ch_drive[i].drive_flags = 0; 874 } 875 876 #ifndef __OpenBSD__ 877 wdc_delref(chp); 878 #endif 879 880 exit: 881 #ifdef WDCDEBUG 882 wdcdebug_mask = savedmask; 883 #endif 884 return; 885 } 886 887 /* 888 * Start I/O on a controller, for the given channel. 889 * The first xfer may be not for our channel if the channel queues 890 * are shared. 891 */ 892 void 893 wdcstart(chp) 894 struct channel_softc *chp; 895 { 896 struct wdc_xfer *xfer; 897 898 splassert(IPL_BIO); 899 900 /* is there a xfer ? */ 901 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) { 902 return; 903 } 904 905 /* adjust chp, in case we have a shared queue */ 906 chp = xfer->chp; 907 908 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 909 return; /* channel already active */ 910 } 911 #ifdef DIAGNOSTIC 912 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 913 panic("wdcstart: channel waiting for irq"); 914 #endif /* DIAGNOSTIC */ 915 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 916 if (!(chp->wdc->claim_hw)(chp, 0)) 917 return; 918 919 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 920 chp->channel, xfer->drive), DEBUG_XFERS); 921 chp->ch_flags |= WDCF_ACTIVE; 922 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 923 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 924 chp->ch_drive[xfer->drive].state = 0; 925 } 926 xfer->c_start(chp, xfer); 927 } 928 929 int 930 wdcdetach(chp, flags) 931 struct channel_softc *chp; 932 int flags; 933 { 934 int s, rv; 935 936 s = splbio(); 937 wdc_kill_pending(chp); 938 939 rv = config_detach_children((struct device *)chp->wdc, flags); 940 splx(s); 941 942 return (rv); 943 } 944 945 /* restart an interrupted I/O */ 946 void 947 wdcrestart(v) 948 void *v; 949 { 950 struct channel_softc *chp = v; 951 int s; 952 953 s = splbio(); 954 wdcstart(chp); 955 splx(s); 956 } 957 958 959 /* 960 * Interrupt routine for the controller. Acknowledge the interrupt, check for 961 * errors on the current operation, mark it done if necessary, and start the 962 * next request. Also check for a partially done transfer, and continue with 963 * the next chunk if so. 964 */ 965 int 966 wdcintr(arg) 967 void *arg; 968 { 969 struct channel_softc *chp = arg; 970 struct wdc_xfer *xfer; 971 int ret; 972 973 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 974 /* Acknowledge interrupt by reading status */ 975 if (chp->_vtbl == 0) { 976 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 977 wdr_status & _WDC_REGMASK); 978 } else { 979 CHP_READ_REG(chp, wdr_status); 980 } 981 982 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 983 return 0; 984 } 985 986 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 987 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 988 chp->ch_flags &= ~WDCF_IRQ_WAIT; 989 ret = xfer->c_intr(chp, xfer, 1); 990 if (ret == 0) /* irq was not for us, still waiting for irq */ 991 chp->ch_flags |= WDCF_IRQ_WAIT; 992 return (ret); 993 } 994 995 /* Put all disk in RESET state */ 996 void wdc_reset_channel(drvp) 997 struct ata_drive_datas *drvp; 998 { 999 struct channel_softc *chp = drvp->chnl_softc; 1000 int drive; 1001 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1002 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1003 DEBUG_FUNCS); 1004 (void) wdcreset(chp, VERBOSE); 1005 for (drive = 0; drive < 2; drive++) { 1006 chp->ch_drive[drive].state = 0; 1007 } 1008 } 1009 1010 int 1011 wdcreset(chp, verb) 1012 struct channel_softc *chp; 1013 int verb; 1014 { 1015 int drv_mask1, drv_mask2; 1016 1017 if (!chp->_vtbl) 1018 chp->_vtbl = &wdc_default_vtbl; 1019 1020 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_RST | WDCTL_4BIT); 1021 delay(10); 1022 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 1023 delay(2000); 1024 1025 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1026 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1027 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 1028 if (verb && drv_mask2 != drv_mask1) { 1029 printf("%s channel %d: reset failed for", 1030 chp->wdc->sc_dev.dv_xname, chp->channel); 1031 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1032 printf(" drive 0"); 1033 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1034 printf(" drive 1"); 1035 printf("\n"); 1036 } 1037 1038 return (drv_mask1 != drv_mask2) ? 1 : 0; 1039 } 1040 1041 static int 1042 __wdcwait_reset(chp, drv_mask) 1043 struct channel_softc *chp; 1044 int drv_mask; 1045 { 1046 int timeout; 1047 u_int8_t st0, st1; 1048 1049 /* wait for BSY to deassert */ 1050 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 1051 wdc_set_drive(chp, 0); 1052 delay(10); 1053 st0 = CHP_READ_REG(chp, wdr_status); 1054 wdc_set_drive(chp, 1); 1055 delay(10); 1056 st1 = CHP_READ_REG(chp, wdr_status); 1057 1058 if ((drv_mask & 0x01) == 0) { 1059 /* no master */ 1060 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1061 /* No master, slave is ready, it's done */ 1062 goto end; 1063 } 1064 } else if ((drv_mask & 0x02) == 0) { 1065 /* no slave */ 1066 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1067 /* No slave, master is ready, it's done */ 1068 goto end; 1069 } 1070 } else { 1071 /* Wait for both master and slave to be ready */ 1072 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1073 goto end; 1074 } 1075 } 1076 delay(WDCDELAY); 1077 } 1078 /* Reset timed out. Maybe it's because drv_mask was not right */ 1079 if (st0 & WDCS_BSY) 1080 drv_mask &= ~0x01; 1081 if (st1 & WDCS_BSY) 1082 drv_mask &= ~0x02; 1083 end: 1084 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x, " 1085 "reset time=%d msec\n", 1086 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1087 st0, st1, timeout*WDCDELAY/1000), DEBUG_PROBE); 1088 1089 return drv_mask; 1090 } 1091 1092 /* 1093 * Wait for a drive to be !BSY, and have mask in its status register. 1094 * return -1 for a timeout after "timeout" ms. 1095 */ 1096 int 1097 wdc_wait_for_status(chp, mask, bits, timeout) 1098 struct channel_softc *chp; 1099 int mask, bits, timeout; 1100 { 1101 u_char status; 1102 int time = 0; 1103 1104 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1105 :"none", chp->channel), DEBUG_STATUS); 1106 chp->ch_error = 0; 1107 1108 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1109 1110 for (;;) { 1111 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 1112 WDC_LOG_STATUS(chp, chp->ch_status); 1113 1114 if (status == 0xff && (chp->ch_flags & WDCF_ONESLAVE)) { 1115 wdc_set_drive(chp, 1); 1116 chp->ch_status = status = 1117 CHP_READ_REG(chp, wdr_status); 1118 WDC_LOG_STATUS(chp, chp->ch_status); 1119 } 1120 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 1121 break; 1122 if (++time > timeout) { 1123 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 1124 "error %x\n", status, 1125 CHP_READ_REG(chp, wdr_error)), 1126 DEBUG_STATUSX | DEBUG_STATUS); 1127 return -1; 1128 } 1129 delay(WDCDELAY); 1130 } 1131 if (status & WDCS_ERR) { 1132 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1133 WDC_LOG_ERROR(chp, chp->ch_error); 1134 1135 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1136 DEBUG_STATUSX | DEBUG_STATUS); 1137 } 1138 1139 #ifdef WDCNDELAY_DEBUG 1140 /* After autoconfig, there should be no long delays. */ 1141 if (!cold && time > WDCNDELAY_DEBUG) { 1142 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1143 if (xfer == NULL) 1144 printf("%s channel %d: warning: busy-wait took %dus\n", 1145 chp->wdc->sc_dev.dv_xname, chp->channel, 1146 WDCDELAY * time); 1147 else 1148 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1149 chp->wdc->sc_dev.dv_xname, chp->channel, 1150 xfer->drive, 1151 WDCDELAY * time); 1152 } 1153 #endif /* WDCNDELAY_DEBUG */ 1154 return time; 1155 } 1156 1157 void 1158 wdctimeout(arg) 1159 void *arg; 1160 { 1161 struct channel_softc *chp = (struct channel_softc *)arg; 1162 struct wdc_xfer *xfer; 1163 int s; 1164 1165 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1166 1167 s = splbio(); 1168 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1169 1170 /* Did we lose a race with the interrupt? */ 1171 if (xfer == NULL || 1172 !timeout_triggered(&chp->ch_timo)) { 1173 splx(s); 1174 return; 1175 } 1176 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1177 __wdcerror(chp, "timeout"); 1178 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1179 "atapi":"ata"); 1180 printf("\tc_bcount: %d\n", xfer->c_bcount); 1181 printf("\tc_skip: %d\n", xfer->c_skip); 1182 /* 1183 * Call the interrupt routine. If we just missed and interrupt, 1184 * it will do what's needed. Else, it will take the needed 1185 * action (reset the device). 1186 */ 1187 xfer->c_flags |= C_TIMEOU; 1188 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1189 xfer->c_intr(chp, xfer, 1); 1190 } else 1191 __wdcerror(chp, "missing untimeout"); 1192 splx(s); 1193 } 1194 1195 /* 1196 * Probe drive's capabilites, for use by the controller later 1197 * Assumes drvp points to an existing drive. 1198 * XXX this should be a controller-indep function 1199 */ 1200 void 1201 wdc_probe_caps(drvp, params) 1202 struct ata_drive_datas *drvp; 1203 struct ataparams *params; 1204 { 1205 struct channel_softc *chp = drvp->chnl_softc; 1206 struct wdc_softc *wdc = chp->wdc; 1207 int i, valid_mode_found; 1208 int cf_flags = drvp->cf_flags; 1209 1210 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1211 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1212 struct ataparams params2; 1213 1214 /* 1215 * Controller claims 16 and 32 bit transfers. 1216 * Re-do an IDENTIFY with 32-bit transfers, 1217 * and compare results. 1218 */ 1219 drvp->drive_flags |= DRIVE_CAP32; 1220 ata_get_params(drvp, at_poll, ¶ms2); 1221 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1222 /* Not good. fall back to 16bits */ 1223 drvp->drive_flags &= ~DRIVE_CAP32; 1224 } 1225 } 1226 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1227 if (params->atap_ata_major > 0x01 && 1228 params->atap_ata_major != 0xffff) { 1229 for (i = 14; i > 0; i--) { 1230 if (params->atap_ata_major & (1 << i)) { 1231 printf("%sATA version %d\n", sep, i); 1232 drvp->ata_vers = i; 1233 break; 1234 } 1235 } 1236 } else 1237 #endif /* 0 */ 1238 /* Use PIO mode 3 as a default value for ATAPI devices */ 1239 if (drvp->drive_flags & DRIVE_ATAPI) 1240 drvp->PIO_mode = 3; 1241 1242 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap %d cf_flags %d\n", 1243 wdc->cap, cf_flags), DEBUG_PROBE); 1244 1245 valid_mode_found = 0; 1246 1247 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__, 1248 params->atap_oldpiotiming), DEBUG_PROBE); 1249 /* 1250 * ATA-4 compliant devices contain PIO mode 1251 * number in atap_oldpiotiming. 1252 */ 1253 if (params->atap_oldpiotiming <= 2) { 1254 drvp->PIO_cap = params->atap_oldpiotiming; 1255 valid_mode_found = 1; 1256 drvp->drive_flags |= DRIVE_MODE; 1257 } else if (params->atap_oldpiotiming > 180 && 1258 params->atap_oldpiotiming <= 600) { 1259 /* 1260 * ATA-2 compliant devices contain cycle 1261 * time in atap_oldpiotiming. 1262 * A device with a cycle time of 180ns 1263 * or less is at least PIO mode 3 and 1264 * should be reporting that in 1265 * atap_piomode_supp, so ignore it here. 1266 * A cycle time greater than 600ns seems 1267 * to be invalid. 1268 */ 1269 if (params->atap_oldpiotiming <= 240) { 1270 drvp->PIO_cap = 2; 1271 } else if (params->atap_oldpiotiming <= 480) { 1272 drvp->PIO_cap = 1; 1273 } else { 1274 drvp->PIO_cap = 0; 1275 } 1276 valid_mode_found = 1; 1277 drvp->drive_flags |= DRIVE_MODE; 1278 } 1279 if (valid_mode_found) 1280 drvp->PIO_mode = drvp->PIO_cap; 1281 1282 /* 1283 * It's not in the specs, but it seems that some drive 1284 * returns 0xffff in atap_extensions when this field is invalid 1285 */ 1286 if (params->atap_extensions != 0xffff && 1287 (params->atap_extensions & WDC_EXT_MODES)) { 1288 /* 1289 * XXX some drives report something wrong here (they claim to 1290 * support PIO mode 8 !). As mode is coded on 3 bits in 1291 * SET FEATURE, limit it to 7 (so limit i to 4). 1292 * If higther mode than 7 is found, abort. 1293 */ 1294 for (i = 7; i >= 0; i--) { 1295 if ((params->atap_piomode_supp & (1 << i)) == 0) 1296 continue; 1297 if (i > 4) 1298 return; 1299 1300 valid_mode_found = 1; 1301 1302 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1303 drvp->PIO_cap = i + 3; 1304 continue; 1305 } 1306 1307 /* 1308 * See if mode is accepted. 1309 * If the controller can't set its PIO mode, 1310 * assume the BIOS set it up correctly 1311 */ 1312 if (ata_set_mode(drvp, 0x08 | (i + 3), 1313 at_poll) != CMD_OK) 1314 continue; 1315 1316 /* 1317 * If controller's driver can't set its PIO mode, 1318 * set the highest one the controller supports 1319 */ 1320 if (wdc->PIO_cap >= i + 3) { 1321 drvp->PIO_mode = i + 3; 1322 drvp->PIO_cap = i + 3; 1323 break; 1324 } 1325 } 1326 if (!valid_mode_found) { 1327 /* 1328 * We didn't find a valid PIO mode. 1329 * Assume the values returned for DMA are buggy too 1330 */ 1331 return; 1332 } 1333 drvp->drive_flags |= DRIVE_MODE; 1334 1335 /* Some controllers don't support ATAPI DMA */ 1336 if ((drvp->drive_flags & DRIVE_ATAPI) && 1337 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1338 return; 1339 1340 valid_mode_found = 0; 1341 for (i = 7; i >= 0; i--) { 1342 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1343 continue; 1344 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1345 (wdc->cap & WDC_CAPABILITY_MODE)) 1346 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1347 != CMD_OK) 1348 continue; 1349 1350 valid_mode_found = 1; 1351 1352 if (wdc->cap & WDC_CAPABILITY_DMA) { 1353 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1354 wdc->DMA_cap < i) 1355 continue; 1356 drvp->DMA_mode = i; 1357 drvp->DMA_cap = i; 1358 drvp->drive_flags |= DRIVE_DMA; 1359 } 1360 break; 1361 } 1362 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1363 for (i = 7; i >= 0; i--) { 1364 if ((params->atap_udmamode_supp & (1 << i)) 1365 == 0) 1366 continue; 1367 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1368 (wdc->cap & WDC_CAPABILITY_UDMA)) 1369 if (ata_set_mode(drvp, 0x40 | i, 1370 at_poll) != CMD_OK) 1371 continue; 1372 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1373 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1374 wdc->UDMA_cap < i) 1375 continue; 1376 drvp->UDMA_mode = i; 1377 drvp->UDMA_cap = i; 1378 drvp->drive_flags |= DRIVE_UDMA; 1379 } 1380 break; 1381 } 1382 } 1383 } 1384 1385 /* Try to guess ATA version here, if it didn't get reported */ 1386 if (drvp->ata_vers == 0) { 1387 if (drvp->drive_flags & DRIVE_UDMA) 1388 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1389 else if (drvp->PIO_cap > 2) 1390 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1391 } 1392 if (cf_flags & ATA_CONFIG_PIO_SET) { 1393 drvp->PIO_mode = 1394 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1395 drvp->drive_flags |= DRIVE_MODE; 1396 } 1397 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1398 /* don't care about DMA modes */ 1399 return; 1400 } 1401 if (cf_flags & ATA_CONFIG_DMA_SET) { 1402 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1403 ATA_CONFIG_DMA_DISABLE) { 1404 drvp->drive_flags &= ~DRIVE_DMA; 1405 } else { 1406 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1407 ATA_CONFIG_DMA_OFF; 1408 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1409 } 1410 } 1411 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1412 /* don't care about UDMA modes */ 1413 return; 1414 } 1415 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1416 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1417 ATA_CONFIG_UDMA_DISABLE) { 1418 drvp->drive_flags &= ~DRIVE_UDMA; 1419 } else { 1420 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1421 ATA_CONFIG_UDMA_OFF; 1422 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1423 } 1424 } 1425 } 1426 1427 void 1428 wdc_output_bytes(drvp, bytes, buflen) 1429 struct ata_drive_datas *drvp; 1430 void *bytes; 1431 unsigned int buflen; 1432 { 1433 struct channel_softc *chp = drvp->chnl_softc; 1434 unsigned int off = 0; 1435 unsigned int len = buflen, roundlen; 1436 1437 if (drvp->drive_flags & DRIVE_CAP32) { 1438 roundlen = len & ~3; 1439 1440 CHP_WRITE_RAW_MULTI_4(chp, 1441 (void *)((u_int8_t *)bytes + off), roundlen); 1442 1443 off += roundlen; 1444 len -= roundlen; 1445 } 1446 1447 if (len > 0) { 1448 roundlen = (len + 1) & ~0x1; 1449 1450 CHP_WRITE_RAW_MULTI_2(chp, 1451 (void *)((u_int8_t *)bytes + off), roundlen); 1452 } 1453 1454 return; 1455 } 1456 1457 void 1458 wdc_input_bytes(drvp, bytes, buflen) 1459 struct ata_drive_datas *drvp; 1460 void *bytes; 1461 unsigned int buflen; 1462 { 1463 struct channel_softc *chp = drvp->chnl_softc; 1464 unsigned int off = 0; 1465 unsigned int len = buflen, roundlen; 1466 1467 if (drvp->drive_flags & DRIVE_CAP32) { 1468 roundlen = len & ~3; 1469 1470 CHP_READ_RAW_MULTI_4(chp, 1471 (void *)((u_int8_t *)bytes + off), roundlen); 1472 1473 off += roundlen; 1474 len -= roundlen; 1475 } 1476 1477 if (len > 0) { 1478 roundlen = (len + 1) & ~0x1; 1479 1480 CHP_READ_RAW_MULTI_2(chp, 1481 (void *)((u_int8_t *)bytes + off), roundlen); 1482 } 1483 1484 return; 1485 } 1486 1487 void 1488 wdc_print_caps(drvp) 1489 struct ata_drive_datas *drvp; 1490 { 1491 /* This is actually a lie until we fix the _probe_caps 1492 algorithm. Don't print out lies */ 1493 #if 0 1494 printf("%s: can use ", drvp->drive_name); 1495 1496 if (drvp->drive_flags & DRIVE_CAP32) { 1497 printf("32-bit"); 1498 } else 1499 printf("16-bit"); 1500 1501 printf(", PIO mode %d", drvp->PIO_cap); 1502 1503 if (drvp->drive_flags & DRIVE_DMA) { 1504 printf(", DMA mode %d", drvp->DMA_cap); 1505 } 1506 1507 if (drvp->drive_flags & DRIVE_UDMA) { 1508 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1509 } 1510 1511 printf("\n"); 1512 #endif /* 0 */ 1513 } 1514 1515 void 1516 wdc_print_current_modes(chp) 1517 struct channel_softc *chp; 1518 { 1519 int drive; 1520 struct ata_drive_datas *drvp; 1521 1522 for (drive = 0; drive < 2; drive++) { 1523 drvp = &chp->ch_drive[drive]; 1524 if ((drvp->drive_flags & DRIVE) == 0) 1525 continue; 1526 1527 printf("%s(%s:%d:%d):", 1528 drvp->drive_name, 1529 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1530 1531 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1532 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1533 printf(" using BIOS timings"); 1534 else 1535 printf(" using PIO mode %d", drvp->PIO_mode); 1536 if (drvp->drive_flags & DRIVE_DMA) 1537 printf(", DMA mode %d", drvp->DMA_mode); 1538 if (drvp->drive_flags & DRIVE_UDMA) 1539 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1540 printf("\n"); 1541 } 1542 } 1543 1544 /* 1545 * downgrade the transfer mode of a drive after an error. return 1 if 1546 * downgrade was possible, 0 otherwise. 1547 */ 1548 int 1549 wdc_downgrade_mode(drvp) 1550 struct ata_drive_datas *drvp; 1551 { 1552 struct channel_softc *chp = drvp->chnl_softc; 1553 struct wdc_softc *wdc = chp->wdc; 1554 int cf_flags = drvp->cf_flags; 1555 1556 /* if drive or controller don't know its mode, we can't do much */ 1557 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1558 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1559 return 0; 1560 /* current drive mode was set by a config flag, let it this way */ 1561 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1562 (cf_flags & ATA_CONFIG_DMA_SET) || 1563 (cf_flags & ATA_CONFIG_UDMA_SET)) 1564 return 0; 1565 1566 /* 1567 * We'd ideally like to use an Ultra DMA mode since they have the 1568 * protection of a CRC. So we try each Ultra DMA mode and see if 1569 * we can find any working combo 1570 */ 1571 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1572 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1573 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1574 drvp->drive_name, drvp->UDMA_mode); 1575 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1576 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1577 /* 1578 * If we were using ultra-DMA, don't downgrade to 1579 * multiword DMA if we noticed a CRC error. It has 1580 * been noticed that CRC errors in ultra-DMA lead to 1581 * silent data corruption in multiword DMA. Data 1582 * corruption is less likely to occur in PIO mode. 1583 */ 1584 drvp->drive_flags &= ~DRIVE_UDMA; 1585 drvp->drive_flags |= DRIVE_DMA; 1586 drvp->DMA_mode = drvp->DMA_cap; 1587 printf("%s: transfer error, downgrading to DMA mode %d\n", 1588 drvp->drive_name, drvp->DMA_mode); 1589 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1590 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1591 drvp->PIO_mode = drvp->PIO_cap; 1592 printf("%s: transfer error, downgrading to PIO mode %d\n", 1593 drvp->drive_name, drvp->PIO_mode); 1594 } else /* already using PIO, can't downgrade */ 1595 return 0; 1596 1597 wdc->set_modes(chp); 1598 /* reset the channel, which will schedule all drives for setup */ 1599 wdc_reset_channel(drvp); 1600 return 1; 1601 } 1602 1603 int 1604 wdc_exec_command(drvp, wdc_c) 1605 struct ata_drive_datas *drvp; 1606 struct wdc_command *wdc_c; 1607 { 1608 struct channel_softc *chp = drvp->chnl_softc; 1609 struct wdc_xfer *xfer; 1610 int s, ret; 1611 1612 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1613 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1614 DEBUG_FUNCS); 1615 1616 /* set up an xfer and queue. Wait for completion */ 1617 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1618 WDC_NOSLEEP); 1619 if (xfer == NULL) { 1620 return WDC_TRY_AGAIN; 1621 } 1622 1623 if (wdc_c->flags & AT_POLL) 1624 xfer->c_flags |= C_POLL; 1625 xfer->drive = drvp->drive; 1626 xfer->databuf = wdc_c->data; 1627 xfer->c_bcount = wdc_c->bcount; 1628 xfer->cmd = wdc_c; 1629 xfer->c_start = __wdccommand_start; 1630 xfer->c_intr = __wdccommand_intr; 1631 xfer->c_kill_xfer = __wdccommand_done; 1632 1633 s = splbio(); 1634 wdc_exec_xfer(chp, xfer); 1635 #ifdef DIAGNOSTIC 1636 if ((wdc_c->flags & AT_POLL) != 0 && 1637 (wdc_c->flags & AT_DONE) == 0) 1638 panic("wdc_exec_command: polled command not done"); 1639 #endif /* DIAGNOSTIC */ 1640 if (wdc_c->flags & AT_DONE) { 1641 ret = WDC_COMPLETE; 1642 } else { 1643 if (wdc_c->flags & AT_WAIT) { 1644 WDCDEBUG_PRINT(("wdc_exec_command sleeping"), 1645 DEBUG_FUNCS); 1646 1647 while ((wdc_c->flags & AT_DONE) == 0) { 1648 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1649 } 1650 ret = WDC_COMPLETE; 1651 } else { 1652 ret = WDC_QUEUED; 1653 } 1654 } 1655 splx(s); 1656 return ret; 1657 } 1658 1659 void 1660 __wdccommand_start(chp, xfer) 1661 struct channel_softc *chp; 1662 struct wdc_xfer *xfer; 1663 { 1664 int drive = xfer->drive; 1665 struct wdc_command *wdc_c = xfer->cmd; 1666 1667 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1668 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1669 DEBUG_FUNCS); 1670 1671 /* 1672 * Disable interrupts if we're polling 1673 */ 1674 if (xfer->c_flags & C_POLL) { 1675 wdc_disable_intr(chp); 1676 } 1677 1678 wdc_set_drive(chp, drive); 1679 DELAY(1); 1680 1681 /* 1682 * For resets, we don't really care to make sure that 1683 * the bus is free 1684 */ 1685 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1686 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1687 wdc_c->timeout) != 0) { 1688 goto timeout; 1689 } 1690 } else 1691 DELAY(10); 1692 1693 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1694 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1695 1696 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) { 1697 delay(10); 1698 if (wait_for_unbusy(chp, wdc_c->timeout) != 0) 1699 goto timeout; 1700 1701 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) { 1702 __wdccommand_done(chp, xfer); 1703 return; 1704 } 1705 1706 if (wait_for_drq(chp, wdc_c->timeout) != 0) 1707 goto timeout; 1708 1709 wdc_output_bytes(&chp->ch_drive[drive], 1710 wdc_c->data, wdc_c->bcount); 1711 } 1712 1713 if ((wdc_c->flags & AT_POLL) == 0) { 1714 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1715 timeout_add(&chp->ch_timo, wdc_c->timeout / 1000 * hz); 1716 return; 1717 } 1718 1719 /* 1720 * Polled command. Wait for drive ready or drq. Done in intr(). 1721 * Wait for at last 400ns for status bit to be valid. 1722 */ 1723 delay(10); 1724 __wdccommand_intr(chp, xfer, 0); 1725 return; 1726 1727 timeout: 1728 wdc_c->flags |= AT_TIMEOU; 1729 __wdccommand_done(chp, xfer); 1730 return; 1731 } 1732 1733 int 1734 __wdccommand_intr(chp, xfer, irq) 1735 struct channel_softc *chp; 1736 struct wdc_xfer *xfer; 1737 int irq; 1738 { 1739 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1740 struct wdc_command *wdc_c = xfer->cmd; 1741 int bcount = wdc_c->bcount; 1742 char *data = wdc_c->data; 1743 1744 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1745 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1746 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1747 (irq == 0) ? wdc_c->timeout : 0)) { 1748 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1749 return 0; /* IRQ was not for us */ 1750 wdc_c->flags |= AT_TIMEOU; 1751 __wdccommand_done(chp, xfer); 1752 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1753 return 1; 1754 } 1755 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1756 chp->wdc->irqack(chp); 1757 1758 if ((wdc_c->flags & AT_READ) && (chp->ch_status & WDCS_DRQ)) { 1759 wdc_input_bytes(drvp, data, bcount); 1760 /* Should we wait for device to indicate idle? */ 1761 } 1762 __wdccommand_done(chp, xfer); 1763 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1764 return 1; 1765 } 1766 1767 void 1768 __wdccommand_done(chp, xfer) 1769 struct channel_softc *chp; 1770 struct wdc_xfer *xfer; 1771 { 1772 struct wdc_command *wdc_c = xfer->cmd; 1773 1774 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1775 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, chp->ch_status), DEBUG_FUNCS); 1776 if (chp->ch_status & WDCS_DWF) 1777 wdc_c->flags |= AT_DF; 1778 if (chp->ch_status & WDCS_ERR) { 1779 wdc_c->flags |= AT_ERROR; 1780 wdc_c->r_error = chp->ch_error; 1781 } 1782 wdc_c->flags |= AT_DONE; 1783 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1784 == 0) { 1785 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1786 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1787 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1788 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1789 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1790 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1791 wdc_c->r_precomp = wdc_c->r_error; 1792 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1793 isn't a readable register */ 1794 } 1795 1796 if (xfer->c_flags & C_POLL) { 1797 wdc_enable_intr(chp); 1798 } 1799 1800 wdc_free_xfer(chp, xfer); 1801 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1802 1803 if (wdc_c->flags & AT_WAIT) 1804 wakeup(wdc_c); 1805 else 1806 if (wdc_c->callback) 1807 wdc_c->callback(wdc_c->callback_arg); 1808 wdcstart(chp); 1809 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1810 return; 1811 } 1812 1813 /* 1814 * Send a command. The drive should be ready. 1815 * Assumes interrupts are blocked. 1816 */ 1817 void 1818 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1819 struct channel_softc *chp; 1820 u_int8_t drive; 1821 u_int8_t command; 1822 u_int16_t cylin; 1823 u_int8_t head, sector, count, precomp; 1824 { 1825 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1826 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1827 chp->channel, drive, command, cylin, head, sector, count, precomp), 1828 DEBUG_FUNCS); 1829 WDC_LOG_ATA_CMDLONG(chp, head, precomp, cylin, cylin >> 8, sector, 1830 count, command); 1831 1832 /* Select drive, head, and addressing mode. */ 1833 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1834 1835 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1836 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1837 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1838 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1839 CHP_WRITE_REG(chp, wdr_sector, sector); 1840 CHP_WRITE_REG(chp, wdr_seccnt, count); 1841 1842 /* Send command. */ 1843 CHP_WRITE_REG(chp, wdr_command, command); 1844 return; 1845 } 1846 1847 /* 1848 * Send a 48-bit addressing command. The drive should be ready. 1849 * Assumes interrupts are blocked. 1850 */ 1851 void 1852 wdccommandext(chp, drive, command, blkno, count) 1853 struct channel_softc *chp; 1854 u_int8_t drive; 1855 u_int8_t command; 1856 u_int64_t blkno; 1857 u_int16_t count; 1858 { 1859 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu " 1860 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1861 chp->channel, drive, command, blkno, count), 1862 DEBUG_FUNCS); 1863 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32, 1864 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command); 1865 1866 /* Select drive and LBA mode. */ 1867 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA); 1868 1869 /* Load parameters. All registers are two byte deep FIFOs. */ 1870 CHP_WRITE_REG(chp, wdr_lba_hi, blkno >> 40); 1871 CHP_WRITE_REG(chp, wdr_lba_hi, blkno >> 16); 1872 CHP_WRITE_REG(chp, wdr_lba_mi, blkno >> 32); 1873 CHP_WRITE_REG(chp, wdr_lba_mi, blkno >> 8); 1874 CHP_WRITE_REG(chp, wdr_lba_lo, blkno >> 24); 1875 CHP_WRITE_REG(chp, wdr_lba_lo, blkno); 1876 CHP_WRITE_REG(chp, wdr_seccnt, count >> 8); 1877 CHP_WRITE_REG(chp, wdr_seccnt, count); 1878 1879 /* Send command. */ 1880 CHP_WRITE_REG(chp, wdr_command, command); 1881 return; 1882 } 1883 1884 /* 1885 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1886 * tested by the caller. 1887 */ 1888 void 1889 wdccommandshort(chp, drive, command) 1890 struct channel_softc *chp; 1891 int drive; 1892 int command; 1893 { 1894 1895 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1896 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1897 DEBUG_FUNCS); 1898 WDC_LOG_ATA_CMDSHORT(chp, command); 1899 1900 /* Select drive. */ 1901 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1902 CHP_WRITE_REG(chp, wdr_command, command); 1903 } 1904 1905 /* Add a command to the queue and start controller. Must be called at splbio */ 1906 1907 void 1908 wdc_exec_xfer(chp, xfer) 1909 struct channel_softc *chp; 1910 struct wdc_xfer *xfer; 1911 { 1912 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1913 chp->channel, xfer->drive), DEBUG_XFERS); 1914 1915 /* complete xfer setup */ 1916 xfer->chp = chp; 1917 1918 /* 1919 * If we are a polled command, and the list is not empty, 1920 * we are doing a dump. Drop the list to allow the polled command 1921 * to complete, we're going to reboot soon anyway. 1922 */ 1923 if ((xfer->c_flags & C_POLL) != 0 && 1924 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) { 1925 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1926 } 1927 /* insert at the end of command list */ 1928 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1929 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1930 chp->ch_flags), DEBUG_XFERS); 1931 wdcstart(chp); 1932 } 1933 1934 struct wdc_xfer * 1935 wdc_get_xfer(flags) 1936 int flags; 1937 { 1938 struct wdc_xfer *xfer; 1939 int s; 1940 1941 s = splbio(); 1942 xfer = pool_get(&wdc_xfer_pool, 1943 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1944 splx(s); 1945 if (xfer != NULL) 1946 memset(xfer, 0, sizeof(struct wdc_xfer)); 1947 return xfer; 1948 } 1949 1950 void 1951 wdc_free_xfer(chp, xfer) 1952 struct channel_softc *chp; 1953 struct wdc_xfer *xfer; 1954 { 1955 struct wdc_softc *wdc = chp->wdc; 1956 int s; 1957 1958 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1959 (*wdc->free_hw)(chp); 1960 s = splbio(); 1961 chp->ch_flags &= ~WDCF_ACTIVE; 1962 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1963 pool_put(&wdc_xfer_pool, xfer); 1964 splx(s); 1965 } 1966 1967 1968 /* 1969 * Kill off all pending xfers for a channel_softc. 1970 * 1971 * Must be called at splbio(). 1972 */ 1973 void 1974 wdc_kill_pending(chp) 1975 struct channel_softc *chp; 1976 { 1977 struct wdc_xfer *xfer; 1978 1979 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1980 chp = xfer->chp; 1981 (*xfer->c_kill_xfer)(chp, xfer); 1982 } 1983 } 1984 1985 static void 1986 __wdcerror(chp, msg) 1987 struct channel_softc *chp; 1988 char *msg; 1989 { 1990 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1991 if (xfer == NULL) 1992 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1993 msg); 1994 else 1995 printf("%s(%s:%d:%d): %s\n", 1996 chp->ch_drive[xfer->drive].drive_name, 1997 chp->wdc->sc_dev.dv_xname, 1998 chp->channel, xfer->drive, msg); 1999 } 2000 2001 /* 2002 * the bit bucket 2003 */ 2004 void 2005 wdcbit_bucket(chp, size) 2006 struct channel_softc *chp; 2007 int size; 2008 { 2009 CHP_READ_RAW_MULTI_2(chp, NULL, size); 2010 } 2011 2012 2013 #include <sys/ataio.h> 2014 #include <sys/file.h> 2015 #include <sys/buf.h> 2016 2017 /* 2018 * Glue necessary to hook ATAIOCCOMMAND into physio 2019 */ 2020 2021 struct wdc_ioctl { 2022 LIST_ENTRY(wdc_ioctl) wi_list; 2023 struct buf wi_bp; 2024 struct uio wi_uio; 2025 struct iovec wi_iov; 2026 atareq_t wi_atareq; 2027 struct ata_drive_datas *wi_drvp; 2028 }; 2029 2030 struct wdc_ioctl *wdc_ioctl_find(struct buf *); 2031 void wdc_ioctl_free(struct wdc_ioctl *); 2032 struct wdc_ioctl *wdc_ioctl_get(void); 2033 void wdc_ioctl_strategy(struct buf *); 2034 2035 LIST_HEAD(, wdc_ioctl) wi_head; 2036 2037 /* 2038 * Allocate space for a ioctl queue structure. Mostly taken from 2039 * scsipi_ioctl.c 2040 */ 2041 struct wdc_ioctl * 2042 wdc_ioctl_get() 2043 { 2044 struct wdc_ioctl *wi; 2045 int s; 2046 2047 wi = malloc(sizeof(struct wdc_ioctl), M_TEMP, M_WAITOK); 2048 bzero(wi, sizeof (struct wdc_ioctl)); 2049 s = splbio(); 2050 LIST_INSERT_HEAD(&wi_head, wi, wi_list); 2051 splx(s); 2052 return (wi); 2053 } 2054 2055 /* 2056 * Free an ioctl structure and remove it from our list 2057 */ 2058 2059 void 2060 wdc_ioctl_free(wi) 2061 struct wdc_ioctl *wi; 2062 { 2063 int s; 2064 2065 s = splbio(); 2066 LIST_REMOVE(wi, wi_list); 2067 splx(s); 2068 free(wi, M_TEMP); 2069 } 2070 2071 /* 2072 * Find a wdc_ioctl structure based on the struct buf. 2073 */ 2074 2075 struct wdc_ioctl * 2076 wdc_ioctl_find(bp) 2077 struct buf *bp; 2078 { 2079 struct wdc_ioctl *wi; 2080 int s; 2081 2082 s = splbio(); 2083 LIST_FOREACH(wi, &wi_head, wi_list) 2084 if (bp == &wi->wi_bp) 2085 break; 2086 splx(s); 2087 return (wi); 2088 } 2089 2090 /* 2091 * Ioctl pseudo strategy routine 2092 * 2093 * This is mostly stolen from scsipi_ioctl.c:scsistrategy(). What 2094 * happens here is: 2095 * 2096 * - wdioctl() queues a wdc_ioctl structure. 2097 * 2098 * - wdioctl() calls physio/wdc_ioctl_strategy based on whether or not 2099 * user space I/O is required. If physio() is called, physio() eventually 2100 * calls wdc_ioctl_strategy(). 2101 * 2102 * - In either case, wdc_ioctl_strategy() calls wdc_exec_command() 2103 * to perform the actual command 2104 * 2105 * The reason for the use of the pseudo strategy routine is because 2106 * when doing I/O to/from user space, physio _really_ wants to be in 2107 * the loop. We could put the entire buffer into the ioctl request 2108 * structure, but that won't scale if we want to do things like download 2109 * microcode. 2110 */ 2111 2112 void 2113 wdc_ioctl_strategy(bp) 2114 struct buf *bp; 2115 { 2116 struct wdc_ioctl *wi; 2117 struct wdc_command wdc_c; 2118 int error = 0; 2119 int s; 2120 2121 wi = wdc_ioctl_find(bp); 2122 if (wi == NULL) { 2123 printf("user_strat: No ioctl\n"); 2124 error = EINVAL; 2125 goto bad; 2126 } 2127 2128 bzero(&wdc_c, sizeof(wdc_c)); 2129 2130 /* 2131 * Abort if physio broke up the transfer 2132 */ 2133 2134 if (bp->b_bcount != wi->wi_atareq.datalen) { 2135 printf("physio split wd ioctl request... cannot proceed\n"); 2136 error = EIO; 2137 goto bad; 2138 } 2139 2140 /* 2141 * Make sure a timeout was supplied in the ioctl request 2142 */ 2143 2144 if (wi->wi_atareq.timeout == 0) { 2145 error = EINVAL; 2146 goto bad; 2147 } 2148 2149 if (wi->wi_atareq.flags & ATACMD_READ) 2150 wdc_c.flags |= AT_READ; 2151 else if (wi->wi_atareq.flags & ATACMD_WRITE) 2152 wdc_c.flags |= AT_WRITE; 2153 2154 if (wi->wi_atareq.flags & ATACMD_READREG) 2155 wdc_c.flags |= AT_READREG; 2156 2157 wdc_c.flags |= AT_WAIT; 2158 2159 wdc_c.timeout = wi->wi_atareq.timeout; 2160 wdc_c.r_command = wi->wi_atareq.command; 2161 wdc_c.r_head = wi->wi_atareq.head & 0x0f; 2162 wdc_c.r_cyl = wi->wi_atareq.cylinder; 2163 wdc_c.r_sector = wi->wi_atareq.sec_num; 2164 wdc_c.r_count = wi->wi_atareq.sec_count; 2165 wdc_c.r_precomp = wi->wi_atareq.features; 2166 if (wi->wi_drvp->drive_flags & DRIVE_ATAPI) { 2167 wdc_c.r_st_bmask = 0; 2168 wdc_c.r_st_pmask = 0; 2169 if (wdc_c.r_command == WDCC_IDENTIFY) 2170 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 2171 } else { 2172 wdc_c.r_st_bmask = WDCS_DRDY; 2173 wdc_c.r_st_pmask = WDCS_DRDY; 2174 } 2175 wdc_c.data = wi->wi_bp.b_data; 2176 wdc_c.bcount = wi->wi_bp.b_bcount; 2177 2178 if (wdc_exec_command(wi->wi_drvp, &wdc_c) != WDC_COMPLETE) { 2179 wi->wi_atareq.retsts = ATACMD_ERROR; 2180 goto bad; 2181 } 2182 2183 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 2184 if (wdc_c.flags & AT_ERROR) { 2185 wi->wi_atareq.retsts = ATACMD_ERROR; 2186 wi->wi_atareq.error = wdc_c.r_error; 2187 } else if (wdc_c.flags & AT_DF) 2188 wi->wi_atareq.retsts = ATACMD_DF; 2189 else 2190 wi->wi_atareq.retsts = ATACMD_TIMEOUT; 2191 } else { 2192 wi->wi_atareq.retsts = ATACMD_OK; 2193 if (wi->wi_atareq.flags & ATACMD_READREG) { 2194 wi->wi_atareq.head = wdc_c.r_head ; 2195 wi->wi_atareq.cylinder = wdc_c.r_cyl; 2196 wi->wi_atareq.sec_num = wdc_c.r_sector; 2197 wi->wi_atareq.sec_count = wdc_c.r_count; 2198 wi->wi_atareq.features = wdc_c.r_precomp; 2199 wi->wi_atareq.error = wdc_c.r_error; 2200 } 2201 } 2202 2203 bp->b_error = 0; 2204 s = splbio(); 2205 biodone(bp); 2206 splx(s); 2207 return; 2208 bad: 2209 bp->b_flags |= B_ERROR; 2210 bp->b_error = error; 2211 s = splbio(); 2212 biodone(bp); 2213 splx(s); 2214 } 2215 2216 int 2217 wdc_ioctl(drvp, xfer, addr, flag, p) 2218 struct ata_drive_datas *drvp; 2219 u_long xfer; 2220 caddr_t addr; 2221 int flag; 2222 struct proc *p; 2223 { 2224 int error = 0; 2225 2226 switch (xfer) { 2227 case ATAIOGETTRACE: { 2228 atagettrace_t *agt = (atagettrace_t *)addr; 2229 unsigned int size = 0; 2230 char *log_to_copy; 2231 2232 size = agt->buf_size; 2233 if (size > 65536) { 2234 size = 65536; 2235 } 2236 2237 log_to_copy = wdc_get_log(&size, &agt->bytes_left); 2238 2239 if (log_to_copy != NULL) { 2240 error = copyout(log_to_copy, agt->buf, size); 2241 free(log_to_copy, M_TEMP); 2242 } 2243 2244 agt->bytes_copied = size; 2245 break; 2246 } 2247 2248 case ATAIOCCOMMAND: 2249 /* 2250 * Make sure this command is (relatively) safe first 2251 */ 2252 if ((((atareq_t *) addr)->flags & ATACMD_READ) == 0 && 2253 (flag & FWRITE) == 0) { 2254 error = EBADF; 2255 goto exit; 2256 } 2257 { 2258 struct wdc_ioctl *wi; 2259 atareq_t *atareq = (atareq_t *) addr; 2260 2261 wi = wdc_ioctl_get(); 2262 wi->wi_drvp = drvp; 2263 wi->wi_atareq = *atareq; 2264 2265 if (atareq->datalen && atareq->flags & 2266 (ATACMD_READ | ATACMD_WRITE)) { 2267 wi->wi_iov.iov_base = atareq->databuf; 2268 wi->wi_iov.iov_len = atareq->datalen; 2269 wi->wi_uio.uio_iov = &wi->wi_iov; 2270 wi->wi_uio.uio_iovcnt = 1; 2271 wi->wi_uio.uio_resid = atareq->datalen; 2272 wi->wi_uio.uio_offset = 0; 2273 wi->wi_uio.uio_segflg = UIO_USERSPACE; 2274 wi->wi_uio.uio_rw = 2275 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE; 2276 wi->wi_uio.uio_procp = curproc; 2277 error = physio(wdc_ioctl_strategy, &wi->wi_bp, 0, 2278 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE, 2279 minphys, &wi->wi_uio); 2280 } else { 2281 /* No need to call physio if we don't have any 2282 user data */ 2283 wi->wi_bp.b_flags = 0; 2284 wi->wi_bp.b_data = 0; 2285 wi->wi_bp.b_bcount = 0; 2286 wi->wi_bp.b_dev = 0; 2287 wi->wi_bp.b_proc = curproc; 2288 LIST_INIT(&wi->wi_bp.b_dep); 2289 wdc_ioctl_strategy(&wi->wi_bp); 2290 error = wi->wi_bp.b_error; 2291 } 2292 *atareq = wi->wi_atareq; 2293 wdc_ioctl_free(wi); 2294 goto exit; 2295 } 2296 default: 2297 error = ENOTTY; 2298 goto exit; 2299 } 2300 2301 exit: 2302 return (error); 2303 } 2304