1 /* $OpenBSD: wdc.c,v 1.41 2001/07/31 07:07:00 csapuntz Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 4 5 /* 6 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1998 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/conf.h> 74 #include <sys/buf.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/syslog.h> 78 #include <sys/proc.h> 79 #include <sys/pool.h> 80 #include <vm/vm.h> 81 82 #include <machine/intr.h> 83 #include <machine/bus.h> 84 85 #include <dev/ata/atavar.h> 86 #include <dev/ata/atareg.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #include "atapiscsi.h" 91 92 #define WDCDELAY 100 /* 100 microseconds */ 93 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 94 #if 0 95 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 96 #define WDCNDELAY_DEBUG 50 97 #endif 98 99 struct pool wdc_xfer_pool; 100 101 static void __wdcerror __P((struct channel_softc*, char *)); 102 static int __wdcwait_reset __P((struct channel_softc *, int)); 103 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 104 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 105 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 106 int wdprint __P((void *, const char *)); 107 void wdc_kill_pending __P((struct channel_softc *)); 108 109 #define DEBUG_INTR 0x01 110 #define DEBUG_XFERS 0x02 111 #define DEBUG_STATUS 0x04 112 #define DEBUG_FUNCS 0x08 113 #define DEBUG_PROBE 0x10 114 #define DEBUG_STATUSX 0x20 115 #define DEBUG_SDRIVE 0x40 116 #define DEBUG_DETACH 0x80 117 118 #ifdef WDCDEBUG 119 int wdcdebug_mask = 0; 120 int wdc_nxfer = 0; 121 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 122 #else 123 #define WDCDEBUG_PRINT(args, level) 124 #endif 125 126 int at_poll = AT_POLL; 127 128 u_int8_t wdc_default_read_reg __P((struct channel_softc *, enum wdc_regs)); 129 void wdc_default_write_reg __P((struct channel_softc *, enum wdc_regs, u_int8_t)); 130 void wdc_default_read_raw_multi_2 __P((struct channel_softc *, 131 void *, unsigned int)); 132 void wdc_default_write_raw_multi_2 __P((struct channel_softc *, 133 void *, unsigned int)); 134 void wdc_default_read_raw_multi_4 __P((struct channel_softc *, 135 void *, unsigned int)); 136 void wdc_default_write_raw_multi_4 __P((struct channel_softc *, 137 void *, unsigned int)); 138 139 int wdc_floating_bus __P((struct channel_softc *, int)); 140 int wdc_preata_drive __P((struct channel_softc *, int)); 141 int wdc_ata_present __P((struct channel_softc *, int)); 142 143 struct channel_softc_vtbl wdc_default_vtbl = { 144 wdc_default_read_reg, 145 wdc_default_write_reg, 146 wdc_default_read_raw_multi_2, 147 wdc_default_write_raw_multi_2, 148 wdc_default_read_raw_multi_4, 149 wdc_default_write_raw_multi_4 150 }; 151 152 u_int8_t 153 wdc_default_read_reg(chp, reg) 154 struct channel_softc *chp; 155 enum wdc_regs reg; 156 { 157 #ifdef DIAGNOSTIC 158 if (reg & _WDC_WRONLY) { 159 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 160 } 161 #endif 162 163 if (reg & _WDC_AUX) 164 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 165 reg & _WDC_REGMASK)); 166 else 167 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 168 reg & _WDC_REGMASK)); 169 } 170 171 void 172 wdc_default_write_reg(chp, reg, val) 173 struct channel_softc *chp; 174 enum wdc_regs reg; 175 u_int8_t val; 176 { 177 #ifdef DIAGNOSTIC 178 if (reg & _WDC_RDONLY) { 179 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 180 } 181 #endif 182 183 if (reg & _WDC_AUX) 184 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 185 reg & _WDC_REGMASK, val); 186 else 187 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 188 reg & _WDC_REGMASK, val); 189 } 190 191 192 void 193 wdc_default_read_raw_multi_2(chp, data, nbytes) 194 struct channel_softc *chp; 195 void *data; 196 unsigned int nbytes; 197 { 198 if (data == NULL) { 199 int i; 200 201 for (i = 0; i < nbytes; i += 2) { 202 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 203 } 204 205 return; 206 } 207 208 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 209 data, nbytes); 210 return; 211 } 212 213 214 void 215 wdc_default_write_raw_multi_2(chp, data, nbytes) 216 struct channel_softc *chp; 217 void *data; 218 unsigned int nbytes; 219 { 220 if (data == NULL) { 221 int i; 222 223 for (i = 0; i < nbytes; i += 2) { 224 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 225 } 226 227 return; 228 } 229 230 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 231 data, nbytes); 232 return; 233 } 234 235 236 void 237 wdc_default_write_raw_multi_4(chp, data, nbytes) 238 struct channel_softc *chp; 239 void *data; 240 unsigned int nbytes; 241 { 242 if (data == NULL) { 243 int i; 244 245 for (i = 0; i < nbytes; i += 4) { 246 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 247 } 248 249 return; 250 } 251 252 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 253 data, nbytes); 254 return; 255 } 256 257 258 void 259 wdc_default_read_raw_multi_4(chp, data, nbytes) 260 struct channel_softc *chp; 261 void *data; 262 unsigned int nbytes; 263 { 264 if (data == NULL) { 265 int i; 266 267 for (i = 0; i < nbytes; i += 4) { 268 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 269 } 270 271 return; 272 } 273 274 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 275 data, nbytes); 276 return; 277 } 278 279 280 int 281 wdprint(aux, pnp) 282 void *aux; 283 const char *pnp; 284 { 285 struct ata_atapi_attach *aa_link = aux; 286 if (pnp) 287 printf("drive at %s", pnp); 288 printf(" channel %d drive %d", aa_link->aa_channel, 289 aa_link->aa_drv_data->drive); 290 return (UNCONF); 291 } 292 293 int 294 atapi_print(aux, pnp) 295 void *aux; 296 const char *pnp; 297 { 298 struct ata_atapi_attach *aa_link = aux; 299 if (pnp) 300 printf("atapiscsi at %s", pnp); 301 printf(" channel %d", aa_link->aa_channel); 302 return (UNCONF); 303 } 304 305 void 306 wdc_disable_intr(chp) 307 struct channel_softc *chp; 308 { 309 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 310 } 311 312 void 313 wdc_enable_intr(chp) 314 struct channel_softc *chp; 315 { 316 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 317 } 318 319 int 320 wdc_floating_bus(chp, drive) 321 struct channel_softc *chp; 322 int drive; 323 324 { 325 u_int8_t cumulative_status, status; 326 int iter; 327 328 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 329 delay(10); 330 331 /* Stolen from Phoenix BIOS Drive Autotyping document */ 332 cumulative_status = 0; 333 for (iter = 0; iter < 100; iter++) { 334 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 335 delay (1); 336 337 status = CHP_READ_REG(chp, wdr_status); 338 339 /* The other bits are meaningless if BSY is set */ 340 if (status & WDCS_BSY) 341 continue; 342 343 cumulative_status |= status; 344 345 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 346 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 347 return 1; 348 } 349 350 351 return 0; 352 } 353 354 355 int 356 wdc_preata_drive(chp, drive) 357 struct channel_softc *chp; 358 int drive; 359 360 { 361 if (wdc_floating_bus(chp, drive)) { 362 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 363 chp->wdc->sc_dev.dv_xname, 364 chp->channel, drive), DEBUG_PROBE); 365 return 0; 366 } 367 368 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 369 delay(100); 370 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 371 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 372 chp->wdc->sc_dev.dv_xname, 373 chp->channel, drive), DEBUG_PROBE); 374 return 0; 375 } 376 377 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 378 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 379 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 380 chp->wdc->sc_dev.dv_xname, 381 chp->channel, drive), DEBUG_PROBE); 382 return 0; 383 } 384 385 return 1; 386 } 387 388 int 389 wdc_ata_present(chp, drive) 390 struct channel_softc *chp; 391 int drive; 392 { 393 int time_to_done; 394 int retry_cnt = 0; 395 396 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 397 delay(10); 398 399 retry: 400 /* 401 You're actually supposed to wait up to 10 seconds 402 for DRDY. However, as a practical matter, most 403 drives assert DRDY very quickly after dropping BSY. 404 405 The 10 seconds wait is sub-optimal because, according 406 to the ATA standard, the master should reply with 00 407 for any reads to a non-existant slave. 408 */ 409 time_to_done = wdc_wait_for_status(chp, 410 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 411 (WDCS_DRDY | WDCS_DSC), 1000); 412 if (time_to_done == -1) { 413 if (retry_cnt == 0 && chp->ch_status == 0x00) { 414 /* At least one flash card needs to be kicked */ 415 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 416 retry_cnt++; 417 goto retry; 418 } 419 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 420 " %02x\n", 421 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 422 chp->channel, drive, chp->ch_status), 423 DEBUG_PROBE); 424 return 0; 425 } 426 427 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 428 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 429 " %02x\n", 430 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 431 chp->channel, drive, chp->ch_status), 432 DEBUG_PROBE); 433 434 return 0; 435 } 436 437 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 438 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 439 chp->channel, drive, time_to_done), DEBUG_PROBE); 440 441 /* 442 * Test register writability 443 */ 444 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 445 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 446 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 447 DELAY(10); 448 449 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 450 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 451 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 452 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 453 chp->channel, drive), DEBUG_PROBE); 454 return 0; 455 } 456 457 return 1; 458 } 459 460 461 /* 462 Test to see controller with at least one attached drive is there. 463 Returns a bit for each possible drive found (0x01 for drive 0, 464 0x02 for drive 1). 465 */ 466 467 int 468 wdcprobe(chp) 469 struct channel_softc *chp; 470 { 471 u_int8_t st0, st1, sc, sn, cl, ch; 472 u_int8_t ret_value = 0x03; 473 u_int8_t drive; 474 475 if (chp->_vtbl == 0) { 476 int s = splbio(); 477 chp->_vtbl = &wdc_default_vtbl; 478 splx(s); 479 } 480 481 #ifdef WDCDEBUG 482 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 483 (chp->wdc && 484 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 485 wdcdebug_mask |= DEBUG_PROBE; 486 #endif 487 488 if (chp->wdc == NULL || 489 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 490 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 491 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM); 492 delay(10); 493 st0 = CHP_READ_REG(chp, wdr_status); 494 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | 0x10); 495 delay(10); 496 st1 = CHP_READ_REG(chp, wdr_status); 497 498 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 499 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 500 chp->channel, st0, st1), DEBUG_PROBE); 501 502 /* 503 If the status is 0x7f or 0xff, then it's 504 an empty channel with pull-up resistors. 505 */ 506 if ((st0 & 0x7f) == 0x7f) 507 ret_value &= ~0x01; 508 if ((st1 & 0x7f) == 0x7f) 509 ret_value &= ~0x02; 510 if (ret_value == 0) 511 return 0; 512 } 513 514 /* reset the channel */ 515 CHP_WRITE_REG(chp,wdr_ctlr, WDCTL_RST | WDCTL_4BIT); 516 delay(10); 517 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 518 delay(2000); 519 520 ret_value = __wdcwait_reset(chp, ret_value); 521 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 522 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 523 ret_value), DEBUG_PROBE); 524 525 if (ret_value == 0) 526 return 0; 527 528 /* 529 * Use signatures to find potential ATAPI drives 530 */ 531 for (drive = 0; drive < 2; drive++) { 532 if ((ret_value & (0x01 << drive)) == 0) 533 continue; 534 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 535 delay(10); 536 /* Save registers contents */ 537 st0 = CHP_READ_REG(chp, wdr_status); 538 sc = CHP_READ_REG(chp, wdr_seccnt); 539 sn = CHP_READ_REG(chp, wdr_sector); 540 cl = CHP_READ_REG(chp, wdr_cyl_lo); 541 ch = CHP_READ_REG(chp, wdr_cyl_hi); 542 543 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%x, sc=0x%x" 544 " sn=0x%x cl=0x%x ch=0x%x\n", 545 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 546 chp->channel, drive, st0, sc, sn, cl, ch), DEBUG_PROBE); 547 /* 548 * This is a simplification of the test in the ATAPI 549 * spec since not all drives seem to set the other regs 550 * correctly. 551 */ 552 if (cl == 0x14 && ch == 0xeb) 553 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 554 } 555 556 /* 557 * Detect ATA drives by poking around the registers 558 */ 559 for (drive = 0; drive < 2; drive++) { 560 if ((ret_value & (0x01 << drive)) == 0) 561 continue; 562 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 563 continue; 564 565 wdc_disable_intr(chp); 566 /* ATA detect */ 567 if (wdc_ata_present(chp, drive)) { 568 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 569 if (chp->wdc == NULL || 570 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 571 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 572 } else { 573 ret_value &= ~(1 << drive); 574 } 575 wdc_enable_intr(chp); 576 } 577 578 #ifdef WDCDEBUG 579 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 580 (chp->wdc && 581 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 582 wdcdebug_mask &= ~DEBUG_PROBE; 583 #endif 584 return (ret_value); 585 } 586 587 /* 588 * Call activate routine of underlying devices. 589 */ 590 int 591 wdcactivate(self, act) 592 struct device *self; 593 enum devact act; 594 { 595 int error = 0; 596 int s; 597 598 s = splbio(); 599 config_activate_children(self, act); 600 splx(s); 601 602 return (error); 603 } 604 605 void 606 wdcattach(chp) 607 struct channel_softc *chp; 608 { 609 int channel_flags, ctrl_flags, i; 610 #ifndef __OpenBSD__ 611 int error; 612 #endif 613 struct ata_atapi_attach aa_link; 614 static int inited = 0; 615 #ifdef WDCDEBUG 616 int savedmask = wdcdebug_mask; 617 #endif 618 619 if (!cold) 620 at_poll = AT_WAIT; 621 622 #ifndef __OpenBSD__ 623 if ((error = wdc_addref(chp)) != 0) { 624 printf("%s: unable to enable controller\n", 625 chp->wdc->sc_dev.dv_xname); 626 return; 627 } 628 #endif 629 if (!chp->_vtbl) 630 chp->_vtbl = &wdc_default_vtbl; 631 632 if (wdcprobe(chp) == 0) { 633 /* If no drives, abort attach here. */ 634 #ifndef __OpenBSD__ 635 wdc_delref(chp); 636 #endif 637 return; 638 } 639 640 /* ATAPI drives need settling time. Give them 250ms */ 641 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 642 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 643 delay(250 * 1000); 644 } 645 646 #ifdef WDCDEBUG 647 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 648 wdcdebug_mask |= DEBUG_PROBE; 649 650 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 651 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 652 wdcdebug_mask = DEBUG_PROBE; 653 } 654 #endif 655 656 /* initialise global data */ 657 if (inited == 0) { 658 /* Initialize the wdc_xfer pool. */ 659 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 660 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 661 inited++; 662 } 663 TAILQ_INIT(&chp->ch_queue->sc_xfer); 664 timeout_set(&chp->ch_timo, wdctimeout, chp); 665 666 for (i = 0; i < 2; i++) { 667 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 668 669 drvp->chnl_softc = chp; 670 drvp->drive = i; 671 /* If controller can't do 16bit flag the drives as 32bit */ 672 if ((chp->wdc->cap & 673 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 674 WDC_CAPABILITY_DATA32) 675 drvp->drive_flags |= DRIVE_CAP32; 676 677 if ((drvp->drive_flags & DRIVE) == 0) 678 continue; 679 680 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 681 chp->ch_flags |= WDCF_ONESLAVE; 682 /* 683 * Issue an IDENTIFY command in order to distinct ATA from OLD. 684 * This also kill ATAPI ghost. 685 */ 686 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 687 CMD_OK) { 688 /* If IDENTIFY succeded, this is not an OLD ctrl */ 689 drvp->drive_flags &= ~DRIVE_OLD; 690 } else { 691 drvp->drive_flags &= 692 ~(DRIVE_ATA | DRIVE_ATAPI); 693 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 694 chp->wdc->sc_dev.dv_xname, 695 chp->channel, i), DEBUG_PROBE); 696 697 if ((drvp->drive_flags & DRIVE_OLD) && 698 !wdc_preata_drive(chp, i)) 699 drvp->drive_flags &= ~DRIVE_OLD; 700 } 701 } 702 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 703 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 704 705 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 706 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 707 DEBUG_PROBE); 708 709 /* If no drives, abort here */ 710 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 711 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 712 goto exit; 713 714 for (i = 0; i < 2; i++) { 715 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 716 continue; 717 } 718 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 719 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 720 aa_link.aa_type = T_ATAPI; 721 else 722 aa_link.aa_type = T_ATA; 723 aa_link.aa_channel = chp->channel; 724 aa_link.aa_openings = 1; 725 aa_link.aa_drv_data = &chp->ch_drive[i]; 726 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 727 } 728 729 /* 730 * reset drive_flags for unnatached devices, reset state for attached 731 * ones 732 */ 733 for (i = 0; i < 2; i++) { 734 if (chp->ch_drive[i].drive_name[0] == 0) 735 chp->ch_drive[i].drive_flags = 0; 736 } 737 738 #ifndef __OpenBSD__ 739 wdc_delref(chp); 740 #endif 741 742 exit: 743 #ifdef WDCDEBUG 744 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 745 wdcdebug_mask &= ~DEBUG_PROBE; 746 747 wdcdebug_mask = savedmask; 748 #endif 749 return; 750 } 751 752 /* 753 * Start I/O on a controller, for the given channel. 754 * The first xfer may be not for our channel if the channel queues 755 * are shared. 756 */ 757 void 758 wdcstart(chp) 759 struct channel_softc *chp; 760 { 761 struct wdc_xfer *xfer; 762 763 #ifdef WDC_DIAGNOSTIC 764 int spl1, spl2; 765 766 spl1 = splbio(); 767 spl2 = splbio(); 768 if (spl2 != spl1) { 769 printf("wdcstart: not at splbio()\n"); 770 panic("wdcstart"); 771 } 772 splx(spl2); 773 splx(spl1); 774 #endif /* WDC_DIAGNOSTIC */ 775 776 /* is there a xfer ? */ 777 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) { 778 return; 779 } 780 781 /* adjust chp, in case we have a shared queue */ 782 chp = xfer->chp; 783 784 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 785 return; /* channel already active */ 786 } 787 #ifdef DIAGNOSTIC 788 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 789 panic("wdcstart: channel waiting for irq\n"); 790 #endif 791 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 792 if (!(chp->wdc->claim_hw)(chp, 0)) 793 return; 794 795 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 796 chp->channel, xfer->drive), DEBUG_XFERS); 797 chp->ch_flags |= WDCF_ACTIVE; 798 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 799 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 800 chp->ch_drive[xfer->drive].state = 0; 801 } 802 xfer->c_start(chp, xfer); 803 } 804 805 int 806 wdcdetach(chp, flags) 807 struct channel_softc *chp; 808 int flags; 809 { 810 int s, rv; 811 812 s = splbio(); 813 wdc_kill_pending(chp); 814 815 rv = config_detach_children((struct device *)chp->wdc, flags); 816 splx(s); 817 818 return (rv); 819 } 820 821 /* restart an interrupted I/O */ 822 void 823 wdcrestart(v) 824 void *v; 825 { 826 struct channel_softc *chp = v; 827 int s; 828 829 s = splbio(); 830 wdcstart(chp); 831 splx(s); 832 } 833 834 835 /* 836 * Interrupt routine for the controller. Acknowledge the interrupt, check for 837 * errors on the current operation, mark it done if necessary, and start the 838 * next request. Also check for a partially done transfer, and continue with 839 * the next chunk if so. 840 */ 841 int 842 wdcintr(arg) 843 void *arg; 844 { 845 struct channel_softc *chp = arg; 846 struct wdc_xfer *xfer; 847 int ret; 848 849 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 850 /* Acknowledge interrupt by reading status */ 851 if (chp->_vtbl == 0) { 852 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 853 wdr_status & _WDC_REGMASK); 854 } else { 855 CHP_READ_REG(chp, wdr_status); 856 } 857 858 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 859 return 0; 860 } 861 862 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 863 xfer = chp->ch_queue->sc_xfer.tqh_first; 864 chp->ch_flags &= ~WDCF_IRQ_WAIT; 865 ret = xfer->c_intr(chp, xfer, 1); 866 if (ret == 0) /* irq was not for us, still waiting for irq */ 867 chp->ch_flags |= WDCF_IRQ_WAIT; 868 return (ret); 869 } 870 871 /* Put all disk in RESET state */ 872 void wdc_reset_channel(drvp) 873 struct ata_drive_datas *drvp; 874 { 875 struct channel_softc *chp = drvp->chnl_softc; 876 int drive; 877 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 878 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 879 DEBUG_FUNCS); 880 (void) wdcreset(chp, VERBOSE); 881 for (drive = 0; drive < 2; drive++) { 882 chp->ch_drive[drive].state = 0; 883 } 884 } 885 886 int 887 wdcreset(chp, verb) 888 struct channel_softc *chp; 889 int verb; 890 { 891 int drv_mask1, drv_mask2; 892 893 if (!chp->_vtbl) 894 chp->_vtbl = &wdc_default_vtbl; 895 896 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_RST | WDCTL_4BIT); 897 delay(10); 898 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 899 delay(2000); 900 901 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 902 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 903 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 904 if (verb && drv_mask2 != drv_mask1) { 905 printf("%s channel %d: reset failed for", 906 chp->wdc->sc_dev.dv_xname, chp->channel); 907 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 908 printf(" drive 0"); 909 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 910 printf(" drive 1"); 911 printf("\n"); 912 } 913 914 return (drv_mask1 != drv_mask2) ? 1 : 0; 915 } 916 917 static int 918 __wdcwait_reset(chp, drv_mask) 919 struct channel_softc *chp; 920 int drv_mask; 921 { 922 int timeout; 923 u_int8_t st0, st1; 924 925 /* wait for BSY to deassert */ 926 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 927 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM); /* master */ 928 delay(10); 929 st0 = CHP_READ_REG(chp, wdr_status); 930 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | 0x10); /* slave */ 931 delay(10); 932 st1 = CHP_READ_REG(chp, wdr_status); 933 934 if ((drv_mask & 0x01) == 0) { 935 /* no master */ 936 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 937 /* No master, slave is ready, it's done */ 938 goto end; 939 } 940 } else if ((drv_mask & 0x02) == 0) { 941 /* no slave */ 942 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 943 /* No slave, master is ready, it's done */ 944 goto end; 945 } 946 } else { 947 /* Wait for both master and slave to be ready */ 948 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 949 goto end; 950 } 951 } 952 delay(WDCDELAY); 953 } 954 /* Reset timed out. Maybe it's because drv_mask was not right */ 955 if (st0 & WDCS_BSY) 956 drv_mask &= ~0x01; 957 if (st1 & WDCS_BSY) 958 drv_mask &= ~0x02; 959 end: 960 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x, " 961 "reset time=%d msec\n", 962 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 963 st0, st1, timeout*WDCDELAY/1000), DEBUG_PROBE); 964 965 return drv_mask; 966 } 967 968 /* 969 * Wait for a drive to be !BSY, and have mask in its status register. 970 * return -1 for a timeout after "timeout" ms. 971 */ 972 int 973 wdc_wait_for_status(chp, mask, bits, timeout) 974 struct channel_softc *chp; 975 int mask, bits, timeout; 976 { 977 u_char status; 978 int time = 0; 979 980 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 981 :"none", chp->channel), DEBUG_STATUS); 982 chp->ch_error = 0; 983 984 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 985 986 for (;;) { 987 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 988 989 if (status == 0xff && (chp->ch_flags & WDCF_ONESLAVE)) { 990 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | 0x10); 991 chp->ch_status = status = 992 CHP_READ_REG(chp, wdr_status); 993 } 994 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 995 break; 996 if (++time > timeout) { 997 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 998 "error %x\n", status, 999 CHP_READ_REG(chp, wdr_error)), 1000 DEBUG_STATUSX | DEBUG_STATUS); 1001 return -1; 1002 } 1003 delay(WDCDELAY); 1004 } 1005 if (status & WDCS_ERR) { 1006 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1007 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1008 DEBUG_STATUSX | DEBUG_STATUS); 1009 } 1010 1011 #ifdef WDCNDELAY_DEBUG 1012 /* After autoconfig, there should be no long delays. */ 1013 if (!cold && time > WDCNDELAY_DEBUG) { 1014 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1015 if (xfer == NULL) 1016 printf("%s channel %d: warning: busy-wait took %dus\n", 1017 chp->wdc->sc_dev.dv_xname, chp->channel, 1018 WDCDELAY * time); 1019 else 1020 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1021 chp->wdc->sc_dev.dv_xname, chp->channel, 1022 xfer->drive, 1023 WDCDELAY * time); 1024 } 1025 #endif 1026 return time; 1027 } 1028 1029 void 1030 wdctimeout(arg) 1031 void *arg; 1032 { 1033 struct channel_softc *chp = (struct channel_softc *)arg; 1034 struct wdc_xfer *xfer; 1035 int s; 1036 1037 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1038 1039 s = splbio(); 1040 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1041 1042 /* Did we lose a race with the interrupt? */ 1043 if (xfer == NULL || 1044 !timeout_triggered(&chp->ch_timo)) { 1045 splx(s); 1046 return; 1047 } 1048 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1049 __wdcerror(chp, "timeout"); 1050 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1051 "atapi":"ata"); 1052 printf("\tc_bcount: %d\n", xfer->c_bcount); 1053 printf("\tc_skip: %d\n", xfer->c_skip); 1054 /* 1055 * Call the interrupt routine. If we just missed and interrupt, 1056 * it will do what's needed. Else, it will take the needed 1057 * action (reset the device). 1058 */ 1059 xfer->c_flags |= C_TIMEOU; 1060 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1061 xfer->c_intr(chp, xfer, 1); 1062 } else 1063 __wdcerror(chp, "missing untimeout"); 1064 splx(s); 1065 } 1066 1067 /* 1068 * Probe drive's capabilites, for use by the controller later 1069 * Assumes drvp points to an existing drive. 1070 * XXX this should be a controller-indep function 1071 */ 1072 void 1073 wdc_probe_caps(drvp, params) 1074 struct ata_drive_datas *drvp; 1075 struct ataparams *params; 1076 { 1077 struct channel_softc *chp = drvp->chnl_softc; 1078 struct wdc_softc *wdc = chp->wdc; 1079 int i, valid_mode_found; 1080 int cf_flags = drvp->cf_flags; 1081 1082 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1083 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1084 struct ataparams params2; 1085 1086 /* 1087 * Controller claims 16 and 32 bit transfers. 1088 * Re-do an IDENTIFY with 32-bit transfers, 1089 * and compare results. 1090 */ 1091 drvp->drive_flags |= DRIVE_CAP32; 1092 ata_get_params(drvp, at_poll, ¶ms2); 1093 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1094 /* Not good. fall back to 16bits */ 1095 drvp->drive_flags &= ~DRIVE_CAP32; 1096 } 1097 } 1098 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1099 if (params->atap_ata_major > 0x01 && 1100 params->atap_ata_major != 0xffff) { 1101 for (i = 14; i > 0; i--) { 1102 if (params->atap_ata_major & (1 << i)) { 1103 printf("%sATA version %d\n", sep, i); 1104 drvp->ata_vers = i; 1105 break; 1106 } 1107 } 1108 } else 1109 #endif 1110 /* An ATAPI device is at last PIO mode 3 */ 1111 if (drvp->drive_flags & DRIVE_ATAPI) 1112 drvp->PIO_mode = 3; 1113 1114 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap %d cf_flags %d\n", 1115 wdc->cap, cf_flags), DEBUG_PROBE); 1116 1117 /* 1118 * It's not in the specs, but it seems that some drive 1119 * returns 0xffff in atap_extensions when this field is invalid 1120 */ 1121 if (params->atap_extensions != 0xffff && 1122 (params->atap_extensions & WDC_EXT_MODES)) { 1123 valid_mode_found = 0; 1124 /* 1125 * XXX some drives report something wrong here (they claim to 1126 * support PIO mode 8 !). As mode is coded on 3 bits in 1127 * SET FEATURE, limit it to 7 (so limit i to 4). 1128 * If higther mode than 7 is found, abort. 1129 */ 1130 for (i = 7; i >= 0; i--) { 1131 if ((params->atap_piomode_supp & (1 << i)) == 0) 1132 continue; 1133 if (i > 4) 1134 return; 1135 1136 valid_mode_found = 1; 1137 1138 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1139 drvp->PIO_cap = i + 3; 1140 continue; 1141 } 1142 1143 /* 1144 * See if mode is accepted. 1145 * If the controller can't set its PIO mode, 1146 * assume the BIOS set it up correctly 1147 */ 1148 if (ata_set_mode(drvp, 0x08 | (i + 3), 1149 at_poll) != CMD_OK) 1150 continue; 1151 1152 /* 1153 * If controller's driver can't set its PIO mode, 1154 * set the highest one the controller supports 1155 */ 1156 if (wdc->PIO_cap >= i + 3) { 1157 drvp->PIO_mode = i + 3; 1158 drvp->PIO_cap = i + 3; 1159 break; 1160 } 1161 } 1162 if (!valid_mode_found) { 1163 /* 1164 * We didn't find a valid PIO mode. 1165 * Assume the values returned for DMA are buggy too 1166 */ 1167 return; 1168 } 1169 drvp->drive_flags |= DRIVE_MODE; 1170 1171 /* Some controllers don't support ATAPI DMA */ 1172 if ((drvp->drive_flags & DRIVE_ATAPI) && 1173 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1174 return; 1175 1176 valid_mode_found = 0; 1177 for (i = 7; i >= 0; i--) { 1178 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1179 continue; 1180 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1181 (wdc->cap & WDC_CAPABILITY_MODE)) 1182 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1183 != CMD_OK) 1184 continue; 1185 1186 valid_mode_found = 1; 1187 1188 if (wdc->cap & WDC_CAPABILITY_DMA) { 1189 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1190 wdc->DMA_cap < i) 1191 continue; 1192 drvp->DMA_mode = i; 1193 drvp->DMA_cap = i; 1194 drvp->drive_flags |= DRIVE_DMA; 1195 } 1196 break; 1197 } 1198 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1199 for (i = 7; i >= 0; i--) { 1200 if ((params->atap_udmamode_supp & (1 << i)) 1201 == 0) 1202 continue; 1203 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1204 (wdc->cap & WDC_CAPABILITY_UDMA)) 1205 if (ata_set_mode(drvp, 0x40 | i, 1206 at_poll) != CMD_OK) 1207 continue; 1208 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1209 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1210 wdc->UDMA_cap < i) 1211 continue; 1212 drvp->UDMA_mode = i; 1213 drvp->UDMA_cap = i; 1214 drvp->drive_flags |= DRIVE_UDMA; 1215 } 1216 break; 1217 } 1218 } 1219 } 1220 1221 /* Try to guess ATA version here, if it didn't get reported */ 1222 if (drvp->ata_vers == 0) { 1223 if (drvp->drive_flags & DRIVE_UDMA) 1224 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1225 else if (drvp->PIO_cap > 2) 1226 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1227 } 1228 if (cf_flags & ATA_CONFIG_PIO_SET) { 1229 drvp->PIO_mode = 1230 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1231 drvp->drive_flags |= DRIVE_MODE; 1232 } 1233 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1234 /* don't care about DMA modes */ 1235 return; 1236 } 1237 if (cf_flags & ATA_CONFIG_DMA_SET) { 1238 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1239 ATA_CONFIG_DMA_DISABLE) { 1240 drvp->drive_flags &= ~DRIVE_DMA; 1241 } else { 1242 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1243 ATA_CONFIG_DMA_OFF; 1244 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1245 } 1246 } 1247 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1248 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1249 ATA_CONFIG_UDMA_DISABLE) { 1250 drvp->drive_flags &= ~DRIVE_UDMA; 1251 } else { 1252 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1253 ATA_CONFIG_UDMA_OFF; 1254 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1255 } 1256 } 1257 } 1258 1259 void 1260 wdc_output_bytes(drvp, bytes, buflen) 1261 struct ata_drive_datas *drvp; 1262 void *bytes; 1263 unsigned int buflen; 1264 { 1265 struct channel_softc *chp = drvp->chnl_softc; 1266 unsigned int off = 0; 1267 unsigned int len = buflen, roundlen; 1268 1269 if (drvp->drive_flags & DRIVE_CAP32) { 1270 roundlen = len & ~3; 1271 1272 CHP_WRITE_RAW_MULTI_4(chp, 1273 (void *)((u_int8_t *)bytes + off), roundlen); 1274 1275 off += roundlen; 1276 len -= roundlen; 1277 } 1278 1279 if (len > 0) { 1280 roundlen = (len + 1) & ~0x1; 1281 1282 CHP_WRITE_RAW_MULTI_2(chp, 1283 (void *)((u_int8_t *)bytes + off), roundlen); 1284 } 1285 1286 return; 1287 } 1288 1289 void 1290 wdc_input_bytes(drvp, bytes, buflen) 1291 struct ata_drive_datas *drvp; 1292 void *bytes; 1293 unsigned int buflen; 1294 { 1295 struct channel_softc *chp = drvp->chnl_softc; 1296 unsigned int off = 0; 1297 unsigned int len = buflen, roundlen; 1298 1299 if (drvp->drive_flags & DRIVE_CAP32) { 1300 roundlen = len & ~3; 1301 1302 CHP_READ_RAW_MULTI_4(chp, 1303 (void *)((u_int8_t *)bytes + off), roundlen); 1304 1305 off += roundlen; 1306 len -= roundlen; 1307 } 1308 1309 if (len > 0) { 1310 roundlen = (len + 1) & ~0x1; 1311 1312 CHP_READ_RAW_MULTI_2(chp, 1313 (void *)((u_int8_t *)bytes + off), roundlen); 1314 } 1315 1316 return; 1317 } 1318 1319 void 1320 wdc_print_caps(drvp) 1321 struct ata_drive_datas *drvp; 1322 { 1323 /* This is actually a lie until we fix the _probe_caps 1324 algorithm. Don't print out lies */ 1325 #if 0 1326 printf("%s: can use ", drvp->drive_name); 1327 1328 if (drvp->drive_flags & DRIVE_CAP32) { 1329 printf("32-bit"); 1330 } else 1331 printf("16-bit"); 1332 1333 printf(", PIO mode %d", drvp->PIO_cap); 1334 1335 if (drvp->drive_flags & DRIVE_DMA) { 1336 printf(", DMA mode %d", drvp->DMA_cap); 1337 } 1338 1339 if (drvp->drive_flags & DRIVE_UDMA) { 1340 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1341 } 1342 1343 printf("\n"); 1344 #endif 1345 } 1346 1347 void 1348 wdc_print_current_modes(chp) 1349 struct channel_softc *chp; 1350 { 1351 int drive; 1352 struct ata_drive_datas *drvp; 1353 1354 for (drive = 0; drive < 2; drive++) { 1355 drvp = &chp->ch_drive[drive]; 1356 if ((drvp->drive_flags & DRIVE) == 0) 1357 continue; 1358 1359 printf("%s(%s:%d:%d):", 1360 drvp->drive_name, 1361 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1362 1363 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1364 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1365 printf(" using BIOS timings"); 1366 else 1367 printf(" using PIO mode %d", drvp->PIO_mode); 1368 if (drvp->drive_flags & DRIVE_DMA) 1369 printf(", DMA mode %d", drvp->DMA_mode); 1370 if (drvp->drive_flags & DRIVE_UDMA) 1371 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1372 printf("\n"); 1373 } 1374 } 1375 1376 /* 1377 * downgrade the transfer mode of a drive after an error. return 1 if 1378 * downgrade was possible, 0 otherwise. 1379 */ 1380 int 1381 wdc_downgrade_mode(drvp) 1382 struct ata_drive_datas *drvp; 1383 { 1384 struct channel_softc *chp = drvp->chnl_softc; 1385 struct wdc_softc *wdc = chp->wdc; 1386 int cf_flags = drvp->cf_flags; 1387 1388 /* if drive or controller don't know its mode, we can't do much */ 1389 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1390 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1391 return 0; 1392 /* current drive mode was set by a config flag, let it this way */ 1393 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1394 (cf_flags & ATA_CONFIG_DMA_SET) || 1395 (cf_flags & ATA_CONFIG_UDMA_SET)) 1396 return 0; 1397 1398 /* 1399 * We'd ideally like to use an Ultra DMA mode since they have the 1400 * protection of a CRC. So we try each Ultra DMA mode and see if 1401 * we can find any working combo 1402 */ 1403 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1404 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1405 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1406 drvp->drive_name, drvp->UDMA_mode); 1407 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1408 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1409 /* 1410 * If we were using ultra-DMA, don't downgrade to 1411 * multiword DMA if we noticed a CRC error. It has 1412 * been noticed that CRC errors in ultra-DMA lead to 1413 * silent data corruption in multiword DMA. Data 1414 * corruption is less likely to occur in PIO mode. 1415 */ 1416 drvp->drive_flags &= ~DRIVE_UDMA; 1417 drvp->drive_flags |= DRIVE_DMA; 1418 drvp->DMA_mode = drvp->DMA_cap; 1419 printf("%s: transfer error, downgrading to DMA mode %d\n", 1420 drvp->drive_name, drvp->DMA_mode); 1421 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1422 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1423 drvp->PIO_mode = drvp->PIO_cap; 1424 printf("%s: transfer error, downgrading to PIO mode %d\n", 1425 drvp->drive_name, drvp->PIO_mode); 1426 } else /* already using PIO, can't downgrade */ 1427 return 0; 1428 1429 wdc->set_modes(chp); 1430 /* reset the channel, which will schedule all drives for setup */ 1431 wdc_reset_channel(drvp); 1432 return 1; 1433 } 1434 1435 int 1436 wdc_exec_command(drvp, wdc_c) 1437 struct ata_drive_datas *drvp; 1438 struct wdc_command *wdc_c; 1439 { 1440 struct channel_softc *chp = drvp->chnl_softc; 1441 struct wdc_xfer *xfer; 1442 int s, ret; 1443 1444 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1445 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1446 DEBUG_FUNCS); 1447 1448 /* set up an xfer and queue. Wait for completion */ 1449 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1450 WDC_NOSLEEP); 1451 if (xfer == NULL) { 1452 return WDC_TRY_AGAIN; 1453 } 1454 1455 if (wdc_c->flags & AT_POLL) 1456 xfer->c_flags |= C_POLL; 1457 xfer->drive = drvp->drive; 1458 xfer->databuf = wdc_c->data; 1459 xfer->c_bcount = wdc_c->bcount; 1460 xfer->cmd = wdc_c; 1461 xfer->c_start = __wdccommand_start; 1462 xfer->c_intr = __wdccommand_intr; 1463 xfer->c_kill_xfer = __wdccommand_done; 1464 1465 s = splbio(); 1466 wdc_exec_xfer(chp, xfer); 1467 #ifdef DIAGNOSTIC 1468 if ((wdc_c->flags & AT_POLL) != 0 && 1469 (wdc_c->flags & AT_DONE) == 0) 1470 panic("wdc_exec_command: polled command not done\n"); 1471 #endif 1472 if (wdc_c->flags & AT_DONE) { 1473 ret = WDC_COMPLETE; 1474 } else { 1475 if (wdc_c->flags & AT_WAIT) { 1476 WDCDEBUG_PRINT(("wdc_exec_command sleeping"), 1477 DEBUG_FUNCS); 1478 1479 while ((wdc_c->flags & AT_DONE) == 0) { 1480 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1481 } 1482 ret = WDC_COMPLETE; 1483 } else { 1484 ret = WDC_QUEUED; 1485 } 1486 } 1487 splx(s); 1488 return ret; 1489 } 1490 1491 void 1492 __wdccommand_start(chp, xfer) 1493 struct channel_softc *chp; 1494 struct wdc_xfer *xfer; 1495 { 1496 int drive = xfer->drive; 1497 struct wdc_command *wdc_c = xfer->cmd; 1498 1499 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1500 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1501 DEBUG_FUNCS); 1502 1503 /* 1504 * Disable interrupts if we're polling 1505 */ 1506 if (xfer->c_flags & C_POLL) { 1507 wdc_disable_intr(chp); 1508 } 1509 1510 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1511 DELAY(1); 1512 1513 /* 1514 * For resets, we don't really care to make sure that 1515 * the bus is free 1516 */ 1517 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1518 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1519 wdc_c->timeout) != 0) { 1520 wdc_c->flags |= AT_TIMEOU; 1521 __wdccommand_done(chp, xfer); 1522 return; 1523 } 1524 } else 1525 DELAY(10); 1526 1527 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1528 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1529 if ((wdc_c->flags & AT_POLL) == 0) { 1530 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1531 timeout_add(&chp->ch_timo, wdc_c->timeout / 1000 * hz); 1532 return; 1533 } 1534 /* 1535 * Polled command. Wait for drive ready or drq. Done in intr(). 1536 * Wait for at last 400ns for status bit to be valid. 1537 */ 1538 delay(10); 1539 __wdccommand_intr(chp, xfer, 0); 1540 } 1541 1542 int 1543 __wdccommand_intr(chp, xfer, irq) 1544 struct channel_softc *chp; 1545 struct wdc_xfer *xfer; 1546 int irq; 1547 { 1548 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1549 struct wdc_command *wdc_c = xfer->cmd; 1550 int bcount = wdc_c->bcount; 1551 char *data = wdc_c->data; 1552 1553 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1554 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1555 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1556 (irq == 0) ? wdc_c->timeout : 0)) { 1557 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1558 return 0; /* IRQ was not for us */ 1559 wdc_c->flags |= AT_TIMEOU; 1560 __wdccommand_done(chp, xfer); 1561 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1562 return 1; 1563 } 1564 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1565 chp->wdc->irqack(chp); 1566 if (wdc_c->flags & AT_READ) { 1567 wdc_input_bytes(drvp, data, bcount); 1568 } else if (wdc_c->flags & AT_WRITE) { 1569 wdc_output_bytes(drvp, data, bcount); 1570 } 1571 __wdccommand_done(chp, xfer); 1572 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1573 return 1; 1574 } 1575 1576 void 1577 __wdccommand_done(chp, xfer) 1578 struct channel_softc *chp; 1579 struct wdc_xfer *xfer; 1580 { 1581 struct wdc_command *wdc_c = xfer->cmd; 1582 1583 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1584 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, chp->ch_status), DEBUG_FUNCS); 1585 if (chp->ch_status & WDCS_DWF) 1586 wdc_c->flags |= AT_DF; 1587 if (chp->ch_status & WDCS_ERR) { 1588 wdc_c->flags |= AT_ERROR; 1589 wdc_c->r_error = chp->ch_error; 1590 } 1591 wdc_c->flags |= AT_DONE; 1592 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1593 == 0) { 1594 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1595 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1596 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1597 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1598 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1599 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1600 wdc_c->r_precomp = wdc_c->r_error; 1601 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1602 isn't a readable register */ 1603 } 1604 1605 if (xfer->c_flags & C_POLL) { 1606 wdc_enable_intr(chp); 1607 } 1608 1609 wdc_free_xfer(chp, xfer); 1610 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1611 1612 if (wdc_c->flags & AT_WAIT) 1613 wakeup(wdc_c); 1614 else 1615 if (wdc_c->callback) 1616 wdc_c->callback(wdc_c->callback_arg); 1617 wdcstart(chp); 1618 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1619 return; 1620 } 1621 1622 /* 1623 * Send a command. The drive should be ready. 1624 * Assumes interrupts are blocked. 1625 */ 1626 void 1627 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1628 struct channel_softc *chp; 1629 u_int8_t drive; 1630 u_int8_t command; 1631 u_int16_t cylin; 1632 u_int8_t head, sector, count, precomp; 1633 { 1634 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1635 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1636 chp->channel, drive, command, cylin, head, sector, count, precomp), 1637 DEBUG_FUNCS); 1638 1639 /* Select drive, head, and addressing mode. */ 1640 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1641 1642 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1643 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1644 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1645 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1646 CHP_WRITE_REG(chp, wdr_sector, sector); 1647 CHP_WRITE_REG(chp, wdr_seccnt, count); 1648 1649 /* Send command. */ 1650 CHP_WRITE_REG(chp, wdr_command, command); 1651 return; 1652 } 1653 1654 /* 1655 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1656 * tested by the caller. 1657 */ 1658 void 1659 wdccommandshort(chp, drive, command) 1660 struct channel_softc *chp; 1661 int drive; 1662 int command; 1663 { 1664 1665 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1666 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1667 DEBUG_FUNCS); 1668 1669 /* Select drive. */ 1670 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1671 CHP_WRITE_REG(chp, wdr_command, command); 1672 } 1673 1674 /* Add a command to the queue and start controller. Must be called at splbio */ 1675 1676 void 1677 wdc_exec_xfer(chp, xfer) 1678 struct channel_softc *chp; 1679 struct wdc_xfer *xfer; 1680 { 1681 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1682 chp->channel, xfer->drive), DEBUG_XFERS); 1683 1684 /* complete xfer setup */ 1685 xfer->chp = chp; 1686 1687 /* 1688 * If we are a polled command, and the list is not empty, 1689 * we are doing a dump. Drop the list to allow the polled command 1690 * to complete, we're going to reboot soon anyway. 1691 */ 1692 if ((xfer->c_flags & C_POLL) != 0 && 1693 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1694 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1695 } 1696 /* insert at the end of command list */ 1697 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1698 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1699 chp->ch_flags), DEBUG_XFERS); 1700 wdcstart(chp); 1701 } 1702 1703 struct wdc_xfer * 1704 wdc_get_xfer(flags) 1705 int flags; 1706 { 1707 struct wdc_xfer *xfer; 1708 int s; 1709 1710 s = splbio(); 1711 xfer = pool_get(&wdc_xfer_pool, 1712 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1713 splx(s); 1714 if (xfer != NULL) 1715 memset(xfer, 0, sizeof(struct wdc_xfer)); 1716 return xfer; 1717 } 1718 1719 void 1720 wdc_free_xfer(chp, xfer) 1721 struct channel_softc *chp; 1722 struct wdc_xfer *xfer; 1723 { 1724 struct wdc_softc *wdc = chp->wdc; 1725 int s; 1726 1727 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1728 (*wdc->free_hw)(chp); 1729 s = splbio(); 1730 chp->ch_flags &= ~WDCF_ACTIVE; 1731 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1732 pool_put(&wdc_xfer_pool, xfer); 1733 splx(s); 1734 } 1735 1736 1737 /* 1738 * Kill off all pending xfers for a channel_softc. 1739 * 1740 * Must be called at splbio(). 1741 */ 1742 void 1743 wdc_kill_pending(chp) 1744 struct channel_softc *chp; 1745 { 1746 struct wdc_xfer *xfer; 1747 1748 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1749 chp = xfer->chp; 1750 (*xfer->c_kill_xfer)(chp, xfer); 1751 } 1752 } 1753 1754 static void 1755 __wdcerror(chp, msg) 1756 struct channel_softc *chp; 1757 char *msg; 1758 { 1759 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1760 if (xfer == NULL) 1761 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1762 msg); 1763 else 1764 printf("%s(%s:%d:%d): %s\n", 1765 chp->ch_drive[xfer->drive].drive_name, 1766 chp->wdc->sc_dev.dv_xname, 1767 chp->channel, xfer->drive, msg); 1768 } 1769 1770 /* 1771 * the bit bucket 1772 */ 1773 void 1774 wdcbit_bucket(chp, size) 1775 struct channel_softc *chp; 1776 int size; 1777 { 1778 CHP_READ_RAW_MULTI_2(chp, NULL, size); 1779 } 1780 1781 1782 #include <sys/ataio.h> 1783 #include <sys/file.h> 1784 #include <sys/buf.h> 1785 1786 /* 1787 * Glue necessary to hook ATAIOCCOMMAND into physio 1788 */ 1789 1790 struct wdc_ioctl { 1791 LIST_ENTRY(wdc_ioctl) wi_list; 1792 struct buf wi_bp; 1793 struct uio wi_uio; 1794 struct iovec wi_iov; 1795 atareq_t wi_atareq; 1796 struct ata_drive_datas *wi_drvp; 1797 }; 1798 1799 struct wdc_ioctl *wdc_ioctl_find __P((struct buf *)); 1800 void wdc_ioctl_free __P((struct wdc_ioctl *)); 1801 struct wdc_ioctl *wdc_ioctl_get __P((void)); 1802 void wdc_ioctl_strategy __P((struct buf *)); 1803 1804 LIST_HEAD(, wdc_ioctl) wi_head; 1805 1806 /* 1807 * Allocate space for a ioctl queue structure. Mostly taken from 1808 * scsipi_ioctl.c 1809 */ 1810 struct wdc_ioctl * 1811 wdc_ioctl_get() 1812 { 1813 struct wdc_ioctl *wi; 1814 int s; 1815 1816 wi = malloc(sizeof(struct wdc_ioctl), M_TEMP, M_WAITOK); 1817 bzero(wi, sizeof (struct wdc_ioctl)); 1818 s = splbio(); 1819 LIST_INSERT_HEAD(&wi_head, wi, wi_list); 1820 splx(s); 1821 return (wi); 1822 } 1823 1824 /* 1825 * Free an ioctl structure and remove it from our list 1826 */ 1827 1828 void 1829 wdc_ioctl_free(wi) 1830 struct wdc_ioctl *wi; 1831 { 1832 int s; 1833 1834 s = splbio(); 1835 LIST_REMOVE(wi, wi_list); 1836 splx(s); 1837 free(wi, M_TEMP); 1838 } 1839 1840 /* 1841 * Find a wdc_ioctl structure based on the struct buf. 1842 */ 1843 1844 struct wdc_ioctl * 1845 wdc_ioctl_find(bp) 1846 struct buf *bp; 1847 { 1848 struct wdc_ioctl *wi; 1849 int s; 1850 1851 s = splbio(); 1852 for (wi = wi_head.lh_first; wi != 0; wi = wi->wi_list.le_next) 1853 if (bp == &wi->wi_bp) 1854 break; 1855 splx(s); 1856 return (wi); 1857 } 1858 1859 /* 1860 * Ioctl pseudo strategy routine 1861 * 1862 * This is mostly stolen from scsipi_ioctl.c:scsistrategy(). What 1863 * happens here is: 1864 * 1865 * - wdioctl() queues a wdc_ioctl structure. 1866 * 1867 * - wdioctl() calls physio/wdc_ioctl_strategy based on whether or not 1868 * user space I/O is required. If physio() is called, physio() eventually 1869 * calls wdc_ioctl_strategy(). 1870 * 1871 * - In either case, wdc_ioctl_strategy() calls wdc_exec_command() 1872 * to perform the actual command 1873 * 1874 * The reason for the use of the pseudo strategy routine is because 1875 * when doing I/O to/from user space, physio _really_ wants to be in 1876 * the loop. We could put the entire buffer into the ioctl request 1877 * structure, but that won't scale if we want to do things like download 1878 * microcode. 1879 */ 1880 1881 void 1882 wdc_ioctl_strategy(bp) 1883 struct buf *bp; 1884 { 1885 struct wdc_ioctl *wi; 1886 struct wdc_command wdc_c; 1887 int error = 0; 1888 1889 wi = wdc_ioctl_find(bp); 1890 if (wi == NULL) { 1891 printf("user_strat: No ioctl\n"); 1892 error = EINVAL; 1893 goto bad; 1894 } 1895 1896 bzero(&wdc_c, sizeof(wdc_c)); 1897 1898 /* 1899 * Abort if physio broke up the transfer 1900 */ 1901 1902 if (bp->b_bcount != wi->wi_atareq.datalen) { 1903 printf("physio split wd ioctl request... cannot proceed\n"); 1904 error = EIO; 1905 goto bad; 1906 } 1907 1908 /* 1909 * Make sure a timeout was supplied in the ioctl request 1910 */ 1911 1912 if (wi->wi_atareq.timeout == 0) { 1913 error = EINVAL; 1914 goto bad; 1915 } 1916 1917 if (wi->wi_atareq.flags & ATACMD_READ) 1918 wdc_c.flags |= AT_READ; 1919 else if (wi->wi_atareq.flags & ATACMD_WRITE) 1920 wdc_c.flags |= AT_WRITE; 1921 1922 if (wi->wi_atareq.flags & ATACMD_READREG) 1923 wdc_c.flags |= AT_READREG; 1924 1925 wdc_c.flags |= AT_WAIT; 1926 1927 wdc_c.timeout = wi->wi_atareq.timeout; 1928 wdc_c.r_command = wi->wi_atareq.command; 1929 wdc_c.r_head = wi->wi_atareq.head & 0x0f; 1930 wdc_c.r_cyl = wi->wi_atareq.cylinder; 1931 wdc_c.r_sector = wi->wi_atareq.sec_num; 1932 wdc_c.r_count = wi->wi_atareq.sec_count; 1933 wdc_c.r_precomp = wi->wi_atareq.features; 1934 if (wi->wi_drvp->drive_flags & DRIVE_ATAPI) { 1935 wdc_c.r_st_bmask = 0; 1936 wdc_c.r_st_pmask = 0; 1937 if (wdc_c.r_command == WDCC_IDENTIFY) 1938 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 1939 } else { 1940 wdc_c.r_st_bmask = WDCS_DRDY; 1941 wdc_c.r_st_pmask = WDCS_DRDY; 1942 } 1943 wdc_c.data = wi->wi_bp.b_data; 1944 wdc_c.bcount = wi->wi_bp.b_bcount; 1945 1946 if (wdc_exec_command(wi->wi_drvp, &wdc_c) != WDC_COMPLETE) { 1947 wi->wi_atareq.retsts = ATACMD_ERROR; 1948 goto bad; 1949 } 1950 1951 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 1952 if (wdc_c.flags & AT_ERROR) { 1953 wi->wi_atareq.retsts = ATACMD_ERROR; 1954 wi->wi_atareq.error = wdc_c.r_error; 1955 } else if (wdc_c.flags & AT_DF) 1956 wi->wi_atareq.retsts = ATACMD_DF; 1957 else 1958 wi->wi_atareq.retsts = ATACMD_TIMEOUT; 1959 } else { 1960 wi->wi_atareq.retsts = ATACMD_OK; 1961 if (wi->wi_atareq.flags & ATACMD_READREG) { 1962 wi->wi_atareq.head = wdc_c.r_head ; 1963 wi->wi_atareq.cylinder = wdc_c.r_cyl; 1964 wi->wi_atareq.sec_num = wdc_c.r_sector; 1965 wi->wi_atareq.sec_count = wdc_c.r_count; 1966 wi->wi_atareq.features = wdc_c.r_precomp; 1967 wi->wi_atareq.error = wdc_c.r_error; 1968 } 1969 } 1970 1971 bp->b_error = 0; 1972 biodone(bp); 1973 return; 1974 bad: 1975 bp->b_flags |= B_ERROR; 1976 bp->b_error = error; 1977 biodone(bp); 1978 } 1979 1980 int 1981 wdc_ioctl(drvp, xfer, addr, flag) 1982 struct ata_drive_datas *drvp; 1983 u_long xfer; 1984 caddr_t addr; 1985 int flag; 1986 { 1987 int error = 0; 1988 1989 switch (xfer) { 1990 case ATAIOCCOMMAND: 1991 /* 1992 * Make sure this command is (relatively) safe first 1993 */ 1994 if ((((atareq_t *) addr)->flags & ATACMD_READ) == 0 && 1995 (flag & FWRITE) == 0) { 1996 error = EBADF; 1997 goto exit; 1998 } 1999 { 2000 struct wdc_ioctl *wi; 2001 atareq_t *atareq = (atareq_t *) addr; 2002 2003 wi = wdc_ioctl_get(); 2004 wi->wi_drvp = drvp; 2005 wi->wi_atareq = *atareq; 2006 2007 if (atareq->datalen && atareq->flags & 2008 (ATACMD_READ | ATACMD_WRITE)) { 2009 wi->wi_iov.iov_base = atareq->databuf; 2010 wi->wi_iov.iov_len = atareq->datalen; 2011 wi->wi_uio.uio_iov = &wi->wi_iov; 2012 wi->wi_uio.uio_iovcnt = 1; 2013 wi->wi_uio.uio_resid = atareq->datalen; 2014 wi->wi_uio.uio_offset = 0; 2015 wi->wi_uio.uio_segflg = UIO_USERSPACE; 2016 wi->wi_uio.uio_rw = 2017 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE; 2018 wi->wi_uio.uio_procp = curproc; 2019 error = physio(wdc_ioctl_strategy, &wi->wi_bp, 0, 2020 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE, 2021 minphys, &wi->wi_uio); 2022 } else { 2023 /* No need to call physio if we don't have any 2024 user data */ 2025 wi->wi_bp.b_flags = 0; 2026 wi->wi_bp.b_data = 0; 2027 wi->wi_bp.b_bcount = 0; 2028 wi->wi_bp.b_dev = 0; 2029 wi->wi_bp.b_proc = curproc; 2030 LIST_INIT(&wi->wi_bp.b_dep); 2031 wdc_ioctl_strategy(&wi->wi_bp); 2032 error = wi->wi_bp.b_error; 2033 } 2034 *atareq = wi->wi_atareq; 2035 wdc_ioctl_free(wi); 2036 goto exit; 2037 } 2038 default: 2039 error = ENOTTY; 2040 goto exit; 2041 } 2042 2043 exit: 2044 return (error); 2045 } 2046