1 /* $OpenBSD: wdc.c,v 1.102 2009/02/07 08:07:28 grange Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/conf.h> 65 #include <sys/buf.h> 66 #include <sys/device.h> 67 #include <sys/malloc.h> 68 #include <sys/syslog.h> 69 #include <sys/proc.h> 70 #include <sys/pool.h> 71 #include <uvm/uvm_extern.h> 72 73 #include <machine/intr.h> 74 #include <machine/bus.h> 75 76 #include <dev/ata/atavar.h> 77 #include <dev/ata/atareg.h> 78 #include <dev/ic/wdcreg.h> 79 #include <dev/ic/wdcvar.h> 80 #include <dev/ic/wdcevent.h> 81 82 #include "atapiscsi.h" 83 84 #define WDCDELAY 100 /* 100 microseconds */ 85 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 86 #if 0 87 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 88 #define WDCNDELAY_DEBUG 50 89 #endif /* 0 */ 90 91 struct pool wdc_xfer_pool; 92 93 void __wdcerror(struct channel_softc *, char *); 94 int __wdcwait_reset(struct channel_softc *, int); 95 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *); 96 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *); 97 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int); 98 int wdprint(void *, const char *); 99 void wdc_kill_pending(struct channel_softc *); 100 101 #define DEBUG_INTR 0x01 102 #define DEBUG_XFERS 0x02 103 #define DEBUG_STATUS 0x04 104 #define DEBUG_FUNCS 0x08 105 #define DEBUG_PROBE 0x10 106 #define DEBUG_STATUSX 0x20 107 #define DEBUG_SDRIVE 0x40 108 #define DEBUG_DETACH 0x80 109 110 #ifdef WDCDEBUG 111 #ifndef WDCDEBUG_MASK 112 #define WDCDEBUG_MASK 0x00 113 #endif 114 int wdcdebug_mask = WDCDEBUG_MASK; 115 int wdc_nxfer = 0; 116 #define WDCDEBUG_PRINT(args, level) do { \ 117 if ((wdcdebug_mask & (level)) != 0) \ 118 printf args; \ 119 } while (0) 120 #else 121 #define WDCDEBUG_PRINT(args, level) 122 #endif /* WDCDEBUG */ 123 124 int at_poll = AT_POLL; 125 126 int wdc_floating_bus(struct channel_softc *, int); 127 int wdc_preata_drive(struct channel_softc *, int); 128 int wdc_ata_present(struct channel_softc *, int); 129 130 struct channel_softc_vtbl wdc_default_vtbl = { 131 wdc_default_read_reg, 132 wdc_default_write_reg, 133 wdc_default_lba48_write_reg, 134 wdc_default_read_raw_multi_2, 135 wdc_default_write_raw_multi_2, 136 wdc_default_read_raw_multi_4, 137 wdc_default_write_raw_multi_4 138 }; 139 140 #ifdef WDCDEBUG 141 static char *wdc_log_buf = NULL; 142 static unsigned int wdc_tail = 0; 143 static unsigned int wdc_head = 0; 144 static unsigned int wdc_log_cap = 16 * 1024; 145 static int chp_idx = 1; 146 147 void 148 wdc_log(struct channel_softc *chp, enum wdcevent_type type, 149 unsigned int size, char val[]) 150 { 151 unsigned int request_size; 152 char *ptr; 153 int log_size; 154 unsigned int head = wdc_head; 155 unsigned int tail = wdc_tail; 156 157 #ifdef DIAGNOSTIC 158 if (head < 0 || head > wdc_log_cap || 159 tail < 0 || tail > wdc_log_cap) { 160 printf ("wdc_log: head %x wdc_tail %x\n", head, 161 tail); 162 return; 163 } 164 165 if (size > wdc_log_cap / 2) { 166 printf ("wdc_log: type %d size %x\n", type, size); 167 return; 168 } 169 #endif 170 171 if (wdc_log_buf == NULL) { 172 wdc_log_buf = malloc(wdc_log_cap, M_DEVBUF, M_NOWAIT); 173 if (wdc_log_buf == NULL) 174 return; 175 } 176 if (chp->ch_log_idx == 0) 177 chp->ch_log_idx = chp_idx++; 178 179 request_size = size + 2; 180 181 /* Check how many bytes are left */ 182 log_size = head - tail; 183 if (log_size < 0) log_size += wdc_log_cap; 184 185 if (log_size + request_size >= wdc_log_cap) { 186 int nb = 0; 187 int rec_size; 188 189 while (nb <= (request_size * 2)) { 190 if (wdc_log_buf[tail] == 0) 191 rec_size = 1; 192 else 193 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 194 tail = (tail + rec_size) % wdc_log_cap; 195 nb += rec_size; 196 } 197 } 198 199 /* Avoid wrapping in the middle of a request */ 200 if (head + request_size >= wdc_log_cap) { 201 memset(&wdc_log_buf[head], 0, wdc_log_cap - head); 202 head = 0; 203 } 204 205 ptr = &wdc_log_buf[head]; 206 *ptr++ = type & 0xff; 207 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f); 208 memcpy(ptr, val, size); 209 210 wdc_head = (head + request_size) % wdc_log_cap; 211 wdc_tail = tail; 212 } 213 214 char *wdc_get_log(unsigned int *, unsigned int *); 215 216 char * 217 wdc_get_log(unsigned int * size, unsigned int *left) 218 { 219 int log_size; 220 char *retbuf = NULL; 221 int nb, tocopy; 222 int s; 223 unsigned int head = wdc_head; 224 unsigned int tail = wdc_tail; 225 226 s = splbio(); 227 228 log_size = (head - tail); 229 if (left != NULL) 230 *left = 0; 231 232 if (log_size < 0) 233 log_size += wdc_log_cap; 234 235 tocopy = log_size; 236 if ((u_int)tocopy > *size) 237 tocopy = *size; 238 239 if (wdc_log_buf == NULL) { 240 *size = 0; 241 *left = 0; 242 goto out; 243 } 244 245 #ifdef DIAGNOSTIC 246 if (head < 0 || head > wdc_log_cap || 247 tail < 0 || tail > wdc_log_cap) { 248 printf ("wdc_log: head %x tail %x\n", head, 249 tail); 250 *size = 0; 251 *left = 0; 252 goto out; 253 } 254 #endif 255 256 retbuf = malloc(tocopy, M_TEMP, M_NOWAIT); 257 if (retbuf == NULL) { 258 *size = 0; 259 *left = log_size; 260 goto out; 261 } 262 263 nb = 0; 264 for (;;) { 265 int rec_size; 266 267 if (wdc_log_buf[tail] == 0) 268 rec_size = 1; 269 else 270 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 271 272 if ((nb + rec_size) >= tocopy) 273 break; 274 275 memcpy(&retbuf[nb], &wdc_log_buf[tail], rec_size); 276 tail = (tail + rec_size) % wdc_log_cap; 277 nb += rec_size; 278 } 279 280 wdc_tail = tail; 281 *size = nb; 282 *left = log_size - nb; 283 284 out: 285 splx(s); 286 return (retbuf); 287 } 288 #endif /* WDCDEBUG */ 289 290 u_int8_t 291 wdc_default_read_reg(chp, reg) 292 struct channel_softc *chp; 293 enum wdc_regs reg; 294 { 295 #ifdef DIAGNOSTIC 296 if (reg & _WDC_WRONLY) { 297 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 298 } 299 #endif /* DIAGNOSTIC */ 300 301 if (reg & _WDC_AUX) 302 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 303 reg & _WDC_REGMASK)); 304 else 305 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 306 reg & _WDC_REGMASK)); 307 } 308 309 void 310 wdc_default_write_reg(chp, reg, val) 311 struct channel_softc *chp; 312 enum wdc_regs reg; 313 u_int8_t val; 314 { 315 #ifdef DIAGNOSTIC 316 if (reg & _WDC_RDONLY) { 317 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 318 } 319 #endif /* DIAGNOSTIC */ 320 321 if (reg & _WDC_AUX) 322 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 323 reg & _WDC_REGMASK, val); 324 else 325 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 326 reg & _WDC_REGMASK, val); 327 } 328 329 void 330 wdc_default_lba48_write_reg(chp, reg, val) 331 struct channel_softc *chp; 332 enum wdc_regs reg; 333 u_int16_t val; 334 { 335 /* All registers are two byte deep FIFOs. */ 336 CHP_WRITE_REG(chp, reg, val >> 8); 337 CHP_WRITE_REG(chp, reg, val); 338 } 339 340 void 341 wdc_default_read_raw_multi_2(chp, data, nbytes) 342 struct channel_softc *chp; 343 void *data; 344 unsigned int nbytes; 345 { 346 if (data == NULL) { 347 unsigned int i; 348 349 for (i = 0; i < nbytes; i += 2) { 350 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 351 } 352 353 return; 354 } 355 356 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 357 data, nbytes); 358 } 359 360 361 void 362 wdc_default_write_raw_multi_2(chp, data, nbytes) 363 struct channel_softc *chp; 364 void *data; 365 unsigned int nbytes; 366 { 367 if (data == NULL) { 368 unsigned int i; 369 370 for (i = 0; i < nbytes; i += 2) { 371 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 372 } 373 374 return; 375 } 376 377 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 378 data, nbytes); 379 } 380 381 382 void 383 wdc_default_write_raw_multi_4(chp, data, nbytes) 384 struct channel_softc *chp; 385 void *data; 386 unsigned int nbytes; 387 { 388 if (data == NULL) { 389 unsigned int i; 390 391 for (i = 0; i < nbytes; i += 4) { 392 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 393 } 394 395 return; 396 } 397 398 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 399 data, nbytes); 400 } 401 402 403 void 404 wdc_default_read_raw_multi_4(chp, data, nbytes) 405 struct channel_softc *chp; 406 void *data; 407 unsigned int nbytes; 408 { 409 if (data == NULL) { 410 unsigned int i; 411 412 for (i = 0; i < nbytes; i += 4) { 413 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 414 } 415 416 return; 417 } 418 419 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 420 data, nbytes); 421 } 422 423 424 int 425 wdprint(aux, pnp) 426 void *aux; 427 const char *pnp; 428 { 429 struct ata_atapi_attach *aa_link = aux; 430 if (pnp) 431 printf("drive at %s", pnp); 432 printf(" channel %d drive %d", aa_link->aa_channel, 433 aa_link->aa_drv_data->drive); 434 return (UNCONF); 435 } 436 437 void 438 wdc_disable_intr(chp) 439 struct channel_softc *chp; 440 { 441 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 442 } 443 444 void 445 wdc_enable_intr(chp) 446 struct channel_softc *chp; 447 { 448 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 449 } 450 451 void 452 wdc_set_drive(struct channel_softc *chp, int drive) 453 { 454 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM); 455 WDC_LOG_SET_DRIVE(chp, drive); 456 } 457 458 int 459 wdc_floating_bus(chp, drive) 460 struct channel_softc *chp; 461 int drive; 462 463 { 464 u_int8_t cumulative_status, status; 465 int iter; 466 467 wdc_set_drive(chp, drive); 468 delay(10); 469 470 /* Stolen from Phoenix BIOS Drive Autotyping document */ 471 cumulative_status = 0; 472 for (iter = 0; iter < 100; iter++) { 473 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 474 delay (1); 475 476 status = CHP_READ_REG(chp, wdr_status); 477 478 /* The other bits are meaningless if BSY is set */ 479 if (status & WDCS_BSY) 480 continue; 481 482 cumulative_status |= status; 483 484 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 485 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 486 return 1; 487 } 488 489 490 return 0; 491 } 492 493 494 int 495 wdc_preata_drive(chp, drive) 496 struct channel_softc *chp; 497 int drive; 498 499 { 500 if (wdc_floating_bus(chp, drive)) { 501 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 502 chp->wdc->sc_dev.dv_xname, 503 chp->channel, drive), DEBUG_PROBE); 504 return 0; 505 } 506 507 wdc_set_drive(chp, drive); 508 delay(100); 509 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 510 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 511 chp->wdc->sc_dev.dv_xname, 512 chp->channel, drive), DEBUG_PROBE); 513 return 0; 514 } 515 516 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 517 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL); 518 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 519 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 520 chp->wdc->sc_dev.dv_xname, 521 chp->channel, drive), DEBUG_PROBE); 522 return 0; 523 } 524 525 return 1; 526 } 527 528 int 529 wdc_ata_present(chp, drive) 530 struct channel_softc *chp; 531 int drive; 532 { 533 int time_to_done; 534 int retry_cnt = 0; 535 536 wdc_set_drive(chp, drive); 537 delay(10); 538 539 retry: 540 /* 541 You're actually supposed to wait up to 10 seconds 542 for DRDY. However, as a practical matter, most 543 drives assert DRDY very quickly after dropping BSY. 544 545 The 10 seconds wait is sub-optimal because, according 546 to the ATA standard, the master should reply with 00 547 for any reads to a non-existent slave. 548 */ 549 time_to_done = wdc_wait_for_status(chp, 550 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 551 (WDCS_DRDY | WDCS_DSC), 1000); 552 if (time_to_done == -1) { 553 if (retry_cnt == 0 && chp->ch_status == 0x00) { 554 /* At least one flash card needs to be kicked */ 555 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 556 retry_cnt++; 557 goto retry; 558 } 559 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 560 " %02x\n", 561 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 562 chp->channel, drive, chp->ch_status), 563 DEBUG_PROBE); 564 return 0; 565 } 566 567 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 568 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 569 " %02x\n", 570 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 571 chp->channel, drive, chp->ch_status), 572 DEBUG_PROBE); 573 574 return 0; 575 } 576 577 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 578 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 579 chp->channel, drive, time_to_done), DEBUG_PROBE); 580 581 /* 582 * Test register writability 583 */ 584 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 585 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 586 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 587 DELAY(10); 588 589 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 590 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 591 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 592 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 593 chp->channel, drive), DEBUG_PROBE); 594 return 0; 595 } 596 597 return 1; 598 } 599 600 601 /* 602 * Test to see controller with at least one attached drive is there. 603 * Returns a bit for each possible drive found (0x01 for drive 0, 604 * 0x02 for drive 1). 605 * Logic: 606 * - If a status register is at 0x7f or 0xff, assume there is no drive here 607 * (ISA has pull-up resistors). Similarly if the status register has 608 * the value we last wrote to the bus (for IDE interfaces without pullups). 609 * If no drive at all -> return. 610 * - reset the controller, wait for it to complete (may take up to 31s !). 611 * If timeout -> return. 612 * - test ATA/ATAPI signatures. If at last one drive found -> return. 613 * - try an ATA command on the master. 614 */ 615 616 int 617 wdcprobe(chp) 618 struct channel_softc *chp; 619 { 620 u_int8_t st0, st1, sc, sn, cl, ch; 621 u_int8_t ret_value = 0x03; 622 u_int8_t drive; 623 #ifdef WDCDEBUG 624 int savedmask = wdcdebug_mask; 625 #endif 626 627 if (chp->_vtbl == 0) { 628 int s = splbio(); 629 chp->_vtbl = &wdc_default_vtbl; 630 splx(s); 631 } 632 633 #ifdef WDCDEBUG 634 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 635 (chp->wdc && 636 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 637 wdcdebug_mask |= DEBUG_PROBE; 638 #endif /* WDCDEBUG */ 639 640 if (chp->wdc == NULL || 641 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 642 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 643 wdc_set_drive(chp, 0); 644 delay(10); 645 st0 = CHP_READ_REG(chp, wdr_status); 646 WDC_LOG_STATUS(chp, st0); 647 wdc_set_drive(chp, 1); 648 delay(10); 649 st1 = CHP_READ_REG(chp, wdr_status); 650 WDC_LOG_STATUS(chp, st1); 651 652 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%b, st1=0x%b\n", 653 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 654 chp->channel, st0, WDCS_BITS, st1, WDCS_BITS), 655 DEBUG_PROBE); 656 657 if (st0 == 0xff || st0 == WDSD_IBM) 658 ret_value &= ~0x01; 659 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 660 ret_value &= ~0x02; 661 if (ret_value == 0) 662 return 0; 663 } 664 665 /* reset the channel */ 666 wdc_do_reset(chp); 667 668 ret_value = __wdcwait_reset(chp, ret_value); 669 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 670 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 671 ret_value), DEBUG_PROBE); 672 673 if (ret_value == 0) 674 return 0; 675 676 /* 677 * Use signatures to find potential ATAPI drives 678 */ 679 for (drive = 0; drive < 2; drive++) { 680 if ((ret_value & (0x01 << drive)) == 0) 681 continue; 682 wdc_set_drive(chp, drive); 683 delay(10); 684 /* Save registers contents */ 685 st0 = CHP_READ_REG(chp, wdr_status); 686 sc = CHP_READ_REG(chp, wdr_seccnt); 687 sn = CHP_READ_REG(chp, wdr_sector); 688 cl = CHP_READ_REG(chp, wdr_cyl_lo); 689 ch = CHP_READ_REG(chp, wdr_cyl_hi); 690 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl); 691 692 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%b, sc=0x%x" 693 " sn=0x%x cl=0x%x ch=0x%x\n", 694 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 695 chp->channel, drive, st0, WDCS_BITS, sc, sn, cl, ch), 696 DEBUG_PROBE); 697 /* 698 * This is a simplification of the test in the ATAPI 699 * spec since not all drives seem to set the other regs 700 * correctly. 701 */ 702 if (cl == 0x14 && ch == 0xeb) 703 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 704 } 705 706 /* 707 * Detect ATA drives by poking around the registers 708 */ 709 for (drive = 0; drive < 2; drive++) { 710 if ((ret_value & (0x01 << drive)) == 0) 711 continue; 712 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 713 continue; 714 715 wdc_disable_intr(chp); 716 /* ATA detect */ 717 if (wdc_ata_present(chp, drive)) { 718 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 719 if (chp->wdc == NULL || 720 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 721 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 722 } else { 723 ret_value &= ~(1 << drive); 724 } 725 wdc_enable_intr(chp); 726 } 727 728 #ifdef WDCDEBUG 729 wdcdebug_mask = savedmask; 730 #endif 731 return (ret_value); 732 } 733 734 /* 735 * Call activate routine of underlying devices. 736 */ 737 int 738 wdcactivate(self, act) 739 struct device *self; 740 enum devact act; 741 { 742 int error = 0; 743 int s; 744 745 s = splbio(); 746 config_activate_children(self, act); 747 splx(s); 748 749 return (error); 750 } 751 752 void 753 wdcattach(chp) 754 struct channel_softc *chp; 755 { 756 int channel_flags, ctrl_flags, i; 757 struct ata_atapi_attach aa_link; 758 static int inited = 0; 759 #ifdef WDCDEBUG 760 int savedmask = wdcdebug_mask; 761 #endif 762 763 if (!cold) 764 at_poll = AT_WAIT; 765 766 if (chp->wdc->reset == NULL) 767 chp->wdc->reset = wdc_do_reset; 768 769 timeout_set(&chp->ch_timo, wdctimeout, chp); 770 771 if (!chp->_vtbl) 772 chp->_vtbl = &wdc_default_vtbl; 773 774 if (chp->wdc->drv_probe != NULL) { 775 chp->wdc->drv_probe(chp); 776 } else { 777 if (wdcprobe(chp) == 0) 778 /* If no drives, abort attach here. */ 779 return; 780 } 781 782 /* ATAPI drives need settling time. Give them 250ms */ 783 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 784 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 785 delay(250 * 1000); 786 } 787 788 #ifdef WDCDEBUG 789 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 790 wdcdebug_mask |= DEBUG_PROBE; 791 792 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 793 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 794 wdcdebug_mask = DEBUG_PROBE; 795 } 796 #endif /* WDCDEBUG */ 797 798 /* initialise global data */ 799 if (inited == 0) { 800 /* Initialize the wdc_xfer pool. */ 801 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 802 0, 0, "wdcspl", NULL); 803 inited++; 804 } 805 TAILQ_INIT(&chp->ch_queue->sc_xfer); 806 807 for (i = 0; i < 2; i++) { 808 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 809 810 drvp->chnl_softc = chp; 811 drvp->drive = i; 812 /* If controller can't do 16bit flag the drives as 32bit */ 813 if ((chp->wdc->cap & 814 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 815 WDC_CAPABILITY_DATA32) 816 drvp->drive_flags |= DRIVE_CAP32; 817 818 if ((drvp->drive_flags & DRIVE) == 0) 819 continue; 820 821 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 822 chp->ch_flags |= WDCF_ONESLAVE; 823 /* 824 * Wait a bit, some devices are weird just after a reset. 825 * Then issue a IDENTIFY command, to try to detect slave ghost. 826 */ 827 delay(5000); 828 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 829 CMD_OK) { 830 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 831 drvp->drive_flags &= ~DRIVE_OLD; 832 } else { 833 bzero(&drvp->id, sizeof(struct ataparams)); 834 drvp->drive_flags &= 835 ~(DRIVE_ATA | DRIVE_ATAPI); 836 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 837 chp->wdc->sc_dev.dv_xname, 838 chp->channel, i), DEBUG_PROBE); 839 840 if ((drvp->drive_flags & DRIVE_OLD) && 841 !wdc_preata_drive(chp, i)) 842 drvp->drive_flags &= ~DRIVE_OLD; 843 } 844 } 845 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 846 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 847 848 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 849 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 850 DEBUG_PROBE); 851 852 /* If no drives, abort here */ 853 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 854 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 855 goto exit; 856 857 for (i = 0; i < 2; i++) { 858 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 859 continue; 860 } 861 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 862 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 863 aa_link.aa_type = T_ATAPI; 864 else 865 aa_link.aa_type = T_ATA; 866 aa_link.aa_channel = chp->channel; 867 aa_link.aa_openings = 1; 868 aa_link.aa_drv_data = &chp->ch_drive[i]; 869 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 870 } 871 872 /* 873 * reset drive_flags for unattached devices, reset state for attached 874 * ones 875 */ 876 for (i = 0; i < 2; i++) { 877 if (chp->ch_drive[i].drive_name[0] == 0) 878 chp->ch_drive[i].drive_flags = 0; 879 } 880 881 exit: 882 #ifdef WDCDEBUG 883 wdcdebug_mask = savedmask; 884 #endif 885 return; /* for the ``exit'' label above */ 886 } 887 888 /* 889 * Start I/O on a controller, for the given channel. 890 * The first xfer may be not for our channel if the channel queues 891 * are shared. 892 */ 893 void 894 wdcstart(chp) 895 struct channel_softc *chp; 896 { 897 struct wdc_xfer *xfer; 898 899 splassert(IPL_BIO); 900 901 /* is there a xfer ? */ 902 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) { 903 return; 904 } 905 906 /* adjust chp, in case we have a shared queue */ 907 chp = xfer->chp; 908 909 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 910 return; /* channel already active */ 911 } 912 #ifdef DIAGNOSTIC 913 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 914 panic("wdcstart: channel waiting for irq"); 915 #endif /* DIAGNOSTIC */ 916 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 917 if (!(chp->wdc->claim_hw)(chp, 0)) 918 return; 919 920 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 921 chp->channel, xfer->drive), DEBUG_XFERS); 922 chp->ch_flags |= WDCF_ACTIVE; 923 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 924 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 925 chp->ch_drive[xfer->drive].state = 0; 926 } 927 xfer->c_start(chp, xfer); 928 } 929 930 int 931 wdcdetach(chp, flags) 932 struct channel_softc *chp; 933 int flags; 934 { 935 int s, rv; 936 937 s = splbio(); 938 wdc_kill_pending(chp); 939 940 rv = config_detach_children((struct device *)chp->wdc, flags); 941 splx(s); 942 943 return (rv); 944 } 945 946 /* 947 * Interrupt routine for the controller. Acknowledge the interrupt, check for 948 * errors on the current operation, mark it done if necessary, and start the 949 * next request. Also check for a partially done transfer, and continue with 950 * the next chunk if so. 951 */ 952 int 953 wdcintr(arg) 954 void *arg; 955 { 956 struct channel_softc *chp = arg; 957 struct wdc_xfer *xfer; 958 int ret; 959 960 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 961 /* Acknowledge interrupt by reading status */ 962 if (chp->_vtbl == 0) { 963 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 964 wdr_status & _WDC_REGMASK); 965 } else { 966 CHP_READ_REG(chp, wdr_status); 967 } 968 969 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 970 return 0; 971 } 972 973 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 974 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 975 if (chp->ch_flags & WDCF_DMA_WAIT) { 976 chp->wdc->dma_status = 977 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 978 xfer->drive, 0); 979 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 980 /* IRQ not for us, not detected by DMA engine */ 981 return 0; 982 } 983 chp->ch_flags &= ~WDCF_DMA_WAIT; 984 } 985 chp->ch_flags &= ~WDCF_IRQ_WAIT; 986 ret = xfer->c_intr(chp, xfer, 1); 987 if (ret == 0) /* irq was not for us, still waiting for irq */ 988 chp->ch_flags |= WDCF_IRQ_WAIT; 989 return (ret); 990 } 991 992 /* Put all disk in RESET state */ 993 void wdc_reset_channel(drvp) 994 struct ata_drive_datas *drvp; 995 { 996 struct channel_softc *chp = drvp->chnl_softc; 997 int drive; 998 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 999 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1000 DEBUG_FUNCS); 1001 (void) wdcreset(chp, VERBOSE); 1002 for (drive = 0; drive < 2; drive++) { 1003 chp->ch_drive[drive].state = 0; 1004 } 1005 } 1006 1007 int 1008 wdcreset(chp, verb) 1009 struct channel_softc *chp; 1010 int verb; 1011 { 1012 int drv_mask1, drv_mask2; 1013 1014 if (!chp->_vtbl) 1015 chp->_vtbl = &wdc_default_vtbl; 1016 1017 chp->wdc->reset(chp); 1018 1019 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1020 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1021 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 1022 if (verb && drv_mask2 != drv_mask1) { 1023 printf("%s channel %d: reset failed for", 1024 chp->wdc->sc_dev.dv_xname, chp->channel); 1025 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1026 printf(" drive 0"); 1027 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1028 printf(" drive 1"); 1029 printf("\n"); 1030 } 1031 1032 return (drv_mask1 != drv_mask2) ? 1 : 0; 1033 } 1034 1035 void 1036 wdc_do_reset(struct channel_softc *chp) 1037 { 1038 wdc_set_drive(chp, 0); 1039 DELAY(10); 1040 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT | WDCTL_RST); 1041 delay(10000); 1042 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 1043 delay(10000); 1044 } 1045 1046 int 1047 __wdcwait_reset(chp, drv_mask) 1048 struct channel_softc *chp; 1049 int drv_mask; 1050 { 1051 int timeout; 1052 u_int8_t st0, er0, st1, er1; 1053 1054 /* wait for BSY to deassert */ 1055 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 1056 wdc_set_drive(chp, 0); 1057 delay(10); 1058 st0 = CHP_READ_REG(chp, wdr_status); 1059 er0 = CHP_READ_REG(chp, wdr_error); 1060 wdc_set_drive(chp, 1); 1061 delay(10); 1062 st1 = CHP_READ_REG(chp, wdr_status); 1063 er1 = CHP_READ_REG(chp, wdr_error); 1064 1065 if ((drv_mask & 0x01) == 0) { 1066 /* no master */ 1067 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1068 /* No master, slave is ready, it's done */ 1069 goto end; 1070 } 1071 } else if ((drv_mask & 0x02) == 0) { 1072 /* no slave */ 1073 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1074 /* No slave, master is ready, it's done */ 1075 goto end; 1076 } 1077 } else { 1078 /* Wait for both master and slave to be ready */ 1079 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1080 goto end; 1081 } 1082 } 1083 delay(WDCDELAY); 1084 } 1085 /* Reset timed out. Maybe it's because drv_mask was not right */ 1086 if (st0 & WDCS_BSY) 1087 drv_mask &= ~0x01; 1088 if (st1 & WDCS_BSY) 1089 drv_mask &= ~0x02; 1090 end: 1091 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%b, er0=0x%x, " 1092 "st1=0x%b, er1=0x%x, reset time=%d msec\n", 1093 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1094 st0, WDCS_BITS, er0, st1, WDCS_BITS, er1, 1095 timeout * WDCDELAY / 1000), DEBUG_PROBE); 1096 1097 return drv_mask; 1098 } 1099 1100 /* 1101 * Wait for a drive to be !BSY, and have mask in its status register. 1102 * return -1 for a timeout after "timeout" ms. 1103 */ 1104 int 1105 wdc_wait_for_status(chp, mask, bits, timeout) 1106 struct channel_softc *chp; 1107 int mask, bits, timeout; 1108 { 1109 u_char status; 1110 int time = 0; 1111 1112 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1113 :"none", chp->channel), DEBUG_STATUS); 1114 chp->ch_error = 0; 1115 1116 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1117 1118 for (;;) { 1119 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 1120 WDC_LOG_STATUS(chp, chp->ch_status); 1121 1122 if (status == 0xff && (chp->ch_flags & WDCF_ONESLAVE)) { 1123 wdc_set_drive(chp, 1); 1124 chp->ch_status = status = 1125 CHP_READ_REG(chp, wdr_status); 1126 WDC_LOG_STATUS(chp, chp->ch_status); 1127 } 1128 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 1129 break; 1130 if (++time > timeout) { 1131 WDCDEBUG_PRINT(("wdcwait: timeout, status 0x%b " 1132 "error 0x%x\n", status, WDCS_BITS, 1133 CHP_READ_REG(chp, wdr_error)), 1134 DEBUG_STATUSX | DEBUG_STATUS); 1135 return -1; 1136 } 1137 delay(WDCDELAY); 1138 } 1139 if (status & WDCS_ERR) { 1140 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1141 WDC_LOG_ERROR(chp, chp->ch_error); 1142 1143 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1144 DEBUG_STATUSX | DEBUG_STATUS); 1145 } 1146 1147 #ifdef WDCNDELAY_DEBUG 1148 /* After autoconfig, there should be no long delays. */ 1149 if (!cold && time > WDCNDELAY_DEBUG) { 1150 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1151 if (xfer == NULL) 1152 printf("%s channel %d: warning: busy-wait took %dus\n", 1153 chp->wdc->sc_dev.dv_xname, chp->channel, 1154 WDCDELAY * time); 1155 else 1156 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1157 chp->wdc->sc_dev.dv_xname, chp->channel, 1158 xfer->drive, 1159 WDCDELAY * time); 1160 } 1161 #endif /* WDCNDELAY_DEBUG */ 1162 return time; 1163 } 1164 1165 /* 1166 * Busy-wait for DMA to complete 1167 */ 1168 int 1169 wdc_dmawait(chp, xfer, timeout) 1170 struct channel_softc *chp; 1171 struct wdc_xfer *xfer; 1172 int timeout; 1173 { 1174 int time; 1175 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1176 chp->wdc->dma_status = 1177 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1178 chp->channel, xfer->drive, 0); 1179 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1180 return 0; 1181 delay(WDCDELAY); 1182 } 1183 /* timeout, force a DMA halt */ 1184 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1185 chp->channel, xfer->drive, 1); 1186 return 1; 1187 } 1188 1189 void 1190 wdctimeout(arg) 1191 void *arg; 1192 { 1193 struct channel_softc *chp = (struct channel_softc *)arg; 1194 struct wdc_xfer *xfer; 1195 int s; 1196 1197 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1198 1199 s = splbio(); 1200 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1201 1202 /* Did we lose a race with the interrupt? */ 1203 if (xfer == NULL || 1204 !timeout_triggered(&chp->ch_timo)) { 1205 splx(s); 1206 return; 1207 } 1208 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1209 __wdcerror(chp, "timeout"); 1210 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1211 "atapi":"ata"); 1212 printf("\tc_bcount: %d\n", xfer->c_bcount); 1213 printf("\tc_skip: %d\n", xfer->c_skip); 1214 if (chp->ch_flags & WDCF_DMA_WAIT) { 1215 chp->wdc->dma_status = 1216 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1217 chp->channel, xfer->drive, 1); 1218 chp->ch_flags &= ~WDCF_DMA_WAIT; 1219 } 1220 /* 1221 * Call the interrupt routine. If we just missed and interrupt, 1222 * it will do what's needed. Else, it will take the needed 1223 * action (reset the device). 1224 */ 1225 xfer->c_flags |= C_TIMEOU; 1226 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1227 xfer->c_intr(chp, xfer, 1); 1228 } else 1229 __wdcerror(chp, "missing untimeout"); 1230 splx(s); 1231 } 1232 1233 /* 1234 * Probe drive's capabilities, for use by the controller later. 1235 * Assumes drvp points to an existing drive. 1236 * XXX this should be a controller-indep function 1237 */ 1238 void 1239 wdc_probe_caps(drvp, params) 1240 struct ata_drive_datas *drvp; 1241 struct ataparams *params; 1242 { 1243 struct channel_softc *chp = drvp->chnl_softc; 1244 struct wdc_softc *wdc = chp->wdc; 1245 int i, valid_mode_found; 1246 int cf_flags = drvp->cf_flags; 1247 1248 if ((wdc->cap & WDC_CAPABILITY_SATA) != 0 && 1249 (params->atap_sata_caps != 0x0000 && 1250 params->atap_sata_caps != 0xffff)) { 1251 WDCDEBUG_PRINT(("%s: atap_sata_caps=0x%x\n", __func__, 1252 params->atap_sata_caps), DEBUG_PROBE); 1253 1254 /* Skip ATA modes detection for native SATA drives */ 1255 drvp->PIO_mode = drvp->PIO_cap = 4; 1256 drvp->DMA_mode = drvp->DMA_cap = 2; 1257 drvp->UDMA_mode = drvp->UDMA_cap = 5; 1258 drvp->drive_flags |= DRIVE_SATA | DRIVE_MODE | DRIVE_UDMA; 1259 drvp->ata_vers = 4; 1260 return; 1261 } 1262 1263 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1264 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1265 struct ataparams params2; 1266 1267 /* 1268 * Controller claims 16 and 32 bit transfers. 1269 * Re-do an IDENTIFY with 32-bit transfers, 1270 * and compare results. 1271 */ 1272 drvp->drive_flags |= DRIVE_CAP32; 1273 ata_get_params(drvp, at_poll, ¶ms2); 1274 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1275 /* Not good. fall back to 16bits */ 1276 drvp->drive_flags &= ~DRIVE_CAP32; 1277 } 1278 } 1279 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1280 if (params->atap_ata_major > 0x01 && 1281 params->atap_ata_major != 0xffff) { 1282 for (i = 14; i > 0; i--) { 1283 if (params->atap_ata_major & (1 << i)) { 1284 printf("%sATA version %d\n", sep, i); 1285 drvp->ata_vers = i; 1286 break; 1287 } 1288 } 1289 } else 1290 #endif /* 0 */ 1291 /* Use PIO mode 3 as a default value for ATAPI devices */ 1292 if (drvp->drive_flags & DRIVE_ATAPI) 1293 drvp->PIO_mode = 3; 1294 1295 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap 0x%x cf_flags 0x%x\n", 1296 wdc->cap, cf_flags), DEBUG_PROBE); 1297 1298 valid_mode_found = 0; 1299 1300 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__, 1301 params->atap_oldpiotiming), DEBUG_PROBE); 1302 /* 1303 * ATA-4 compliant devices contain PIO mode 1304 * number in atap_oldpiotiming. 1305 */ 1306 if (params->atap_oldpiotiming <= 2) { 1307 drvp->PIO_cap = params->atap_oldpiotiming; 1308 valid_mode_found = 1; 1309 drvp->drive_flags |= DRIVE_MODE; 1310 } else if (params->atap_oldpiotiming > 180) { 1311 /* 1312 * ATA-2 compliant devices contain cycle 1313 * time in atap_oldpiotiming. 1314 * A device with a cycle time of 180ns 1315 * or less is at least PIO mode 3 and 1316 * should be reporting that in 1317 * atap_piomode_supp, so ignore it here. 1318 */ 1319 if (params->atap_oldpiotiming <= 240) { 1320 drvp->PIO_cap = 2; 1321 } else { 1322 drvp->PIO_cap = 1; 1323 } 1324 valid_mode_found = 1; 1325 drvp->drive_flags |= DRIVE_MODE; 1326 } 1327 if (valid_mode_found) 1328 drvp->PIO_mode = drvp->PIO_cap; 1329 1330 WDCDEBUG_PRINT(("%s: atap_extensions=0x%x, atap_piomode_supp=0x%x, " 1331 "atap_dmamode_supp=0x%x, atap_udmamode_supp=0x%x\n", 1332 __func__, params->atap_extensions, params->atap_piomode_supp, 1333 params->atap_dmamode_supp, params->atap_udmamode_supp), 1334 DEBUG_PROBE); 1335 1336 /* 1337 * It's not in the specs, but it seems that some drive 1338 * returns 0xffff in atap_extensions when this field is invalid 1339 */ 1340 if (params->atap_extensions != 0xffff && 1341 (params->atap_extensions & WDC_EXT_MODES)) { 1342 /* 1343 * XXX some drives report something wrong here (they claim to 1344 * support PIO mode 8 !). As mode is coded on 3 bits in 1345 * SET FEATURE, limit it to 7 (so limit i to 4). 1346 * If higher mode than 7 is found, abort. 1347 */ 1348 for (i = 7; i >= 0; i--) { 1349 if ((params->atap_piomode_supp & (1 << i)) == 0) 1350 continue; 1351 if (i > 4) 1352 return; 1353 1354 valid_mode_found = 1; 1355 1356 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1357 drvp->PIO_cap = i + 3; 1358 continue; 1359 } 1360 1361 /* 1362 * See if mode is accepted. 1363 * If the controller can't set its PIO mode, 1364 * assume the BIOS set it up correctly 1365 */ 1366 if (ata_set_mode(drvp, 0x08 | (i + 3), 1367 at_poll) != CMD_OK) 1368 continue; 1369 1370 /* 1371 * If controller's driver can't set its PIO mode, 1372 * set the highest one the controller supports 1373 */ 1374 if (wdc->PIO_cap >= i + 3) { 1375 drvp->PIO_mode = i + 3; 1376 drvp->PIO_cap = i + 3; 1377 break; 1378 } 1379 } 1380 if (!valid_mode_found) { 1381 /* 1382 * We didn't find a valid PIO mode. 1383 * Assume the values returned for DMA are buggy too 1384 */ 1385 return; 1386 } 1387 drvp->drive_flags |= DRIVE_MODE; 1388 1389 /* Some controllers don't support ATAPI DMA */ 1390 if ((drvp->drive_flags & DRIVE_ATAPI) && 1391 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1392 return; 1393 1394 valid_mode_found = 0; 1395 for (i = 7; i >= 0; i--) { 1396 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1397 continue; 1398 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1399 (wdc->cap & WDC_CAPABILITY_MODE)) 1400 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1401 != CMD_OK) 1402 continue; 1403 1404 valid_mode_found = 1; 1405 1406 if (wdc->cap & WDC_CAPABILITY_DMA) { 1407 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1408 wdc->DMA_cap < i) 1409 continue; 1410 drvp->DMA_mode = i; 1411 drvp->DMA_cap = i; 1412 drvp->drive_flags |= DRIVE_DMA; 1413 } 1414 break; 1415 } 1416 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1417 for (i = 7; i >= 0; i--) { 1418 if ((params->atap_udmamode_supp & (1 << i)) 1419 == 0) 1420 continue; 1421 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1422 (wdc->cap & WDC_CAPABILITY_UDMA)) 1423 if (ata_set_mode(drvp, 0x40 | i, 1424 at_poll) != CMD_OK) 1425 continue; 1426 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1427 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1428 wdc->UDMA_cap < i) 1429 continue; 1430 drvp->UDMA_mode = i; 1431 drvp->UDMA_cap = i; 1432 drvp->drive_flags |= DRIVE_UDMA; 1433 } 1434 break; 1435 } 1436 } 1437 } 1438 1439 /* Try to guess ATA version here, if it didn't get reported */ 1440 if (drvp->ata_vers == 0) { 1441 if (drvp->drive_flags & DRIVE_UDMA) 1442 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1443 else if (drvp->PIO_cap > 2) 1444 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1445 } 1446 if (cf_flags & ATA_CONFIG_PIO_SET) { 1447 drvp->PIO_mode = 1448 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1449 drvp->drive_flags |= DRIVE_MODE; 1450 } 1451 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1452 /* don't care about DMA modes */ 1453 return; 1454 } 1455 if (cf_flags & ATA_CONFIG_DMA_SET) { 1456 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1457 ATA_CONFIG_DMA_DISABLE) { 1458 drvp->drive_flags &= ~DRIVE_DMA; 1459 } else { 1460 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1461 ATA_CONFIG_DMA_OFF; 1462 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1463 } 1464 } 1465 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1466 /* don't care about UDMA modes */ 1467 return; 1468 } 1469 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1470 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1471 ATA_CONFIG_UDMA_DISABLE) { 1472 drvp->drive_flags &= ~DRIVE_UDMA; 1473 } else { 1474 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1475 ATA_CONFIG_UDMA_OFF; 1476 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1477 } 1478 } 1479 } 1480 1481 void 1482 wdc_output_bytes(drvp, bytes, buflen) 1483 struct ata_drive_datas *drvp; 1484 void *bytes; 1485 unsigned int buflen; 1486 { 1487 struct channel_softc *chp = drvp->chnl_softc; 1488 unsigned int off = 0; 1489 unsigned int len = buflen, roundlen; 1490 1491 if (drvp->drive_flags & DRIVE_CAP32) { 1492 roundlen = len & ~3; 1493 1494 CHP_WRITE_RAW_MULTI_4(chp, 1495 (void *)((u_int8_t *)bytes + off), roundlen); 1496 1497 off += roundlen; 1498 len -= roundlen; 1499 } 1500 1501 if (len > 0) { 1502 roundlen = (len + 1) & ~0x1; 1503 1504 CHP_WRITE_RAW_MULTI_2(chp, 1505 (void *)((u_int8_t *)bytes + off), roundlen); 1506 } 1507 } 1508 1509 void 1510 wdc_input_bytes(drvp, bytes, buflen) 1511 struct ata_drive_datas *drvp; 1512 void *bytes; 1513 unsigned int buflen; 1514 { 1515 struct channel_softc *chp = drvp->chnl_softc; 1516 unsigned int off = 0; 1517 unsigned int len = buflen, roundlen; 1518 1519 if (drvp->drive_flags & DRIVE_CAP32) { 1520 roundlen = len & ~3; 1521 1522 CHP_READ_RAW_MULTI_4(chp, 1523 (void *)((u_int8_t *)bytes + off), roundlen); 1524 1525 off += roundlen; 1526 len -= roundlen; 1527 } 1528 1529 if (len > 0) { 1530 roundlen = (len + 1) & ~0x1; 1531 1532 CHP_READ_RAW_MULTI_2(chp, 1533 (void *)((u_int8_t *)bytes + off), roundlen); 1534 } 1535 } 1536 1537 void 1538 wdc_print_caps(drvp) 1539 struct ata_drive_datas *drvp; 1540 { 1541 /* This is actually a lie until we fix the _probe_caps 1542 algorithm. Don't print out lies */ 1543 #if 0 1544 printf("%s: can use ", drvp->drive_name); 1545 1546 if (drvp->drive_flags & DRIVE_CAP32) { 1547 printf("32-bit"); 1548 } else 1549 printf("16-bit"); 1550 1551 printf(", PIO mode %d", drvp->PIO_cap); 1552 1553 if (drvp->drive_flags & DRIVE_DMA) { 1554 printf(", DMA mode %d", drvp->DMA_cap); 1555 } 1556 1557 if (drvp->drive_flags & DRIVE_UDMA) { 1558 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1559 } 1560 1561 printf("\n"); 1562 #endif /* 0 */ 1563 } 1564 1565 void 1566 wdc_print_current_modes(chp) 1567 struct channel_softc *chp; 1568 { 1569 int drive; 1570 struct ata_drive_datas *drvp; 1571 1572 for (drive = 0; drive < 2; drive++) { 1573 drvp = &chp->ch_drive[drive]; 1574 if ((drvp->drive_flags & DRIVE) == 0) 1575 continue; 1576 1577 printf("%s(%s:%d:%d):", 1578 drvp->drive_name, 1579 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1580 1581 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1582 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1583 printf(" using BIOS timings"); 1584 else 1585 printf(" using PIO mode %d", drvp->PIO_mode); 1586 if (drvp->drive_flags & DRIVE_DMA) 1587 printf(", DMA mode %d", drvp->DMA_mode); 1588 if (drvp->drive_flags & DRIVE_UDMA) 1589 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1590 printf("\n"); 1591 } 1592 } 1593 1594 /* 1595 * downgrade the transfer mode of a drive after an error. return 1 if 1596 * downgrade was possible, 0 otherwise. 1597 */ 1598 int 1599 wdc_downgrade_mode(drvp) 1600 struct ata_drive_datas *drvp; 1601 { 1602 struct channel_softc *chp = drvp->chnl_softc; 1603 struct wdc_softc *wdc = chp->wdc; 1604 int cf_flags = drvp->cf_flags; 1605 1606 /* if drive or controller don't know its mode, we can't do much */ 1607 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1608 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1609 return 0; 1610 /* current drive mode was set by a config flag, let it this way */ 1611 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1612 (cf_flags & ATA_CONFIG_DMA_SET) || 1613 (cf_flags & ATA_CONFIG_UDMA_SET)) 1614 return 0; 1615 1616 /* 1617 * We'd ideally like to use an Ultra DMA mode since they have the 1618 * protection of a CRC. So we try each Ultra DMA mode and see if 1619 * we can find any working combo 1620 */ 1621 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1622 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1623 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1624 drvp->drive_name, drvp->UDMA_mode); 1625 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1626 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1627 /* 1628 * If we were using ultra-DMA, don't downgrade to 1629 * multiword DMA if we noticed a CRC error. It has 1630 * been noticed that CRC errors in ultra-DMA lead to 1631 * silent data corruption in multiword DMA. Data 1632 * corruption is less likely to occur in PIO mode. 1633 */ 1634 drvp->drive_flags &= ~DRIVE_UDMA; 1635 drvp->drive_flags |= DRIVE_DMA; 1636 drvp->DMA_mode = drvp->DMA_cap; 1637 printf("%s: transfer error, downgrading to DMA mode %d\n", 1638 drvp->drive_name, drvp->DMA_mode); 1639 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1640 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1641 drvp->PIO_mode = drvp->PIO_cap; 1642 printf("%s: transfer error, downgrading to PIO mode %d\n", 1643 drvp->drive_name, drvp->PIO_mode); 1644 } else /* already using PIO, can't downgrade */ 1645 return 0; 1646 1647 wdc->set_modes(chp); 1648 /* reset the channel, which will schedule all drives for setup */ 1649 wdc_reset_channel(drvp); 1650 return 1; 1651 } 1652 1653 int 1654 wdc_exec_command(drvp, wdc_c) 1655 struct ata_drive_datas *drvp; 1656 struct wdc_command *wdc_c; 1657 { 1658 struct channel_softc *chp = drvp->chnl_softc; 1659 struct wdc_xfer *xfer; 1660 int s, ret; 1661 1662 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1663 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1664 DEBUG_FUNCS); 1665 1666 /* set up an xfer and queue. Wait for completion */ 1667 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1668 WDC_NOSLEEP); 1669 if (xfer == NULL) { 1670 return WDC_TRY_AGAIN; 1671 } 1672 1673 if (wdc_c->flags & AT_POLL) 1674 xfer->c_flags |= C_POLL; 1675 xfer->drive = drvp->drive; 1676 xfer->databuf = wdc_c->data; 1677 xfer->c_bcount = wdc_c->bcount; 1678 xfer->cmd = wdc_c; 1679 xfer->c_start = __wdccommand_start; 1680 xfer->c_intr = __wdccommand_intr; 1681 xfer->c_kill_xfer = __wdccommand_done; 1682 1683 s = splbio(); 1684 wdc_exec_xfer(chp, xfer); 1685 #ifdef DIAGNOSTIC 1686 if ((wdc_c->flags & AT_POLL) != 0 && 1687 (wdc_c->flags & AT_DONE) == 0) 1688 panic("wdc_exec_command: polled command not done"); 1689 #endif /* DIAGNOSTIC */ 1690 if (wdc_c->flags & AT_DONE) { 1691 ret = WDC_COMPLETE; 1692 } else { 1693 if (wdc_c->flags & AT_WAIT) { 1694 WDCDEBUG_PRINT(("wdc_exec_command sleeping\n"), 1695 DEBUG_FUNCS); 1696 1697 while ((wdc_c->flags & AT_DONE) == 0) { 1698 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1699 } 1700 ret = WDC_COMPLETE; 1701 } else { 1702 ret = WDC_QUEUED; 1703 } 1704 } 1705 splx(s); 1706 return ret; 1707 } 1708 1709 void 1710 __wdccommand_start(chp, xfer) 1711 struct channel_softc *chp; 1712 struct wdc_xfer *xfer; 1713 { 1714 int drive = xfer->drive; 1715 struct wdc_command *wdc_c = xfer->cmd; 1716 1717 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1718 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1719 DEBUG_FUNCS); 1720 1721 /* 1722 * Disable interrupts if we're polling 1723 */ 1724 if (xfer->c_flags & C_POLL) { 1725 wdc_disable_intr(chp); 1726 } 1727 1728 wdc_set_drive(chp, drive); 1729 DELAY(1); 1730 1731 /* 1732 * For resets, we don't really care to make sure that 1733 * the bus is free 1734 */ 1735 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1736 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1737 wdc_c->r_st_bmask, wdc_c->timeout) != 0) { 1738 goto timeout; 1739 } 1740 } else 1741 DELAY(10); 1742 1743 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1744 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1745 1746 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) { 1747 /* wait at least 400ns before reading status register */ 1748 DELAY(10); 1749 if (wait_for_unbusy(chp, wdc_c->timeout) != 0) 1750 goto timeout; 1751 1752 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) { 1753 __wdccommand_done(chp, xfer); 1754 return; 1755 } 1756 1757 if (wait_for_drq(chp, wdc_c->timeout) != 0) 1758 goto timeout; 1759 1760 wdc_output_bytes(&chp->ch_drive[drive], 1761 wdc_c->data, wdc_c->bcount); 1762 } 1763 1764 if ((wdc_c->flags & AT_POLL) == 0) { 1765 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1766 timeout_add_msec(&chp->ch_timo, wdc_c->timeout); 1767 return; 1768 } 1769 1770 /* 1771 * Polled command. Wait for drive ready or drq. Done in intr(). 1772 * Wait for at last 400ns for status bit to be valid. 1773 */ 1774 delay(10); 1775 __wdccommand_intr(chp, xfer, 0); 1776 return; 1777 1778 timeout: 1779 wdc_c->flags |= AT_TIMEOU; 1780 __wdccommand_done(chp, xfer); 1781 } 1782 1783 int 1784 __wdccommand_intr(chp, xfer, irq) 1785 struct channel_softc *chp; 1786 struct wdc_xfer *xfer; 1787 int irq; 1788 { 1789 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1790 struct wdc_command *wdc_c = xfer->cmd; 1791 int bcount = wdc_c->bcount; 1792 char *data = wdc_c->data; 1793 1794 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1795 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1796 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1797 (irq == 0) ? wdc_c->timeout : 0)) { 1798 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1799 return 0; /* IRQ was not for us */ 1800 wdc_c->flags |= AT_TIMEOU; 1801 goto out; 1802 } 1803 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1804 chp->wdc->irqack(chp); 1805 if (wdc_c->flags & AT_READ) { 1806 if ((chp->ch_status & WDCS_DRQ) == 0) { 1807 wdc_c->flags |= AT_TIMEOU; 1808 goto out; 1809 } 1810 wdc_input_bytes(drvp, data, bcount); 1811 /* Should we wait for device to indicate idle? */ 1812 } 1813 out: 1814 __wdccommand_done(chp, xfer); 1815 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1816 return 1; 1817 } 1818 1819 void 1820 __wdccommand_done(chp, xfer) 1821 struct channel_softc *chp; 1822 struct wdc_xfer *xfer; 1823 { 1824 struct wdc_command *wdc_c = xfer->cmd; 1825 1826 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1827 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 1828 chp->ch_status), DEBUG_FUNCS); 1829 if (chp->ch_status & WDCS_DWF) 1830 wdc_c->flags |= AT_DF; 1831 if (chp->ch_status & WDCS_ERR) { 1832 wdc_c->flags |= AT_ERROR; 1833 wdc_c->r_error = chp->ch_error; 1834 } 1835 wdc_c->flags |= AT_DONE; 1836 if ((wdc_c->flags & AT_READREG) != 0 && 1837 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1838 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1839 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1840 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1841 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1842 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1843 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1844 wdc_c->r_precomp = wdc_c->r_error; 1845 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1846 isn't a readable register */ 1847 } 1848 1849 if (xfer->c_flags & C_POLL) { 1850 wdc_enable_intr(chp); 1851 } 1852 1853 wdc_free_xfer(chp, xfer); 1854 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1855 1856 if (wdc_c->flags & AT_WAIT) 1857 wakeup(wdc_c); 1858 else 1859 if (wdc_c->callback) 1860 wdc_c->callback(wdc_c->callback_arg); 1861 wdcstart(chp); 1862 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1863 } 1864 1865 /* 1866 * Send a command. The drive should be ready. 1867 * Assumes interrupts are blocked. 1868 */ 1869 void 1870 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1871 struct channel_softc *chp; 1872 u_int8_t drive; 1873 u_int8_t command; 1874 u_int16_t cylin; 1875 u_int8_t head, sector, count, precomp; 1876 { 1877 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1878 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1879 chp->channel, drive, command, cylin, head, sector, count, precomp), 1880 DEBUG_FUNCS); 1881 WDC_LOG_ATA_CMDLONG(chp, head, precomp, cylin, cylin >> 8, sector, 1882 count, command); 1883 1884 /* Select drive, head, and addressing mode. */ 1885 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1886 1887 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1888 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1889 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1890 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1891 CHP_WRITE_REG(chp, wdr_sector, sector); 1892 CHP_WRITE_REG(chp, wdr_seccnt, count); 1893 1894 /* Send command. */ 1895 CHP_WRITE_REG(chp, wdr_command, command); 1896 } 1897 1898 /* 1899 * Send a 48-bit addressing command. The drive should be ready. 1900 * Assumes interrupts are blocked. 1901 */ 1902 void 1903 wdccommandext(chp, drive, command, blkno, count) 1904 struct channel_softc *chp; 1905 u_int8_t drive; 1906 u_int8_t command; 1907 u_int64_t blkno; 1908 u_int16_t count; 1909 { 1910 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu " 1911 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1912 chp->channel, drive, command, blkno, count), 1913 DEBUG_FUNCS); 1914 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32, 1915 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command); 1916 1917 /* Select drive and LBA mode. */ 1918 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA); 1919 1920 /* Load parameters. */ 1921 CHP_LBA48_WRITE_REG(chp, wdr_lba_hi, 1922 ((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0xff)); 1923 CHP_LBA48_WRITE_REG(chp, wdr_lba_mi, 1924 ((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0xff)); 1925 CHP_LBA48_WRITE_REG(chp, wdr_lba_lo, 1926 ((blkno >> 16) & 0xff00) | (blkno & 0xff)); 1927 CHP_LBA48_WRITE_REG(chp, wdr_seccnt, count); 1928 1929 /* Send command. */ 1930 CHP_WRITE_REG(chp, wdr_command, command); 1931 } 1932 1933 /* 1934 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1935 * tested by the caller. 1936 */ 1937 void 1938 wdccommandshort(chp, drive, command) 1939 struct channel_softc *chp; 1940 int drive; 1941 int command; 1942 { 1943 1944 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1945 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1946 DEBUG_FUNCS); 1947 WDC_LOG_ATA_CMDSHORT(chp, command); 1948 1949 /* Select drive. */ 1950 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1951 CHP_WRITE_REG(chp, wdr_command, command); 1952 } 1953 1954 /* Add a command to the queue and start controller. Must be called at splbio */ 1955 1956 void 1957 wdc_exec_xfer(chp, xfer) 1958 struct channel_softc *chp; 1959 struct wdc_xfer *xfer; 1960 { 1961 WDCDEBUG_PRINT(("wdc_exec_xfer %p flags 0x%x channel %d drive %d\n", 1962 xfer, xfer->c_flags, chp->channel, xfer->drive), DEBUG_XFERS); 1963 1964 /* complete xfer setup */ 1965 xfer->chp = chp; 1966 1967 /* 1968 * If we are a polled command, and the list is not empty, 1969 * we are doing a dump. Drop the list to allow the polled command 1970 * to complete, we're going to reboot soon anyway. 1971 */ 1972 if ((xfer->c_flags & C_POLL) != 0 && 1973 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) { 1974 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1975 } 1976 /* insert at the end of command list */ 1977 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1978 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1979 chp->ch_flags), DEBUG_XFERS); 1980 wdcstart(chp); 1981 } 1982 1983 struct wdc_xfer * 1984 wdc_get_xfer(flags) 1985 int flags; 1986 { 1987 struct wdc_xfer *xfer; 1988 int s; 1989 1990 s = splbio(); 1991 xfer = pool_get(&wdc_xfer_pool, 1992 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1993 splx(s); 1994 if (xfer != NULL) 1995 memset(xfer, 0, sizeof(struct wdc_xfer)); 1996 return xfer; 1997 } 1998 1999 void 2000 wdc_free_xfer(chp, xfer) 2001 struct channel_softc *chp; 2002 struct wdc_xfer *xfer; 2003 { 2004 struct wdc_softc *wdc = chp->wdc; 2005 int s; 2006 2007 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2008 (*wdc->free_hw)(chp); 2009 s = splbio(); 2010 chp->ch_flags &= ~WDCF_ACTIVE; 2011 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2012 pool_put(&wdc_xfer_pool, xfer); 2013 splx(s); 2014 } 2015 2016 2017 /* 2018 * Kill off all pending xfers for a channel_softc. 2019 * 2020 * Must be called at splbio(). 2021 */ 2022 void 2023 wdc_kill_pending(chp) 2024 struct channel_softc *chp; 2025 { 2026 struct wdc_xfer *xfer; 2027 2028 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2029 chp = xfer->chp; 2030 (*xfer->c_kill_xfer)(chp, xfer); 2031 } 2032 } 2033 2034 void 2035 __wdcerror(chp, msg) 2036 struct channel_softc *chp; 2037 char *msg; 2038 { 2039 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 2040 if (xfer == NULL) 2041 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2042 msg); 2043 else 2044 printf("%s(%s:%d:%d): %s\n", 2045 chp->ch_drive[xfer->drive].drive_name, 2046 chp->wdc->sc_dev.dv_xname, 2047 chp->channel, xfer->drive, msg); 2048 } 2049 2050 /* 2051 * the bit bucket 2052 */ 2053 void 2054 wdcbit_bucket(chp, size) 2055 struct channel_softc *chp; 2056 int size; 2057 { 2058 CHP_READ_RAW_MULTI_2(chp, NULL, size); 2059 } 2060 2061 2062 #include <sys/ataio.h> 2063 #include <sys/file.h> 2064 #include <sys/buf.h> 2065 2066 /* 2067 * Glue necessary to hook ATAIOCCOMMAND into physio 2068 */ 2069 2070 struct wdc_ioctl { 2071 LIST_ENTRY(wdc_ioctl) wi_list; 2072 struct buf wi_bp; 2073 struct uio wi_uio; 2074 struct iovec wi_iov; 2075 atareq_t wi_atareq; 2076 struct ata_drive_datas *wi_drvp; 2077 }; 2078 2079 struct wdc_ioctl *wdc_ioctl_find(struct buf *); 2080 void wdc_ioctl_free(struct wdc_ioctl *); 2081 struct wdc_ioctl *wdc_ioctl_get(void); 2082 void wdc_ioctl_strategy(struct buf *); 2083 2084 LIST_HEAD(, wdc_ioctl) wi_head; 2085 2086 /* 2087 * Allocate space for a ioctl queue structure. Mostly taken from 2088 * scsipi_ioctl.c 2089 */ 2090 struct wdc_ioctl * 2091 wdc_ioctl_get() 2092 { 2093 struct wdc_ioctl *wi; 2094 int s; 2095 2096 wi = malloc(sizeof(*wi), M_TEMP, M_WAITOK | M_ZERO); 2097 s = splbio(); 2098 LIST_INSERT_HEAD(&wi_head, wi, wi_list); 2099 splx(s); 2100 return (wi); 2101 } 2102 2103 /* 2104 * Free an ioctl structure and remove it from our list 2105 */ 2106 2107 void 2108 wdc_ioctl_free(wi) 2109 struct wdc_ioctl *wi; 2110 { 2111 int s; 2112 2113 s = splbio(); 2114 LIST_REMOVE(wi, wi_list); 2115 splx(s); 2116 free(wi, M_TEMP); 2117 } 2118 2119 /* 2120 * Find a wdc_ioctl structure based on the struct buf. 2121 */ 2122 2123 struct wdc_ioctl * 2124 wdc_ioctl_find(bp) 2125 struct buf *bp; 2126 { 2127 struct wdc_ioctl *wi; 2128 int s; 2129 2130 s = splbio(); 2131 LIST_FOREACH(wi, &wi_head, wi_list) 2132 if (bp == &wi->wi_bp) 2133 break; 2134 splx(s); 2135 return (wi); 2136 } 2137 2138 /* 2139 * Ioctl pseudo strategy routine 2140 * 2141 * This is mostly stolen from scsipi_ioctl.c:scsistrategy(). What 2142 * happens here is: 2143 * 2144 * - wdioctl() queues a wdc_ioctl structure. 2145 * 2146 * - wdioctl() calls physio/wdc_ioctl_strategy based on whether or not 2147 * user space I/O is required. If physio() is called, physio() eventually 2148 * calls wdc_ioctl_strategy(). 2149 * 2150 * - In either case, wdc_ioctl_strategy() calls wdc_exec_command() 2151 * to perform the actual command 2152 * 2153 * The reason for the use of the pseudo strategy routine is because 2154 * when doing I/O to/from user space, physio _really_ wants to be in 2155 * the loop. We could put the entire buffer into the ioctl request 2156 * structure, but that won't scale if we want to do things like download 2157 * microcode. 2158 */ 2159 2160 void 2161 wdc_ioctl_strategy(bp) 2162 struct buf *bp; 2163 { 2164 struct wdc_ioctl *wi; 2165 struct wdc_command wdc_c; 2166 int error = 0; 2167 int s; 2168 2169 wi = wdc_ioctl_find(bp); 2170 if (wi == NULL) { 2171 printf("user_strat: No ioctl\n"); 2172 error = EINVAL; 2173 goto bad; 2174 } 2175 2176 bzero(&wdc_c, sizeof(wdc_c)); 2177 2178 /* 2179 * Abort if physio broke up the transfer 2180 */ 2181 2182 if ((u_long)bp->b_bcount != wi->wi_atareq.datalen) { 2183 printf("physio split wd ioctl request... cannot proceed\n"); 2184 error = EIO; 2185 goto bad; 2186 } 2187 2188 /* 2189 * Make sure a timeout was supplied in the ioctl request 2190 */ 2191 2192 if (wi->wi_atareq.timeout == 0) { 2193 error = EINVAL; 2194 goto bad; 2195 } 2196 2197 if (wi->wi_atareq.flags & ATACMD_READ) 2198 wdc_c.flags |= AT_READ; 2199 else if (wi->wi_atareq.flags & ATACMD_WRITE) 2200 wdc_c.flags |= AT_WRITE; 2201 2202 if (wi->wi_atareq.flags & ATACMD_READREG) 2203 wdc_c.flags |= AT_READREG; 2204 2205 wdc_c.flags |= AT_WAIT; 2206 2207 wdc_c.timeout = wi->wi_atareq.timeout; 2208 wdc_c.r_command = wi->wi_atareq.command; 2209 wdc_c.r_head = wi->wi_atareq.head & 0x0f; 2210 wdc_c.r_cyl = wi->wi_atareq.cylinder; 2211 wdc_c.r_sector = wi->wi_atareq.sec_num; 2212 wdc_c.r_count = wi->wi_atareq.sec_count; 2213 wdc_c.r_precomp = wi->wi_atareq.features; 2214 if (wi->wi_drvp->drive_flags & DRIVE_ATAPI) { 2215 wdc_c.r_st_bmask = 0; 2216 wdc_c.r_st_pmask = 0; 2217 if (wdc_c.r_command == WDCC_IDENTIFY) 2218 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 2219 } else { 2220 wdc_c.r_st_bmask = WDCS_DRDY; 2221 wdc_c.r_st_pmask = WDCS_DRDY; 2222 } 2223 wdc_c.data = wi->wi_bp.b_data; 2224 wdc_c.bcount = wi->wi_bp.b_bcount; 2225 2226 if (wdc_exec_command(wi->wi_drvp, &wdc_c) != WDC_COMPLETE) { 2227 wi->wi_atareq.retsts = ATACMD_ERROR; 2228 goto bad; 2229 } 2230 2231 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 2232 if (wdc_c.flags & AT_ERROR) { 2233 wi->wi_atareq.retsts = ATACMD_ERROR; 2234 wi->wi_atareq.error = wdc_c.r_error; 2235 } else if (wdc_c.flags & AT_DF) 2236 wi->wi_atareq.retsts = ATACMD_DF; 2237 else 2238 wi->wi_atareq.retsts = ATACMD_TIMEOUT; 2239 } else { 2240 wi->wi_atareq.retsts = ATACMD_OK; 2241 if (wi->wi_atareq.flags & ATACMD_READREG) { 2242 wi->wi_atareq.head = wdc_c.r_head ; 2243 wi->wi_atareq.cylinder = wdc_c.r_cyl; 2244 wi->wi_atareq.sec_num = wdc_c.r_sector; 2245 wi->wi_atareq.sec_count = wdc_c.r_count; 2246 wi->wi_atareq.features = wdc_c.r_precomp; 2247 wi->wi_atareq.error = wdc_c.r_error; 2248 } 2249 } 2250 2251 bp->b_error = 0; 2252 s = splbio(); 2253 biodone(bp); 2254 splx(s); 2255 return; 2256 bad: 2257 bp->b_flags |= B_ERROR; 2258 bp->b_error = error; 2259 s = splbio(); 2260 biodone(bp); 2261 splx(s); 2262 } 2263 2264 int 2265 wdc_ioctl(drvp, xfer, addr, flag, p) 2266 struct ata_drive_datas *drvp; 2267 u_long xfer; 2268 caddr_t addr; 2269 int flag; 2270 struct proc *p; 2271 { 2272 int error = 0; 2273 2274 switch (xfer) { 2275 #ifdef WDCDEBUG 2276 case ATAIOGETTRACE: { 2277 atagettrace_t *agt = (atagettrace_t *)addr; 2278 unsigned int size = 0; 2279 char *log_to_copy; 2280 2281 size = agt->buf_size; 2282 if (size > 65536) { 2283 size = 65536; 2284 } 2285 2286 log_to_copy = wdc_get_log(&size, &agt->bytes_left); 2287 2288 if (log_to_copy != NULL) { 2289 error = copyout(log_to_copy, agt->buf, size); 2290 free(log_to_copy, M_TEMP); 2291 } 2292 2293 agt->bytes_copied = size; 2294 break; 2295 } 2296 #endif /* WDCDEBUG */ 2297 2298 case ATAIOCCOMMAND: 2299 /* 2300 * Make sure this command is (relatively) safe first 2301 */ 2302 if ((((atareq_t *) addr)->flags & ATACMD_READ) == 0 && 2303 (flag & FWRITE) == 0) { 2304 error = EBADF; 2305 goto exit; 2306 } 2307 { 2308 struct wdc_ioctl *wi; 2309 atareq_t *atareq = (atareq_t *) addr; 2310 2311 wi = wdc_ioctl_get(); 2312 wi->wi_drvp = drvp; 2313 wi->wi_atareq = *atareq; 2314 2315 if (atareq->datalen && atareq->flags & 2316 (ATACMD_READ | ATACMD_WRITE)) { 2317 wi->wi_iov.iov_base = atareq->databuf; 2318 wi->wi_iov.iov_len = atareq->datalen; 2319 wi->wi_uio.uio_iov = &wi->wi_iov; 2320 wi->wi_uio.uio_iovcnt = 1; 2321 wi->wi_uio.uio_resid = atareq->datalen; 2322 wi->wi_uio.uio_offset = 0; 2323 wi->wi_uio.uio_segflg = UIO_USERSPACE; 2324 wi->wi_uio.uio_rw = 2325 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE; 2326 wi->wi_uio.uio_procp = curproc; 2327 error = physio(wdc_ioctl_strategy, &wi->wi_bp, 0, 2328 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE, 2329 minphys, &wi->wi_uio); 2330 } else { 2331 /* No need to call physio if we don't have any 2332 user data */ 2333 wi->wi_bp.b_flags = 0; 2334 wi->wi_bp.b_data = 0; 2335 wi->wi_bp.b_bcount = 0; 2336 wi->wi_bp.b_dev = 0; 2337 wi->wi_bp.b_proc = curproc; 2338 LIST_INIT(&wi->wi_bp.b_dep); 2339 wdc_ioctl_strategy(&wi->wi_bp); 2340 error = wi->wi_bp.b_error; 2341 } 2342 *atareq = wi->wi_atareq; 2343 wdc_ioctl_free(wi); 2344 goto exit; 2345 } 2346 default: 2347 error = ENOTTY; 2348 goto exit; 2349 } 2350 2351 exit: 2352 return (error); 2353 } 2354