1 /* $OpenBSD: wdc.c,v 1.80 2003/11/19 21:30:43 grange Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 4 5 /* 6 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1998 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/conf.h> 74 #include <sys/buf.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/syslog.h> 78 #include <sys/proc.h> 79 #include <sys/pool.h> 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/intr.h> 83 #include <machine/bus.h> 84 85 #include <dev/ata/atavar.h> 86 #include <dev/ata/atareg.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 #include <dev/ic/wdcevent.h> 90 91 #include "atapiscsi.h" 92 93 #define WDCDELAY 100 /* 100 microseconds */ 94 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 95 #if 0 96 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 97 #define WDCNDELAY_DEBUG 50 98 #endif /* 0 */ 99 100 struct pool wdc_xfer_pool; 101 102 void __wdcerror(struct channel_softc *, char *); 103 void __wdcdo_reset(struct channel_softc *); 104 int __wdcwait_reset(struct channel_softc *, int); 105 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *); 106 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *); 107 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int); 108 int wdprint(void *, const char *); 109 void wdc_kill_pending(struct channel_softc *); 110 111 #define DEBUG_INTR 0x01 112 #define DEBUG_XFERS 0x02 113 #define DEBUG_STATUS 0x04 114 #define DEBUG_FUNCS 0x08 115 #define DEBUG_PROBE 0x10 116 #define DEBUG_STATUSX 0x20 117 #define DEBUG_SDRIVE 0x40 118 #define DEBUG_DETACH 0x80 119 120 #ifdef WDCDEBUG 121 #ifndef WDCDEBUG_MASK 122 #define WDCDEBUG_MASK 0x00 123 #endif 124 int wdcdebug_mask = WDCDEBUG_MASK; 125 int wdc_nxfer = 0; 126 #define WDCDEBUG_PRINT(args, level) do { \ 127 if ((wdcdebug_mask & (level)) != 0) \ 128 printf args; \ 129 } while (0) 130 #else 131 #define WDCDEBUG_PRINT(args, level) 132 #endif /* WDCDEBUG */ 133 134 int at_poll = AT_POLL; 135 136 u_int8_t wdc_default_read_reg(struct channel_softc *, enum wdc_regs); 137 void wdc_default_write_reg(struct channel_softc *, enum wdc_regs, u_int8_t); 138 void wdc_default_read_raw_multi_2(struct channel_softc *, 139 void *, unsigned int); 140 void wdc_default_write_raw_multi_2(struct channel_softc *, 141 void *, unsigned int); 142 void wdc_default_read_raw_multi_4(struct channel_softc *, 143 void *, unsigned int); 144 void wdc_default_write_raw_multi_4(struct channel_softc *, 145 void *, unsigned int); 146 147 int wdc_floating_bus(struct channel_softc *, int); 148 int wdc_preata_drive(struct channel_softc *, int); 149 int wdc_ata_present(struct channel_softc *, int); 150 151 struct channel_softc_vtbl wdc_default_vtbl = { 152 wdc_default_read_reg, 153 wdc_default_write_reg, 154 wdc_default_read_raw_multi_2, 155 wdc_default_write_raw_multi_2, 156 wdc_default_read_raw_multi_4, 157 wdc_default_write_raw_multi_4 158 }; 159 160 static char *wdc_log_buf = NULL; 161 static int wdc_tail = 0; 162 static int wdc_head = 0; 163 static int wdc_size = 16 * 1024; 164 static int chp_idx = 1; 165 166 void 167 wdc_log(struct channel_softc *chp, enum wdcevent_type type, 168 unsigned int size, char val[]) 169 { 170 unsigned int request_size; 171 int idx; 172 char *ptr; 173 int nbytes; 174 175 if (wdc_head < 0 || wdc_head > wdc_size || 176 wdc_tail < 0 || wdc_tail > wdc_size) { 177 printf ("wdc_log: wdc_head %x wdc_tail %x\n", wdc_head, 178 wdc_tail); 179 return; 180 } 181 182 if (size > wdc_size / 2) { 183 printf ("wdc_log: type %d size %x\n", type, size); 184 } 185 186 if (wdc_log_buf == NULL) { 187 wdc_log_buf = malloc(wdc_size, M_DEVBUF, M_NOWAIT); 188 if (wdc_log_buf == NULL) 189 return; 190 } 191 if (chp->ch_log_idx == 0) 192 chp->ch_log_idx = chp_idx++; 193 194 request_size = size + 2; 195 196 /* Check how many bytes are left */ 197 nbytes = wdc_head - wdc_tail; 198 if (nbytes < 0) nbytes += wdc_size; 199 200 if (nbytes + request_size >= wdc_size) { 201 wdc_tail = (wdc_tail + request_size * 2) % wdc_size; 202 } 203 204 /* Avoid wrapping in the middle of a request */ 205 if (wdc_head + request_size >= wdc_size) { 206 memset(&wdc_log_buf[wdc_head], 0, wdc_size - wdc_head); 207 wdc_head = 0; 208 } 209 210 ptr = &wdc_log_buf[wdc_head]; 211 *ptr++ = type & 0xff; 212 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f); 213 214 idx = 0; 215 while (size--) { 216 *ptr++ = val[idx]; 217 idx++; 218 } 219 wdc_head += request_size; 220 } 221 222 char *wdc_get_log(unsigned int *, unsigned int *); 223 224 char * 225 wdc_get_log(unsigned int * size, unsigned int *left) 226 { 227 int bytes = (wdc_head - wdc_tail); 228 char *retbuf; 229 int ot, c1, c2; 230 231 if (left != NULL) 232 *left = 0; 233 234 if (bytes < 0) 235 bytes += wdc_size; 236 if (bytes > *size) { 237 if (left != NULL) { 238 *left = bytes - *size; 239 } 240 bytes = *size; 241 } 242 243 if (wdc_log_buf == NULL) { 244 *size = 0; 245 *left = 0; 246 return (NULL); 247 } 248 249 if (wdc_head < 0 || wdc_head > wdc_size || 250 wdc_tail < 0 || wdc_tail > wdc_size) { 251 printf ("wdc_log: wdc_head %x wdc_tail %x\n", wdc_head, 252 wdc_tail); 253 *size = 0; 254 *left = 0; 255 return (NULL); 256 } 257 258 retbuf = malloc(bytes, M_TEMP, M_NOWAIT); 259 if (retbuf == NULL) { 260 *size = 0; 261 *left = bytes; 262 return (NULL); 263 } 264 265 *size = bytes; 266 267 ot = wdc_tail; 268 wdc_tail += bytes; 269 if (wdc_tail > wdc_size) { 270 wdc_tail -= wdc_size; 271 c2 = wdc_tail; 272 c1 = bytes - wdc_tail; 273 } else { 274 c1 = bytes; 275 c2 = 0; 276 } 277 278 memcpy(retbuf, &wdc_log_buf[ot], c1); 279 memcpy(&retbuf[c1], &wdc_log_buf[0], c2); 280 281 return (retbuf); 282 } 283 284 285 u_int8_t 286 wdc_default_read_reg(chp, reg) 287 struct channel_softc *chp; 288 enum wdc_regs reg; 289 { 290 #ifdef DIAGNOSTIC 291 if (reg & _WDC_WRONLY) { 292 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 293 } 294 #endif /* DIAGNOSTIC */ 295 296 if (reg & _WDC_AUX) 297 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 298 reg & _WDC_REGMASK)); 299 else 300 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 301 reg & _WDC_REGMASK)); 302 } 303 304 void 305 wdc_default_write_reg(chp, reg, val) 306 struct channel_softc *chp; 307 enum wdc_regs reg; 308 u_int8_t val; 309 { 310 #ifdef DIAGNOSTIC 311 if (reg & _WDC_RDONLY) { 312 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 313 } 314 #endif /* DIAGNOSTIC */ 315 316 if (reg & _WDC_AUX) 317 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 318 reg & _WDC_REGMASK, val); 319 else 320 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 321 reg & _WDC_REGMASK, val); 322 } 323 324 325 void 326 wdc_default_read_raw_multi_2(chp, data, nbytes) 327 struct channel_softc *chp; 328 void *data; 329 unsigned int nbytes; 330 { 331 if (data == NULL) { 332 int i; 333 334 for (i = 0; i < nbytes; i += 2) { 335 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 336 } 337 338 return; 339 } 340 341 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 342 data, nbytes); 343 return; 344 } 345 346 347 void 348 wdc_default_write_raw_multi_2(chp, data, nbytes) 349 struct channel_softc *chp; 350 void *data; 351 unsigned int nbytes; 352 { 353 if (data == NULL) { 354 int i; 355 356 for (i = 0; i < nbytes; i += 2) { 357 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 358 } 359 360 return; 361 } 362 363 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 364 data, nbytes); 365 return; 366 } 367 368 369 void 370 wdc_default_write_raw_multi_4(chp, data, nbytes) 371 struct channel_softc *chp; 372 void *data; 373 unsigned int nbytes; 374 { 375 if (data == NULL) { 376 int i; 377 378 for (i = 0; i < nbytes; i += 4) { 379 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 380 } 381 382 return; 383 } 384 385 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 386 data, nbytes); 387 return; 388 } 389 390 391 void 392 wdc_default_read_raw_multi_4(chp, data, nbytes) 393 struct channel_softc *chp; 394 void *data; 395 unsigned int nbytes; 396 { 397 if (data == NULL) { 398 int i; 399 400 for (i = 0; i < nbytes; i += 4) { 401 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 402 } 403 404 return; 405 } 406 407 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 408 data, nbytes); 409 return; 410 } 411 412 413 int 414 wdprint(aux, pnp) 415 void *aux; 416 const char *pnp; 417 { 418 struct ata_atapi_attach *aa_link = aux; 419 if (pnp) 420 printf("drive at %s", pnp); 421 printf(" channel %d drive %d", aa_link->aa_channel, 422 aa_link->aa_drv_data->drive); 423 return (UNCONF); 424 } 425 426 int 427 atapi_print(aux, pnp) 428 void *aux; 429 const char *pnp; 430 { 431 struct ata_atapi_attach *aa_link = aux; 432 if (pnp) 433 printf("atapiscsi at %s", pnp); 434 printf(" channel %d", aa_link->aa_channel); 435 return (UNCONF); 436 } 437 438 void 439 wdc_disable_intr(chp) 440 struct channel_softc *chp; 441 { 442 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 443 } 444 445 void 446 wdc_enable_intr(chp) 447 struct channel_softc *chp; 448 { 449 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 450 } 451 452 void 453 wdc_set_drive(struct channel_softc *chp, int drive) 454 { 455 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM); 456 WDC_LOG_SET_DRIVE(chp, drive); 457 } 458 459 int 460 wdc_floating_bus(chp, drive) 461 struct channel_softc *chp; 462 int drive; 463 464 { 465 u_int8_t cumulative_status, status; 466 int iter; 467 468 wdc_set_drive(chp, drive); 469 delay(10); 470 471 /* Stolen from Phoenix BIOS Drive Autotyping document */ 472 cumulative_status = 0; 473 for (iter = 0; iter < 100; iter++) { 474 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 475 delay (1); 476 477 status = CHP_READ_REG(chp, wdr_status); 478 479 /* The other bits are meaningless if BSY is set */ 480 if (status & WDCS_BSY) 481 continue; 482 483 cumulative_status |= status; 484 485 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 486 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 487 return 1; 488 } 489 490 491 return 0; 492 } 493 494 495 int 496 wdc_preata_drive(chp, drive) 497 struct channel_softc *chp; 498 int drive; 499 500 { 501 if (wdc_floating_bus(chp, drive)) { 502 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 503 chp->wdc->sc_dev.dv_xname, 504 chp->channel, drive), DEBUG_PROBE); 505 return 0; 506 } 507 508 wdc_set_drive(chp, drive); 509 delay(100); 510 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 511 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 512 chp->wdc->sc_dev.dv_xname, 513 chp->channel, drive), DEBUG_PROBE); 514 return 0; 515 } 516 517 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 518 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL); 519 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 520 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 521 chp->wdc->sc_dev.dv_xname, 522 chp->channel, drive), DEBUG_PROBE); 523 return 0; 524 } 525 526 return 1; 527 } 528 529 int 530 wdc_ata_present(chp, drive) 531 struct channel_softc *chp; 532 int drive; 533 { 534 int time_to_done; 535 int retry_cnt = 0; 536 537 wdc_set_drive(chp, drive); 538 delay(10); 539 540 retry: 541 /* 542 You're actually supposed to wait up to 10 seconds 543 for DRDY. However, as a practical matter, most 544 drives assert DRDY very quickly after dropping BSY. 545 546 The 10 seconds wait is sub-optimal because, according 547 to the ATA standard, the master should reply with 00 548 for any reads to a non-existent slave. 549 */ 550 time_to_done = wdc_wait_for_status(chp, 551 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 552 (WDCS_DRDY | WDCS_DSC), 1000); 553 if (time_to_done == -1) { 554 if (retry_cnt == 0 && chp->ch_status == 0x00) { 555 /* At least one flash card needs to be kicked */ 556 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 557 retry_cnt++; 558 goto retry; 559 } 560 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 561 " %02x\n", 562 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 563 chp->channel, drive, chp->ch_status), 564 DEBUG_PROBE); 565 return 0; 566 } 567 568 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 569 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 570 " %02x\n", 571 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 572 chp->channel, drive, chp->ch_status), 573 DEBUG_PROBE); 574 575 return 0; 576 } 577 578 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 579 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 580 chp->channel, drive, time_to_done), DEBUG_PROBE); 581 582 /* 583 * Test register writability 584 */ 585 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 586 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 587 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 588 DELAY(10); 589 590 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 591 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 592 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 593 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 594 chp->channel, drive), DEBUG_PROBE); 595 return 0; 596 } 597 598 return 1; 599 } 600 601 602 /* 603 * Test to see controller with at least one attached drive is there. 604 * Returns a bit for each possible drive found (0x01 for drive 0, 605 * 0x02 for drive 1). 606 * Logic: 607 * - If a status register is at 0x7f or 0xff, assume there is no drive here 608 * (ISA has pull-up resistors). Similarly if the status register has 609 * the value we last wrote to the bus (for IDE interfaces without pullups). 610 * If no drive at all -> return. 611 * - reset the controller, wait for it to complete (may take up to 31s !). 612 * If timeout -> return. 613 * - test ATA/ATAPI signatures. If at last one drive found -> return. 614 * - try an ATA command on the master. 615 */ 616 617 int 618 wdcprobe(chp) 619 struct channel_softc *chp; 620 { 621 u_int8_t st0, st1, sc, sn, cl, ch; 622 u_int8_t ret_value = 0x03; 623 u_int8_t drive; 624 #ifdef WDCDEBUG 625 int savedmask = wdcdebug_mask; 626 #endif 627 628 if (chp->_vtbl == 0) { 629 int s = splbio(); 630 chp->_vtbl = &wdc_default_vtbl; 631 splx(s); 632 } 633 634 #ifdef WDCDEBUG 635 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 636 (chp->wdc && 637 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 638 wdcdebug_mask |= DEBUG_PROBE; 639 #endif /* WDCDEBUG */ 640 641 if (chp->wdc == NULL || 642 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 643 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 644 wdc_set_drive(chp, 0); 645 delay(10); 646 st0 = CHP_READ_REG(chp, wdr_status); 647 WDC_LOG_STATUS(chp, st0); 648 wdc_set_drive(chp, 1); 649 delay(10); 650 st1 = CHP_READ_REG(chp, wdr_status); 651 WDC_LOG_STATUS(chp, st1); 652 653 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 654 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 655 chp->channel, st0, st1), DEBUG_PROBE); 656 657 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM) 658 ret_value &= ~0x01; 659 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10)) 660 ret_value &= ~0x02; 661 if (ret_value == 0) 662 return 0; 663 } 664 665 /* reset the channel */ 666 __wdcdo_reset(chp); 667 668 ret_value = __wdcwait_reset(chp, ret_value); 669 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 670 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 671 ret_value), DEBUG_PROBE); 672 673 if (ret_value == 0) 674 return 0; 675 676 /* 677 * Use signatures to find potential ATAPI drives 678 */ 679 for (drive = 0; drive < 2; drive++) { 680 if ((ret_value & (0x01 << drive)) == 0) 681 continue; 682 wdc_set_drive(chp, drive); 683 delay(10); 684 /* Save registers contents */ 685 st0 = CHP_READ_REG(chp, wdr_status); 686 sc = CHP_READ_REG(chp, wdr_seccnt); 687 sn = CHP_READ_REG(chp, wdr_sector); 688 cl = CHP_READ_REG(chp, wdr_cyl_lo); 689 ch = CHP_READ_REG(chp, wdr_cyl_hi); 690 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl); 691 692 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%x, sc=0x%x" 693 " sn=0x%x cl=0x%x ch=0x%x\n", 694 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 695 chp->channel, drive, st0, sc, sn, cl, ch), DEBUG_PROBE); 696 /* 697 * This is a simplification of the test in the ATAPI 698 * spec since not all drives seem to set the other regs 699 * correctly. 700 */ 701 if (cl == 0x14 && ch == 0xeb) 702 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 703 } 704 705 /* 706 * Detect ATA drives by poking around the registers 707 */ 708 for (drive = 0; drive < 2; drive++) { 709 if ((ret_value & (0x01 << drive)) == 0) 710 continue; 711 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 712 continue; 713 714 wdc_disable_intr(chp); 715 /* ATA detect */ 716 if (wdc_ata_present(chp, drive)) { 717 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 718 if (chp->wdc == NULL || 719 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 720 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 721 } else { 722 ret_value &= ~(1 << drive); 723 } 724 wdc_enable_intr(chp); 725 } 726 727 #ifdef WDCDEBUG 728 wdcdebug_mask = savedmask; 729 #endif 730 return (ret_value); 731 } 732 733 /* 734 * Call activate routine of underlying devices. 735 */ 736 int 737 wdcactivate(self, act) 738 struct device *self; 739 enum devact act; 740 { 741 int error = 0; 742 int s; 743 744 s = splbio(); 745 config_activate_children(self, act); 746 splx(s); 747 748 return (error); 749 } 750 751 void 752 wdcattach(chp) 753 struct channel_softc *chp; 754 { 755 int channel_flags, ctrl_flags, i; 756 #ifndef __OpenBSD__ 757 int error; 758 #endif 759 struct ata_atapi_attach aa_link; 760 static int inited = 0; 761 #ifdef WDCDEBUG 762 int savedmask = wdcdebug_mask; 763 #endif 764 765 if (!cold) 766 at_poll = AT_WAIT; 767 768 timeout_set(&chp->ch_timo, wdctimeout, chp); 769 770 #ifndef __OpenBSD__ 771 if ((error = wdc_addref(chp)) != 0) { 772 printf("%s: unable to enable controller\n", 773 chp->wdc->sc_dev.dv_xname); 774 return; 775 } 776 #endif /* __OpenBSD__ */ 777 if (!chp->_vtbl) 778 chp->_vtbl = &wdc_default_vtbl; 779 780 if (wdcprobe(chp) == 0) { 781 /* If no drives, abort attach here. */ 782 #ifndef __OpenBSD__ 783 wdc_delref(chp); 784 #endif 785 return; 786 } 787 788 /* ATAPI drives need settling time. Give them 250ms */ 789 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 790 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 791 delay(250 * 1000); 792 } 793 794 #ifdef WDCDEBUG 795 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 796 wdcdebug_mask |= DEBUG_PROBE; 797 798 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 799 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 800 wdcdebug_mask = DEBUG_PROBE; 801 } 802 #endif /* WDCDEBUG */ 803 804 /* initialise global data */ 805 if (inited == 0) { 806 /* Initialize the wdc_xfer pool. */ 807 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 808 0, 0, "wdcspl", NULL); 809 inited++; 810 } 811 TAILQ_INIT(&chp->ch_queue->sc_xfer); 812 813 for (i = 0; i < 2; i++) { 814 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 815 816 drvp->chnl_softc = chp; 817 drvp->drive = i; 818 /* If controller can't do 16bit flag the drives as 32bit */ 819 if ((chp->wdc->cap & 820 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 821 WDC_CAPABILITY_DATA32) 822 drvp->drive_flags |= DRIVE_CAP32; 823 824 if ((drvp->drive_flags & DRIVE) == 0) 825 continue; 826 827 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 828 chp->ch_flags |= WDCF_ONESLAVE; 829 /* 830 * Wait a bit, some devices are weird just after a reset. 831 * Then issue a IDENTIFY command, to try to detect slave ghost. 832 */ 833 delay(5000); 834 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 835 CMD_OK) { 836 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 837 drvp->drive_flags &= ~DRIVE_OLD; 838 } else { 839 drvp->drive_flags &= 840 ~(DRIVE_ATA | DRIVE_ATAPI); 841 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 842 chp->wdc->sc_dev.dv_xname, 843 chp->channel, i), DEBUG_PROBE); 844 845 if ((drvp->drive_flags & DRIVE_OLD) && 846 !wdc_preata_drive(chp, i)) 847 drvp->drive_flags &= ~DRIVE_OLD; 848 } 849 } 850 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 851 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 852 853 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 854 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 855 DEBUG_PROBE); 856 857 /* If no drives, abort here */ 858 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 859 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 860 goto exit; 861 862 for (i = 0; i < 2; i++) { 863 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 864 continue; 865 } 866 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 867 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 868 aa_link.aa_type = T_ATAPI; 869 else 870 aa_link.aa_type = T_ATA; 871 aa_link.aa_channel = chp->channel; 872 aa_link.aa_openings = 1; 873 aa_link.aa_drv_data = &chp->ch_drive[i]; 874 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 875 } 876 877 /* 878 * reset drive_flags for unattached devices, reset state for attached 879 * ones 880 */ 881 for (i = 0; i < 2; i++) { 882 if (chp->ch_drive[i].drive_name[0] == 0) 883 chp->ch_drive[i].drive_flags = 0; 884 } 885 886 #ifndef __OpenBSD__ 887 wdc_delref(chp); 888 #endif 889 890 exit: 891 #ifdef WDCDEBUG 892 wdcdebug_mask = savedmask; 893 #endif 894 return; 895 } 896 897 /* 898 * Start I/O on a controller, for the given channel. 899 * The first xfer may be not for our channel if the channel queues 900 * are shared. 901 */ 902 void 903 wdcstart(chp) 904 struct channel_softc *chp; 905 { 906 struct wdc_xfer *xfer; 907 908 splassert(IPL_BIO); 909 910 /* is there a xfer ? */ 911 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) { 912 return; 913 } 914 915 /* adjust chp, in case we have a shared queue */ 916 chp = xfer->chp; 917 918 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 919 return; /* channel already active */ 920 } 921 #ifdef DIAGNOSTIC 922 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 923 panic("wdcstart: channel waiting for irq"); 924 #endif /* DIAGNOSTIC */ 925 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 926 if (!(chp->wdc->claim_hw)(chp, 0)) 927 return; 928 929 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 930 chp->channel, xfer->drive), DEBUG_XFERS); 931 chp->ch_flags |= WDCF_ACTIVE; 932 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 933 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 934 chp->ch_drive[xfer->drive].state = 0; 935 } 936 xfer->c_start(chp, xfer); 937 } 938 939 int 940 wdcdetach(chp, flags) 941 struct channel_softc *chp; 942 int flags; 943 { 944 int s, rv; 945 946 s = splbio(); 947 wdc_kill_pending(chp); 948 949 rv = config_detach_children((struct device *)chp->wdc, flags); 950 splx(s); 951 952 return (rv); 953 } 954 955 /* restart an interrupted I/O */ 956 void 957 wdcrestart(v) 958 void *v; 959 { 960 struct channel_softc *chp = v; 961 int s; 962 963 s = splbio(); 964 wdcstart(chp); 965 splx(s); 966 } 967 968 969 /* 970 * Interrupt routine for the controller. Acknowledge the interrupt, check for 971 * errors on the current operation, mark it done if necessary, and start the 972 * next request. Also check for a partially done transfer, and continue with 973 * the next chunk if so. 974 */ 975 int 976 wdcintr(arg) 977 void *arg; 978 { 979 struct channel_softc *chp = arg; 980 struct wdc_xfer *xfer; 981 int ret; 982 983 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 984 /* Acknowledge interrupt by reading status */ 985 if (chp->_vtbl == 0) { 986 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 987 wdr_status & _WDC_REGMASK); 988 } else { 989 CHP_READ_REG(chp, wdr_status); 990 } 991 992 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 993 return 0; 994 } 995 996 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 997 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 998 if (chp->ch_flags & WDCF_DMA_WAIT) { 999 chp->wdc->dma_status = 1000 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1001 xfer->drive, 0); 1002 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1003 /* IRQ not for us, not detected by DMA engine */ 1004 return 0; 1005 } 1006 chp->ch_flags &= ~WDCF_DMA_WAIT; 1007 } 1008 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1009 ret = xfer->c_intr(chp, xfer, 1); 1010 if (ret == 0) /* irq was not for us, still waiting for irq */ 1011 chp->ch_flags |= WDCF_IRQ_WAIT; 1012 return (ret); 1013 } 1014 1015 /* Put all disk in RESET state */ 1016 void wdc_reset_channel(drvp) 1017 struct ata_drive_datas *drvp; 1018 { 1019 struct channel_softc *chp = drvp->chnl_softc; 1020 int drive; 1021 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1022 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1023 DEBUG_FUNCS); 1024 (void) wdcreset(chp, VERBOSE); 1025 for (drive = 0; drive < 2; drive++) { 1026 chp->ch_drive[drive].state = 0; 1027 } 1028 } 1029 1030 int 1031 wdcreset(chp, verb) 1032 struct channel_softc *chp; 1033 int verb; 1034 { 1035 int drv_mask1, drv_mask2; 1036 1037 if (!chp->_vtbl) 1038 chp->_vtbl = &wdc_default_vtbl; 1039 1040 __wdcdo_reset(chp); 1041 1042 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1043 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1044 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 1045 if (verb && drv_mask2 != drv_mask1) { 1046 printf("%s channel %d: reset failed for", 1047 chp->wdc->sc_dev.dv_xname, chp->channel); 1048 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1049 printf(" drive 0"); 1050 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1051 printf(" drive 1"); 1052 printf("\n"); 1053 } 1054 1055 return (drv_mask1 != drv_mask2) ? 1 : 0; 1056 } 1057 1058 void 1059 __wdcdo_reset(struct channel_softc *chp) 1060 { 1061 wdc_set_drive(chp, 0); 1062 DELAY(10); 1063 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT | WDCTL_RST); 1064 delay(10000); 1065 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 1066 delay(10000); 1067 } 1068 1069 int 1070 __wdcwait_reset(chp, drv_mask) 1071 struct channel_softc *chp; 1072 int drv_mask; 1073 { 1074 int timeout; 1075 u_int8_t st0, er0, st1, er1; 1076 1077 /* wait for BSY to deassert */ 1078 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 1079 wdc_set_drive(chp, 0); 1080 delay(10); 1081 st0 = CHP_READ_REG(chp, wdr_status); 1082 er0 = CHP_READ_REG(chp, wdr_error); 1083 wdc_set_drive(chp, 1); 1084 delay(10); 1085 st1 = CHP_READ_REG(chp, wdr_status); 1086 er1 = CHP_READ_REG(chp, wdr_error); 1087 1088 if ((drv_mask & 0x01) == 0) { 1089 /* no master */ 1090 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1091 /* No master, slave is ready, it's done */ 1092 goto end; 1093 } 1094 } else if ((drv_mask & 0x02) == 0) { 1095 /* no slave */ 1096 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1097 /* No slave, master is ready, it's done */ 1098 goto end; 1099 } 1100 } else { 1101 /* Wait for both master and slave to be ready */ 1102 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1103 goto end; 1104 } 1105 } 1106 delay(WDCDELAY); 1107 } 1108 /* Reset timed out. Maybe it's because drv_mask was not right */ 1109 if (st0 & WDCS_BSY) 1110 drv_mask &= ~0x01; 1111 if (st1 & WDCS_BSY) 1112 drv_mask &= ~0x02; 1113 end: 1114 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, er0=0x%x, " 1115 "st1=0x%x, er1=0x%x, reset time=%d msec\n", 1116 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1117 st0, er0, st1, er1, timeout * WDCDELAY / 1000), DEBUG_PROBE); 1118 1119 return drv_mask; 1120 } 1121 1122 /* 1123 * Wait for a drive to be !BSY, and have mask in its status register. 1124 * return -1 for a timeout after "timeout" ms. 1125 */ 1126 int 1127 wdc_wait_for_status(chp, mask, bits, timeout) 1128 struct channel_softc *chp; 1129 int mask, bits, timeout; 1130 { 1131 u_char status; 1132 int time = 0; 1133 1134 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1135 :"none", chp->channel), DEBUG_STATUS); 1136 chp->ch_error = 0; 1137 1138 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1139 1140 for (;;) { 1141 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 1142 WDC_LOG_STATUS(chp, chp->ch_status); 1143 1144 if (status == 0xff && (chp->ch_flags & WDCF_ONESLAVE)) { 1145 wdc_set_drive(chp, 1); 1146 chp->ch_status = status = 1147 CHP_READ_REG(chp, wdr_status); 1148 WDC_LOG_STATUS(chp, chp->ch_status); 1149 } 1150 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 1151 break; 1152 if (++time > timeout) { 1153 WDCDEBUG_PRINT(("wdcwait: timeout, status 0x%x " 1154 "error 0x%x\n", status, 1155 CHP_READ_REG(chp, wdr_error)), 1156 DEBUG_STATUSX | DEBUG_STATUS); 1157 return -1; 1158 } 1159 delay(WDCDELAY); 1160 } 1161 if (status & WDCS_ERR) { 1162 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1163 WDC_LOG_ERROR(chp, chp->ch_error); 1164 1165 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1166 DEBUG_STATUSX | DEBUG_STATUS); 1167 } 1168 1169 #ifdef WDCNDELAY_DEBUG 1170 /* After autoconfig, there should be no long delays. */ 1171 if (!cold && time > WDCNDELAY_DEBUG) { 1172 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1173 if (xfer == NULL) 1174 printf("%s channel %d: warning: busy-wait took %dus\n", 1175 chp->wdc->sc_dev.dv_xname, chp->channel, 1176 WDCDELAY * time); 1177 else 1178 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1179 chp->wdc->sc_dev.dv_xname, chp->channel, 1180 xfer->drive, 1181 WDCDELAY * time); 1182 } 1183 #endif /* WDCNDELAY_DEBUG */ 1184 return time; 1185 } 1186 1187 /* 1188 * Busy-wait for DMA to complete 1189 */ 1190 int 1191 wdc_dmawait(chp, xfer, timeout) 1192 struct channel_softc *chp; 1193 struct wdc_xfer *xfer; 1194 int timeout; 1195 { 1196 int time; 1197 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1198 chp->wdc->dma_status = 1199 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1200 chp->channel, xfer->drive, 0); 1201 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1202 return 0; 1203 delay(WDCDELAY); 1204 } 1205 /* timeout, force a DMA halt */ 1206 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1207 chp->channel, xfer->drive, 1); 1208 return 1; 1209 } 1210 1211 void 1212 wdctimeout(arg) 1213 void *arg; 1214 { 1215 struct channel_softc *chp = (struct channel_softc *)arg; 1216 struct wdc_xfer *xfer; 1217 int s; 1218 1219 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1220 1221 s = splbio(); 1222 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1223 1224 /* Did we lose a race with the interrupt? */ 1225 if (xfer == NULL || 1226 !timeout_triggered(&chp->ch_timo)) { 1227 splx(s); 1228 return; 1229 } 1230 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1231 __wdcerror(chp, "timeout"); 1232 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1233 "atapi":"ata"); 1234 printf("\tc_bcount: %d\n", xfer->c_bcount); 1235 printf("\tc_skip: %d\n", xfer->c_skip); 1236 if (chp->ch_flags & WDCF_DMA_WAIT) { 1237 chp->wdc->dma_status = 1238 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1239 chp->channel, xfer->drive, 1); 1240 chp->ch_flags &= ~WDCF_DMA_WAIT; 1241 } 1242 /* 1243 * Call the interrupt routine. If we just missed and interrupt, 1244 * it will do what's needed. Else, it will take the needed 1245 * action (reset the device). 1246 */ 1247 xfer->c_flags |= C_TIMEOU; 1248 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1249 xfer->c_intr(chp, xfer, 1); 1250 } else 1251 __wdcerror(chp, "missing untimeout"); 1252 splx(s); 1253 } 1254 1255 /* 1256 * Probe drive's capabilities, for use by the controller later. 1257 * Assumes drvp points to an existing drive. 1258 * XXX this should be a controller-indep function 1259 */ 1260 void 1261 wdc_probe_caps(drvp, params) 1262 struct ata_drive_datas *drvp; 1263 struct ataparams *params; 1264 { 1265 struct channel_softc *chp = drvp->chnl_softc; 1266 struct wdc_softc *wdc = chp->wdc; 1267 int i, valid_mode_found; 1268 int cf_flags = drvp->cf_flags; 1269 1270 if ((wdc->cap & WDC_CAPABILITY_SATA) != 0 && 1271 (params->atap_sata_caps != 0x0000 && 1272 params->atap_sata_caps != 0xffff)) { 1273 WDCDEBUG_PRINT(("%s: atap_sata_caps=0x%x\n", __func__, 1274 params->atap_sata_caps), DEBUG_PROBE); 1275 1276 /* Skip ATA modes detection for native SATA drives */ 1277 drvp->PIO_mode = drvp->PIO_cap = 4; 1278 drvp->DMA_mode = drvp->DMA_cap = 2; 1279 drvp->UDMA_mode = drvp->UDMA_cap = 5; 1280 drvp->drive_flags |= DRIVE_SATA | DRIVE_MODE | DRIVE_UDMA; 1281 drvp->ata_vers = 4; 1282 return; 1283 } 1284 1285 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1286 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1287 struct ataparams params2; 1288 1289 /* 1290 * Controller claims 16 and 32 bit transfers. 1291 * Re-do an IDENTIFY with 32-bit transfers, 1292 * and compare results. 1293 */ 1294 drvp->drive_flags |= DRIVE_CAP32; 1295 ata_get_params(drvp, at_poll, ¶ms2); 1296 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1297 /* Not good. fall back to 16bits */ 1298 drvp->drive_flags &= ~DRIVE_CAP32; 1299 } 1300 } 1301 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1302 if (params->atap_ata_major > 0x01 && 1303 params->atap_ata_major != 0xffff) { 1304 for (i = 14; i > 0; i--) { 1305 if (params->atap_ata_major & (1 << i)) { 1306 printf("%sATA version %d\n", sep, i); 1307 drvp->ata_vers = i; 1308 break; 1309 } 1310 } 1311 } else 1312 #endif /* 0 */ 1313 /* Use PIO mode 3 as a default value for ATAPI devices */ 1314 if (drvp->drive_flags & DRIVE_ATAPI) 1315 drvp->PIO_mode = 3; 1316 1317 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap 0x%x cf_flags 0x%x\n", 1318 wdc->cap, cf_flags), DEBUG_PROBE); 1319 1320 valid_mode_found = 0; 1321 1322 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__, 1323 params->atap_oldpiotiming), DEBUG_PROBE); 1324 /* 1325 * ATA-4 compliant devices contain PIO mode 1326 * number in atap_oldpiotiming. 1327 */ 1328 if (params->atap_oldpiotiming <= 2) { 1329 drvp->PIO_cap = params->atap_oldpiotiming; 1330 valid_mode_found = 1; 1331 drvp->drive_flags |= DRIVE_MODE; 1332 } else if (params->atap_oldpiotiming > 180) { 1333 /* 1334 * ATA-2 compliant devices contain cycle 1335 * time in atap_oldpiotiming. 1336 * A device with a cycle time of 180ns 1337 * or less is at least PIO mode 3 and 1338 * should be reporting that in 1339 * atap_piomode_supp, so ignore it here. 1340 */ 1341 if (params->atap_oldpiotiming <= 240) { 1342 drvp->PIO_cap = 2; 1343 } else { 1344 drvp->PIO_cap = 1; 1345 } 1346 valid_mode_found = 1; 1347 drvp->drive_flags |= DRIVE_MODE; 1348 } 1349 if (valid_mode_found) 1350 drvp->PIO_mode = drvp->PIO_cap; 1351 1352 WDCDEBUG_PRINT(("%s: atap_extensions=0x%x, atap_piomode_supp=0x%x, " 1353 "atap_dmamode_supp=0x%x, atap_udmamode_supp=0x%x\n", 1354 __func__, params->atap_extensions, params->atap_piomode_supp, 1355 params->atap_dmamode_supp, params->atap_udmamode_supp), 1356 DEBUG_PROBE); 1357 1358 /* 1359 * It's not in the specs, but it seems that some drive 1360 * returns 0xffff in atap_extensions when this field is invalid 1361 */ 1362 if (params->atap_extensions != 0xffff && 1363 (params->atap_extensions & WDC_EXT_MODES)) { 1364 /* 1365 * XXX some drives report something wrong here (they claim to 1366 * support PIO mode 8 !). As mode is coded on 3 bits in 1367 * SET FEATURE, limit it to 7 (so limit i to 4). 1368 * If higher mode than 7 is found, abort. 1369 */ 1370 for (i = 7; i >= 0; i--) { 1371 if ((params->atap_piomode_supp & (1 << i)) == 0) 1372 continue; 1373 if (i > 4) 1374 return; 1375 1376 valid_mode_found = 1; 1377 1378 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1379 drvp->PIO_cap = i + 3; 1380 continue; 1381 } 1382 1383 /* 1384 * See if mode is accepted. 1385 * If the controller can't set its PIO mode, 1386 * assume the BIOS set it up correctly 1387 */ 1388 if (ata_set_mode(drvp, 0x08 | (i + 3), 1389 at_poll) != CMD_OK) 1390 continue; 1391 1392 /* 1393 * If controller's driver can't set its PIO mode, 1394 * set the highest one the controller supports 1395 */ 1396 if (wdc->PIO_cap >= i + 3) { 1397 drvp->PIO_mode = i + 3; 1398 drvp->PIO_cap = i + 3; 1399 break; 1400 } 1401 } 1402 if (!valid_mode_found) { 1403 /* 1404 * We didn't find a valid PIO mode. 1405 * Assume the values returned for DMA are buggy too 1406 */ 1407 return; 1408 } 1409 drvp->drive_flags |= DRIVE_MODE; 1410 1411 /* Some controllers don't support ATAPI DMA */ 1412 if ((drvp->drive_flags & DRIVE_ATAPI) && 1413 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1414 return; 1415 1416 valid_mode_found = 0; 1417 for (i = 7; i >= 0; i--) { 1418 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1419 continue; 1420 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1421 (wdc->cap & WDC_CAPABILITY_MODE)) 1422 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1423 != CMD_OK) 1424 continue; 1425 1426 valid_mode_found = 1; 1427 1428 if (wdc->cap & WDC_CAPABILITY_DMA) { 1429 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1430 wdc->DMA_cap < i) 1431 continue; 1432 drvp->DMA_mode = i; 1433 drvp->DMA_cap = i; 1434 drvp->drive_flags |= DRIVE_DMA; 1435 } 1436 break; 1437 } 1438 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1439 for (i = 7; i >= 0; i--) { 1440 if ((params->atap_udmamode_supp & (1 << i)) 1441 == 0) 1442 continue; 1443 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1444 (wdc->cap & WDC_CAPABILITY_UDMA)) 1445 if (ata_set_mode(drvp, 0x40 | i, 1446 at_poll) != CMD_OK) 1447 continue; 1448 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1449 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1450 wdc->UDMA_cap < i) 1451 continue; 1452 drvp->UDMA_mode = i; 1453 drvp->UDMA_cap = i; 1454 drvp->drive_flags |= DRIVE_UDMA; 1455 } 1456 break; 1457 } 1458 } 1459 } 1460 1461 /* Try to guess ATA version here, if it didn't get reported */ 1462 if (drvp->ata_vers == 0) { 1463 if (drvp->drive_flags & DRIVE_UDMA) 1464 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1465 else if (drvp->PIO_cap > 2) 1466 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1467 } 1468 if (cf_flags & ATA_CONFIG_PIO_SET) { 1469 drvp->PIO_mode = 1470 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1471 drvp->drive_flags |= DRIVE_MODE; 1472 } 1473 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1474 /* don't care about DMA modes */ 1475 return; 1476 } 1477 if (cf_flags & ATA_CONFIG_DMA_SET) { 1478 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1479 ATA_CONFIG_DMA_DISABLE) { 1480 drvp->drive_flags &= ~DRIVE_DMA; 1481 } else { 1482 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1483 ATA_CONFIG_DMA_OFF; 1484 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1485 } 1486 } 1487 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1488 /* don't care about UDMA modes */ 1489 return; 1490 } 1491 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1492 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1493 ATA_CONFIG_UDMA_DISABLE) { 1494 drvp->drive_flags &= ~DRIVE_UDMA; 1495 } else { 1496 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1497 ATA_CONFIG_UDMA_OFF; 1498 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1499 } 1500 } 1501 } 1502 1503 void 1504 wdc_output_bytes(drvp, bytes, buflen) 1505 struct ata_drive_datas *drvp; 1506 void *bytes; 1507 unsigned int buflen; 1508 { 1509 struct channel_softc *chp = drvp->chnl_softc; 1510 unsigned int off = 0; 1511 unsigned int len = buflen, roundlen; 1512 1513 if (drvp->drive_flags & DRIVE_CAP32) { 1514 roundlen = len & ~3; 1515 1516 CHP_WRITE_RAW_MULTI_4(chp, 1517 (void *)((u_int8_t *)bytes + off), roundlen); 1518 1519 off += roundlen; 1520 len -= roundlen; 1521 } 1522 1523 if (len > 0) { 1524 roundlen = (len + 1) & ~0x1; 1525 1526 CHP_WRITE_RAW_MULTI_2(chp, 1527 (void *)((u_int8_t *)bytes + off), roundlen); 1528 } 1529 1530 return; 1531 } 1532 1533 void 1534 wdc_input_bytes(drvp, bytes, buflen) 1535 struct ata_drive_datas *drvp; 1536 void *bytes; 1537 unsigned int buflen; 1538 { 1539 struct channel_softc *chp = drvp->chnl_softc; 1540 unsigned int off = 0; 1541 unsigned int len = buflen, roundlen; 1542 1543 if (drvp->drive_flags & DRIVE_CAP32) { 1544 roundlen = len & ~3; 1545 1546 CHP_READ_RAW_MULTI_4(chp, 1547 (void *)((u_int8_t *)bytes + off), roundlen); 1548 1549 off += roundlen; 1550 len -= roundlen; 1551 } 1552 1553 if (len > 0) { 1554 roundlen = (len + 1) & ~0x1; 1555 1556 CHP_READ_RAW_MULTI_2(chp, 1557 (void *)((u_int8_t *)bytes + off), roundlen); 1558 } 1559 1560 return; 1561 } 1562 1563 void 1564 wdc_print_caps(drvp) 1565 struct ata_drive_datas *drvp; 1566 { 1567 /* This is actually a lie until we fix the _probe_caps 1568 algorithm. Don't print out lies */ 1569 #if 0 1570 printf("%s: can use ", drvp->drive_name); 1571 1572 if (drvp->drive_flags & DRIVE_CAP32) { 1573 printf("32-bit"); 1574 } else 1575 printf("16-bit"); 1576 1577 printf(", PIO mode %d", drvp->PIO_cap); 1578 1579 if (drvp->drive_flags & DRIVE_DMA) { 1580 printf(", DMA mode %d", drvp->DMA_cap); 1581 } 1582 1583 if (drvp->drive_flags & DRIVE_UDMA) { 1584 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1585 } 1586 1587 printf("\n"); 1588 #endif /* 0 */ 1589 } 1590 1591 void 1592 wdc_print_current_modes(chp) 1593 struct channel_softc *chp; 1594 { 1595 int drive; 1596 struct ata_drive_datas *drvp; 1597 1598 for (drive = 0; drive < 2; drive++) { 1599 drvp = &chp->ch_drive[drive]; 1600 if ((drvp->drive_flags & DRIVE) == 0) 1601 continue; 1602 1603 printf("%s(%s:%d:%d):", 1604 drvp->drive_name, 1605 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1606 1607 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1608 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1609 printf(" using BIOS timings"); 1610 else 1611 printf(" using PIO mode %d", drvp->PIO_mode); 1612 if (drvp->drive_flags & DRIVE_DMA) 1613 printf(", DMA mode %d", drvp->DMA_mode); 1614 if (drvp->drive_flags & DRIVE_UDMA) 1615 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1616 printf("\n"); 1617 } 1618 } 1619 1620 /* 1621 * downgrade the transfer mode of a drive after an error. return 1 if 1622 * downgrade was possible, 0 otherwise. 1623 */ 1624 int 1625 wdc_downgrade_mode(drvp) 1626 struct ata_drive_datas *drvp; 1627 { 1628 struct channel_softc *chp = drvp->chnl_softc; 1629 struct wdc_softc *wdc = chp->wdc; 1630 int cf_flags = drvp->cf_flags; 1631 1632 /* if drive or controller don't know its mode, we can't do much */ 1633 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1634 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1635 return 0; 1636 /* current drive mode was set by a config flag, let it this way */ 1637 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1638 (cf_flags & ATA_CONFIG_DMA_SET) || 1639 (cf_flags & ATA_CONFIG_UDMA_SET)) 1640 return 0; 1641 1642 /* 1643 * We'd ideally like to use an Ultra DMA mode since they have the 1644 * protection of a CRC. So we try each Ultra DMA mode and see if 1645 * we can find any working combo 1646 */ 1647 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1648 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1649 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1650 drvp->drive_name, drvp->UDMA_mode); 1651 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1652 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1653 /* 1654 * If we were using ultra-DMA, don't downgrade to 1655 * multiword DMA if we noticed a CRC error. It has 1656 * been noticed that CRC errors in ultra-DMA lead to 1657 * silent data corruption in multiword DMA. Data 1658 * corruption is less likely to occur in PIO mode. 1659 */ 1660 drvp->drive_flags &= ~DRIVE_UDMA; 1661 drvp->drive_flags |= DRIVE_DMA; 1662 drvp->DMA_mode = drvp->DMA_cap; 1663 printf("%s: transfer error, downgrading to DMA mode %d\n", 1664 drvp->drive_name, drvp->DMA_mode); 1665 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1666 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1667 drvp->PIO_mode = drvp->PIO_cap; 1668 printf("%s: transfer error, downgrading to PIO mode %d\n", 1669 drvp->drive_name, drvp->PIO_mode); 1670 } else /* already using PIO, can't downgrade */ 1671 return 0; 1672 1673 wdc->set_modes(chp); 1674 /* reset the channel, which will schedule all drives for setup */ 1675 wdc_reset_channel(drvp); 1676 return 1; 1677 } 1678 1679 int 1680 wdc_exec_command(drvp, wdc_c) 1681 struct ata_drive_datas *drvp; 1682 struct wdc_command *wdc_c; 1683 { 1684 struct channel_softc *chp = drvp->chnl_softc; 1685 struct wdc_xfer *xfer; 1686 int s, ret; 1687 1688 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1689 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1690 DEBUG_FUNCS); 1691 1692 /* set up an xfer and queue. Wait for completion */ 1693 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1694 WDC_NOSLEEP); 1695 if (xfer == NULL) { 1696 return WDC_TRY_AGAIN; 1697 } 1698 1699 if (wdc_c->flags & AT_POLL) 1700 xfer->c_flags |= C_POLL; 1701 xfer->drive = drvp->drive; 1702 xfer->databuf = wdc_c->data; 1703 xfer->c_bcount = wdc_c->bcount; 1704 xfer->cmd = wdc_c; 1705 xfer->c_start = __wdccommand_start; 1706 xfer->c_intr = __wdccommand_intr; 1707 xfer->c_kill_xfer = __wdccommand_done; 1708 1709 s = splbio(); 1710 wdc_exec_xfer(chp, xfer); 1711 #ifdef DIAGNOSTIC 1712 if ((wdc_c->flags & AT_POLL) != 0 && 1713 (wdc_c->flags & AT_DONE) == 0) 1714 panic("wdc_exec_command: polled command not done"); 1715 #endif /* DIAGNOSTIC */ 1716 if (wdc_c->flags & AT_DONE) { 1717 ret = WDC_COMPLETE; 1718 } else { 1719 if (wdc_c->flags & AT_WAIT) { 1720 WDCDEBUG_PRINT(("wdc_exec_command sleeping"), 1721 DEBUG_FUNCS); 1722 1723 while ((wdc_c->flags & AT_DONE) == 0) { 1724 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1725 } 1726 ret = WDC_COMPLETE; 1727 } else { 1728 ret = WDC_QUEUED; 1729 } 1730 } 1731 splx(s); 1732 return ret; 1733 } 1734 1735 void 1736 __wdccommand_start(chp, xfer) 1737 struct channel_softc *chp; 1738 struct wdc_xfer *xfer; 1739 { 1740 int drive = xfer->drive; 1741 struct wdc_command *wdc_c = xfer->cmd; 1742 1743 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1744 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1745 DEBUG_FUNCS); 1746 1747 /* 1748 * Disable interrupts if we're polling 1749 */ 1750 if (xfer->c_flags & C_POLL) { 1751 wdc_disable_intr(chp); 1752 } 1753 1754 wdc_set_drive(chp, drive); 1755 DELAY(1); 1756 1757 /* 1758 * For resets, we don't really care to make sure that 1759 * the bus is free 1760 */ 1761 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1762 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1763 wdc_c->r_st_bmask, wdc_c->timeout) != 0) { 1764 goto timeout; 1765 } 1766 } else 1767 DELAY(10); 1768 1769 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1770 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1771 1772 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) { 1773 /* wait at least 400ns before reading status register */ 1774 DELAY(10); 1775 if (wait_for_unbusy(chp, wdc_c->timeout) != 0) 1776 goto timeout; 1777 1778 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) { 1779 __wdccommand_done(chp, xfer); 1780 return; 1781 } 1782 1783 if (wait_for_drq(chp, wdc_c->timeout) != 0) 1784 goto timeout; 1785 1786 wdc_output_bytes(&chp->ch_drive[drive], 1787 wdc_c->data, wdc_c->bcount); 1788 } 1789 1790 if ((wdc_c->flags & AT_POLL) == 0) { 1791 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1792 timeout_add(&chp->ch_timo, wdc_c->timeout / 1000 * hz); 1793 return; 1794 } 1795 1796 /* 1797 * Polled command. Wait for drive ready or drq. Done in intr(). 1798 * Wait for at last 400ns for status bit to be valid. 1799 */ 1800 delay(10); 1801 __wdccommand_intr(chp, xfer, 0); 1802 return; 1803 1804 timeout: 1805 wdc_c->flags |= AT_TIMEOU; 1806 __wdccommand_done(chp, xfer); 1807 } 1808 1809 int 1810 __wdccommand_intr(chp, xfer, irq) 1811 struct channel_softc *chp; 1812 struct wdc_xfer *xfer; 1813 int irq; 1814 { 1815 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1816 struct wdc_command *wdc_c = xfer->cmd; 1817 int bcount = wdc_c->bcount; 1818 char *data = wdc_c->data; 1819 1820 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1821 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1822 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1823 (irq == 0) ? wdc_c->timeout : 0)) { 1824 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1825 return 0; /* IRQ was not for us */ 1826 wdc_c->flags |= AT_TIMEOU; 1827 goto out; 1828 } 1829 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1830 chp->wdc->irqack(chp); 1831 if (wdc_c->flags & AT_READ) { 1832 if ((chp->ch_status & WDCS_DRQ) == 0) { 1833 wdc_c->flags |= AT_TIMEOU; 1834 goto out; 1835 } 1836 wdc_input_bytes(drvp, data, bcount); 1837 /* Should we wait for device to indicate idle? */ 1838 } 1839 out: 1840 __wdccommand_done(chp, xfer); 1841 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1842 return 1; 1843 } 1844 1845 void 1846 __wdccommand_done(chp, xfer) 1847 struct channel_softc *chp; 1848 struct wdc_xfer *xfer; 1849 { 1850 struct wdc_command *wdc_c = xfer->cmd; 1851 1852 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1853 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 1854 chp->ch_status), DEBUG_FUNCS); 1855 if (chp->ch_status & WDCS_DWF) 1856 wdc_c->flags |= AT_DF; 1857 if (chp->ch_status & WDCS_ERR) { 1858 wdc_c->flags |= AT_ERROR; 1859 wdc_c->r_error = chp->ch_error; 1860 } 1861 wdc_c->flags |= AT_DONE; 1862 if ((wdc_c->flags & AT_READREG) != 0 && 1863 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1864 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1865 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1866 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1867 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1868 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1869 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1870 wdc_c->r_precomp = wdc_c->r_error; 1871 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1872 isn't a readable register */ 1873 } 1874 1875 if (xfer->c_flags & C_POLL) { 1876 wdc_enable_intr(chp); 1877 } 1878 1879 wdc_free_xfer(chp, xfer); 1880 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1881 1882 if (wdc_c->flags & AT_WAIT) 1883 wakeup(wdc_c); 1884 else 1885 if (wdc_c->callback) 1886 wdc_c->callback(wdc_c->callback_arg); 1887 wdcstart(chp); 1888 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1889 } 1890 1891 /* 1892 * Send a command. The drive should be ready. 1893 * Assumes interrupts are blocked. 1894 */ 1895 void 1896 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1897 struct channel_softc *chp; 1898 u_int8_t drive; 1899 u_int8_t command; 1900 u_int16_t cylin; 1901 u_int8_t head, sector, count, precomp; 1902 { 1903 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1904 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1905 chp->channel, drive, command, cylin, head, sector, count, precomp), 1906 DEBUG_FUNCS); 1907 WDC_LOG_ATA_CMDLONG(chp, head, precomp, cylin, cylin >> 8, sector, 1908 count, command); 1909 1910 /* Select drive, head, and addressing mode. */ 1911 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1912 1913 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1914 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1915 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1916 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1917 CHP_WRITE_REG(chp, wdr_sector, sector); 1918 CHP_WRITE_REG(chp, wdr_seccnt, count); 1919 1920 /* Send command. */ 1921 CHP_WRITE_REG(chp, wdr_command, command); 1922 return; 1923 } 1924 1925 /* 1926 * Send a 48-bit addressing command. The drive should be ready. 1927 * Assumes interrupts are blocked. 1928 */ 1929 void 1930 wdccommandext(chp, drive, command, blkno, count) 1931 struct channel_softc *chp; 1932 u_int8_t drive; 1933 u_int8_t command; 1934 u_int64_t blkno; 1935 u_int16_t count; 1936 { 1937 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu " 1938 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1939 chp->channel, drive, command, blkno, count), 1940 DEBUG_FUNCS); 1941 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32, 1942 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command); 1943 1944 /* Select drive and LBA mode. */ 1945 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA); 1946 1947 /* Load parameters. All registers are two byte deep FIFOs. */ 1948 CHP_WRITE_REG(chp, wdr_lba_hi, blkno >> 40); 1949 CHP_WRITE_REG(chp, wdr_lba_hi, blkno >> 16); 1950 CHP_WRITE_REG(chp, wdr_lba_mi, blkno >> 32); 1951 CHP_WRITE_REG(chp, wdr_lba_mi, blkno >> 8); 1952 CHP_WRITE_REG(chp, wdr_lba_lo, blkno >> 24); 1953 CHP_WRITE_REG(chp, wdr_lba_lo, blkno); 1954 CHP_WRITE_REG(chp, wdr_seccnt, count >> 8); 1955 CHP_WRITE_REG(chp, wdr_seccnt, count); 1956 1957 /* Send command. */ 1958 CHP_WRITE_REG(chp, wdr_command, command); 1959 return; 1960 } 1961 1962 /* 1963 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1964 * tested by the caller. 1965 */ 1966 void 1967 wdccommandshort(chp, drive, command) 1968 struct channel_softc *chp; 1969 int drive; 1970 int command; 1971 { 1972 1973 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1974 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1975 DEBUG_FUNCS); 1976 WDC_LOG_ATA_CMDSHORT(chp, command); 1977 1978 /* Select drive. */ 1979 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1980 CHP_WRITE_REG(chp, wdr_command, command); 1981 } 1982 1983 /* Add a command to the queue and start controller. Must be called at splbio */ 1984 1985 void 1986 wdc_exec_xfer(chp, xfer) 1987 struct channel_softc *chp; 1988 struct wdc_xfer *xfer; 1989 { 1990 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1991 chp->channel, xfer->drive), DEBUG_XFERS); 1992 1993 /* complete xfer setup */ 1994 xfer->chp = chp; 1995 1996 /* 1997 * If we are a polled command, and the list is not empty, 1998 * we are doing a dump. Drop the list to allow the polled command 1999 * to complete, we're going to reboot soon anyway. 2000 */ 2001 if ((xfer->c_flags & C_POLL) != 0 && 2002 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) { 2003 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2004 } 2005 /* insert at the end of command list */ 2006 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2007 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2008 chp->ch_flags), DEBUG_XFERS); 2009 wdcstart(chp); 2010 } 2011 2012 struct wdc_xfer * 2013 wdc_get_xfer(flags) 2014 int flags; 2015 { 2016 struct wdc_xfer *xfer; 2017 int s; 2018 2019 s = splbio(); 2020 xfer = pool_get(&wdc_xfer_pool, 2021 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2022 splx(s); 2023 if (xfer != NULL) 2024 memset(xfer, 0, sizeof(struct wdc_xfer)); 2025 return xfer; 2026 } 2027 2028 void 2029 wdc_free_xfer(chp, xfer) 2030 struct channel_softc *chp; 2031 struct wdc_xfer *xfer; 2032 { 2033 struct wdc_softc *wdc = chp->wdc; 2034 int s; 2035 2036 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2037 (*wdc->free_hw)(chp); 2038 s = splbio(); 2039 chp->ch_flags &= ~WDCF_ACTIVE; 2040 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2041 pool_put(&wdc_xfer_pool, xfer); 2042 splx(s); 2043 } 2044 2045 2046 /* 2047 * Kill off all pending xfers for a channel_softc. 2048 * 2049 * Must be called at splbio(). 2050 */ 2051 void 2052 wdc_kill_pending(chp) 2053 struct channel_softc *chp; 2054 { 2055 struct wdc_xfer *xfer; 2056 2057 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2058 chp = xfer->chp; 2059 (*xfer->c_kill_xfer)(chp, xfer); 2060 } 2061 } 2062 2063 void 2064 __wdcerror(chp, msg) 2065 struct channel_softc *chp; 2066 char *msg; 2067 { 2068 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 2069 if (xfer == NULL) 2070 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2071 msg); 2072 else 2073 printf("%s(%s:%d:%d): %s\n", 2074 chp->ch_drive[xfer->drive].drive_name, 2075 chp->wdc->sc_dev.dv_xname, 2076 chp->channel, xfer->drive, msg); 2077 } 2078 2079 /* 2080 * the bit bucket 2081 */ 2082 void 2083 wdcbit_bucket(chp, size) 2084 struct channel_softc *chp; 2085 int size; 2086 { 2087 CHP_READ_RAW_MULTI_2(chp, NULL, size); 2088 } 2089 2090 2091 #include <sys/ataio.h> 2092 #include <sys/file.h> 2093 #include <sys/buf.h> 2094 2095 /* 2096 * Glue necessary to hook ATAIOCCOMMAND into physio 2097 */ 2098 2099 struct wdc_ioctl { 2100 LIST_ENTRY(wdc_ioctl) wi_list; 2101 struct buf wi_bp; 2102 struct uio wi_uio; 2103 struct iovec wi_iov; 2104 atareq_t wi_atareq; 2105 struct ata_drive_datas *wi_drvp; 2106 }; 2107 2108 struct wdc_ioctl *wdc_ioctl_find(struct buf *); 2109 void wdc_ioctl_free(struct wdc_ioctl *); 2110 struct wdc_ioctl *wdc_ioctl_get(void); 2111 void wdc_ioctl_strategy(struct buf *); 2112 2113 LIST_HEAD(, wdc_ioctl) wi_head; 2114 2115 /* 2116 * Allocate space for a ioctl queue structure. Mostly taken from 2117 * scsipi_ioctl.c 2118 */ 2119 struct wdc_ioctl * 2120 wdc_ioctl_get() 2121 { 2122 struct wdc_ioctl *wi; 2123 int s; 2124 2125 wi = malloc(sizeof(struct wdc_ioctl), M_TEMP, M_WAITOK); 2126 bzero(wi, sizeof (struct wdc_ioctl)); 2127 s = splbio(); 2128 LIST_INSERT_HEAD(&wi_head, wi, wi_list); 2129 splx(s); 2130 return (wi); 2131 } 2132 2133 /* 2134 * Free an ioctl structure and remove it from our list 2135 */ 2136 2137 void 2138 wdc_ioctl_free(wi) 2139 struct wdc_ioctl *wi; 2140 { 2141 int s; 2142 2143 s = splbio(); 2144 LIST_REMOVE(wi, wi_list); 2145 splx(s); 2146 free(wi, M_TEMP); 2147 } 2148 2149 /* 2150 * Find a wdc_ioctl structure based on the struct buf. 2151 */ 2152 2153 struct wdc_ioctl * 2154 wdc_ioctl_find(bp) 2155 struct buf *bp; 2156 { 2157 struct wdc_ioctl *wi; 2158 int s; 2159 2160 s = splbio(); 2161 LIST_FOREACH(wi, &wi_head, wi_list) 2162 if (bp == &wi->wi_bp) 2163 break; 2164 splx(s); 2165 return (wi); 2166 } 2167 2168 /* 2169 * Ioctl pseudo strategy routine 2170 * 2171 * This is mostly stolen from scsipi_ioctl.c:scsistrategy(). What 2172 * happens here is: 2173 * 2174 * - wdioctl() queues a wdc_ioctl structure. 2175 * 2176 * - wdioctl() calls physio/wdc_ioctl_strategy based on whether or not 2177 * user space I/O is required. If physio() is called, physio() eventually 2178 * calls wdc_ioctl_strategy(). 2179 * 2180 * - In either case, wdc_ioctl_strategy() calls wdc_exec_command() 2181 * to perform the actual command 2182 * 2183 * The reason for the use of the pseudo strategy routine is because 2184 * when doing I/O to/from user space, physio _really_ wants to be in 2185 * the loop. We could put the entire buffer into the ioctl request 2186 * structure, but that won't scale if we want to do things like download 2187 * microcode. 2188 */ 2189 2190 void 2191 wdc_ioctl_strategy(bp) 2192 struct buf *bp; 2193 { 2194 struct wdc_ioctl *wi; 2195 struct wdc_command wdc_c; 2196 int error = 0; 2197 int s; 2198 2199 wi = wdc_ioctl_find(bp); 2200 if (wi == NULL) { 2201 printf("user_strat: No ioctl\n"); 2202 error = EINVAL; 2203 goto bad; 2204 } 2205 2206 bzero(&wdc_c, sizeof(wdc_c)); 2207 2208 /* 2209 * Abort if physio broke up the transfer 2210 */ 2211 2212 if (bp->b_bcount != wi->wi_atareq.datalen) { 2213 printf("physio split wd ioctl request... cannot proceed\n"); 2214 error = EIO; 2215 goto bad; 2216 } 2217 2218 /* 2219 * Make sure a timeout was supplied in the ioctl request 2220 */ 2221 2222 if (wi->wi_atareq.timeout == 0) { 2223 error = EINVAL; 2224 goto bad; 2225 } 2226 2227 if (wi->wi_atareq.flags & ATACMD_READ) 2228 wdc_c.flags |= AT_READ; 2229 else if (wi->wi_atareq.flags & ATACMD_WRITE) 2230 wdc_c.flags |= AT_WRITE; 2231 2232 if (wi->wi_atareq.flags & ATACMD_READREG) 2233 wdc_c.flags |= AT_READREG; 2234 2235 wdc_c.flags |= AT_WAIT; 2236 2237 wdc_c.timeout = wi->wi_atareq.timeout; 2238 wdc_c.r_command = wi->wi_atareq.command; 2239 wdc_c.r_head = wi->wi_atareq.head & 0x0f; 2240 wdc_c.r_cyl = wi->wi_atareq.cylinder; 2241 wdc_c.r_sector = wi->wi_atareq.sec_num; 2242 wdc_c.r_count = wi->wi_atareq.sec_count; 2243 wdc_c.r_precomp = wi->wi_atareq.features; 2244 if (wi->wi_drvp->drive_flags & DRIVE_ATAPI) { 2245 wdc_c.r_st_bmask = 0; 2246 wdc_c.r_st_pmask = 0; 2247 if (wdc_c.r_command == WDCC_IDENTIFY) 2248 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 2249 } else { 2250 wdc_c.r_st_bmask = WDCS_DRDY; 2251 wdc_c.r_st_pmask = WDCS_DRDY; 2252 } 2253 wdc_c.data = wi->wi_bp.b_data; 2254 wdc_c.bcount = wi->wi_bp.b_bcount; 2255 2256 if (wdc_exec_command(wi->wi_drvp, &wdc_c) != WDC_COMPLETE) { 2257 wi->wi_atareq.retsts = ATACMD_ERROR; 2258 goto bad; 2259 } 2260 2261 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 2262 if (wdc_c.flags & AT_ERROR) { 2263 wi->wi_atareq.retsts = ATACMD_ERROR; 2264 wi->wi_atareq.error = wdc_c.r_error; 2265 } else if (wdc_c.flags & AT_DF) 2266 wi->wi_atareq.retsts = ATACMD_DF; 2267 else 2268 wi->wi_atareq.retsts = ATACMD_TIMEOUT; 2269 } else { 2270 wi->wi_atareq.retsts = ATACMD_OK; 2271 if (wi->wi_atareq.flags & ATACMD_READREG) { 2272 wi->wi_atareq.head = wdc_c.r_head ; 2273 wi->wi_atareq.cylinder = wdc_c.r_cyl; 2274 wi->wi_atareq.sec_num = wdc_c.r_sector; 2275 wi->wi_atareq.sec_count = wdc_c.r_count; 2276 wi->wi_atareq.features = wdc_c.r_precomp; 2277 wi->wi_atareq.error = wdc_c.r_error; 2278 } 2279 } 2280 2281 bp->b_error = 0; 2282 s = splbio(); 2283 biodone(bp); 2284 splx(s); 2285 return; 2286 bad: 2287 bp->b_flags |= B_ERROR; 2288 bp->b_error = error; 2289 s = splbio(); 2290 biodone(bp); 2291 splx(s); 2292 } 2293 2294 int 2295 wdc_ioctl(drvp, xfer, addr, flag, p) 2296 struct ata_drive_datas *drvp; 2297 u_long xfer; 2298 caddr_t addr; 2299 int flag; 2300 struct proc *p; 2301 { 2302 int error = 0; 2303 2304 switch (xfer) { 2305 case ATAIOGETTRACE: { 2306 atagettrace_t *agt = (atagettrace_t *)addr; 2307 unsigned int size = 0; 2308 char *log_to_copy; 2309 2310 size = agt->buf_size; 2311 if (size > 65536) { 2312 size = 65536; 2313 } 2314 2315 log_to_copy = wdc_get_log(&size, &agt->bytes_left); 2316 2317 if (log_to_copy != NULL) { 2318 error = copyout(log_to_copy, agt->buf, size); 2319 free(log_to_copy, M_TEMP); 2320 } 2321 2322 agt->bytes_copied = size; 2323 break; 2324 } 2325 2326 case ATAIOCCOMMAND: 2327 /* 2328 * Make sure this command is (relatively) safe first 2329 */ 2330 if ((((atareq_t *) addr)->flags & ATACMD_READ) == 0 && 2331 (flag & FWRITE) == 0) { 2332 error = EBADF; 2333 goto exit; 2334 } 2335 { 2336 struct wdc_ioctl *wi; 2337 atareq_t *atareq = (atareq_t *) addr; 2338 2339 wi = wdc_ioctl_get(); 2340 wi->wi_drvp = drvp; 2341 wi->wi_atareq = *atareq; 2342 2343 if (atareq->datalen && atareq->flags & 2344 (ATACMD_READ | ATACMD_WRITE)) { 2345 wi->wi_iov.iov_base = atareq->databuf; 2346 wi->wi_iov.iov_len = atareq->datalen; 2347 wi->wi_uio.uio_iov = &wi->wi_iov; 2348 wi->wi_uio.uio_iovcnt = 1; 2349 wi->wi_uio.uio_resid = atareq->datalen; 2350 wi->wi_uio.uio_offset = 0; 2351 wi->wi_uio.uio_segflg = UIO_USERSPACE; 2352 wi->wi_uio.uio_rw = 2353 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE; 2354 wi->wi_uio.uio_procp = curproc; 2355 error = physio(wdc_ioctl_strategy, &wi->wi_bp, 0, 2356 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE, 2357 minphys, &wi->wi_uio); 2358 } else { 2359 /* No need to call physio if we don't have any 2360 user data */ 2361 wi->wi_bp.b_flags = 0; 2362 wi->wi_bp.b_data = 0; 2363 wi->wi_bp.b_bcount = 0; 2364 wi->wi_bp.b_dev = 0; 2365 wi->wi_bp.b_proc = curproc; 2366 LIST_INIT(&wi->wi_bp.b_dep); 2367 wdc_ioctl_strategy(&wi->wi_bp); 2368 error = wi->wi_bp.b_error; 2369 } 2370 *atareq = wi->wi_atareq; 2371 wdc_ioctl_free(wi); 2372 goto exit; 2373 } 2374 default: 2375 error = ENOTTY; 2376 goto exit; 2377 } 2378 2379 exit: 2380 return (error); 2381 } 2382