1 /* $OpenBSD: wdc.c,v 1.125 2014/07/12 18:48:17 tedu Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/conf.h> 60 #include <sys/buf.h> 61 #include <sys/device.h> 62 #include <sys/malloc.h> 63 #include <sys/syslog.h> 64 #include <sys/proc.h> 65 #include <sys/disk.h> 66 #include <sys/pool.h> 67 68 #include <machine/intr.h> 69 #include <machine/bus.h> 70 71 #include <dev/ata/atavar.h> 72 #include <dev/ata/atareg.h> 73 #include <dev/ic/wdcreg.h> 74 #include <dev/ic/wdcvar.h> 75 #include <dev/ic/wdcevent.h> 76 77 #include <scsi/scsi_all.h> 78 #include <scsi/scsiconf.h> 79 80 #define WDCDELAY 100 /* 100 microseconds */ 81 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 82 #if 0 83 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 84 #define WDCNDELAY_DEBUG 50 85 #endif /* 0 */ 86 87 struct pool wdc_xfer_pool; 88 struct scsi_iopool wdc_xfer_iopool; 89 90 void * wdc_xfer_get(void *); 91 void wdc_xfer_put(void *, void *); 92 93 void __wdcerror(struct channel_softc *, char *); 94 int __wdcwait_reset(struct channel_softc *, int); 95 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *); 96 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *); 97 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int); 98 int wdprint(void *, const char *); 99 void wdc_kill_pending(struct channel_softc *); 100 101 #define DEBUG_INTR 0x01 102 #define DEBUG_XFERS 0x02 103 #define DEBUG_STATUS 0x04 104 #define DEBUG_FUNCS 0x08 105 #define DEBUG_PROBE 0x10 106 #define DEBUG_STATUSX 0x20 107 #define DEBUG_SDRIVE 0x40 108 #define DEBUG_DETACH 0x80 109 110 #ifdef WDCDEBUG 111 #ifndef WDCDEBUG_MASK 112 #define WDCDEBUG_MASK 0x00 113 #endif 114 int wdcdebug_mask = WDCDEBUG_MASK; 115 int wdc_nxfer = 0; 116 #define WDCDEBUG_PRINT(args, level) do { \ 117 if ((wdcdebug_mask & (level)) != 0) \ 118 printf args; \ 119 } while (0) 120 #else 121 #define WDCDEBUG_PRINT(args, level) 122 #endif /* WDCDEBUG */ 123 124 int at_poll = AT_POLL; 125 126 int wdc_floating_bus(struct channel_softc *, int); 127 int wdc_preata_drive(struct channel_softc *, int); 128 int wdc_ata_present(struct channel_softc *, int); 129 130 struct cfdriver wdc_cd = { 131 NULL, "wdc", DV_DULL 132 }; 133 134 struct channel_softc_vtbl wdc_default_vtbl = { 135 wdc_default_read_reg, 136 wdc_default_write_reg, 137 wdc_default_lba48_write_reg, 138 wdc_default_read_raw_multi_2, 139 wdc_default_write_raw_multi_2, 140 wdc_default_read_raw_multi_4, 141 wdc_default_write_raw_multi_4 142 }; 143 144 #ifdef WDCDEBUG 145 static char *wdc_log_buf = NULL; 146 static unsigned int wdc_tail = 0; 147 static unsigned int wdc_head = 0; 148 static unsigned int wdc_log_cap = 16 * 1024; 149 static int chp_idx = 1; 150 151 void 152 wdc_log(struct channel_softc *chp, enum wdcevent_type type, 153 unsigned int size, char val[]) 154 { 155 unsigned int request_size; 156 char *ptr; 157 int log_size; 158 unsigned int head = wdc_head; 159 unsigned int tail = wdc_tail; 160 161 #ifdef DIAGNOSTIC 162 if (head < 0 || head > wdc_log_cap || 163 tail < 0 || tail > wdc_log_cap) { 164 printf ("wdc_log: head %x wdc_tail %x\n", head, 165 tail); 166 return; 167 } 168 169 if (size > wdc_log_cap / 2) { 170 printf ("wdc_log: type %d size %x\n", type, size); 171 return; 172 } 173 #endif 174 175 if (wdc_log_buf == NULL) { 176 wdc_log_buf = malloc(wdc_log_cap, M_DEVBUF, M_NOWAIT); 177 if (wdc_log_buf == NULL) 178 return; 179 } 180 if (chp->ch_log_idx == 0) 181 chp->ch_log_idx = chp_idx++; 182 183 request_size = size + 2; 184 185 /* Check how many bytes are left */ 186 log_size = head - tail; 187 if (log_size < 0) log_size += wdc_log_cap; 188 189 if (log_size + request_size >= wdc_log_cap) { 190 int nb = 0; 191 int rec_size; 192 193 while (nb <= (request_size * 2)) { 194 if (wdc_log_buf[tail] == 0) 195 rec_size = 1; 196 else 197 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 198 tail = (tail + rec_size) % wdc_log_cap; 199 nb += rec_size; 200 } 201 } 202 203 /* Avoid wrapping in the middle of a request */ 204 if (head + request_size >= wdc_log_cap) { 205 memset(&wdc_log_buf[head], 0, wdc_log_cap - head); 206 head = 0; 207 } 208 209 ptr = &wdc_log_buf[head]; 210 *ptr++ = type & 0xff; 211 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f); 212 memcpy(ptr, val, size); 213 214 wdc_head = (head + request_size) % wdc_log_cap; 215 wdc_tail = tail; 216 } 217 218 char *wdc_get_log(unsigned int *, unsigned int *); 219 220 char * 221 wdc_get_log(unsigned int * size, unsigned int *left) 222 { 223 int log_size; 224 char *retbuf = NULL; 225 int nb, tocopy; 226 int s; 227 unsigned int head = wdc_head; 228 unsigned int tail = wdc_tail; 229 230 s = splbio(); 231 232 log_size = (head - tail); 233 if (left != NULL) 234 *left = 0; 235 236 if (log_size < 0) 237 log_size += wdc_log_cap; 238 239 tocopy = log_size; 240 if ((u_int)tocopy > *size) 241 tocopy = *size; 242 243 if (wdc_log_buf == NULL) { 244 *size = 0; 245 *left = 0; 246 goto out; 247 } 248 249 #ifdef DIAGNOSTIC 250 if (head < 0 || head > wdc_log_cap || 251 tail < 0 || tail > wdc_log_cap) { 252 printf ("wdc_log: head %x tail %x\n", head, 253 tail); 254 *size = 0; 255 *left = 0; 256 goto out; 257 } 258 #endif 259 260 retbuf = malloc(tocopy, M_TEMP, M_NOWAIT); 261 if (retbuf == NULL) { 262 *size = 0; 263 *left = log_size; 264 goto out; 265 } 266 267 nb = 0; 268 for (;;) { 269 int rec_size; 270 271 if (wdc_log_buf[tail] == 0) 272 rec_size = 1; 273 else 274 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 275 276 if ((nb + rec_size) >= tocopy) 277 break; 278 279 memcpy(&retbuf[nb], &wdc_log_buf[tail], rec_size); 280 tail = (tail + rec_size) % wdc_log_cap; 281 nb += rec_size; 282 } 283 284 wdc_tail = tail; 285 *size = nb; 286 *left = log_size - nb; 287 288 out: 289 splx(s); 290 return (retbuf); 291 } 292 #endif /* WDCDEBUG */ 293 294 u_int8_t 295 wdc_default_read_reg(struct channel_softc *chp, enum wdc_regs reg) 296 { 297 #ifdef DIAGNOSTIC 298 if (reg & _WDC_WRONLY) { 299 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 300 } 301 #endif /* DIAGNOSTIC */ 302 303 if (reg & _WDC_AUX) 304 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 305 reg & _WDC_REGMASK)); 306 else 307 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 308 reg & _WDC_REGMASK)); 309 } 310 311 void 312 wdc_default_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 313 { 314 #ifdef DIAGNOSTIC 315 if (reg & _WDC_RDONLY) { 316 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 317 } 318 #endif /* DIAGNOSTIC */ 319 320 if (reg & _WDC_AUX) 321 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 322 reg & _WDC_REGMASK, val); 323 else 324 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 325 reg & _WDC_REGMASK, val); 326 } 327 328 void 329 wdc_default_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, 330 u_int16_t val) 331 { 332 /* All registers are two byte deep FIFOs. */ 333 CHP_WRITE_REG(chp, reg, val >> 8); 334 CHP_WRITE_REG(chp, reg, val); 335 } 336 337 void 338 wdc_default_read_raw_multi_2(struct channel_softc *chp, void *data, 339 unsigned int nbytes) 340 { 341 if (data == NULL) { 342 unsigned int i; 343 344 for (i = 0; i < nbytes; i += 2) { 345 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 346 } 347 348 return; 349 } 350 351 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 352 data, nbytes); 353 } 354 355 356 void 357 wdc_default_write_raw_multi_2(struct channel_softc *chp, void *data, 358 unsigned int nbytes) 359 { 360 if (data == NULL) { 361 unsigned int i; 362 363 for (i = 0; i < nbytes; i += 2) { 364 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 365 } 366 367 return; 368 } 369 370 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 371 data, nbytes); 372 } 373 374 375 void 376 wdc_default_write_raw_multi_4(struct channel_softc *chp, void *data, 377 unsigned int nbytes) 378 { 379 if (data == NULL) { 380 unsigned int i; 381 382 for (i = 0; i < nbytes; i += 4) { 383 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 384 } 385 386 return; 387 } 388 389 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 390 data, nbytes); 391 } 392 393 394 void 395 wdc_default_read_raw_multi_4(struct channel_softc *chp, void *data, 396 unsigned int nbytes) 397 { 398 if (data == NULL) { 399 unsigned int i; 400 401 for (i = 0; i < nbytes; i += 4) { 402 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 403 } 404 405 return; 406 } 407 408 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 409 data, nbytes); 410 } 411 412 int 413 wdprint(void *aux, const char *pnp) 414 { 415 struct ata_atapi_attach *aa_link = aux; 416 if (pnp) 417 printf("drive at %s", pnp); 418 printf(" channel %d drive %d", aa_link->aa_channel, 419 aa_link->aa_drv_data->drive); 420 return (UNCONF); 421 } 422 423 void 424 wdc_disable_intr(struct channel_softc *chp) 425 { 426 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 427 } 428 429 void 430 wdc_enable_intr(struct channel_softc *chp) 431 { 432 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 433 } 434 435 void 436 wdc_set_drive(struct channel_softc *chp, int drive) 437 { 438 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM); 439 WDC_LOG_SET_DRIVE(chp, drive); 440 } 441 442 int 443 wdc_floating_bus(struct channel_softc *chp, int drive) 444 { 445 u_int8_t cumulative_status, status; 446 int iter; 447 448 wdc_set_drive(chp, drive); 449 delay(10); 450 451 /* Stolen from Phoenix BIOS Drive Autotyping document */ 452 cumulative_status = 0; 453 for (iter = 0; iter < 100; iter++) { 454 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 455 delay (1); 456 457 status = CHP_READ_REG(chp, wdr_status); 458 459 /* The other bits are meaningless if BSY is set */ 460 if (status & WDCS_BSY) 461 continue; 462 463 cumulative_status |= status; 464 465 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 466 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 467 return 1; 468 } 469 470 471 return 0; 472 } 473 474 int 475 wdc_preata_drive(struct channel_softc *chp, int drive) 476 { 477 if (wdc_floating_bus(chp, drive)) { 478 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 479 chp->wdc->sc_dev.dv_xname, 480 chp->channel, drive), DEBUG_PROBE); 481 return 0; 482 } 483 484 wdc_set_drive(chp, drive); 485 delay(100); 486 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 487 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 488 chp->wdc->sc_dev.dv_xname, 489 chp->channel, drive), DEBUG_PROBE); 490 return 0; 491 } 492 493 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 494 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL); 495 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 496 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 497 chp->wdc->sc_dev.dv_xname, 498 chp->channel, drive), DEBUG_PROBE); 499 return 0; 500 } 501 502 return 1; 503 } 504 505 int 506 wdc_ata_present(struct channel_softc *chp, int drive) 507 { 508 int time_to_done; 509 int retry_cnt = 0; 510 511 wdc_set_drive(chp, drive); 512 delay(10); 513 514 retry: 515 /* 516 You're actually supposed to wait up to 10 seconds 517 for DRDY. However, as a practical matter, most 518 drives assert DRDY very quickly after dropping BSY. 519 520 The 10 seconds wait is sub-optimal because, according 521 to the ATA standard, the master should reply with 00 522 for any reads to a non-existent slave. 523 */ 524 time_to_done = wdc_wait_for_status(chp, 525 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 526 (WDCS_DRDY | WDCS_DSC), 1000); 527 if (time_to_done == -1) { 528 if (retry_cnt == 0 && chp->ch_status == 0x00) { 529 /* At least one flash card needs to be kicked */ 530 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 531 retry_cnt++; 532 goto retry; 533 } 534 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 535 " %02x\n", 536 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 537 chp->channel, drive, chp->ch_status), 538 DEBUG_PROBE); 539 return 0; 540 } 541 542 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 543 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 544 " %02x\n", 545 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 546 chp->channel, drive, chp->ch_status), 547 DEBUG_PROBE); 548 549 return 0; 550 } 551 552 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 553 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 554 chp->channel, drive, time_to_done), DEBUG_PROBE); 555 556 /* 557 * Test register writability 558 */ 559 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 560 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 561 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 562 DELAY(10); 563 564 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 565 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 566 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 567 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 568 chp->channel, drive), DEBUG_PROBE); 569 return 0; 570 } 571 572 return 1; 573 } 574 575 576 /* 577 * Test to see controller with at least one attached drive is there. 578 * Returns a bit for each possible drive found (0x01 for drive 0, 579 * 0x02 for drive 1). 580 * Logic: 581 * - If a status register is at 0x7f or 0xff, assume there is no drive here 582 * (ISA has pull-up resistors). Similarly if the status register has 583 * the value we last wrote to the bus (for IDE interfaces without pullups). 584 * If no drive at all -> return. 585 * - reset the controller, wait for it to complete (may take up to 31s !). 586 * If timeout -> return. 587 * - test ATA/ATAPI signatures. If at last one drive found -> return. 588 * - try an ATA command on the master. 589 */ 590 591 int 592 wdcprobe(struct channel_softc *chp) 593 { 594 u_int8_t st0, st1, sc, sn, cl, ch; 595 u_int8_t ret_value = 0x03; 596 u_int8_t drive; 597 #ifdef WDCDEBUG 598 int savedmask = wdcdebug_mask; 599 #endif 600 601 if (chp->_vtbl == 0) { 602 int s = splbio(); 603 chp->_vtbl = &wdc_default_vtbl; 604 splx(s); 605 } 606 607 #ifdef WDCDEBUG 608 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 609 (chp->wdc && 610 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 611 wdcdebug_mask |= DEBUG_PROBE; 612 #endif /* WDCDEBUG */ 613 614 if (chp->wdc == NULL || 615 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 616 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 617 wdc_set_drive(chp, 0); 618 delay(10); 619 st0 = CHP_READ_REG(chp, wdr_status); 620 WDC_LOG_STATUS(chp, st0); 621 wdc_set_drive(chp, 1); 622 delay(10); 623 st1 = CHP_READ_REG(chp, wdr_status); 624 WDC_LOG_STATUS(chp, st1); 625 626 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%b, st1=0x%b\n", 627 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 628 chp->channel, st0, WDCS_BITS, st1, WDCS_BITS), 629 DEBUG_PROBE); 630 631 if (st0 == 0xff || st0 == WDSD_IBM) 632 ret_value &= ~0x01; 633 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 634 ret_value &= ~0x02; 635 if (ret_value == 0) 636 return 0; 637 } 638 639 /* reset the channel */ 640 wdc_do_reset(chp); 641 642 ret_value = __wdcwait_reset(chp, ret_value); 643 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 644 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 645 ret_value), DEBUG_PROBE); 646 647 if (ret_value == 0) 648 return 0; 649 650 /* 651 * Use signatures to find potential ATAPI drives 652 */ 653 for (drive = 0; drive < 2; drive++) { 654 if ((ret_value & (0x01 << drive)) == 0) 655 continue; 656 wdc_set_drive(chp, drive); 657 delay(10); 658 /* Save registers contents */ 659 st0 = CHP_READ_REG(chp, wdr_status); 660 sc = CHP_READ_REG(chp, wdr_seccnt); 661 sn = CHP_READ_REG(chp, wdr_sector); 662 cl = CHP_READ_REG(chp, wdr_cyl_lo); 663 ch = CHP_READ_REG(chp, wdr_cyl_hi); 664 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl); 665 666 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%b, sc=0x%x" 667 " sn=0x%x cl=0x%x ch=0x%x\n", 668 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 669 chp->channel, drive, st0, WDCS_BITS, sc, sn, cl, ch), 670 DEBUG_PROBE); 671 /* 672 * This is a simplification of the test in the ATAPI 673 * spec since not all drives seem to set the other regs 674 * correctly. 675 */ 676 if (cl == 0x14 && ch == 0xeb) 677 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 678 } 679 680 /* 681 * Detect ATA drives by poking around the registers 682 */ 683 for (drive = 0; drive < 2; drive++) { 684 if ((ret_value & (0x01 << drive)) == 0) 685 continue; 686 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 687 continue; 688 689 wdc_disable_intr(chp); 690 /* ATA detect */ 691 if (wdc_ata_present(chp, drive)) { 692 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 693 if (chp->wdc == NULL || 694 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 695 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 696 } else { 697 ret_value &= ~(1 << drive); 698 } 699 wdc_enable_intr(chp); 700 } 701 702 #ifdef WDCDEBUG 703 wdcdebug_mask = savedmask; 704 #endif 705 return (ret_value); 706 } 707 708 struct channel_queue * 709 wdc_alloc_queue(void) 710 { 711 static int inited = 0; 712 struct channel_queue *queue; 713 714 /* Initialize global data. */ 715 if (inited == 0) { 716 /* Initialize the wdc_xfer pool. */ 717 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 718 0, 0, "wdcxfer", NULL); 719 pool_setipl(&wdc_xfer_pool, IPL_BIO); 720 scsi_iopool_init(&wdc_xfer_iopool, NULL, 721 wdc_xfer_get, wdc_xfer_put); 722 inited = 1; 723 } 724 725 queue = malloc(sizeof(*queue), M_DEVBUF, M_NOWAIT); 726 if (queue != NULL) { 727 TAILQ_INIT(&queue->sc_xfer); 728 } 729 return (queue); 730 } 731 732 void 733 wdc_free_queue(struct channel_queue *queue) 734 { 735 free(queue, M_DEVBUF, 0); 736 } 737 738 void 739 wdcattach(struct channel_softc *chp) 740 { 741 int i; 742 struct ata_atapi_attach aa_link; 743 #ifdef WDCDEBUG 744 int savedmask = wdcdebug_mask; 745 #endif 746 747 if (!cold) 748 at_poll = AT_WAIT; 749 750 if (chp->wdc->reset == NULL) 751 chp->wdc->reset = wdc_do_reset; 752 753 timeout_set(&chp->ch_timo, wdctimeout, chp); 754 755 if (!chp->_vtbl) 756 chp->_vtbl = &wdc_default_vtbl; 757 758 for (i = 0; i < 2; i++) { 759 chp->ch_drive[i].chnl_softc = chp; 760 chp->ch_drive[i].drive = i; 761 } 762 763 if (chp->wdc->drv_probe != NULL) { 764 chp->wdc->drv_probe(chp); 765 } else { 766 if (wdcprobe(chp) == 0) 767 /* If no drives, abort attach here. */ 768 return; 769 } 770 771 /* ATAPI drives need settling time. Give them 250ms */ 772 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 773 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 774 delay(250 * 1000); 775 } 776 777 #ifdef WDCDEBUG 778 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 779 wdcdebug_mask |= DEBUG_PROBE; 780 781 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 782 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 783 wdcdebug_mask = DEBUG_PROBE; 784 } 785 #endif /* WDCDEBUG */ 786 787 for (i = 0; i < 2; i++) { 788 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 789 790 /* If controller can't do 16bit flag the drives as 32bit */ 791 if ((chp->wdc->cap & 792 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 793 WDC_CAPABILITY_DATA32) 794 drvp->drive_flags |= DRIVE_CAP32; 795 796 if ((drvp->drive_flags & DRIVE) == 0) 797 continue; 798 799 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 800 chp->ch_flags |= WDCF_ONESLAVE; 801 /* 802 * Wait a bit, some devices are weird just after a reset. 803 * Then issue a IDENTIFY command, to try to detect slave ghost. 804 */ 805 delay(5000); 806 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 807 CMD_OK) { 808 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 809 drvp->drive_flags &= ~DRIVE_OLD; 810 } else { 811 bzero(&drvp->id, sizeof(struct ataparams)); 812 drvp->drive_flags &= 813 ~(DRIVE_ATA | DRIVE_ATAPI); 814 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 815 chp->wdc->sc_dev.dv_xname, 816 chp->channel, i), DEBUG_PROBE); 817 818 if ((drvp->drive_flags & DRIVE_OLD) && 819 !wdc_preata_drive(chp, i)) 820 drvp->drive_flags &= ~DRIVE_OLD; 821 } 822 } 823 824 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 825 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 826 DEBUG_PROBE); 827 828 /* If no drives, abort here */ 829 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 830 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 831 goto exit; 832 833 for (i = 0; i < 2; i++) { 834 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 835 continue; 836 } 837 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 838 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 839 aa_link.aa_type = T_ATAPI; 840 else 841 aa_link.aa_type = T_ATA; 842 aa_link.aa_channel = chp->channel; 843 aa_link.aa_openings = 1; 844 aa_link.aa_drv_data = &chp->ch_drive[i]; 845 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 846 } 847 848 /* 849 * reset drive_flags for unattached devices, reset state for attached 850 * ones 851 */ 852 for (i = 0; i < 2; i++) { 853 if (chp->ch_drive[i].drive_name[0] == 0) 854 chp->ch_drive[i].drive_flags = 0; 855 } 856 857 exit: 858 #ifdef WDCDEBUG 859 wdcdebug_mask = savedmask; 860 #endif 861 return; /* for the ``exit'' label above */ 862 } 863 864 /* 865 * Start I/O on a controller, for the given channel. 866 * The first xfer may be not for our channel if the channel queues 867 * are shared. 868 */ 869 void 870 wdcstart(struct channel_softc *chp) 871 { 872 struct wdc_xfer *xfer; 873 874 splassert(IPL_BIO); 875 876 /* is there a xfer ? */ 877 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) { 878 return; 879 } 880 881 /* adjust chp, in case we have a shared queue */ 882 chp = xfer->chp; 883 884 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 885 return; /* channel already active */ 886 } 887 #ifdef DIAGNOSTIC 888 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 889 panic("wdcstart: channel waiting for irq"); 890 #endif /* DIAGNOSTIC */ 891 892 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 893 chp->channel, xfer->drive), DEBUG_XFERS); 894 chp->ch_flags |= WDCF_ACTIVE; 895 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 896 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 897 chp->ch_drive[xfer->drive].state = 0; 898 } 899 xfer->c_start(chp, xfer); 900 } 901 902 int 903 wdcdetach(struct channel_softc *chp, int flags) 904 { 905 int s, rv; 906 907 s = splbio(); 908 chp->dying = 1; 909 910 wdc_kill_pending(chp); 911 timeout_del(&chp->ch_timo); 912 913 rv = config_detach_children((struct device *)chp->wdc, flags); 914 splx(s); 915 916 return (rv); 917 } 918 919 /* 920 * Interrupt routine for the controller. Acknowledge the interrupt, check for 921 * errors on the current operation, mark it done if necessary, and start the 922 * next request. Also check for a partially done transfer, and continue with 923 * the next chunk if so. 924 */ 925 int 926 wdcintr(void *arg) 927 { 928 struct channel_softc *chp = arg; 929 struct wdc_xfer *xfer; 930 u_int8_t st = 0; 931 int ret = 0; 932 933 /* Acknowledge interrupt by reading status */ 934 if (chp->_vtbl == 0) 935 st = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 936 wdr_status & _WDC_REGMASK); 937 else 938 st = CHP_READ_REG(chp, wdr_status); 939 if (st == 0xff) 940 return (-1); 941 942 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 943 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 944 return ret; 945 } 946 947 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 948 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 949 if (chp->ch_flags & WDCF_DMA_WAIT) { 950 chp->wdc->dma_status = 951 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 952 xfer->drive, 0); 953 if (chp->wdc->dma_status == 0xff) 954 return (-1); 955 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 956 /* IRQ not for us, not detected by DMA engine */ 957 return 0; 958 } 959 chp->ch_flags &= ~WDCF_DMA_WAIT; 960 } 961 962 chp->ch_flags &= ~WDCF_IRQ_WAIT; 963 ret = xfer->c_intr(chp, xfer, 1); 964 if (ret == 0) /* irq was not for us, still waiting for irq */ 965 chp->ch_flags |= WDCF_IRQ_WAIT; 966 return (ret); 967 } 968 969 /* Put all disk in RESET state */ 970 void 971 wdc_reset_channel(struct ata_drive_datas *drvp, int nowait) 972 { 973 struct channel_softc *chp = drvp->chnl_softc; 974 int drive; 975 976 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 977 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 978 DEBUG_FUNCS); 979 (void) wdcreset(chp, nowait ? NOWAIT : VERBOSE); 980 for (drive = 0; drive < 2; drive++) { 981 chp->ch_drive[drive].state = 0; 982 } 983 } 984 985 int 986 wdcreset(struct channel_softc *chp, int flags) 987 { 988 int drv_mask1, drv_mask2; 989 990 if (!chp->_vtbl) 991 chp->_vtbl = &wdc_default_vtbl; 992 993 chp->wdc->reset(chp); 994 995 if (flags & NOWAIT) 996 return 0; 997 998 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 999 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1000 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 1001 1002 if ((flags & VERBOSE) && drv_mask2 != drv_mask1) { 1003 printf("%s channel %d: reset failed for", 1004 chp->wdc->sc_dev.dv_xname, chp->channel); 1005 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1006 printf(" drive 0"); 1007 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1008 printf(" drive 1"); 1009 printf("\n"); 1010 } 1011 1012 return (drv_mask1 != drv_mask2) ? 1 : 0; 1013 } 1014 1015 void 1016 wdc_do_reset(struct channel_softc *chp) 1017 { 1018 wdc_set_drive(chp, 0); 1019 DELAY(10); 1020 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT | WDCTL_RST); 1021 delay(10000); 1022 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 1023 delay(10000); 1024 } 1025 1026 int 1027 __wdcwait_reset(struct channel_softc *chp, int drv_mask) 1028 { 1029 int timeout; 1030 u_int8_t st0, er0, st1, er1; 1031 1032 /* wait for BSY to deassert */ 1033 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 1034 wdc_set_drive(chp, 0); 1035 delay(10); 1036 st0 = CHP_READ_REG(chp, wdr_status); 1037 er0 = CHP_READ_REG(chp, wdr_error); 1038 wdc_set_drive(chp, 1); 1039 delay(10); 1040 st1 = CHP_READ_REG(chp, wdr_status); 1041 er1 = CHP_READ_REG(chp, wdr_error); 1042 1043 if ((drv_mask & 0x01) == 0) { 1044 /* no master */ 1045 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1046 /* No master, slave is ready, it's done */ 1047 goto end; 1048 } 1049 } else if ((drv_mask & 0x02) == 0) { 1050 /* no slave */ 1051 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1052 /* No slave, master is ready, it's done */ 1053 goto end; 1054 } 1055 } else { 1056 /* Wait for both master and slave to be ready */ 1057 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1058 goto end; 1059 } 1060 } 1061 delay(WDCDELAY); 1062 } 1063 /* Reset timed out. Maybe it's because drv_mask was not right */ 1064 if (st0 & WDCS_BSY) 1065 drv_mask &= ~0x01; 1066 if (st1 & WDCS_BSY) 1067 drv_mask &= ~0x02; 1068 end: 1069 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%b, er0=0x%x, " 1070 "st1=0x%b, er1=0x%x, reset time=%d msec\n", 1071 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1072 st0, WDCS_BITS, er0, st1, WDCS_BITS, er1, 1073 timeout * WDCDELAY / 1000), DEBUG_PROBE); 1074 1075 return drv_mask; 1076 } 1077 1078 /* 1079 * Wait for a drive to be !BSY, and have mask in its status register. 1080 * return -1 for a timeout after "timeout" ms. 1081 */ 1082 int 1083 wdc_wait_for_status(struct channel_softc *chp, int mask, int bits, int timeout) 1084 { 1085 u_char status; 1086 int time = 0; 1087 1088 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1089 :"none", chp->channel), DEBUG_STATUS); 1090 chp->ch_error = 0; 1091 1092 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1093 1094 for (;;) { 1095 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 1096 WDC_LOG_STATUS(chp, chp->ch_status); 1097 1098 if (status == 0xff) { 1099 if ((chp->ch_flags & WDCF_ONESLAVE)) { 1100 wdc_set_drive(chp, 1); 1101 chp->ch_status = status = 1102 CHP_READ_REG(chp, wdr_status); 1103 WDC_LOG_STATUS(chp, chp->ch_status); 1104 } 1105 } 1106 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 1107 break; 1108 if (++time > timeout) { 1109 WDCDEBUG_PRINT(("wdcwait: timeout, status 0x%b " 1110 "error 0x%x\n", status, WDCS_BITS, 1111 CHP_READ_REG(chp, wdr_error)), 1112 DEBUG_STATUSX | DEBUG_STATUS); 1113 return -1; 1114 } 1115 delay(WDCDELAY); 1116 } 1117 if (status & WDCS_ERR) { 1118 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1119 WDC_LOG_ERROR(chp, chp->ch_error); 1120 1121 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1122 DEBUG_STATUSX | DEBUG_STATUS); 1123 } 1124 1125 #ifdef WDCNDELAY_DEBUG 1126 /* After autoconfig, there should be no long delays. */ 1127 if (!cold && time > WDCNDELAY_DEBUG) { 1128 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1129 if (xfer == NULL) 1130 printf("%s channel %d: warning: busy-wait took %dus\n", 1131 chp->wdc->sc_dev.dv_xname, chp->channel, 1132 WDCDELAY * time); 1133 else 1134 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1135 chp->wdc->sc_dev.dv_xname, chp->channel, 1136 xfer->drive, 1137 WDCDELAY * time); 1138 } 1139 #endif /* WDCNDELAY_DEBUG */ 1140 return time; 1141 } 1142 1143 /* 1144 * Busy-wait for DMA to complete 1145 */ 1146 int 1147 wdc_dmawait(struct channel_softc *chp, struct wdc_xfer *xfer, int timeout) 1148 { 1149 int time; 1150 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1151 chp->wdc->dma_status = 1152 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1153 chp->channel, xfer->drive, 0); 1154 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1155 return 0; 1156 if (chp->wdc->dma_status == 0xff) { 1157 chp->dying = 1; 1158 return -1; 1159 } 1160 delay(WDCDELAY); 1161 } 1162 /* timeout, force a DMA halt */ 1163 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1164 chp->channel, xfer->drive, 1); 1165 return 1; 1166 } 1167 1168 void 1169 wdctimeout(void *arg) 1170 { 1171 struct channel_softc *chp = (struct channel_softc *)arg; 1172 struct wdc_xfer *xfer; 1173 int s; 1174 1175 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1176 1177 s = splbio(); 1178 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1179 1180 /* Did we lose a race with the interrupt? */ 1181 if (xfer == NULL || 1182 !timeout_triggered(&chp->ch_timo)) { 1183 splx(s); 1184 return; 1185 } 1186 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1187 __wdcerror(chp, "timeout"); 1188 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1189 "atapi":"ata"); 1190 printf("\tc_bcount: %d\n", xfer->c_bcount); 1191 printf("\tc_skip: %d\n", xfer->c_skip); 1192 if (chp->ch_flags & WDCF_DMA_WAIT) { 1193 chp->wdc->dma_status = 1194 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1195 chp->channel, xfer->drive, 1); 1196 chp->ch_flags &= ~WDCF_DMA_WAIT; 1197 } 1198 /* 1199 * Call the interrupt routine. If we just missed and interrupt, 1200 * it will do what's needed. Else, it will take the needed 1201 * action (reset the device). 1202 */ 1203 xfer->c_flags |= C_TIMEOU; 1204 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1205 xfer->c_intr(chp, xfer, 1); 1206 } else 1207 __wdcerror(chp, "missing untimeout"); 1208 splx(s); 1209 } 1210 1211 /* 1212 * Probe drive's capabilities, for use by the controller later. 1213 * Assumes drvp points to an existing drive. 1214 * XXX this should be a controller-indep function 1215 */ 1216 void 1217 wdc_probe_caps(struct ata_drive_datas *drvp, struct ataparams *params) 1218 { 1219 struct channel_softc *chp = drvp->chnl_softc; 1220 struct wdc_softc *wdc = chp->wdc; 1221 int i, valid_mode_found; 1222 int cf_flags = drvp->cf_flags; 1223 1224 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1225 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1226 struct ataparams params2; 1227 1228 /* 1229 * Controller claims 16 and 32 bit transfers. 1230 * Re-do an IDENTIFY with 32-bit transfers, 1231 * and compare results. 1232 */ 1233 drvp->drive_flags |= DRIVE_CAP32; 1234 ata_get_params(drvp, at_poll, ¶ms2); 1235 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1236 /* Not good. fall back to 16bits */ 1237 drvp->drive_flags &= ~DRIVE_CAP32; 1238 } 1239 } 1240 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1241 if (params->atap_ata_major > 0x01 && 1242 params->atap_ata_major != 0xffff) { 1243 for (i = 14; i > 0; i--) { 1244 if (params->atap_ata_major & (1 << i)) { 1245 printf("%sATA version %d\n", sep, i); 1246 drvp->ata_vers = i; 1247 break; 1248 } 1249 } 1250 } else 1251 #endif /* 0 */ 1252 /* Use PIO mode 3 as a default value for ATAPI devices */ 1253 if (drvp->drive_flags & DRIVE_ATAPI) 1254 drvp->PIO_mode = 3; 1255 1256 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap 0x%x cf_flags 0x%x\n", 1257 wdc->cap, cf_flags), DEBUG_PROBE); 1258 1259 valid_mode_found = 0; 1260 1261 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__, 1262 params->atap_oldpiotiming), DEBUG_PROBE); 1263 /* 1264 * ATA-4 compliant devices contain PIO mode 1265 * number in atap_oldpiotiming. 1266 */ 1267 if (params->atap_oldpiotiming <= 2) { 1268 drvp->PIO_cap = params->atap_oldpiotiming; 1269 valid_mode_found = 1; 1270 drvp->drive_flags |= DRIVE_MODE; 1271 } else if (params->atap_oldpiotiming > 180) { 1272 /* 1273 * ATA-2 compliant devices contain cycle 1274 * time in atap_oldpiotiming. 1275 * A device with a cycle time of 180ns 1276 * or less is at least PIO mode 3 and 1277 * should be reporting that in 1278 * atap_piomode_supp, so ignore it here. 1279 */ 1280 if (params->atap_oldpiotiming <= 240) { 1281 drvp->PIO_cap = 2; 1282 } else { 1283 drvp->PIO_cap = 1; 1284 } 1285 valid_mode_found = 1; 1286 drvp->drive_flags |= DRIVE_MODE; 1287 } 1288 if (valid_mode_found) 1289 drvp->PIO_mode = drvp->PIO_cap; 1290 1291 WDCDEBUG_PRINT(("%s: atap_extensions=0x%x, atap_piomode_supp=0x%x, " 1292 "atap_dmamode_supp=0x%x, atap_udmamode_supp=0x%x\n", 1293 __func__, params->atap_extensions, params->atap_piomode_supp, 1294 params->atap_dmamode_supp, params->atap_udmamode_supp), 1295 DEBUG_PROBE); 1296 1297 /* 1298 * It's not in the specs, but it seems that some drive 1299 * returns 0xffff in atap_extensions when this field is invalid 1300 */ 1301 if (params->atap_extensions != 0xffff && 1302 (params->atap_extensions & WDC_EXT_MODES)) { 1303 /* 1304 * XXX some drives report something wrong here (they claim to 1305 * support PIO mode 8 !). As mode is coded on 3 bits in 1306 * SET FEATURE, limit it to 7 (so limit i to 4). 1307 * If higher mode than 7 is found, abort. 1308 */ 1309 for (i = 7; i >= 0; i--) { 1310 if ((params->atap_piomode_supp & (1 << i)) == 0) 1311 continue; 1312 if (i > 4) 1313 return; 1314 1315 valid_mode_found = 1; 1316 1317 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1318 drvp->PIO_cap = i + 3; 1319 continue; 1320 } 1321 1322 /* 1323 * See if mode is accepted. 1324 * If the controller can't set its PIO mode, 1325 * assume the BIOS set it up correctly 1326 */ 1327 if (ata_set_mode(drvp, 0x08 | (i + 3), 1328 at_poll) != CMD_OK) 1329 continue; 1330 1331 /* 1332 * If controller's driver can't set its PIO mode, 1333 * set the highest one the controller supports 1334 */ 1335 if (wdc->PIO_cap >= i + 3) { 1336 drvp->PIO_mode = i + 3; 1337 drvp->PIO_cap = i + 3; 1338 break; 1339 } 1340 } 1341 if (!valid_mode_found) { 1342 /* 1343 * We didn't find a valid PIO mode. 1344 * Assume the values returned for DMA are buggy too 1345 */ 1346 return; 1347 } 1348 drvp->drive_flags |= DRIVE_MODE; 1349 1350 /* Some controllers don't support ATAPI DMA */ 1351 if ((drvp->drive_flags & DRIVE_ATAPI) && 1352 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1353 return; 1354 1355 valid_mode_found = 0; 1356 for (i = 7; i >= 0; i--) { 1357 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1358 continue; 1359 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1360 (wdc->cap & WDC_CAPABILITY_MODE)) 1361 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1362 != CMD_OK) 1363 continue; 1364 1365 valid_mode_found = 1; 1366 1367 if (wdc->cap & WDC_CAPABILITY_DMA) { 1368 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1369 wdc->DMA_cap < i) 1370 continue; 1371 drvp->DMA_mode = i; 1372 drvp->DMA_cap = i; 1373 drvp->drive_flags |= DRIVE_DMA; 1374 } 1375 break; 1376 } 1377 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1378 for (i = 7; i >= 0; i--) { 1379 if ((params->atap_udmamode_supp & (1 << i)) 1380 == 0) 1381 continue; 1382 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1383 (wdc->cap & WDC_CAPABILITY_UDMA)) 1384 if (ata_set_mode(drvp, 0x40 | i, 1385 at_poll) != CMD_OK) 1386 continue; 1387 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1388 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1389 wdc->UDMA_cap < i) 1390 continue; 1391 drvp->UDMA_mode = i; 1392 drvp->UDMA_cap = i; 1393 drvp->drive_flags |= DRIVE_UDMA; 1394 } 1395 break; 1396 } 1397 } 1398 } 1399 1400 /* Try to guess ATA version here, if it didn't get reported */ 1401 if (drvp->ata_vers == 0) { 1402 if (drvp->drive_flags & DRIVE_UDMA) 1403 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1404 else if (drvp->PIO_cap > 2) 1405 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1406 } 1407 if (cf_flags & ATA_CONFIG_PIO_SET) { 1408 drvp->PIO_mode = 1409 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1410 drvp->drive_flags |= DRIVE_MODE; 1411 } 1412 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1413 /* don't care about DMA modes */ 1414 return; 1415 } 1416 if (cf_flags & ATA_CONFIG_DMA_SET) { 1417 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1418 ATA_CONFIG_DMA_DISABLE) { 1419 drvp->drive_flags &= ~DRIVE_DMA; 1420 } else { 1421 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1422 ATA_CONFIG_DMA_OFF; 1423 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1424 } 1425 } 1426 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1427 /* don't care about UDMA modes */ 1428 return; 1429 } 1430 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1431 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1432 ATA_CONFIG_UDMA_DISABLE) { 1433 drvp->drive_flags &= ~DRIVE_UDMA; 1434 } else { 1435 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1436 ATA_CONFIG_UDMA_OFF; 1437 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1438 } 1439 } 1440 } 1441 1442 void 1443 wdc_output_bytes(struct ata_drive_datas *drvp, void *bytes, unsigned int buflen) 1444 { 1445 struct channel_softc *chp = drvp->chnl_softc; 1446 unsigned int off = 0; 1447 unsigned int len = buflen, roundlen; 1448 1449 if (drvp->drive_flags & DRIVE_CAP32) { 1450 roundlen = len & ~3; 1451 1452 CHP_WRITE_RAW_MULTI_4(chp, 1453 (void *)((u_int8_t *)bytes + off), roundlen); 1454 1455 off += roundlen; 1456 len -= roundlen; 1457 } 1458 1459 if (len > 0) { 1460 roundlen = (len + 1) & ~0x1; 1461 1462 CHP_WRITE_RAW_MULTI_2(chp, 1463 (void *)((u_int8_t *)bytes + off), roundlen); 1464 } 1465 } 1466 1467 void 1468 wdc_input_bytes(struct ata_drive_datas *drvp, void *bytes, unsigned int buflen) 1469 { 1470 struct channel_softc *chp = drvp->chnl_softc; 1471 unsigned int off = 0; 1472 unsigned int len = buflen, roundlen; 1473 1474 if (drvp->drive_flags & DRIVE_CAP32) { 1475 roundlen = len & ~3; 1476 1477 CHP_READ_RAW_MULTI_4(chp, 1478 (void *)((u_int8_t *)bytes + off), roundlen); 1479 1480 off += roundlen; 1481 len -= roundlen; 1482 } 1483 1484 if (len > 0) { 1485 roundlen = (len + 1) & ~0x1; 1486 1487 CHP_READ_RAW_MULTI_2(chp, 1488 (void *)((u_int8_t *)bytes + off), roundlen); 1489 } 1490 } 1491 1492 void 1493 wdc_print_caps(struct ata_drive_datas *drvp) 1494 { 1495 /* This is actually a lie until we fix the _probe_caps 1496 algorithm. Don't print out lies */ 1497 #if 0 1498 printf("%s: can use ", drvp->drive_name); 1499 1500 if (drvp->drive_flags & DRIVE_CAP32) { 1501 printf("32-bit"); 1502 } else 1503 printf("16-bit"); 1504 1505 printf(", PIO mode %d", drvp->PIO_cap); 1506 1507 if (drvp->drive_flags & DRIVE_DMA) { 1508 printf(", DMA mode %d", drvp->DMA_cap); 1509 } 1510 1511 if (drvp->drive_flags & DRIVE_UDMA) { 1512 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1513 } 1514 1515 printf("\n"); 1516 #endif /* 0 */ 1517 } 1518 1519 void 1520 wdc_print_current_modes(struct channel_softc *chp) 1521 { 1522 int drive; 1523 struct ata_drive_datas *drvp; 1524 1525 for (drive = 0; drive < 2; drive++) { 1526 drvp = &chp->ch_drive[drive]; 1527 if ((drvp->drive_flags & DRIVE) == 0) 1528 continue; 1529 1530 printf("%s(%s:%d:%d):", 1531 drvp->drive_name, 1532 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1533 1534 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1535 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1536 printf(" using BIOS timings"); 1537 else 1538 printf(" using PIO mode %d", drvp->PIO_mode); 1539 if (drvp->drive_flags & DRIVE_DMA) 1540 printf(", DMA mode %d", drvp->DMA_mode); 1541 if (drvp->drive_flags & DRIVE_UDMA) 1542 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1543 printf("\n"); 1544 } 1545 } 1546 1547 /* 1548 * downgrade the transfer mode of a drive after an error. return 1 if 1549 * downgrade was possible, 0 otherwise. 1550 */ 1551 int 1552 wdc_downgrade_mode(struct ata_drive_datas *drvp) 1553 { 1554 struct channel_softc *chp = drvp->chnl_softc; 1555 struct wdc_softc *wdc = chp->wdc; 1556 int cf_flags = drvp->cf_flags; 1557 1558 /* if drive or controller don't know its mode, we can't do much */ 1559 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1560 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1561 return 0; 1562 /* current drive mode was set by a config flag, let it this way */ 1563 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1564 (cf_flags & ATA_CONFIG_DMA_SET) || 1565 (cf_flags & ATA_CONFIG_UDMA_SET)) 1566 return 0; 1567 1568 /* 1569 * We'd ideally like to use an Ultra DMA mode since they have the 1570 * protection of a CRC. So we try each Ultra DMA mode and see if 1571 * we can find any working combo 1572 */ 1573 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1574 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1575 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1576 drvp->drive_name, drvp->UDMA_mode); 1577 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1578 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1579 /* 1580 * If we were using ultra-DMA, don't downgrade to 1581 * multiword DMA if we noticed a CRC error. It has 1582 * been noticed that CRC errors in ultra-DMA lead to 1583 * silent data corruption in multiword DMA. Data 1584 * corruption is less likely to occur in PIO mode. 1585 */ 1586 drvp->drive_flags &= ~DRIVE_UDMA; 1587 drvp->drive_flags |= DRIVE_DMA; 1588 drvp->DMA_mode = drvp->DMA_cap; 1589 printf("%s: transfer error, downgrading to DMA mode %d\n", 1590 drvp->drive_name, drvp->DMA_mode); 1591 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1592 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1593 drvp->PIO_mode = drvp->PIO_cap; 1594 printf("%s: transfer error, downgrading to PIO mode %d\n", 1595 drvp->drive_name, drvp->PIO_mode); 1596 } else /* already using PIO, can't downgrade */ 1597 return 0; 1598 1599 wdc->set_modes(chp); 1600 /* reset the channel, which will schedule all drives for setup */ 1601 wdc_reset_channel(drvp, 0); 1602 return 1; 1603 } 1604 1605 int 1606 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1607 { 1608 struct channel_softc *chp = drvp->chnl_softc; 1609 struct wdc_xfer *xfer; 1610 int s, ret; 1611 1612 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1613 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1614 DEBUG_FUNCS); 1615 1616 /* set up an xfer and queue. Wait for completion */ 1617 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1618 WDC_NOSLEEP); 1619 if (xfer == NULL) { 1620 return WDC_TRY_AGAIN; 1621 } 1622 1623 if (wdc_c->flags & AT_POLL) 1624 xfer->c_flags |= C_POLL; 1625 xfer->drive = drvp->drive; 1626 xfer->databuf = wdc_c->data; 1627 xfer->c_bcount = wdc_c->bcount; 1628 xfer->cmd = wdc_c; 1629 xfer->c_start = __wdccommand_start; 1630 xfer->c_intr = __wdccommand_intr; 1631 xfer->c_kill_xfer = __wdccommand_done; 1632 1633 s = splbio(); 1634 wdc_exec_xfer(chp, xfer); 1635 #ifdef DIAGNOSTIC 1636 if ((wdc_c->flags & AT_POLL) != 0 && 1637 (wdc_c->flags & AT_DONE) == 0) 1638 panic("wdc_exec_command: polled command not done"); 1639 #endif /* DIAGNOSTIC */ 1640 if (wdc_c->flags & AT_DONE) { 1641 ret = WDC_COMPLETE; 1642 } else { 1643 if (wdc_c->flags & AT_WAIT) { 1644 WDCDEBUG_PRINT(("wdc_exec_command sleeping\n"), 1645 DEBUG_FUNCS); 1646 1647 while ((wdc_c->flags & AT_DONE) == 0) { 1648 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1649 } 1650 ret = WDC_COMPLETE; 1651 } else { 1652 ret = WDC_QUEUED; 1653 } 1654 } 1655 splx(s); 1656 return ret; 1657 } 1658 1659 void 1660 __wdccommand_start(struct channel_softc *chp, struct wdc_xfer *xfer) 1661 { 1662 int drive = xfer->drive; 1663 struct wdc_command *wdc_c = xfer->cmd; 1664 1665 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1666 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1667 DEBUG_FUNCS); 1668 1669 /* 1670 * Disable interrupts if we're polling 1671 */ 1672 if (xfer->c_flags & C_POLL) { 1673 wdc_disable_intr(chp); 1674 } 1675 1676 wdc_set_drive(chp, drive); 1677 DELAY(1); 1678 1679 /* 1680 * For resets, we don't really care to make sure that 1681 * the bus is free 1682 */ 1683 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1684 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1685 wdc_c->r_st_bmask, wdc_c->timeout) != 0) { 1686 goto timeout; 1687 } 1688 } else 1689 DELAY(10); 1690 1691 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1692 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1693 1694 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) { 1695 /* wait at least 400ns before reading status register */ 1696 DELAY(10); 1697 if (wait_for_unbusy(chp, wdc_c->timeout) != 0) 1698 goto timeout; 1699 1700 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) { 1701 __wdccommand_done(chp, xfer); 1702 return; 1703 } 1704 1705 if (wait_for_drq(chp, wdc_c->timeout) != 0) 1706 goto timeout; 1707 1708 wdc_output_bytes(&chp->ch_drive[drive], 1709 wdc_c->data, wdc_c->bcount); 1710 } 1711 1712 if ((wdc_c->flags & AT_POLL) == 0) { 1713 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1714 timeout_add_msec(&chp->ch_timo, wdc_c->timeout); 1715 return; 1716 } 1717 1718 /* 1719 * Polled command. Wait for drive ready or drq. Done in intr(). 1720 * Wait for at last 400ns for status bit to be valid. 1721 */ 1722 delay(10); 1723 __wdccommand_intr(chp, xfer, 0); 1724 return; 1725 1726 timeout: 1727 wdc_c->flags |= AT_TIMEOU; 1728 __wdccommand_done(chp, xfer); 1729 } 1730 1731 int 1732 __wdccommand_intr(struct channel_softc *chp, struct wdc_xfer *xfer, int irq) 1733 { 1734 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1735 struct wdc_command *wdc_c = xfer->cmd; 1736 int bcount = wdc_c->bcount; 1737 char *data = wdc_c->data; 1738 1739 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1740 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1741 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1742 (irq == 0) ? wdc_c->timeout : 0)) { 1743 if (chp->dying) { 1744 __wdccommand_done(chp, xfer); 1745 return -1; 1746 } 1747 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1748 return 0; /* IRQ was not for us */ 1749 wdc_c->flags |= AT_TIMEOU; 1750 goto out; 1751 } 1752 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1753 chp->wdc->irqack(chp); 1754 if (wdc_c->flags & AT_READ) { 1755 if ((chp->ch_status & WDCS_DRQ) == 0) { 1756 wdc_c->flags |= AT_TIMEOU; 1757 goto out; 1758 } 1759 wdc_input_bytes(drvp, data, bcount); 1760 /* Should we wait for device to indicate idle? */ 1761 } 1762 out: 1763 __wdccommand_done(chp, xfer); 1764 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1765 return 1; 1766 } 1767 1768 void 1769 __wdccommand_done(struct channel_softc *chp, struct wdc_xfer *xfer) 1770 { 1771 struct wdc_command *wdc_c = xfer->cmd; 1772 1773 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1774 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 1775 chp->ch_status), DEBUG_FUNCS); 1776 if (chp->dying) 1777 goto killit; 1778 if (chp->ch_status & WDCS_DWF) 1779 wdc_c->flags |= AT_DF; 1780 if (chp->ch_status & WDCS_ERR) { 1781 wdc_c->flags |= AT_ERROR; 1782 wdc_c->r_error = chp->ch_error; 1783 } 1784 wdc_c->flags |= AT_DONE; 1785 if ((wdc_c->flags & AT_READREG) != 0 && 1786 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1787 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1788 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1789 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1790 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1791 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1792 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1793 wdc_c->r_precomp = wdc_c->r_error; 1794 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1795 isn't a readable register */ 1796 } 1797 1798 killit: 1799 if (xfer->c_flags & C_POLL) { 1800 wdc_enable_intr(chp); 1801 } else 1802 timeout_del(&chp->ch_timo); 1803 1804 wdc_free_xfer(chp, xfer); 1805 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1806 1807 if (chp->dying) 1808 return; 1809 1810 if (wdc_c->flags & AT_WAIT) 1811 wakeup(wdc_c); 1812 else 1813 if (wdc_c->callback) 1814 wdc_c->callback(wdc_c->callback_arg); 1815 wdcstart(chp); 1816 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1817 } 1818 1819 /* 1820 * Send a command. The drive should be ready. 1821 * Assumes interrupts are blocked. 1822 */ 1823 void 1824 wdccommand(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1825 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1826 u_int8_t precomp) 1827 { 1828 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1829 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1830 chp->channel, drive, command, cylin, head, sector, count, precomp), 1831 DEBUG_FUNCS); 1832 WDC_LOG_ATA_CMDLONG(chp, head, precomp, cylin, cylin >> 8, sector, 1833 count, command); 1834 1835 /* Select drive, head, and addressing mode. */ 1836 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1837 1838 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1839 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1840 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1841 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1842 CHP_WRITE_REG(chp, wdr_sector, sector); 1843 CHP_WRITE_REG(chp, wdr_seccnt, count); 1844 1845 /* Send command. */ 1846 CHP_WRITE_REG(chp, wdr_command, command); 1847 } 1848 1849 /* 1850 * Send a 48-bit addressing command. The drive should be ready. 1851 * Assumes interrupts are blocked. 1852 */ 1853 void 1854 wdccommandext(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1855 u_int64_t blkno, u_int16_t count) 1856 { 1857 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu " 1858 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1859 chp->channel, drive, command, blkno, count), 1860 DEBUG_FUNCS); 1861 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32, 1862 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command); 1863 1864 /* Select drive and LBA mode. */ 1865 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA); 1866 1867 /* Load parameters. */ 1868 CHP_LBA48_WRITE_REG(chp, wdr_lba_hi, 1869 ((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0xff)); 1870 CHP_LBA48_WRITE_REG(chp, wdr_lba_mi, 1871 ((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0xff)); 1872 CHP_LBA48_WRITE_REG(chp, wdr_lba_lo, 1873 ((blkno >> 16) & 0xff00) | (blkno & 0xff)); 1874 CHP_LBA48_WRITE_REG(chp, wdr_seccnt, count); 1875 1876 /* Send command. */ 1877 CHP_WRITE_REG(chp, wdr_command, command); 1878 } 1879 1880 /* 1881 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1882 * tested by the caller. 1883 */ 1884 void 1885 wdccommandshort(struct channel_softc *chp, int drive, int command) 1886 { 1887 1888 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1889 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1890 DEBUG_FUNCS); 1891 WDC_LOG_ATA_CMDSHORT(chp, command); 1892 1893 /* Select drive. */ 1894 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1895 CHP_WRITE_REG(chp, wdr_command, command); 1896 } 1897 1898 /* Add a command to the queue and start controller. Must be called at splbio */ 1899 1900 void 1901 wdc_exec_xfer(struct channel_softc *chp, struct wdc_xfer *xfer) 1902 { 1903 WDCDEBUG_PRINT(("wdc_exec_xfer %p flags 0x%x channel %d drive %d\n", 1904 xfer, xfer->c_flags, chp->channel, xfer->drive), DEBUG_XFERS); 1905 1906 /* complete xfer setup */ 1907 xfer->chp = chp; 1908 1909 /* 1910 * If we are a polled command, and the list is not empty, 1911 * we are doing a dump. Drop the list to allow the polled command 1912 * to complete, we're going to reboot soon anyway. 1913 */ 1914 if ((xfer->c_flags & C_POLL) != 0 && 1915 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) { 1916 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1917 } 1918 /* insert at the end of command list */ 1919 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1920 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1921 chp->ch_flags), DEBUG_XFERS); 1922 wdcstart(chp); 1923 } 1924 1925 void * 1926 wdc_xfer_get(void *null) 1927 { 1928 return (pool_get(&wdc_xfer_pool, PR_NOWAIT | PR_ZERO)); 1929 } 1930 1931 void 1932 wdc_scrub_xfer(struct wdc_xfer *xfer) 1933 { 1934 memset(xfer, 0, sizeof(*xfer)); 1935 xfer->c_flags = C_SCSIXFER; 1936 } 1937 1938 void 1939 wdc_xfer_put(void *null, void *xxfer) 1940 { 1941 struct wdc_xfer *xfer = xxfer; 1942 int put = 0; 1943 int s; 1944 1945 s = splbio(); 1946 if (ISSET(xfer->c_flags, C_SCSIXFER)) 1947 CLR(xfer->c_flags, C_SCSIXFER); 1948 else 1949 put = 1; 1950 splx(s); 1951 1952 if (put) 1953 pool_put(&wdc_xfer_pool, xfer); 1954 } 1955 1956 struct wdc_xfer * 1957 wdc_get_xfer(int flags) 1958 { 1959 return (scsi_io_get(&wdc_xfer_iopool, 1960 ISSET(flags, WDC_NOSLEEP) ? SCSI_NOSLEEP : 0)); 1961 } 1962 1963 void 1964 wdc_free_xfer(struct channel_softc *chp, struct wdc_xfer *xfer) 1965 { 1966 int put = 0; 1967 int s; 1968 1969 if (xfer->c_flags & C_PRIVATEXFER) { 1970 chp->ch_flags &= ~WDCF_ACTIVE; 1971 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1972 return; 1973 } 1974 1975 s = splbio(); 1976 chp->ch_flags &= ~WDCF_ACTIVE; 1977 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1978 put = !ISSET(xfer->c_flags, C_SCSIXFER); 1979 splx(s); 1980 1981 if (put) 1982 scsi_io_put(&wdc_xfer_iopool, xfer); 1983 } 1984 1985 1986 /* 1987 * Kill off all pending xfers for a channel_softc. 1988 * 1989 * Must be called at splbio(). 1990 */ 1991 void 1992 wdc_kill_pending(struct channel_softc *chp) 1993 { 1994 struct wdc_xfer *xfer; 1995 1996 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1997 chp = xfer->chp; 1998 (*xfer->c_kill_xfer)(chp, xfer); 1999 } 2000 } 2001 2002 void 2003 __wdcerror(struct channel_softc *chp, char *msg) 2004 { 2005 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 2006 if (xfer == NULL) 2007 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2008 msg); 2009 else 2010 printf("%s(%s:%d:%d): %s\n", 2011 chp->ch_drive[xfer->drive].drive_name, 2012 chp->wdc->sc_dev.dv_xname, 2013 chp->channel, xfer->drive, msg); 2014 } 2015 2016 /* 2017 * the bit bucket 2018 */ 2019 void 2020 wdcbit_bucket(struct channel_softc *chp, int size) 2021 { 2022 CHP_READ_RAW_MULTI_2(chp, NULL, size); 2023 } 2024 2025 2026 #include <sys/ataio.h> 2027 #include <sys/file.h> 2028 2029 int wdc_ioc_ata_cmd(struct ata_drive_datas *, atareq_t *); 2030 2031 int 2032 wdc_ioc_ata_cmd(struct ata_drive_datas *drvp, atareq_t *atareq) 2033 { 2034 struct wdc_command wdc_c; 2035 int err = 0; 2036 2037 /* 2038 * Make sure a timeout was supplied in the ioctl request 2039 */ 2040 if (atareq->timeout == 0) 2041 return (EINVAL); 2042 2043 if (atareq->datalen > MAXPHYS) 2044 return (EINVAL); 2045 2046 bzero(&wdc_c, sizeof(wdc_c)); 2047 2048 if (atareq->datalen > 0) { 2049 wdc_c.data = dma_alloc(atareq->datalen, PR_NOWAIT | PR_ZERO); 2050 if (wdc_c.data == NULL) { 2051 err = ENOMEM; 2052 goto err; 2053 } 2054 wdc_c.bcount = atareq->datalen; 2055 } 2056 2057 wdc_c.flags = AT_WAIT; 2058 if (atareq->flags & ATACMD_READ) 2059 wdc_c.flags |= AT_READ; 2060 if (atareq->flags & ATACMD_WRITE) { 2061 if (atareq->datalen > 0) { 2062 err = copyin(atareq->databuf, wdc_c.data, 2063 atareq->datalen); 2064 if (err != 0) 2065 goto err; 2066 } 2067 wdc_c.flags |= AT_WRITE; 2068 } 2069 if (atareq->flags & ATACMD_READREG) 2070 wdc_c.flags |= AT_READREG; 2071 2072 wdc_c.timeout = atareq->timeout; 2073 wdc_c.r_command = atareq->command; 2074 wdc_c.r_head = atareq->head & 0x0f; 2075 wdc_c.r_cyl = atareq->cylinder; 2076 wdc_c.r_sector = atareq->sec_num; 2077 wdc_c.r_count = atareq->sec_count; 2078 wdc_c.r_precomp = atareq->features; 2079 if (drvp->drive_flags & DRIVE_ATAPI) { 2080 if (wdc_c.r_command == WDCC_IDENTIFY) 2081 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 2082 } else { 2083 wdc_c.r_st_bmask = WDCS_DRDY; 2084 wdc_c.r_st_pmask = WDCS_DRDY; 2085 } 2086 2087 if (wdc_exec_command(drvp, &wdc_c) != WDC_COMPLETE) { 2088 atareq->retsts = ATACMD_ERROR; 2089 goto copyout; 2090 } 2091 2092 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 2093 if (wdc_c.flags & AT_ERROR) { 2094 atareq->retsts = ATACMD_ERROR; 2095 atareq->error = wdc_c.r_error; 2096 } else if (wdc_c.flags & AT_DF) 2097 atareq->retsts = ATACMD_DF; 2098 else 2099 atareq->retsts = ATACMD_TIMEOUT; 2100 } else { 2101 atareq->retsts = ATACMD_OK; 2102 if (atareq->flags & ATACMD_READREG) { 2103 atareq->head = wdc_c.r_head; 2104 atareq->cylinder = wdc_c.r_cyl; 2105 atareq->sec_num = wdc_c.r_sector; 2106 atareq->sec_count = wdc_c.r_count; 2107 atareq->features = wdc_c.r_precomp; 2108 atareq->error = wdc_c.r_error; 2109 } 2110 } 2111 2112 copyout: 2113 if (atareq->datalen > 0 && atareq->flags & ATACMD_READ) { 2114 err = copyout(wdc_c.data, atareq->databuf, atareq->datalen); 2115 if (err != 0) 2116 goto err; 2117 } 2118 2119 err: 2120 if (wdc_c.data) 2121 dma_free(wdc_c.data, atareq->datalen); 2122 return (err); 2123 } 2124 2125 int 2126 wdc_ioctl(struct ata_drive_datas *drvp, u_long xfer, caddr_t addr, int flag, 2127 struct proc *p) 2128 { 2129 int error = 0; 2130 2131 switch (xfer) { 2132 #ifdef WDCDEBUG 2133 case ATAIOGETTRACE: { 2134 atagettrace_t *agt = (atagettrace_t *)addr; 2135 unsigned int size = 0; 2136 char *log_to_copy; 2137 2138 size = agt->buf_size; 2139 if (size > 65536) { 2140 size = 65536; 2141 } 2142 2143 log_to_copy = wdc_get_log(&size, &agt->bytes_left); 2144 2145 if (log_to_copy != NULL) { 2146 error = copyout(log_to_copy, agt->buf, size); 2147 free(log_to_copy, M_TEMP, 0); 2148 } 2149 2150 agt->bytes_copied = size; 2151 break; 2152 } 2153 #endif /* WDCDEBUG */ 2154 2155 case ATAIOCCOMMAND: { 2156 atareq_t *atareq = (atareq_t *)addr; 2157 2158 /* 2159 * Make sure this command is (relatively) safe first 2160 */ 2161 if ((flag & FWRITE) == 0 && atareq->flags & ATACMD_WRITE) 2162 error = EPERM; 2163 else 2164 error = wdc_ioc_ata_cmd(drvp, atareq); 2165 break; 2166 } 2167 2168 default: 2169 error = ENOTTY; 2170 goto exit; 2171 } 2172 2173 exit: 2174 return (error); 2175 } 2176