1 /* $OpenBSD: wdc.c,v 1.43 2001/11/06 19:53:18 miod Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 4 5 /* 6 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1998 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/conf.h> 74 #include <sys/buf.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/syslog.h> 78 #include <sys/proc.h> 79 #include <sys/pool.h> 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/intr.h> 83 #include <machine/bus.h> 84 85 #include <dev/ata/atavar.h> 86 #include <dev/ata/atareg.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #include "atapiscsi.h" 91 92 #define WDCDELAY 100 /* 100 microseconds */ 93 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 94 #if 0 95 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 96 #define WDCNDELAY_DEBUG 50 97 #endif 98 99 struct pool wdc_xfer_pool; 100 101 static void __wdcerror __P((struct channel_softc*, char *)); 102 static int __wdcwait_reset __P((struct channel_softc *, int)); 103 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 104 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 105 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 106 int wdprint __P((void *, const char *)); 107 void wdc_kill_pending __P((struct channel_softc *)); 108 109 #define DEBUG_INTR 0x01 110 #define DEBUG_XFERS 0x02 111 #define DEBUG_STATUS 0x04 112 #define DEBUG_FUNCS 0x08 113 #define DEBUG_PROBE 0x10 114 #define DEBUG_STATUSX 0x20 115 #define DEBUG_SDRIVE 0x40 116 #define DEBUG_DETACH 0x80 117 118 #ifdef WDCDEBUG 119 int wdcdebug_mask = 0; 120 int wdc_nxfer = 0; 121 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 122 #else 123 #define WDCDEBUG_PRINT(args, level) 124 #endif 125 126 int at_poll = AT_POLL; 127 128 u_int8_t wdc_default_read_reg __P((struct channel_softc *, enum wdc_regs)); 129 void wdc_default_write_reg __P((struct channel_softc *, enum wdc_regs, u_int8_t)); 130 void wdc_default_read_raw_multi_2 __P((struct channel_softc *, 131 void *, unsigned int)); 132 void wdc_default_write_raw_multi_2 __P((struct channel_softc *, 133 void *, unsigned int)); 134 void wdc_default_read_raw_multi_4 __P((struct channel_softc *, 135 void *, unsigned int)); 136 void wdc_default_write_raw_multi_4 __P((struct channel_softc *, 137 void *, unsigned int)); 138 139 int wdc_floating_bus __P((struct channel_softc *, int)); 140 int wdc_preata_drive __P((struct channel_softc *, int)); 141 int wdc_ata_present __P((struct channel_softc *, int)); 142 143 struct channel_softc_vtbl wdc_default_vtbl = { 144 wdc_default_read_reg, 145 wdc_default_write_reg, 146 wdc_default_read_raw_multi_2, 147 wdc_default_write_raw_multi_2, 148 wdc_default_read_raw_multi_4, 149 wdc_default_write_raw_multi_4 150 }; 151 152 u_int8_t 153 wdc_default_read_reg(chp, reg) 154 struct channel_softc *chp; 155 enum wdc_regs reg; 156 { 157 #ifdef DIAGNOSTIC 158 if (reg & _WDC_WRONLY) { 159 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 160 } 161 #endif 162 163 if (reg & _WDC_AUX) 164 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 165 reg & _WDC_REGMASK)); 166 else 167 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 168 reg & _WDC_REGMASK)); 169 } 170 171 void 172 wdc_default_write_reg(chp, reg, val) 173 struct channel_softc *chp; 174 enum wdc_regs reg; 175 u_int8_t val; 176 { 177 #ifdef DIAGNOSTIC 178 if (reg & _WDC_RDONLY) { 179 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 180 } 181 #endif 182 183 if (reg & _WDC_AUX) 184 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 185 reg & _WDC_REGMASK, val); 186 else 187 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 188 reg & _WDC_REGMASK, val); 189 } 190 191 192 void 193 wdc_default_read_raw_multi_2(chp, data, nbytes) 194 struct channel_softc *chp; 195 void *data; 196 unsigned int nbytes; 197 { 198 if (data == NULL) { 199 int i; 200 201 for (i = 0; i < nbytes; i += 2) { 202 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 203 } 204 205 return; 206 } 207 208 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 209 data, nbytes); 210 return; 211 } 212 213 214 void 215 wdc_default_write_raw_multi_2(chp, data, nbytes) 216 struct channel_softc *chp; 217 void *data; 218 unsigned int nbytes; 219 { 220 if (data == NULL) { 221 int i; 222 223 for (i = 0; i < nbytes; i += 2) { 224 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 225 } 226 227 return; 228 } 229 230 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 231 data, nbytes); 232 return; 233 } 234 235 236 void 237 wdc_default_write_raw_multi_4(chp, data, nbytes) 238 struct channel_softc *chp; 239 void *data; 240 unsigned int nbytes; 241 { 242 if (data == NULL) { 243 int i; 244 245 for (i = 0; i < nbytes; i += 4) { 246 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 247 } 248 249 return; 250 } 251 252 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 253 data, nbytes); 254 return; 255 } 256 257 258 void 259 wdc_default_read_raw_multi_4(chp, data, nbytes) 260 struct channel_softc *chp; 261 void *data; 262 unsigned int nbytes; 263 { 264 if (data == NULL) { 265 int i; 266 267 for (i = 0; i < nbytes; i += 4) { 268 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 269 } 270 271 return; 272 } 273 274 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 275 data, nbytes); 276 return; 277 } 278 279 280 int 281 wdprint(aux, pnp) 282 void *aux; 283 const char *pnp; 284 { 285 struct ata_atapi_attach *aa_link = aux; 286 if (pnp) 287 printf("drive at %s", pnp); 288 printf(" channel %d drive %d", aa_link->aa_channel, 289 aa_link->aa_drv_data->drive); 290 return (UNCONF); 291 } 292 293 int 294 atapi_print(aux, pnp) 295 void *aux; 296 const char *pnp; 297 { 298 struct ata_atapi_attach *aa_link = aux; 299 if (pnp) 300 printf("atapiscsi at %s", pnp); 301 printf(" channel %d", aa_link->aa_channel); 302 return (UNCONF); 303 } 304 305 void 306 wdc_disable_intr(chp) 307 struct channel_softc *chp; 308 { 309 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 310 } 311 312 void 313 wdc_enable_intr(chp) 314 struct channel_softc *chp; 315 { 316 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 317 } 318 319 int 320 wdc_floating_bus(chp, drive) 321 struct channel_softc *chp; 322 int drive; 323 324 { 325 u_int8_t cumulative_status, status; 326 int iter; 327 328 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 329 delay(10); 330 331 /* Stolen from Phoenix BIOS Drive Autotyping document */ 332 cumulative_status = 0; 333 for (iter = 0; iter < 100; iter++) { 334 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 335 delay (1); 336 337 status = CHP_READ_REG(chp, wdr_status); 338 339 /* The other bits are meaningless if BSY is set */ 340 if (status & WDCS_BSY) 341 continue; 342 343 cumulative_status |= status; 344 345 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 346 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 347 return 1; 348 } 349 350 351 return 0; 352 } 353 354 355 int 356 wdc_preata_drive(chp, drive) 357 struct channel_softc *chp; 358 int drive; 359 360 { 361 if (wdc_floating_bus(chp, drive)) { 362 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 363 chp->wdc->sc_dev.dv_xname, 364 chp->channel, drive), DEBUG_PROBE); 365 return 0; 366 } 367 368 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 369 delay(100); 370 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 371 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 372 chp->wdc->sc_dev.dv_xname, 373 chp->channel, drive), DEBUG_PROBE); 374 return 0; 375 } 376 377 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 378 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 379 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 380 chp->wdc->sc_dev.dv_xname, 381 chp->channel, drive), DEBUG_PROBE); 382 return 0; 383 } 384 385 return 1; 386 } 387 388 int 389 wdc_ata_present(chp, drive) 390 struct channel_softc *chp; 391 int drive; 392 { 393 int time_to_done; 394 int retry_cnt = 0; 395 396 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 397 delay(10); 398 399 retry: 400 /* 401 You're actually supposed to wait up to 10 seconds 402 for DRDY. However, as a practical matter, most 403 drives assert DRDY very quickly after dropping BSY. 404 405 The 10 seconds wait is sub-optimal because, according 406 to the ATA standard, the master should reply with 00 407 for any reads to a non-existant slave. 408 */ 409 time_to_done = wdc_wait_for_status(chp, 410 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 411 (WDCS_DRDY | WDCS_DSC), 1000); 412 if (time_to_done == -1) { 413 if (retry_cnt == 0 && chp->ch_status == 0x00) { 414 /* At least one flash card needs to be kicked */ 415 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 416 retry_cnt++; 417 goto retry; 418 } 419 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 420 " %02x\n", 421 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 422 chp->channel, drive, chp->ch_status), 423 DEBUG_PROBE); 424 return 0; 425 } 426 427 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 428 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 429 " %02x\n", 430 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 431 chp->channel, drive, chp->ch_status), 432 DEBUG_PROBE); 433 434 return 0; 435 } 436 437 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 438 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 439 chp->channel, drive, time_to_done), DEBUG_PROBE); 440 441 /* 442 * Test register writability 443 */ 444 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 445 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 446 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 447 DELAY(10); 448 449 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 450 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 451 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 452 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 453 chp->channel, drive), DEBUG_PROBE); 454 return 0; 455 } 456 457 return 1; 458 } 459 460 461 /* 462 Test to see controller with at least one attached drive is there. 463 Returns a bit for each possible drive found (0x01 for drive 0, 464 0x02 for drive 1). 465 */ 466 467 int 468 wdcprobe(chp) 469 struct channel_softc *chp; 470 { 471 u_int8_t st0, st1, sc, sn, cl, ch; 472 u_int8_t ret_value = 0x03; 473 u_int8_t drive; 474 475 if (chp->_vtbl == 0) { 476 int s = splbio(); 477 chp->_vtbl = &wdc_default_vtbl; 478 splx(s); 479 } 480 481 #ifdef WDCDEBUG 482 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 483 (chp->wdc && 484 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 485 wdcdebug_mask |= DEBUG_PROBE; 486 #endif 487 488 if (chp->wdc == NULL || 489 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 490 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 491 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM); 492 delay(10); 493 st0 = CHP_READ_REG(chp, wdr_status); 494 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | 0x10); 495 delay(10); 496 st1 = CHP_READ_REG(chp, wdr_status); 497 498 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 499 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 500 chp->channel, st0, st1), DEBUG_PROBE); 501 502 /* 503 If the status is 0x7f or 0xff, then it's 504 an empty channel with pull-up resistors. 505 */ 506 if ((st0 & 0x7f) == 0x7f) 507 ret_value &= ~0x01; 508 if ((st1 & 0x7f) == 0x7f) 509 ret_value &= ~0x02; 510 if (ret_value == 0) 511 return 0; 512 } 513 514 /* reset the channel */ 515 CHP_WRITE_REG(chp,wdr_ctlr, WDCTL_RST | WDCTL_4BIT); 516 delay(10); 517 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 518 delay(2000); 519 520 ret_value = __wdcwait_reset(chp, ret_value); 521 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 522 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 523 ret_value), DEBUG_PROBE); 524 525 if (ret_value == 0) 526 return 0; 527 528 /* 529 * Use signatures to find potential ATAPI drives 530 */ 531 for (drive = 0; drive < 2; drive++) { 532 if ((ret_value & (0x01 << drive)) == 0) 533 continue; 534 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 535 delay(10); 536 /* Save registers contents */ 537 st0 = CHP_READ_REG(chp, wdr_status); 538 sc = CHP_READ_REG(chp, wdr_seccnt); 539 sn = CHP_READ_REG(chp, wdr_sector); 540 cl = CHP_READ_REG(chp, wdr_cyl_lo); 541 ch = CHP_READ_REG(chp, wdr_cyl_hi); 542 543 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%x, sc=0x%x" 544 " sn=0x%x cl=0x%x ch=0x%x\n", 545 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 546 chp->channel, drive, st0, sc, sn, cl, ch), DEBUG_PROBE); 547 /* 548 * This is a simplification of the test in the ATAPI 549 * spec since not all drives seem to set the other regs 550 * correctly. 551 */ 552 if (cl == 0x14 && ch == 0xeb) 553 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 554 } 555 556 /* 557 * Detect ATA drives by poking around the registers 558 */ 559 for (drive = 0; drive < 2; drive++) { 560 if ((ret_value & (0x01 << drive)) == 0) 561 continue; 562 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 563 continue; 564 565 wdc_disable_intr(chp); 566 /* ATA detect */ 567 if (wdc_ata_present(chp, drive)) { 568 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 569 if (chp->wdc == NULL || 570 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 571 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 572 } else { 573 ret_value &= ~(1 << drive); 574 } 575 wdc_enable_intr(chp); 576 } 577 578 #ifdef WDCDEBUG 579 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 580 (chp->wdc && 581 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 582 wdcdebug_mask &= ~DEBUG_PROBE; 583 #endif 584 return (ret_value); 585 } 586 587 /* 588 * Call activate routine of underlying devices. 589 */ 590 int 591 wdcactivate(self, act) 592 struct device *self; 593 enum devact act; 594 { 595 int error = 0; 596 int s; 597 598 s = splbio(); 599 config_activate_children(self, act); 600 splx(s); 601 602 return (error); 603 } 604 605 void 606 wdcattach(chp) 607 struct channel_softc *chp; 608 { 609 int channel_flags, ctrl_flags, i; 610 #ifndef __OpenBSD__ 611 int error; 612 #endif 613 struct ata_atapi_attach aa_link; 614 static int inited = 0; 615 #ifdef WDCDEBUG 616 int savedmask = wdcdebug_mask; 617 #endif 618 619 if (!cold) 620 at_poll = AT_WAIT; 621 622 timeout_set(&chp->ch_timo, wdctimeout, chp); 623 624 #ifndef __OpenBSD__ 625 if ((error = wdc_addref(chp)) != 0) { 626 printf("%s: unable to enable controller\n", 627 chp->wdc->sc_dev.dv_xname); 628 return; 629 } 630 #endif 631 if (!chp->_vtbl) 632 chp->_vtbl = &wdc_default_vtbl; 633 634 if (wdcprobe(chp) == 0) { 635 /* If no drives, abort attach here. */ 636 #ifndef __OpenBSD__ 637 wdc_delref(chp); 638 #endif 639 return; 640 } 641 642 /* ATAPI drives need settling time. Give them 250ms */ 643 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 644 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 645 delay(250 * 1000); 646 } 647 648 #ifdef WDCDEBUG 649 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 650 wdcdebug_mask |= DEBUG_PROBE; 651 652 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 653 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 654 wdcdebug_mask = DEBUG_PROBE; 655 } 656 #endif 657 658 /* initialise global data */ 659 if (inited == 0) { 660 /* Initialize the wdc_xfer pool. */ 661 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 662 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 663 inited++; 664 } 665 TAILQ_INIT(&chp->ch_queue->sc_xfer); 666 667 for (i = 0; i < 2; i++) { 668 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 669 670 drvp->chnl_softc = chp; 671 drvp->drive = i; 672 /* If controller can't do 16bit flag the drives as 32bit */ 673 if ((chp->wdc->cap & 674 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 675 WDC_CAPABILITY_DATA32) 676 drvp->drive_flags |= DRIVE_CAP32; 677 678 if ((drvp->drive_flags & DRIVE) == 0) 679 continue; 680 681 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 682 chp->ch_flags |= WDCF_ONESLAVE; 683 /* 684 * Issue an IDENTIFY command in order to distinct ATA from OLD. 685 * This also kill ATAPI ghost. 686 */ 687 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 688 CMD_OK) { 689 /* If IDENTIFY succeded, this is not an OLD ctrl */ 690 drvp->drive_flags &= ~DRIVE_OLD; 691 } else { 692 drvp->drive_flags &= 693 ~(DRIVE_ATA | DRIVE_ATAPI); 694 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 695 chp->wdc->sc_dev.dv_xname, 696 chp->channel, i), DEBUG_PROBE); 697 698 if ((drvp->drive_flags & DRIVE_OLD) && 699 !wdc_preata_drive(chp, i)) 700 drvp->drive_flags &= ~DRIVE_OLD; 701 } 702 } 703 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 704 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 705 706 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 707 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 708 DEBUG_PROBE); 709 710 /* If no drives, abort here */ 711 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 712 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 713 goto exit; 714 715 for (i = 0; i < 2; i++) { 716 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 717 continue; 718 } 719 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 720 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 721 aa_link.aa_type = T_ATAPI; 722 else 723 aa_link.aa_type = T_ATA; 724 aa_link.aa_channel = chp->channel; 725 aa_link.aa_openings = 1; 726 aa_link.aa_drv_data = &chp->ch_drive[i]; 727 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 728 } 729 730 /* 731 * reset drive_flags for unnatached devices, reset state for attached 732 * ones 733 */ 734 for (i = 0; i < 2; i++) { 735 if (chp->ch_drive[i].drive_name[0] == 0) 736 chp->ch_drive[i].drive_flags = 0; 737 } 738 739 #ifndef __OpenBSD__ 740 wdc_delref(chp); 741 #endif 742 743 exit: 744 #ifdef WDCDEBUG 745 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 746 wdcdebug_mask &= ~DEBUG_PROBE; 747 748 wdcdebug_mask = savedmask; 749 #endif 750 return; 751 } 752 753 /* 754 * Start I/O on a controller, for the given channel. 755 * The first xfer may be not for our channel if the channel queues 756 * are shared. 757 */ 758 void 759 wdcstart(chp) 760 struct channel_softc *chp; 761 { 762 struct wdc_xfer *xfer; 763 764 #ifdef WDC_DIAGNOSTIC 765 int spl1, spl2; 766 767 spl1 = splbio(); 768 spl2 = splbio(); 769 if (spl2 != spl1) { 770 printf("wdcstart: not at splbio()\n"); 771 panic("wdcstart"); 772 } 773 splx(spl2); 774 splx(spl1); 775 #endif /* WDC_DIAGNOSTIC */ 776 777 /* is there a xfer ? */ 778 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) { 779 return; 780 } 781 782 /* adjust chp, in case we have a shared queue */ 783 chp = xfer->chp; 784 785 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 786 return; /* channel already active */ 787 } 788 #ifdef DIAGNOSTIC 789 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 790 panic("wdcstart: channel waiting for irq\n"); 791 #endif 792 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 793 if (!(chp->wdc->claim_hw)(chp, 0)) 794 return; 795 796 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 797 chp->channel, xfer->drive), DEBUG_XFERS); 798 chp->ch_flags |= WDCF_ACTIVE; 799 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 800 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 801 chp->ch_drive[xfer->drive].state = 0; 802 } 803 xfer->c_start(chp, xfer); 804 } 805 806 int 807 wdcdetach(chp, flags) 808 struct channel_softc *chp; 809 int flags; 810 { 811 int s, rv; 812 813 s = splbio(); 814 wdc_kill_pending(chp); 815 816 rv = config_detach_children((struct device *)chp->wdc, flags); 817 splx(s); 818 819 return (rv); 820 } 821 822 /* restart an interrupted I/O */ 823 void 824 wdcrestart(v) 825 void *v; 826 { 827 struct channel_softc *chp = v; 828 int s; 829 830 s = splbio(); 831 wdcstart(chp); 832 splx(s); 833 } 834 835 836 /* 837 * Interrupt routine for the controller. Acknowledge the interrupt, check for 838 * errors on the current operation, mark it done if necessary, and start the 839 * next request. Also check for a partially done transfer, and continue with 840 * the next chunk if so. 841 */ 842 int 843 wdcintr(arg) 844 void *arg; 845 { 846 struct channel_softc *chp = arg; 847 struct wdc_xfer *xfer; 848 int ret; 849 850 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 851 /* Acknowledge interrupt by reading status */ 852 if (chp->_vtbl == 0) { 853 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 854 wdr_status & _WDC_REGMASK); 855 } else { 856 CHP_READ_REG(chp, wdr_status); 857 } 858 859 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 860 return 0; 861 } 862 863 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 864 xfer = chp->ch_queue->sc_xfer.tqh_first; 865 chp->ch_flags &= ~WDCF_IRQ_WAIT; 866 ret = xfer->c_intr(chp, xfer, 1); 867 if (ret == 0) /* irq was not for us, still waiting for irq */ 868 chp->ch_flags |= WDCF_IRQ_WAIT; 869 return (ret); 870 } 871 872 /* Put all disk in RESET state */ 873 void wdc_reset_channel(drvp) 874 struct ata_drive_datas *drvp; 875 { 876 struct channel_softc *chp = drvp->chnl_softc; 877 int drive; 878 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 879 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 880 DEBUG_FUNCS); 881 (void) wdcreset(chp, VERBOSE); 882 for (drive = 0; drive < 2; drive++) { 883 chp->ch_drive[drive].state = 0; 884 } 885 } 886 887 int 888 wdcreset(chp, verb) 889 struct channel_softc *chp; 890 int verb; 891 { 892 int drv_mask1, drv_mask2; 893 894 if (!chp->_vtbl) 895 chp->_vtbl = &wdc_default_vtbl; 896 897 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_RST | WDCTL_4BIT); 898 delay(10); 899 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 900 delay(2000); 901 902 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 903 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 904 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 905 if (verb && drv_mask2 != drv_mask1) { 906 printf("%s channel %d: reset failed for", 907 chp->wdc->sc_dev.dv_xname, chp->channel); 908 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 909 printf(" drive 0"); 910 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 911 printf(" drive 1"); 912 printf("\n"); 913 } 914 915 return (drv_mask1 != drv_mask2) ? 1 : 0; 916 } 917 918 static int 919 __wdcwait_reset(chp, drv_mask) 920 struct channel_softc *chp; 921 int drv_mask; 922 { 923 int timeout; 924 u_int8_t st0, st1; 925 926 /* wait for BSY to deassert */ 927 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 928 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM); /* master */ 929 delay(10); 930 st0 = CHP_READ_REG(chp, wdr_status); 931 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | 0x10); /* slave */ 932 delay(10); 933 st1 = CHP_READ_REG(chp, wdr_status); 934 935 if ((drv_mask & 0x01) == 0) { 936 /* no master */ 937 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 938 /* No master, slave is ready, it's done */ 939 goto end; 940 } 941 } else if ((drv_mask & 0x02) == 0) { 942 /* no slave */ 943 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 944 /* No slave, master is ready, it's done */ 945 goto end; 946 } 947 } else { 948 /* Wait for both master and slave to be ready */ 949 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 950 goto end; 951 } 952 } 953 delay(WDCDELAY); 954 } 955 /* Reset timed out. Maybe it's because drv_mask was not right */ 956 if (st0 & WDCS_BSY) 957 drv_mask &= ~0x01; 958 if (st1 & WDCS_BSY) 959 drv_mask &= ~0x02; 960 end: 961 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x, " 962 "reset time=%d msec\n", 963 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 964 st0, st1, timeout*WDCDELAY/1000), DEBUG_PROBE); 965 966 return drv_mask; 967 } 968 969 /* 970 * Wait for a drive to be !BSY, and have mask in its status register. 971 * return -1 for a timeout after "timeout" ms. 972 */ 973 int 974 wdc_wait_for_status(chp, mask, bits, timeout) 975 struct channel_softc *chp; 976 int mask, bits, timeout; 977 { 978 u_char status; 979 int time = 0; 980 981 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 982 :"none", chp->channel), DEBUG_STATUS); 983 chp->ch_error = 0; 984 985 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 986 987 for (;;) { 988 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 989 990 if (status == 0xff && (chp->ch_flags & WDCF_ONESLAVE)) { 991 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | 0x10); 992 chp->ch_status = status = 993 CHP_READ_REG(chp, wdr_status); 994 } 995 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 996 break; 997 if (++time > timeout) { 998 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 999 "error %x\n", status, 1000 CHP_READ_REG(chp, wdr_error)), 1001 DEBUG_STATUSX | DEBUG_STATUS); 1002 return -1; 1003 } 1004 delay(WDCDELAY); 1005 } 1006 if (status & WDCS_ERR) { 1007 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1008 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1009 DEBUG_STATUSX | DEBUG_STATUS); 1010 } 1011 1012 #ifdef WDCNDELAY_DEBUG 1013 /* After autoconfig, there should be no long delays. */ 1014 if (!cold && time > WDCNDELAY_DEBUG) { 1015 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1016 if (xfer == NULL) 1017 printf("%s channel %d: warning: busy-wait took %dus\n", 1018 chp->wdc->sc_dev.dv_xname, chp->channel, 1019 WDCDELAY * time); 1020 else 1021 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1022 chp->wdc->sc_dev.dv_xname, chp->channel, 1023 xfer->drive, 1024 WDCDELAY * time); 1025 } 1026 #endif 1027 return time; 1028 } 1029 1030 void 1031 wdctimeout(arg) 1032 void *arg; 1033 { 1034 struct channel_softc *chp = (struct channel_softc *)arg; 1035 struct wdc_xfer *xfer; 1036 int s; 1037 1038 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1039 1040 s = splbio(); 1041 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1042 1043 /* Did we lose a race with the interrupt? */ 1044 if (xfer == NULL || 1045 !timeout_triggered(&chp->ch_timo)) { 1046 splx(s); 1047 return; 1048 } 1049 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1050 __wdcerror(chp, "timeout"); 1051 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1052 "atapi":"ata"); 1053 printf("\tc_bcount: %d\n", xfer->c_bcount); 1054 printf("\tc_skip: %d\n", xfer->c_skip); 1055 /* 1056 * Call the interrupt routine. If we just missed and interrupt, 1057 * it will do what's needed. Else, it will take the needed 1058 * action (reset the device). 1059 */ 1060 xfer->c_flags |= C_TIMEOU; 1061 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1062 xfer->c_intr(chp, xfer, 1); 1063 } else 1064 __wdcerror(chp, "missing untimeout"); 1065 splx(s); 1066 } 1067 1068 /* 1069 * Probe drive's capabilites, for use by the controller later 1070 * Assumes drvp points to an existing drive. 1071 * XXX this should be a controller-indep function 1072 */ 1073 void 1074 wdc_probe_caps(drvp, params) 1075 struct ata_drive_datas *drvp; 1076 struct ataparams *params; 1077 { 1078 struct channel_softc *chp = drvp->chnl_softc; 1079 struct wdc_softc *wdc = chp->wdc; 1080 int i, valid_mode_found; 1081 int cf_flags = drvp->cf_flags; 1082 1083 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1084 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1085 struct ataparams params2; 1086 1087 /* 1088 * Controller claims 16 and 32 bit transfers. 1089 * Re-do an IDENTIFY with 32-bit transfers, 1090 * and compare results. 1091 */ 1092 drvp->drive_flags |= DRIVE_CAP32; 1093 ata_get_params(drvp, at_poll, ¶ms2); 1094 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1095 /* Not good. fall back to 16bits */ 1096 drvp->drive_flags &= ~DRIVE_CAP32; 1097 } 1098 } 1099 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1100 if (params->atap_ata_major > 0x01 && 1101 params->atap_ata_major != 0xffff) { 1102 for (i = 14; i > 0; i--) { 1103 if (params->atap_ata_major & (1 << i)) { 1104 printf("%sATA version %d\n", sep, i); 1105 drvp->ata_vers = i; 1106 break; 1107 } 1108 } 1109 } else 1110 #endif 1111 /* An ATAPI device is at last PIO mode 3 */ 1112 if (drvp->drive_flags & DRIVE_ATAPI) 1113 drvp->PIO_mode = 3; 1114 1115 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap %d cf_flags %d\n", 1116 wdc->cap, cf_flags), DEBUG_PROBE); 1117 1118 /* 1119 * It's not in the specs, but it seems that some drive 1120 * returns 0xffff in atap_extensions when this field is invalid 1121 */ 1122 if (params->atap_extensions != 0xffff && 1123 (params->atap_extensions & WDC_EXT_MODES)) { 1124 valid_mode_found = 0; 1125 /* 1126 * XXX some drives report something wrong here (they claim to 1127 * support PIO mode 8 !). As mode is coded on 3 bits in 1128 * SET FEATURE, limit it to 7 (so limit i to 4). 1129 * If higther mode than 7 is found, abort. 1130 */ 1131 for (i = 7; i >= 0; i--) { 1132 if ((params->atap_piomode_supp & (1 << i)) == 0) 1133 continue; 1134 if (i > 4) 1135 return; 1136 1137 valid_mode_found = 1; 1138 1139 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1140 drvp->PIO_cap = i + 3; 1141 continue; 1142 } 1143 1144 /* 1145 * See if mode is accepted. 1146 * If the controller can't set its PIO mode, 1147 * assume the BIOS set it up correctly 1148 */ 1149 if (ata_set_mode(drvp, 0x08 | (i + 3), 1150 at_poll) != CMD_OK) 1151 continue; 1152 1153 /* 1154 * If controller's driver can't set its PIO mode, 1155 * set the highest one the controller supports 1156 */ 1157 if (wdc->PIO_cap >= i + 3) { 1158 drvp->PIO_mode = i + 3; 1159 drvp->PIO_cap = i + 3; 1160 break; 1161 } 1162 } 1163 if (!valid_mode_found) { 1164 /* 1165 * We didn't find a valid PIO mode. 1166 * Assume the values returned for DMA are buggy too 1167 */ 1168 return; 1169 } 1170 drvp->drive_flags |= DRIVE_MODE; 1171 1172 /* Some controllers don't support ATAPI DMA */ 1173 if ((drvp->drive_flags & DRIVE_ATAPI) && 1174 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1175 return; 1176 1177 valid_mode_found = 0; 1178 for (i = 7; i >= 0; i--) { 1179 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1180 continue; 1181 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1182 (wdc->cap & WDC_CAPABILITY_MODE)) 1183 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1184 != CMD_OK) 1185 continue; 1186 1187 valid_mode_found = 1; 1188 1189 if (wdc->cap & WDC_CAPABILITY_DMA) { 1190 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1191 wdc->DMA_cap < i) 1192 continue; 1193 drvp->DMA_mode = i; 1194 drvp->DMA_cap = i; 1195 drvp->drive_flags |= DRIVE_DMA; 1196 } 1197 break; 1198 } 1199 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1200 for (i = 7; i >= 0; i--) { 1201 if ((params->atap_udmamode_supp & (1 << i)) 1202 == 0) 1203 continue; 1204 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1205 (wdc->cap & WDC_CAPABILITY_UDMA)) 1206 if (ata_set_mode(drvp, 0x40 | i, 1207 at_poll) != CMD_OK) 1208 continue; 1209 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1210 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1211 wdc->UDMA_cap < i) 1212 continue; 1213 drvp->UDMA_mode = i; 1214 drvp->UDMA_cap = i; 1215 drvp->drive_flags |= DRIVE_UDMA; 1216 } 1217 break; 1218 } 1219 } 1220 } 1221 1222 /* Try to guess ATA version here, if it didn't get reported */ 1223 if (drvp->ata_vers == 0) { 1224 if (drvp->drive_flags & DRIVE_UDMA) 1225 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1226 else if (drvp->PIO_cap > 2) 1227 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1228 } 1229 if (cf_flags & ATA_CONFIG_PIO_SET) { 1230 drvp->PIO_mode = 1231 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1232 drvp->drive_flags |= DRIVE_MODE; 1233 } 1234 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1235 /* don't care about DMA modes */ 1236 return; 1237 } 1238 if (cf_flags & ATA_CONFIG_DMA_SET) { 1239 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1240 ATA_CONFIG_DMA_DISABLE) { 1241 drvp->drive_flags &= ~DRIVE_DMA; 1242 } else { 1243 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1244 ATA_CONFIG_DMA_OFF; 1245 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1246 } 1247 } 1248 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1249 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1250 ATA_CONFIG_UDMA_DISABLE) { 1251 drvp->drive_flags &= ~DRIVE_UDMA; 1252 } else { 1253 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1254 ATA_CONFIG_UDMA_OFF; 1255 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1256 } 1257 } 1258 } 1259 1260 void 1261 wdc_output_bytes(drvp, bytes, buflen) 1262 struct ata_drive_datas *drvp; 1263 void *bytes; 1264 unsigned int buflen; 1265 { 1266 struct channel_softc *chp = drvp->chnl_softc; 1267 unsigned int off = 0; 1268 unsigned int len = buflen, roundlen; 1269 1270 if (drvp->drive_flags & DRIVE_CAP32) { 1271 roundlen = len & ~3; 1272 1273 CHP_WRITE_RAW_MULTI_4(chp, 1274 (void *)((u_int8_t *)bytes + off), roundlen); 1275 1276 off += roundlen; 1277 len -= roundlen; 1278 } 1279 1280 if (len > 0) { 1281 roundlen = (len + 1) & ~0x1; 1282 1283 CHP_WRITE_RAW_MULTI_2(chp, 1284 (void *)((u_int8_t *)bytes + off), roundlen); 1285 } 1286 1287 return; 1288 } 1289 1290 void 1291 wdc_input_bytes(drvp, bytes, buflen) 1292 struct ata_drive_datas *drvp; 1293 void *bytes; 1294 unsigned int buflen; 1295 { 1296 struct channel_softc *chp = drvp->chnl_softc; 1297 unsigned int off = 0; 1298 unsigned int len = buflen, roundlen; 1299 1300 if (drvp->drive_flags & DRIVE_CAP32) { 1301 roundlen = len & ~3; 1302 1303 CHP_READ_RAW_MULTI_4(chp, 1304 (void *)((u_int8_t *)bytes + off), roundlen); 1305 1306 off += roundlen; 1307 len -= roundlen; 1308 } 1309 1310 if (len > 0) { 1311 roundlen = (len + 1) & ~0x1; 1312 1313 CHP_READ_RAW_MULTI_2(chp, 1314 (void *)((u_int8_t *)bytes + off), roundlen); 1315 } 1316 1317 return; 1318 } 1319 1320 void 1321 wdc_print_caps(drvp) 1322 struct ata_drive_datas *drvp; 1323 { 1324 /* This is actually a lie until we fix the _probe_caps 1325 algorithm. Don't print out lies */ 1326 #if 0 1327 printf("%s: can use ", drvp->drive_name); 1328 1329 if (drvp->drive_flags & DRIVE_CAP32) { 1330 printf("32-bit"); 1331 } else 1332 printf("16-bit"); 1333 1334 printf(", PIO mode %d", drvp->PIO_cap); 1335 1336 if (drvp->drive_flags & DRIVE_DMA) { 1337 printf(", DMA mode %d", drvp->DMA_cap); 1338 } 1339 1340 if (drvp->drive_flags & DRIVE_UDMA) { 1341 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1342 } 1343 1344 printf("\n"); 1345 #endif 1346 } 1347 1348 void 1349 wdc_print_current_modes(chp) 1350 struct channel_softc *chp; 1351 { 1352 int drive; 1353 struct ata_drive_datas *drvp; 1354 1355 for (drive = 0; drive < 2; drive++) { 1356 drvp = &chp->ch_drive[drive]; 1357 if ((drvp->drive_flags & DRIVE) == 0) 1358 continue; 1359 1360 printf("%s(%s:%d:%d):", 1361 drvp->drive_name, 1362 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1363 1364 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1365 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1366 printf(" using BIOS timings"); 1367 else 1368 printf(" using PIO mode %d", drvp->PIO_mode); 1369 if (drvp->drive_flags & DRIVE_DMA) 1370 printf(", DMA mode %d", drvp->DMA_mode); 1371 if (drvp->drive_flags & DRIVE_UDMA) 1372 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1373 printf("\n"); 1374 } 1375 } 1376 1377 /* 1378 * downgrade the transfer mode of a drive after an error. return 1 if 1379 * downgrade was possible, 0 otherwise. 1380 */ 1381 int 1382 wdc_downgrade_mode(drvp) 1383 struct ata_drive_datas *drvp; 1384 { 1385 struct channel_softc *chp = drvp->chnl_softc; 1386 struct wdc_softc *wdc = chp->wdc; 1387 int cf_flags = drvp->cf_flags; 1388 1389 /* if drive or controller don't know its mode, we can't do much */ 1390 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1391 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1392 return 0; 1393 /* current drive mode was set by a config flag, let it this way */ 1394 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1395 (cf_flags & ATA_CONFIG_DMA_SET) || 1396 (cf_flags & ATA_CONFIG_UDMA_SET)) 1397 return 0; 1398 1399 /* 1400 * We'd ideally like to use an Ultra DMA mode since they have the 1401 * protection of a CRC. So we try each Ultra DMA mode and see if 1402 * we can find any working combo 1403 */ 1404 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1405 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1406 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1407 drvp->drive_name, drvp->UDMA_mode); 1408 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1409 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1410 /* 1411 * If we were using ultra-DMA, don't downgrade to 1412 * multiword DMA if we noticed a CRC error. It has 1413 * been noticed that CRC errors in ultra-DMA lead to 1414 * silent data corruption in multiword DMA. Data 1415 * corruption is less likely to occur in PIO mode. 1416 */ 1417 drvp->drive_flags &= ~DRIVE_UDMA; 1418 drvp->drive_flags |= DRIVE_DMA; 1419 drvp->DMA_mode = drvp->DMA_cap; 1420 printf("%s: transfer error, downgrading to DMA mode %d\n", 1421 drvp->drive_name, drvp->DMA_mode); 1422 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1423 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1424 drvp->PIO_mode = drvp->PIO_cap; 1425 printf("%s: transfer error, downgrading to PIO mode %d\n", 1426 drvp->drive_name, drvp->PIO_mode); 1427 } else /* already using PIO, can't downgrade */ 1428 return 0; 1429 1430 wdc->set_modes(chp); 1431 /* reset the channel, which will schedule all drives for setup */ 1432 wdc_reset_channel(drvp); 1433 return 1; 1434 } 1435 1436 int 1437 wdc_exec_command(drvp, wdc_c) 1438 struct ata_drive_datas *drvp; 1439 struct wdc_command *wdc_c; 1440 { 1441 struct channel_softc *chp = drvp->chnl_softc; 1442 struct wdc_xfer *xfer; 1443 int s, ret; 1444 1445 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1446 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1447 DEBUG_FUNCS); 1448 1449 /* set up an xfer and queue. Wait for completion */ 1450 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1451 WDC_NOSLEEP); 1452 if (xfer == NULL) { 1453 return WDC_TRY_AGAIN; 1454 } 1455 1456 if (wdc_c->flags & AT_POLL) 1457 xfer->c_flags |= C_POLL; 1458 xfer->drive = drvp->drive; 1459 xfer->databuf = wdc_c->data; 1460 xfer->c_bcount = wdc_c->bcount; 1461 xfer->cmd = wdc_c; 1462 xfer->c_start = __wdccommand_start; 1463 xfer->c_intr = __wdccommand_intr; 1464 xfer->c_kill_xfer = __wdccommand_done; 1465 1466 s = splbio(); 1467 wdc_exec_xfer(chp, xfer); 1468 #ifdef DIAGNOSTIC 1469 if ((wdc_c->flags & AT_POLL) != 0 && 1470 (wdc_c->flags & AT_DONE) == 0) 1471 panic("wdc_exec_command: polled command not done\n"); 1472 #endif 1473 if (wdc_c->flags & AT_DONE) { 1474 ret = WDC_COMPLETE; 1475 } else { 1476 if (wdc_c->flags & AT_WAIT) { 1477 WDCDEBUG_PRINT(("wdc_exec_command sleeping"), 1478 DEBUG_FUNCS); 1479 1480 while ((wdc_c->flags & AT_DONE) == 0) { 1481 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1482 } 1483 ret = WDC_COMPLETE; 1484 } else { 1485 ret = WDC_QUEUED; 1486 } 1487 } 1488 splx(s); 1489 return ret; 1490 } 1491 1492 void 1493 __wdccommand_start(chp, xfer) 1494 struct channel_softc *chp; 1495 struct wdc_xfer *xfer; 1496 { 1497 int drive = xfer->drive; 1498 struct wdc_command *wdc_c = xfer->cmd; 1499 1500 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1501 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1502 DEBUG_FUNCS); 1503 1504 /* 1505 * Disable interrupts if we're polling 1506 */ 1507 if (xfer->c_flags & C_POLL) { 1508 wdc_disable_intr(chp); 1509 } 1510 1511 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1512 DELAY(1); 1513 1514 /* 1515 * For resets, we don't really care to make sure that 1516 * the bus is free 1517 */ 1518 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1519 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1520 wdc_c->timeout) != 0) { 1521 wdc_c->flags |= AT_TIMEOU; 1522 __wdccommand_done(chp, xfer); 1523 return; 1524 } 1525 } else 1526 DELAY(10); 1527 1528 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1529 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1530 if ((wdc_c->flags & AT_POLL) == 0) { 1531 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1532 timeout_add(&chp->ch_timo, wdc_c->timeout / 1000 * hz); 1533 return; 1534 } 1535 /* 1536 * Polled command. Wait for drive ready or drq. Done in intr(). 1537 * Wait for at last 400ns for status bit to be valid. 1538 */ 1539 delay(10); 1540 __wdccommand_intr(chp, xfer, 0); 1541 } 1542 1543 int 1544 __wdccommand_intr(chp, xfer, irq) 1545 struct channel_softc *chp; 1546 struct wdc_xfer *xfer; 1547 int irq; 1548 { 1549 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1550 struct wdc_command *wdc_c = xfer->cmd; 1551 int bcount = wdc_c->bcount; 1552 char *data = wdc_c->data; 1553 1554 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1555 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1556 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1557 (irq == 0) ? wdc_c->timeout : 0)) { 1558 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1559 return 0; /* IRQ was not for us */ 1560 wdc_c->flags |= AT_TIMEOU; 1561 __wdccommand_done(chp, xfer); 1562 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1563 return 1; 1564 } 1565 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1566 chp->wdc->irqack(chp); 1567 if (wdc_c->flags & AT_READ) { 1568 wdc_input_bytes(drvp, data, bcount); 1569 } else if (wdc_c->flags & AT_WRITE) { 1570 wdc_output_bytes(drvp, data, bcount); 1571 } 1572 __wdccommand_done(chp, xfer); 1573 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1574 return 1; 1575 } 1576 1577 void 1578 __wdccommand_done(chp, xfer) 1579 struct channel_softc *chp; 1580 struct wdc_xfer *xfer; 1581 { 1582 struct wdc_command *wdc_c = xfer->cmd; 1583 1584 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1585 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, chp->ch_status), DEBUG_FUNCS); 1586 if (chp->ch_status & WDCS_DWF) 1587 wdc_c->flags |= AT_DF; 1588 if (chp->ch_status & WDCS_ERR) { 1589 wdc_c->flags |= AT_ERROR; 1590 wdc_c->r_error = chp->ch_error; 1591 } 1592 wdc_c->flags |= AT_DONE; 1593 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1594 == 0) { 1595 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1596 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1597 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1598 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1599 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1600 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1601 wdc_c->r_precomp = wdc_c->r_error; 1602 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1603 isn't a readable register */ 1604 } 1605 1606 if (xfer->c_flags & C_POLL) { 1607 wdc_enable_intr(chp); 1608 } 1609 1610 wdc_free_xfer(chp, xfer); 1611 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1612 1613 if (wdc_c->flags & AT_WAIT) 1614 wakeup(wdc_c); 1615 else 1616 if (wdc_c->callback) 1617 wdc_c->callback(wdc_c->callback_arg); 1618 wdcstart(chp); 1619 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1620 return; 1621 } 1622 1623 /* 1624 * Send a command. The drive should be ready. 1625 * Assumes interrupts are blocked. 1626 */ 1627 void 1628 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1629 struct channel_softc *chp; 1630 u_int8_t drive; 1631 u_int8_t command; 1632 u_int16_t cylin; 1633 u_int8_t head, sector, count, precomp; 1634 { 1635 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1636 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1637 chp->channel, drive, command, cylin, head, sector, count, precomp), 1638 DEBUG_FUNCS); 1639 1640 /* Select drive, head, and addressing mode. */ 1641 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1642 1643 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1644 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1645 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1646 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1647 CHP_WRITE_REG(chp, wdr_sector, sector); 1648 CHP_WRITE_REG(chp, wdr_seccnt, count); 1649 1650 /* Send command. */ 1651 CHP_WRITE_REG(chp, wdr_command, command); 1652 return; 1653 } 1654 1655 /* 1656 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1657 * tested by the caller. 1658 */ 1659 void 1660 wdccommandshort(chp, drive, command) 1661 struct channel_softc *chp; 1662 int drive; 1663 int command; 1664 { 1665 1666 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1667 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1668 DEBUG_FUNCS); 1669 1670 /* Select drive. */ 1671 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1672 CHP_WRITE_REG(chp, wdr_command, command); 1673 } 1674 1675 /* Add a command to the queue and start controller. Must be called at splbio */ 1676 1677 void 1678 wdc_exec_xfer(chp, xfer) 1679 struct channel_softc *chp; 1680 struct wdc_xfer *xfer; 1681 { 1682 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1683 chp->channel, xfer->drive), DEBUG_XFERS); 1684 1685 /* complete xfer setup */ 1686 xfer->chp = chp; 1687 1688 /* 1689 * If we are a polled command, and the list is not empty, 1690 * we are doing a dump. Drop the list to allow the polled command 1691 * to complete, we're going to reboot soon anyway. 1692 */ 1693 if ((xfer->c_flags & C_POLL) != 0 && 1694 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1695 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1696 } 1697 /* insert at the end of command list */ 1698 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1699 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1700 chp->ch_flags), DEBUG_XFERS); 1701 wdcstart(chp); 1702 } 1703 1704 struct wdc_xfer * 1705 wdc_get_xfer(flags) 1706 int flags; 1707 { 1708 struct wdc_xfer *xfer; 1709 int s; 1710 1711 s = splbio(); 1712 xfer = pool_get(&wdc_xfer_pool, 1713 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1714 splx(s); 1715 if (xfer != NULL) 1716 memset(xfer, 0, sizeof(struct wdc_xfer)); 1717 return xfer; 1718 } 1719 1720 void 1721 wdc_free_xfer(chp, xfer) 1722 struct channel_softc *chp; 1723 struct wdc_xfer *xfer; 1724 { 1725 struct wdc_softc *wdc = chp->wdc; 1726 int s; 1727 1728 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1729 (*wdc->free_hw)(chp); 1730 s = splbio(); 1731 chp->ch_flags &= ~WDCF_ACTIVE; 1732 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1733 pool_put(&wdc_xfer_pool, xfer); 1734 splx(s); 1735 } 1736 1737 1738 /* 1739 * Kill off all pending xfers for a channel_softc. 1740 * 1741 * Must be called at splbio(). 1742 */ 1743 void 1744 wdc_kill_pending(chp) 1745 struct channel_softc *chp; 1746 { 1747 struct wdc_xfer *xfer; 1748 1749 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1750 chp = xfer->chp; 1751 (*xfer->c_kill_xfer)(chp, xfer); 1752 } 1753 } 1754 1755 static void 1756 __wdcerror(chp, msg) 1757 struct channel_softc *chp; 1758 char *msg; 1759 { 1760 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1761 if (xfer == NULL) 1762 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1763 msg); 1764 else 1765 printf("%s(%s:%d:%d): %s\n", 1766 chp->ch_drive[xfer->drive].drive_name, 1767 chp->wdc->sc_dev.dv_xname, 1768 chp->channel, xfer->drive, msg); 1769 } 1770 1771 /* 1772 * the bit bucket 1773 */ 1774 void 1775 wdcbit_bucket(chp, size) 1776 struct channel_softc *chp; 1777 int size; 1778 { 1779 CHP_READ_RAW_MULTI_2(chp, NULL, size); 1780 } 1781 1782 1783 #include <sys/ataio.h> 1784 #include <sys/file.h> 1785 #include <sys/buf.h> 1786 1787 /* 1788 * Glue necessary to hook ATAIOCCOMMAND into physio 1789 */ 1790 1791 struct wdc_ioctl { 1792 LIST_ENTRY(wdc_ioctl) wi_list; 1793 struct buf wi_bp; 1794 struct uio wi_uio; 1795 struct iovec wi_iov; 1796 atareq_t wi_atareq; 1797 struct ata_drive_datas *wi_drvp; 1798 }; 1799 1800 struct wdc_ioctl *wdc_ioctl_find __P((struct buf *)); 1801 void wdc_ioctl_free __P((struct wdc_ioctl *)); 1802 struct wdc_ioctl *wdc_ioctl_get __P((void)); 1803 void wdc_ioctl_strategy __P((struct buf *)); 1804 1805 LIST_HEAD(, wdc_ioctl) wi_head; 1806 1807 /* 1808 * Allocate space for a ioctl queue structure. Mostly taken from 1809 * scsipi_ioctl.c 1810 */ 1811 struct wdc_ioctl * 1812 wdc_ioctl_get() 1813 { 1814 struct wdc_ioctl *wi; 1815 int s; 1816 1817 wi = malloc(sizeof(struct wdc_ioctl), M_TEMP, M_WAITOK); 1818 bzero(wi, sizeof (struct wdc_ioctl)); 1819 s = splbio(); 1820 LIST_INSERT_HEAD(&wi_head, wi, wi_list); 1821 splx(s); 1822 return (wi); 1823 } 1824 1825 /* 1826 * Free an ioctl structure and remove it from our list 1827 */ 1828 1829 void 1830 wdc_ioctl_free(wi) 1831 struct wdc_ioctl *wi; 1832 { 1833 int s; 1834 1835 s = splbio(); 1836 LIST_REMOVE(wi, wi_list); 1837 splx(s); 1838 free(wi, M_TEMP); 1839 } 1840 1841 /* 1842 * Find a wdc_ioctl structure based on the struct buf. 1843 */ 1844 1845 struct wdc_ioctl * 1846 wdc_ioctl_find(bp) 1847 struct buf *bp; 1848 { 1849 struct wdc_ioctl *wi; 1850 int s; 1851 1852 s = splbio(); 1853 for (wi = wi_head.lh_first; wi != 0; wi = wi->wi_list.le_next) 1854 if (bp == &wi->wi_bp) 1855 break; 1856 splx(s); 1857 return (wi); 1858 } 1859 1860 /* 1861 * Ioctl pseudo strategy routine 1862 * 1863 * This is mostly stolen from scsipi_ioctl.c:scsistrategy(). What 1864 * happens here is: 1865 * 1866 * - wdioctl() queues a wdc_ioctl structure. 1867 * 1868 * - wdioctl() calls physio/wdc_ioctl_strategy based on whether or not 1869 * user space I/O is required. If physio() is called, physio() eventually 1870 * calls wdc_ioctl_strategy(). 1871 * 1872 * - In either case, wdc_ioctl_strategy() calls wdc_exec_command() 1873 * to perform the actual command 1874 * 1875 * The reason for the use of the pseudo strategy routine is because 1876 * when doing I/O to/from user space, physio _really_ wants to be in 1877 * the loop. We could put the entire buffer into the ioctl request 1878 * structure, but that won't scale if we want to do things like download 1879 * microcode. 1880 */ 1881 1882 void 1883 wdc_ioctl_strategy(bp) 1884 struct buf *bp; 1885 { 1886 struct wdc_ioctl *wi; 1887 struct wdc_command wdc_c; 1888 int error = 0; 1889 1890 wi = wdc_ioctl_find(bp); 1891 if (wi == NULL) { 1892 printf("user_strat: No ioctl\n"); 1893 error = EINVAL; 1894 goto bad; 1895 } 1896 1897 bzero(&wdc_c, sizeof(wdc_c)); 1898 1899 /* 1900 * Abort if physio broke up the transfer 1901 */ 1902 1903 if (bp->b_bcount != wi->wi_atareq.datalen) { 1904 printf("physio split wd ioctl request... cannot proceed\n"); 1905 error = EIO; 1906 goto bad; 1907 } 1908 1909 /* 1910 * Make sure a timeout was supplied in the ioctl request 1911 */ 1912 1913 if (wi->wi_atareq.timeout == 0) { 1914 error = EINVAL; 1915 goto bad; 1916 } 1917 1918 if (wi->wi_atareq.flags & ATACMD_READ) 1919 wdc_c.flags |= AT_READ; 1920 else if (wi->wi_atareq.flags & ATACMD_WRITE) 1921 wdc_c.flags |= AT_WRITE; 1922 1923 if (wi->wi_atareq.flags & ATACMD_READREG) 1924 wdc_c.flags |= AT_READREG; 1925 1926 wdc_c.flags |= AT_WAIT; 1927 1928 wdc_c.timeout = wi->wi_atareq.timeout; 1929 wdc_c.r_command = wi->wi_atareq.command; 1930 wdc_c.r_head = wi->wi_atareq.head & 0x0f; 1931 wdc_c.r_cyl = wi->wi_atareq.cylinder; 1932 wdc_c.r_sector = wi->wi_atareq.sec_num; 1933 wdc_c.r_count = wi->wi_atareq.sec_count; 1934 wdc_c.r_precomp = wi->wi_atareq.features; 1935 if (wi->wi_drvp->drive_flags & DRIVE_ATAPI) { 1936 wdc_c.r_st_bmask = 0; 1937 wdc_c.r_st_pmask = 0; 1938 if (wdc_c.r_command == WDCC_IDENTIFY) 1939 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 1940 } else { 1941 wdc_c.r_st_bmask = WDCS_DRDY; 1942 wdc_c.r_st_pmask = WDCS_DRDY; 1943 } 1944 wdc_c.data = wi->wi_bp.b_data; 1945 wdc_c.bcount = wi->wi_bp.b_bcount; 1946 1947 if (wdc_exec_command(wi->wi_drvp, &wdc_c) != WDC_COMPLETE) { 1948 wi->wi_atareq.retsts = ATACMD_ERROR; 1949 goto bad; 1950 } 1951 1952 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 1953 if (wdc_c.flags & AT_ERROR) { 1954 wi->wi_atareq.retsts = ATACMD_ERROR; 1955 wi->wi_atareq.error = wdc_c.r_error; 1956 } else if (wdc_c.flags & AT_DF) 1957 wi->wi_atareq.retsts = ATACMD_DF; 1958 else 1959 wi->wi_atareq.retsts = ATACMD_TIMEOUT; 1960 } else { 1961 wi->wi_atareq.retsts = ATACMD_OK; 1962 if (wi->wi_atareq.flags & ATACMD_READREG) { 1963 wi->wi_atareq.head = wdc_c.r_head ; 1964 wi->wi_atareq.cylinder = wdc_c.r_cyl; 1965 wi->wi_atareq.sec_num = wdc_c.r_sector; 1966 wi->wi_atareq.sec_count = wdc_c.r_count; 1967 wi->wi_atareq.features = wdc_c.r_precomp; 1968 wi->wi_atareq.error = wdc_c.r_error; 1969 } 1970 } 1971 1972 bp->b_error = 0; 1973 biodone(bp); 1974 return; 1975 bad: 1976 bp->b_flags |= B_ERROR; 1977 bp->b_error = error; 1978 biodone(bp); 1979 } 1980 1981 int 1982 wdc_ioctl(drvp, xfer, addr, flag) 1983 struct ata_drive_datas *drvp; 1984 u_long xfer; 1985 caddr_t addr; 1986 int flag; 1987 { 1988 int error = 0; 1989 1990 switch (xfer) { 1991 case ATAIOCCOMMAND: 1992 /* 1993 * Make sure this command is (relatively) safe first 1994 */ 1995 if ((((atareq_t *) addr)->flags & ATACMD_READ) == 0 && 1996 (flag & FWRITE) == 0) { 1997 error = EBADF; 1998 goto exit; 1999 } 2000 { 2001 struct wdc_ioctl *wi; 2002 atareq_t *atareq = (atareq_t *) addr; 2003 2004 wi = wdc_ioctl_get(); 2005 wi->wi_drvp = drvp; 2006 wi->wi_atareq = *atareq; 2007 2008 if (atareq->datalen && atareq->flags & 2009 (ATACMD_READ | ATACMD_WRITE)) { 2010 wi->wi_iov.iov_base = atareq->databuf; 2011 wi->wi_iov.iov_len = atareq->datalen; 2012 wi->wi_uio.uio_iov = &wi->wi_iov; 2013 wi->wi_uio.uio_iovcnt = 1; 2014 wi->wi_uio.uio_resid = atareq->datalen; 2015 wi->wi_uio.uio_offset = 0; 2016 wi->wi_uio.uio_segflg = UIO_USERSPACE; 2017 wi->wi_uio.uio_rw = 2018 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE; 2019 wi->wi_uio.uio_procp = curproc; 2020 error = physio(wdc_ioctl_strategy, &wi->wi_bp, 0, 2021 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE, 2022 minphys, &wi->wi_uio); 2023 } else { 2024 /* No need to call physio if we don't have any 2025 user data */ 2026 wi->wi_bp.b_flags = 0; 2027 wi->wi_bp.b_data = 0; 2028 wi->wi_bp.b_bcount = 0; 2029 wi->wi_bp.b_dev = 0; 2030 wi->wi_bp.b_proc = curproc; 2031 LIST_INIT(&wi->wi_bp.b_dep); 2032 wdc_ioctl_strategy(&wi->wi_bp); 2033 error = wi->wi_bp.b_error; 2034 } 2035 *atareq = wi->wi_atareq; 2036 wdc_ioctl_free(wi); 2037 goto exit; 2038 } 2039 default: 2040 error = ENOTTY; 2041 goto exit; 2042 } 2043 2044 exit: 2045 return (error); 2046 } 2047