1 /* $OpenBSD: trm.c,v 1.29 2011/04/27 03:39:32 krw Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.c 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * HISTORY: 13 * 14 * REV# DATE NAME DESCRIPTION 15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x 16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8 17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting 18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic 19 * ------------------------------------------------------------ 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 3. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * ------------------------------------------------------------ 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/buf.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <scsi/scsi_message.h> 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/ic/trm.h> 61 62 /* #define TRM_DEBUG0 */ 63 64 void trm_minphys(struct buf *, struct scsi_link *); 65 66 void trm_initSRB(struct trm_scsi_req_q *); 67 68 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 69 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 70 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 71 72 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 73 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 74 75 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t); 76 77 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t); 78 79 void trm_scsi_cmd(struct scsi_xfer *); 80 81 void *trm_srb_alloc(void *); 82 83 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 84 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 85 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 86 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 87 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 88 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 89 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 90 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 91 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 92 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 93 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 94 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 95 96 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int); 97 98 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t); 99 100 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *); 101 void trm_srb_reinit (struct trm_softc *, struct trm_scsi_req_q *); 102 void trm_srb_free (void *, void *); 103 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *); 104 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *); 105 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *); 106 107 void trm_initAdapter (struct trm_softc *); 108 void trm_Disconnect (struct trm_softc *); 109 void trm_Reselect (struct trm_softc *); 110 void trm_GoingSRB_Done (struct trm_softc *, struct trm_dcb *); 111 void trm_ScsiRstDetect (struct trm_softc *); 112 void trm_ResetSCSIBus (struct trm_softc *); 113 void trm_reset (struct trm_softc *); 114 void trm_StartWaitingSRB (struct trm_softc *); 115 void trm_ResetAllDevParam(struct trm_softc *); 116 void trm_RecoverSRB (struct trm_softc *); 117 void trm_linkSRB (struct trm_softc *); 118 119 void trm_initACB(struct trm_softc *, int); 120 121 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t); 122 123 void trm_EnableMsgOut(struct trm_softc *, u_int8_t); 124 125 void trm_timeout(void *); 126 127 void trm_print_info(struct trm_softc *, struct trm_dcb *); 128 129 /* 130 * Define structures 131 */ 132 struct cfdriver trm_cd = { 133 NULL, "trm", DV_DULL 134 }; 135 136 struct scsi_adapter trm_switch = { 137 trm_scsi_cmd, 138 trm_minphys, 139 NULL, 140 NULL 141 }; 142 143 /* 144 * ------------------------------------------------------------ 145 * 146 * stateV = (void *) trm_SCSI_phase0[phase] 147 * 148 * ------------------------------------------------------------ 149 */ 150 static void *trm_SCSI_phase0[8] = { 151 trm_DataOutPhase0, /* phase:0 */ 152 trm_DataInPhase0, /* phase:1 */ 153 trm_Nop, /* phase:2 */ 154 trm_StatusPhase0, /* phase:3 */ 155 trm_Nop, /* phase:4 */ 156 trm_Nop, /* phase:5 */ 157 trm_MsgOutPhase0, /* phase:6 */ 158 trm_MsgInPhase0, /* phase:7 */ 159 }; 160 161 /* 162 * ------------------------------------------------------------ 163 * 164 * stateV = (void *) trm_SCSI_phase1[phase] 165 * 166 * ------------------------------------------------------------ 167 */ 168 static void *trm_SCSI_phase1[8] = { 169 trm_DataOutPhase1, /* phase:0 */ 170 trm_DataInPhase1, /* phase:1 */ 171 trm_CommandPhase1, /* phase:2 */ 172 trm_StatusPhase1, /* phase:3 */ 173 trm_Nop, /* phase:4 */ 174 trm_Nop, /* phase:5 */ 175 trm_MsgOutPhase1, /* phase:6 */ 176 trm_MsgInPhase1, /* phase:7 */ 177 }; 178 179 180 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 181 /* 182 *Fast20: 000 50ns, 20.0 Mbytes/s 183 * 001 75ns, 13.3 Mbytes/s 184 * 010 100ns, 10.0 Mbytes/s 185 * 011 125ns, 8.0 Mbytes/s 186 * 100 150ns, 6.6 Mbytes/s 187 * 101 175ns, 5.7 Mbytes/s 188 * 110 200ns, 5.0 Mbytes/s 189 * 111 250ns, 4.0 Mbytes/s 190 * 191 *Fast40: 000 25ns, 40.0 Mbytes/s 192 * 001 50ns, 20.0 Mbytes/s 193 * 010 75ns, 13.3 Mbytes/s 194 * 011 100ns, 10.0 Mbytes/s 195 * 100 125ns, 8.0 Mbytes/s 196 * 101 150ns, 6.6 Mbytes/s 197 * 110 175ns, 5.7 Mbytes/s 198 * 111 200ns, 5.0 Mbytes/s 199 */ 200 201 /* 202 * real period: 203 */ 204 u_int8_t trm_clock_period[8] = { 205 /* nanosecond divided by 4 */ 206 12, /* 48 ns 20 MB/sec */ 207 18, /* 72 ns 13.3 MB/sec */ 208 25, /* 100 ns 10.0 MB/sec */ 209 31, /* 124 ns 8.0 MB/sec */ 210 37, /* 148 ns 6.6 MB/sec */ 211 43, /* 172 ns 5.7 MB/sec */ 212 50, /* 200 ns 5.0 MB/sec */ 213 62 /* 248 ns 4.0 MB/sec */ 214 }; 215 216 /* 217 * ------------------------------------------------------------ 218 * Function : trm_srb_alloc 219 * Purpose : Get the first free SRB 220 * Inputs : 221 * Return : NULL or a free SCSI Request block 222 * ------------------------------------------------------------ 223 */ 224 void * 225 trm_srb_alloc(void *xsc) 226 { 227 struct trm_softc *sc = xsc; 228 struct trm_scsi_req_q *pSRB; 229 230 mtx_enter(&sc->sc_srb_mtx); 231 pSRB = TAILQ_FIRST(&sc->freeSRB); 232 if (pSRB != NULL) 233 TAILQ_REMOVE(&sc->freeSRB, pSRB, link); 234 mtx_leave(&sc->sc_srb_mtx); 235 236 #ifdef TRM_DEBUG0 237 printf("%s: trm_srb_alloc. pSRB = %p, next pSRB = %p\n", 238 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB)); 239 #endif 240 241 return pSRB; 242 } 243 244 /* 245 * ------------------------------------------------------------ 246 * Function : trm_RewaitSRB 247 * Purpose : Q back to pending Q 248 * Inputs : struct trm_dcb * - 249 * struct trm_scsi_req_q * - 250 * ------------------------------------------------------------ 251 */ 252 void 253 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 254 { 255 int intflag; 256 257 intflag = splbio(); 258 259 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 260 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 261 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 262 } 263 264 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 265 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 266 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 267 } 268 269 pSRB->SRBState = TRM_READY; 270 pSRB->TargetStatus = SCSI_OK; 271 pSRB->AdaptStatus = TRM_STATUS_GOOD; 272 273 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 274 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 275 276 splx(intflag); 277 } 278 279 /* 280 * ------------------------------------------------------------ 281 * Function : trm_StartWaitingSRB 282 * Purpose : If there is no active DCB then run robin through 283 * the DCB's to find the next waiting SRB 284 * and move it to the going list. 285 * Inputs : struct trm_softc * - 286 * ------------------------------------------------------------ 287 */ 288 void 289 trm_StartWaitingSRB(struct trm_softc *sc) 290 { 291 struct trm_scsi_req_q *pSRB, *next; 292 int intflag; 293 294 intflag = splbio(); 295 296 if ((sc->pActiveDCB != NULL) || 297 (TAILQ_EMPTY(&sc->waitingSRB)) || 298 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0) 299 return; 300 301 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) { 302 next = TAILQ_NEXT(pSRB, link); 303 if (trm_StartSRB(sc, pSRB) == 0) { 304 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 305 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 306 pSRB->SRBFlag |= TRM_ON_GOING_SRB; 307 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link); 308 break; 309 } 310 } 311 312 splx(intflag); 313 } 314 315 /* 316 * ------------------------------------------------------------ 317 * Function : trm_scsi_cmd 318 * Purpose : enqueues a SCSI command 319 * Inputs : 320 * Call By : GENERIC SCSI driver 321 * ------------------------------------------------------------ 322 */ 323 void 324 trm_scsi_cmd(struct scsi_xfer *xs) 325 { 326 struct trm_scsi_req_q *pSRB; 327 bus_space_handle_t ioh; 328 struct trm_softc *sc; 329 bus_space_tag_t iot; 330 struct trm_dcb *pDCB; 331 u_int8_t target, lun; 332 int i, error, intflag, timeout, xferflags; 333 334 target = xs->sc_link->target; 335 lun = xs->sc_link->lun; 336 337 sc = (struct trm_softc *)xs->sc_link->adapter_softc; 338 ioh = sc->sc_iohandle; 339 iot = sc->sc_iotag; 340 341 #ifdef TRM_DEBUG0 342 if ((xs->flags & SCSI_POLL) != 0) { 343 sc_print_addr(xs->sc_link); 344 printf("trm_scsi_cmd. sc = %p, xs = %p, opcode = 0x%02x\n", 345 sc, xs, lun, xs->cmd->opcode); 346 } 347 #endif 348 349 if (target >= TRM_MAX_TARGETS) { 350 sc_print_addr(xs->sc_link); 351 printf("target >= %d\n", TRM_MAX_TARGETS); 352 xs->error = XS_DRIVER_STUFFUP; 353 scsi_done(xs); 354 return; 355 } 356 if (lun >= TRM_MAX_LUNS) { 357 sc_print_addr(xs->sc_link); 358 printf("lun >= %d\n", TRM_MAX_LUNS); 359 xs->error = XS_DRIVER_STUFFUP; 360 scsi_done(xs); 361 return; 362 } 363 364 pDCB = sc->pDCB[target][lun]; 365 if (pDCB == NULL) { 366 /* Removed as a result of INQUIRY proving no device present */ 367 xs->error = XS_DRIVER_STUFFUP; 368 scsi_done(xs); 369 return; 370 } 371 372 xferflags = xs->flags; 373 if (xferflags & SCSI_RESET) { 374 #ifdef TRM_DEBUG0 375 sc_print_addr(xs->sc_link); 376 printf("trm_reset via SCSI_RESET\n"); 377 #endif 378 trm_reset(sc); 379 xs->error = XS_NOERROR; 380 scsi_done(xs); 381 return; 382 } 383 384 pSRB = xs->io; 385 trm_srb_reinit(sc, pSRB); 386 387 xs->error = XS_NOERROR; 388 xs->status = SCSI_OK; 389 xs->resid = 0; 390 391 intflag = splbio(); 392 393 /* 394 * BuildSRB(pSRB,pDCB); 395 */ 396 if (xs->datalen != 0) { 397 #ifdef TRM_DEBUG0 398 sc_print_addr(xs->sc_link); 399 printf("xs->datalen=%x\n", (u_int32_t)xs->datalen); 400 sc_print_addr(xs->sc_link); 401 printf("sc->sc_dmatag=0x%x\n", (u_int32_t)sc->sc_dmatag); 402 sc_print_addr(xs->sc_link); 403 printf("pSRB->dmamapxfer=0x%x\n", (u_int32_t)pSRB->dmamapxfer); 404 sc_print_addr(xs->sc_link); 405 printf("xs->data=0x%x\n", (u_int32_t)xs->data); 406 #endif 407 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer, 408 xs->data, xs->datalen, NULL, 409 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : 410 BUS_DMA_WAITOK)) != 0) { 411 sc_print_addr(xs->sc_link); 412 printf("DMA transfer map unable to load, error = %d\n", 413 error); 414 xs->error = XS_DRIVER_STUFFUP; 415 splx(intflag); 416 scsi_done(xs); 417 return; 418 } 419 420 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 421 0, pSRB->dmamapxfer->dm_mapsize, 422 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 423 424 /* 425 * Set up the scatter gather list 426 */ 427 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) { 428 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr; 429 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len; 430 } 431 pSRB->SRBTotalXferLength = xs->datalen; 432 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs; 433 } 434 435 pSRB->pSRBDCB = pDCB; 436 pSRB->xs = xs; 437 pSRB->ScsiCmdLen = xs->cmdlen; 438 439 memcpy(pSRB->CmdBlock, xs->cmd, xs->cmdlen); 440 441 timeout_set(&xs->stimeout, trm_timeout, pSRB); 442 443 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 444 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link); 445 trm_StartWaitingSRB(sc); 446 447 if ((xferflags & SCSI_POLL) == 0) { 448 timeout_add_msec(&xs->stimeout, xs->timeout); 449 splx(intflag); 450 return; 451 } 452 453 splx(intflag); 454 for (timeout = xs->timeout; timeout > 0; timeout--) { 455 intflag = splbio(); 456 trm_Interrupt(sc); 457 splx(intflag); 458 if (ISSET(xs->flags, ITSDONE)) 459 break; 460 DELAY(1000); 461 } 462 463 if (!ISSET(xs->flags, ITSDONE) && timeout == 0) 464 trm_timeout(pSRB); 465 466 scsi_done(xs); 467 } 468 469 /* 470 * ------------------------------------------------------------ 471 * Function : trm_ResetAllDevParam 472 * Purpose : 473 * Inputs : struct trm_softc * 474 * ------------------------------------------------------------ 475 */ 476 void 477 trm_ResetAllDevParam(struct trm_softc *sc) 478 { 479 struct trm_adapter_nvram *pEEpromBuf; 480 int target, quirks; 481 482 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 483 484 for (target = 0; target < TRM_MAX_TARGETS; target++) { 485 if (target == sc->sc_AdaptSCSIID || sc->pDCB[target][0] == NULL) 486 continue; 487 488 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0) 489 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS; 490 else if (sc->pDCB[target][0]->sc_link != NULL) 491 quirks = sc->pDCB[target][0]->sc_link->quirks; 492 493 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks); 494 } 495 } 496 497 /* 498 * ------------------------------------------------------------ 499 * Function : trm_ResetDevParam 500 * Purpose : 501 * Inputs : 502 * ------------------------------------------------------------ 503 */ 504 void 505 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks) 506 { 507 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 508 u_int8_t PeriodIndex; 509 const int target = pDCB->target; 510 511 pDCB->DCBFlag &= TRM_QUIRKS_VALID; 512 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE); 513 514 pDCB->SyncPeriod = 0; 515 pDCB->SyncOffset = 0; 516 pDCB->MaxNegoPeriod = 0; 517 518 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0; 519 520 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0)); 521 522 if (((quirks & SDEV_NOWIDE) == 0) && 523 (pDCB->DevMode & TRM_WIDE) && 524 ((sc->sc_config & HCC_WIDE_CARD) != 0)) 525 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT; 526 527 if (((quirks & SDEV_NOSYNC) == 0) && 528 ((pDCB->DevMode & TRM_SYNC) != 0)) { 529 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07; 530 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex]; 531 } 532 533 if (((quirks & SDEV_NOTAGS) == 0) && 534 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) && 535 ((pDCB->DevMode & TRM_DISCONNECT) != 0)) 536 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */ 537 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING; 538 539 trm_SetXferParams(sc, pDCB, 0); 540 } 541 542 /* 543 * ------------------------------------------------------------ 544 * Function : trm_RecoverSRB 545 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs 546 * Inputs : struct trm_softc * - 547 * ------------------------------------------------------------ 548 */ 549 void 550 trm_RecoverSRB(struct trm_softc *sc) 551 { 552 struct trm_scsi_req_q *pSRB; 553 554 /* ASSUME we are inside splbio()/splx() */ 555 556 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 557 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 558 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 559 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 560 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 561 } 562 } 563 564 /* 565 * ------------------------------------------------------------ 566 * Function : trm_reset 567 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip). 568 * Inputs : 569 * ------------------------------------------------------------ 570 */ 571 void 572 trm_reset (struct trm_softc *sc) 573 { 574 const bus_space_handle_t ioh = sc->sc_iohandle; 575 const bus_space_tag_t iot = sc->sc_iotag; 576 int i, intflag; 577 578 intflag = splbio(); 579 580 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 581 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 582 583 trm_ResetSCSIBus(sc); 584 for (i = 0; i < 500; i++) 585 DELAY(1000); 586 587 /* 588 * Enable all SCSI interrupts except EN_SCAM 589 */ 590 bus_space_write_1(iot, ioh, 591 TRM_S1040_SCSI_INTEN, 592 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 593 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 594 /* 595 * Enable DMA interrupt 596 */ 597 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 598 /* 599 * Clear DMA FIFO 600 */ 601 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO); 602 /* 603 * Clear SCSI FIFO 604 */ 605 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 606 607 trm_ResetAllDevParam(sc); 608 trm_GoingSRB_Done(sc, NULL); 609 sc->pActiveDCB = NULL; 610 611 /* 612 * RESET_DETECT, RESET_DONE, RESET_DEV 613 */ 614 sc->sc_Flag = 0; 615 trm_StartWaitingSRB(sc); 616 617 splx(intflag); 618 } 619 620 /* 621 * ------------------------------------------------------------ 622 * Function : trm_timeout 623 * Purpose : Prints a timeout message and aborts the timed out SCSI request 624 * Inputs : void * - A struct trm_scsi_req_q * structure pointer 625 * ------------------------------------------------------------ 626 */ 627 void 628 trm_timeout(void *arg1) 629 { 630 struct trm_scsi_req_q *pSRB; 631 struct scsi_xfer *xs; 632 struct trm_softc *sc; 633 634 pSRB = (struct trm_scsi_req_q *)arg1; 635 xs = pSRB->xs; 636 637 if (xs != NULL) { 638 sc = xs->sc_link->adapter_softc; 639 sc_print_addr(xs->sc_link); 640 printf("SCSI OpCode 0x%02x ", xs->cmd->opcode); 641 if (pSRB->SRBFlag & TRM_AUTO_REQSENSE) 642 printf("REQUEST SENSE "); 643 printf("timed out\n"); 644 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 645 trm_FinishSRB(sc, pSRB); 646 #ifdef TRM_DEBUG0 647 sc_print_addr(xs->sc_link); 648 printf("trm_reset via trm_timeout()\n"); 649 #endif 650 trm_reset(sc); 651 trm_StartWaitingSRB(sc); 652 } 653 #ifdef TRM_DEBUG0 654 else 655 printf("%s: trm_timeout called with xs == NULL\n", 656 sc->sc_device.dv_xname); 657 #endif 658 } 659 660 /* 661 * ------------------------------------------------------------ 662 * Function : trm_StartSRB 663 * Purpose : Send the commands in the SRB to the device 664 * Inputs : struct trm_softc * - 665 * struct trm_scsi_req_q * - 666 * Return : 0 - SCSI processor is unoccupied 667 * 1 - SCSI processor is occupied with an SRB 668 * ------------------------------------------------------------ 669 */ 670 int 671 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 672 { 673 const bus_space_handle_t ioh = sc->sc_iohandle; 674 const bus_space_tag_t iot = sc->sc_iotag; 675 struct trm_dcb *pDCB = pSRB->pSRBDCB; 676 u_int32_t tag_mask; 677 u_int8_t tag_id, scsicommand; 678 679 #ifdef TRM_DEBUG0 680 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n", 681 sc->sc_device.dv_xname, sc, pDCB, pSRB); 682 #endif 683 /* 684 * If the queue is full or the SCSI processor has a pending interrupt 685 * then try again later. 686 */ 687 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh, 688 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT)) 689 return (1); 690 691 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 692 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target); 693 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 694 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 695 696 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) && 697 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) { 698 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID; 699 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks); 700 } 701 702 /* 703 * Flush FIFO 704 */ 705 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 706 707 sc->MsgCnt = 1; 708 sc->MsgBuf[0] = pDCB->IdentifyMsg; 709 if (((pSRB->xs->flags & SCSI_POLL) != 0) || 710 (pSRB->CmdBlock[0] == INQUIRY) || 711 (pSRB->CmdBlock[0] == REQUEST_SENSE)) 712 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG; 713 714 scsicommand = SCMD_SEL_ATN; 715 716 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) { 717 scsicommand = SCMD_SEL_ATNSTOP; 718 pSRB->SRBState = TRM_MSGOUT; 719 720 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) { 721 pDCB->DCBFlag |= TRM_QUEUE_FULL; 722 723 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) { 724 if (pSRB->TagNumber == TRM_NO_TAG) { 725 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1) 726 if ((tag_mask & pDCB->TagMask) == 0) { 727 pDCB->TagMask |= tag_mask; 728 pSRB->TagNumber = tag_id; 729 break; 730 } 731 732 if (tag_id >= 32) { 733 pDCB->DCBFlag |= TRM_QUEUE_FULL; 734 sc->MsgCnt = 0; 735 return 1; 736 } 737 } 738 739 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */ 740 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG; 741 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber; 742 743 scsicommand = SCMD_SEL_ATN3; 744 } 745 746 pSRB->SRBState = TRM_START; 747 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 748 sc->pActiveDCB = pDCB; 749 pDCB->pActiveSRB = pSRB; 750 751 if (sc->MsgCnt > 0) { 752 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]); 753 if (sc->MsgCnt > 1) { 754 DELAY(30); 755 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1); 756 } 757 sc->MsgCnt = 0; 758 } 759 760 /* 761 * it's important for atn stop 762 */ 763 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT); 764 /* 765 * SCSI command 766 */ 767 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand); 768 769 return 0; 770 } 771 772 /* 773 * ------------------------------------------------------------ 774 * Function : trm_Interrupt 775 * Purpose : Catch an interrupt from the adapter 776 * Process pending device interrupts. 777 * Inputs : void * - struct trm_softc * structure pointer 778 * ------------------------------------------------------------ 779 */ 780 int 781 trm_Interrupt(void *vsc) 782 { 783 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 784 struct trm_scsi_req_q *pSRB; 785 bus_space_handle_t ioh; 786 struct trm_softc *sc = (struct trm_softc *)vsc; 787 bus_space_tag_t iot; 788 u_int16_t phase; 789 u_int8_t scsi_status, scsi_intstatus; 790 791 if (sc == NULL) 792 return 0; 793 794 ioh = sc->sc_iohandle; 795 iot = sc->sc_iotag; 796 797 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS); 798 if (!(scsi_status & SCSIINTERRUPT)) 799 return 0; 800 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 801 802 #ifdef TRM_DEBUG0 803 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n", 804 sc->sc_device.dv_xname, scsi_status, scsi_intstatus); 805 #endif 806 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0) 807 trm_Disconnect(sc); 808 809 else if ((scsi_intstatus & INT_RESELECTED) != 0) 810 trm_Reselect(sc); 811 812 else if ((scsi_intstatus & INT_SCSIRESET) != 0) 813 trm_ScsiRstDetect(sc); 814 815 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) { 816 pSRB = sc->pActiveDCB->pActiveSRB; 817 /* 818 * software sequential machine 819 */ 820 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 821 /* 822 * 62037 or 62137 823 * call trm_SCSI_phase0[]... "phase entry" 824 * handle every phase before start transfer 825 */ 826 stateV = trm_SCSI_phase0[phase]; 827 stateV(sc, pSRB, &scsi_status); 828 /* 829 * if any exception occurred 830 * scsi_status will be modified to bus free phase 831 * new scsi_status transfer out from previous stateV 832 */ 833 /* 834 * phase:0,1,2,3,4,5,6,7 835 */ 836 pSRB->ScsiPhase = scsi_status & PHASEMASK; 837 phase = (u_int16_t) scsi_status & PHASEMASK; 838 /* 839 * call trm_SCSI_phase1[]... "phase entry" 840 * handle every phase do transfer 841 */ 842 stateV = trm_SCSI_phase1[phase]; 843 stateV(sc, pSRB, &scsi_status); 844 845 } else { 846 return 0; 847 } 848 849 return 1; 850 } 851 852 /* 853 * ------------------------------------------------------------ 854 * Function : trm_MsgOutPhase0 855 * Purpose : Check the state machine before sending a message out 856 * Inputs : struct trm_softc * - 857 * struct trm_scsi_req_q * - 858 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready 859 * ------------------------------------------------------------ 860 */ 861 void 862 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 863 { 864 switch (pSRB->SRBState) { 865 case TRM_UNEXPECT_RESEL: 866 case TRM_ABORT_SENT: 867 *pscsi_status = PH_BUS_FREE; /* initial phase */ 868 break; 869 870 default: 871 break; 872 } 873 } 874 875 /* 876 * ------------------------------------------------------------ 877 * Function : trm_MsgOutPhase1 878 * Purpose : Write the message out to the bus 879 * Inputs : struct trm_softc * - 880 * struct trm_scsi_req_q * - 881 * u_int8_t * - unused 882 * ------------------------------------------------------------ 883 */ 884 void 885 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 886 { 887 const bus_space_handle_t ioh = sc->sc_iohandle; 888 const bus_space_tag_t iot = sc->sc_iotag; 889 struct trm_dcb *pDCB = sc->pActiveDCB; 890 891 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 892 893 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) { 894 /* 895 * WIDE DATA TRANSFER REQUEST code (03h) 896 */ 897 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 898 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO; 899 900 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 901 sc->MsgBuf[1] = MSG_EXTENDED; 902 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN; 903 sc->MsgBuf[3] = MSG_EXT_WDTR; 904 905 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 906 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT; 907 else 908 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 909 910 sc->MsgCnt = 5; 911 912 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 913 914 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE; 915 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO; 916 917 sc->MsgCnt = 0; 918 919 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0) 920 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 921 922 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED; 923 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN; 924 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR; 925 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod; 926 927 if (pDCB->MaxNegoPeriod > 0) 928 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET; 929 else 930 sc->MsgBuf[sc->MsgCnt++] = 0; 931 } 932 933 if (sc->MsgCnt > 0) { 934 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt); 935 if (sc->MsgBuf[0] == MSG_ABORT) 936 pSRB->SRBState = TRM_ABORT_SENT; 937 sc->MsgCnt = 0; 938 } 939 /* 940 * it's important for atn stop 941 */ 942 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 943 /* 944 * Transfer information out 945 */ 946 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 947 } 948 949 /* 950 * ------------------------------------------------------------ 951 * Function : trm_CommandPhase1 952 * Purpose : Send commands to bus 953 * Inputs : 954 * ------------------------------------------------------------ 955 */ 956 void 957 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 958 { 959 const bus_space_handle_t ioh = sc->sc_iohandle; 960 const bus_space_tag_t iot = sc->sc_iotag; 961 962 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 963 964 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen); 965 966 pSRB->SRBState = TRM_COMMAND; 967 /* 968 * it's important for atn stop 969 */ 970 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 971 /* 972 * Transfer information out 973 */ 974 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 975 } 976 977 /* 978 * ------------------------------------------------------------ 979 * Function : trm_DataOutPhase0 980 * Purpose : Ready for Data Out, clear FIFO 981 * Inputs : u_int8_t * - SCSI status, used but not set 982 * ------------------------------------------------------------ 983 */ 984 void 985 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 986 { 987 const bus_space_handle_t ioh = sc->sc_iohandle; 988 const bus_space_tag_t iot = sc->sc_iotag; 989 struct SGentry *pseg; 990 struct trm_dcb *pDCB; 991 u_int32_t dLeftCounter, TempSRBXferredLength; 992 u_int16_t scsi_status; 993 u_int8_t TempDMAstatus, SGIndexTemp; 994 995 dLeftCounter = 0; 996 997 pDCB = pSRB->pSRBDCB; 998 scsi_status = *pscsi_status; 999 1000 if (pSRB->SRBState != TRM_XFERPAD) { 1001 if ((scsi_status & PARITYERROR) != 0) 1002 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1003 if ((scsi_status & SCSIXFERDONE) == 0) { 1004 /* 1005 * when data transfer from DMA FIFO to SCSI FIFO 1006 * if there was some data left in SCSI FIFO 1007 */ 1008 dLeftCounter = (u_int32_t)(bus_space_read_1( 1009 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F); 1010 if (pDCB->SyncPeriod & WIDE_SYNC) { 1011 /* 1012 * if WIDE scsi SCSI FIFOCNT unit is word 1013 * so need to * 2 1014 */ 1015 dLeftCounter <<= 1; 1016 } 1017 } 1018 /* 1019 * calculate all the residue data that not yet transferred 1020 * SCSI transfer counter + left in SCSI FIFO data 1021 * 1022 * .....TRM_S1040_SCSI_COUNTER (24bits) 1023 * The counter always decrement by one for every SCSI byte 1024 * transfer. 1025 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits) 1026 * The counter is SCSI FIFO offset counter 1027 */ 1028 dLeftCounter += bus_space_read_4(iot, ioh, 1029 TRM_S1040_SCSI_COUNTER); 1030 if (dLeftCounter == 1) { 1031 dLeftCounter = 0; 1032 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1033 DO_CLRFIFO); 1034 } 1035 if (dLeftCounter == 0 || 1036 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1037 TempDMAstatus = bus_space_read_1(iot, 1038 ioh, TRM_S1040_DMA_STATUS); 1039 while ((TempDMAstatus & DMAXFERCOMP) == 0) { 1040 TempDMAstatus = bus_space_read_1(iot, 1041 ioh, TRM_S1040_DMA_STATUS); 1042 } 1043 pSRB->SRBTotalXferLength = 0; 1044 } else { 1045 /* 1046 * Update SG list 1047 */ 1048 /* 1049 * if transfer not yet complete 1050 * there were some data residue in SCSI FIFO or 1051 * SCSI transfer counter not empty 1052 */ 1053 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1054 /* 1055 * data that had transferred length 1056 */ 1057 TempSRBXferredLength = pSRB->SRBTotalXferLength 1058 - dLeftCounter; 1059 /* 1060 * next time to be transferred length 1061 */ 1062 pSRB->SRBTotalXferLength = dLeftCounter; 1063 /* 1064 * parsing from last time disconnect SRBSGIndex 1065 */ 1066 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1067 for (SGIndexTemp = pSRB->SRBSGIndex; 1068 SGIndexTemp < pSRB->SRBSGCount; 1069 SGIndexTemp++) { 1070 /* 1071 * find last time which SG transfer be 1072 * disconnect 1073 */ 1074 if (TempSRBXferredLength >= pseg->length) 1075 TempSRBXferredLength -= pseg->length; 1076 else { 1077 /* 1078 * update last time disconnected 1079 * SG list 1080 */ 1081 /* 1082 * residue data length 1083 */ 1084 pseg->length -= 1085 TempSRBXferredLength; 1086 /* 1087 * residue data pointer 1088 */ 1089 pseg->address += 1090 TempSRBXferredLength; 1091 pSRB->SRBSGIndex = SGIndexTemp; 1092 break; 1093 } 1094 pseg++; 1095 } 1096 } 1097 } 1098 } 1099 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 1100 } 1101 1102 /* 1103 * ------------------------------------------------------------ 1104 * Function : trm_DataOutPhase1 1105 * Purpose : Transfers data out, calls trm_DataIO_transfer 1106 * Inputs : 1107 * ------------------------------------------------------------ 1108 */ 1109 void 1110 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1111 { 1112 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT); 1113 } 1114 1115 /* 1116 * ------------------------------------------------------------ 1117 * Function : trm_DataInPhase0 1118 * Purpose : Prepare for reading data in from bus 1119 * Inputs : 1120 * ------------------------------------------------------------ 1121 */ 1122 void 1123 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1124 { 1125 const bus_space_handle_t ioh = sc->sc_iohandle; 1126 const bus_space_tag_t iot = sc->sc_iotag; 1127 struct SGentry *pseg; 1128 u_int32_t TempSRBXferredLength, dLeftCounter; 1129 u_int16_t scsi_status; 1130 u_int8_t SGIndexTemp; 1131 1132 dLeftCounter = 0; 1133 1134 scsi_status = *pscsi_status; 1135 if (pSRB->SRBState != TRM_XFERPAD) { 1136 if ((scsi_status & PARITYERROR) != 0) 1137 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1138 dLeftCounter += bus_space_read_4(iot, ioh, 1139 TRM_S1040_SCSI_COUNTER); 1140 if (dLeftCounter == 0 || 1141 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1142 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0) 1143 ; 1144 pSRB->SRBTotalXferLength = 0; 1145 } else { 1146 /* 1147 * phase changed 1148 * 1149 * parsing the case: 1150 * when a transfer not yet complete 1151 * but be disconnected by uper layer 1152 * if transfer not yet complete 1153 * there were some data residue in SCSI FIFO or 1154 * SCSI transfer counter not empty 1155 */ 1156 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1157 /* 1158 * data that had transferred length 1159 */ 1160 TempSRBXferredLength = pSRB->SRBTotalXferLength 1161 - dLeftCounter; 1162 /* 1163 * next time to be transferred length 1164 */ 1165 pSRB->SRBTotalXferLength = dLeftCounter; 1166 /* 1167 * parsing from last time disconnect SRBSGIndex 1168 */ 1169 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1170 for (SGIndexTemp = pSRB->SRBSGIndex; 1171 SGIndexTemp < pSRB->SRBSGCount; 1172 SGIndexTemp++) { 1173 /* 1174 * find last time which SG transfer be 1175 * disconnect 1176 */ 1177 if (TempSRBXferredLength >= 1178 pseg->length) { 1179 TempSRBXferredLength -= pseg->length; 1180 } else { 1181 /* 1182 * update last time disconnected 1183 * SG list 1184 * 1185 * residue data length 1186 */ 1187 pseg->length -= TempSRBXferredLength; 1188 /* 1189 * residue data pointer 1190 */ 1191 pseg->address += TempSRBXferredLength; 1192 pSRB->SRBSGIndex = SGIndexTemp; 1193 break; 1194 } 1195 pseg++; 1196 } 1197 } 1198 } 1199 } 1200 } 1201 1202 /* 1203 * ------------------------------------------------------------ 1204 * Function : trm_DataInPhase1 1205 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer 1206 * Inputs : 1207 * ------------------------------------------------------------ 1208 */ 1209 void 1210 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1211 { 1212 trm_DataIO_transfer(sc, pSRB, XFERDATAIN); 1213 } 1214 1215 /* 1216 * ------------------------------------------------------------ 1217 * Function : trm_DataIO_transfer 1218 * Purpose : 1219 * Inputs : 1220 * ------------------------------------------------------------ 1221 */ 1222 void 1223 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir) 1224 { 1225 const bus_space_handle_t ioh = sc->sc_iohandle; 1226 const bus_space_tag_t iot = sc->sc_iotag; 1227 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1228 u_int8_t bval; 1229 1230 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1231 if (pSRB->SRBTotalXferLength != 0) { 1232 /* 1233 * load what physical address of Scatter/Gather list 1234 * table want to be transfer 1235 */ 1236 pSRB->SRBState = TRM_DATA_XFER; 1237 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0); 1238 bus_space_write_4(iot, ioh, 1239 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr + 1240 ((u_int32_t)pSRB->SRBSGIndex << 3))); 1241 /* 1242 * load how many bytes in the Scatter/Gather list table 1243 */ 1244 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT, 1245 ((u_int32_t)(pSRB->SRBSGCount - 1246 pSRB->SRBSGIndex) << 3)); 1247 /* 1248 * load total transfer length (24bits, 1249 * pSRB->SRBTotalXferLength) max value 16Mbyte 1250 */ 1251 bus_space_write_4(iot, ioh, 1252 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength); 1253 /* 1254 * Start DMA transfer 1255 */ 1256 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir); 1257 /* bus_space_write_2(iot, ioh, 1258 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/ 1259 /* 1260 * Set the transfer bus and direction 1261 */ 1262 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN; 1263 } else { 1264 /* 1265 * xfer pad 1266 */ 1267 if (pSRB->SRBSGCount) 1268 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN; 1269 1270 if (pDCB->SyncPeriod & WIDE_SYNC) { 1271 bus_space_write_4(iot, ioh, 1272 TRM_S1040_SCSI_COUNTER, 2); 1273 } else { 1274 bus_space_write_4(iot, ioh, 1275 TRM_S1040_SCSI_COUNTER, 1); 1276 } 1277 1278 if (ioDir == XFERDATAOUT) { 1279 bus_space_write_2(iot, 1280 ioh, TRM_S1040_SCSI_FIFO, 0); 1281 } else { 1282 bus_space_read_2(iot, 1283 ioh, TRM_S1040_SCSI_FIFO); 1284 } 1285 pSRB->SRBState = TRM_XFERPAD; 1286 /* 1287 * Set the transfer bus and direction 1288 */ 1289 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN; 1290 } 1291 /* 1292 * it's important for atn stop 1293 */ 1294 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1295 /* 1296 * Tell the bus to do the transfer 1297 */ 1298 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval); 1299 } 1300 } 1301 1302 /* 1303 * ------------------------------------------------------------ 1304 * Function : trm_StatusPhase0 1305 * Purpose : Update Target Status with data from SCSI FIFO 1306 * Inputs : u_int8_t * - Set to PH_BUS_FREE 1307 * ------------------------------------------------------------ 1308 */ 1309 void 1310 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1311 { 1312 const bus_space_handle_t ioh = sc->sc_iohandle; 1313 const bus_space_tag_t iot = sc->sc_iotag; 1314 1315 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1316 1317 pSRB->SRBState = TRM_COMPLETED; 1318 /* 1319 * initial phase 1320 */ 1321 *pscsi_status = PH_BUS_FREE; 1322 /* 1323 * it's important for atn stop 1324 */ 1325 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1326 /* 1327 * Tell bus that the message was accepted 1328 */ 1329 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1330 } 1331 1332 /* 1333 * ------------------------------------------------------------ 1334 * Function : trm_StatusPhase1 1335 * Purpose : Clear FIFO of DMA and SCSI 1336 * Inputs : 1337 * ------------------------------------------------------------ 1338 */ 1339 void 1340 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1341 { 1342 const bus_space_handle_t ioh = sc->sc_iohandle; 1343 const bus_space_tag_t iot = sc->sc_iotag; 1344 1345 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) { 1346 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40) 1347 == 0) { 1348 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1349 DO_CLRFIFO); 1350 } 1351 if ((bus_space_read_2(iot, ioh, 1352 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1353 bus_space_write_1(iot, ioh, 1354 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1355 } 1356 } else { 1357 if ((bus_space_read_2(iot, ioh, 1358 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1359 bus_space_write_1(iot, ioh, 1360 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1361 } 1362 if ((bus_space_read_1(iot, ioh, 1363 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) { 1364 bus_space_write_2(iot, ioh, 1365 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1366 } 1367 } 1368 pSRB->SRBState = TRM_STATUS; 1369 /* 1370 * it's important for atn stop 1371 */ 1372 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1373 /* 1374 * Tell the bus that the command is complete 1375 */ 1376 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP); 1377 } 1378 1379 /* 1380 * ------------------------------------------------------------ 1381 * Function : trm_MsgInPhase0 1382 * Purpose : 1383 * Inputs : 1384 * 1385 * extended message codes: 1386 * code description 1387 * ---- ----------- 1388 * 02h Reserved 1389 * 00h MODIFY DATA POINTER 1390 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1391 * 03h WIDE DATA TRANSFER REQUEST 1392 * 04h - 7Fh Reserved 1393 * 80h - FFh Vendor specific 1394 * 1395 * ------------------------------------------------------------ 1396 */ 1397 void 1398 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1399 { 1400 const bus_space_handle_t ioh = sc->sc_iohandle; 1401 const bus_space_tag_t iot = sc->sc_iotag; 1402 struct trm_dcb *pDCB; 1403 u_int8_t message_in_code, bIndex, message_in_tag_id; 1404 1405 pDCB = sc->pActiveDCB; 1406 1407 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1408 1409 if (pSRB->SRBState != TRM_EXTEND_MSGIN) { 1410 switch (message_in_code) { 1411 case MSG_DISCONNECT: 1412 pSRB->SRBState = TRM_DISCONNECTED; 1413 break; 1414 1415 case MSG_EXTENDED: 1416 case MSG_SIMPLE_Q_TAG: 1417 case MSG_HEAD_OF_Q_TAG: 1418 case MSG_ORDERED_Q_TAG: 1419 pSRB->SRBState = TRM_EXTEND_MSGIN; 1420 /* 1421 * extended message (01h) 1422 */ 1423 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf)); 1424 sc->MsgBuf[0] = message_in_code; 1425 sc->MsgCnt = 1; 1426 /* 1427 * extended message length (n) 1428 */ 1429 break; 1430 1431 case MSG_MESSAGE_REJECT: 1432 /* 1433 * Reject message 1434 */ 1435 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) { 1436 /* 1437 * do wide nego reject 1438 */ 1439 pDCB = pSRB->pSRBDCB; 1440 1441 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO; 1442 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1443 1444 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 1445 /* 1446 * Set ATN, in case ATN was clear 1447 */ 1448 pSRB->SRBState = TRM_MSGOUT; 1449 bus_space_write_2(iot, ioh, 1450 TRM_S1040_SCSI_CONTROL, DO_SETATN); 1451 } else { 1452 /* 1453 * Clear ATN 1454 */ 1455 bus_space_write_2(iot, ioh, 1456 TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1457 } 1458 1459 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) { 1460 /* 1461 * do sync nego reject 1462 */ 1463 pDCB = pSRB->pSRBDCB; 1464 1465 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO; 1466 1467 pDCB->SyncPeriod = 0; 1468 pDCB->SyncOffset = 0; 1469 1470 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1471 goto re_prog; 1472 } 1473 break; 1474 1475 case MSG_IGN_WIDE_RESIDUE: 1476 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1477 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1478 break; 1479 1480 default: 1481 break; 1482 } 1483 1484 } else { 1485 1486 /* 1487 * We are collecting an extended message. Save the latest byte and then 1488 * check to see if the message is complete. If so, process it. 1489 */ 1490 sc->MsgBuf[sc->MsgCnt++] = message_in_code; 1491 #ifdef TRM_DEBUG0 1492 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 1493 sc->sc_device.dv_xname, 1494 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] ); 1495 #endif 1496 switch (sc->MsgBuf[0]) { 1497 case MSG_SIMPLE_Q_TAG: 1498 case MSG_HEAD_OF_Q_TAG: 1499 case MSG_ORDERED_Q_TAG: 1500 if (sc->MsgCnt == 2) { 1501 pSRB->SRBState = TRM_FREE; 1502 message_in_tag_id = sc->MsgBuf[1]; 1503 sc->MsgCnt = 0; 1504 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) { 1505 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id)) 1506 break; 1507 } 1508 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) { 1509 pDCB->pActiveSRB = pSRB; 1510 pSRB->SRBState = TRM_DATA_XFER; 1511 } else { 1512 #ifdef TRM_DEBUG0 1513 printf("%s: TRM_UNEXPECT_RESEL!\n", 1514 sc->sc_device.dv_xname); 1515 #endif 1516 pSRB = &sc->SRB[0]; 1517 trm_srb_reinit(sc, pSRB); 1518 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1519 pDCB->pActiveSRB = pSRB; 1520 trm_EnableMsgOut(sc, MSG_ABORT_TAG); 1521 } 1522 } 1523 break; 1524 1525 case MSG_EXTENDED: 1526 /* TODO XXXX: Correctly handling target initiated negotiations? */ 1527 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) { 1528 /* 1529 * ====================================== 1530 * WIDE DATA TRANSFER REQUEST 1531 * ====================================== 1532 * byte 0 : Extended message (01h) 1533 * byte 1 : Extended message length (02h) 1534 * byte 2 : WIDE DATA TRANSFER code (03h) 1535 * byte 3 : Transfer width exponent 1536 */ 1537 1538 pSRB->SRBState = TRM_FREE; 1539 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO); 1540 1541 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN) 1542 goto reject_offer; 1543 1544 switch (sc->MsgBuf[3]) { 1545 case MSG_EXT_WDTR_BUS_32_BIT: 1546 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 1547 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1548 else 1549 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT; 1550 break; 1551 1552 case MSG_EXT_WDTR_BUS_16_BIT: 1553 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) { 1554 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1555 break; 1556 } 1557 pDCB->SyncPeriod |= WIDE_SYNC; 1558 /* FALL THROUGH == ACCEPT OFFER */ 1559 1560 case MSG_EXT_WDTR_BUS_8_BIT: 1561 pSRB->SRBState = TRM_MSGOUT; 1562 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE); 1563 1564 if (pDCB->MaxNegoPeriod == 0) { 1565 pDCB->SyncPeriod = 0; 1566 pDCB->SyncOffset = 0; 1567 goto re_prog; 1568 } 1569 break; 1570 1571 default: 1572 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 1573 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1574 reject_offer: 1575 sc->MsgCnt = 1; 1576 sc->MsgBuf[0] = MSG_MESSAGE_REJECT; 1577 break; 1578 } 1579 1580 /* Echo accepted offer, or send revised offer */ 1581 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN); 1582 1583 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) { 1584 /* 1585 * ================================= 1586 * SYNCHRONOUS DATA TRANSFER REQUEST 1587 * ================================= 1588 * byte 0 : Extended message (01h) 1589 * byte 1 : Extended message length (03) 1590 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1591 * byte 3 : Transfer period factor 1592 * byte 4 : REQ/ACK offset 1593 */ 1594 1595 pSRB->SRBState = TRM_FREE; 1596 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO); 1597 1598 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN) 1599 goto reject_offer; 1600 1601 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) { 1602 /* 1603 * Asynchronous transfers 1604 */ 1605 pDCB->SyncPeriod = 0; 1606 pDCB->SyncOffset = 0; 1607 1608 } else { 1609 /* 1610 * Synchronous transfers 1611 */ 1612 /* 1613 * REQ/ACK offset 1614 */ 1615 pDCB->SyncOffset = sc->MsgBuf[4]; 1616 1617 for (bIndex = 0; bIndex < 7; bIndex++) 1618 if (sc->MsgBuf[3] <= trm_clock_period[bIndex]) 1619 break; 1620 1621 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 1622 } 1623 1624 re_prog: /* 1625 * program SCSI control register 1626 */ 1627 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1628 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1629 1630 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID)); 1631 } 1632 break; 1633 1634 default: 1635 break; 1636 } 1637 } 1638 1639 /* 1640 * initial phase 1641 */ 1642 *pscsi_status = PH_BUS_FREE; 1643 /* 1644 * it's important for atn stop 1645 */ 1646 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1647 /* 1648 * Tell bus that the message was accepted 1649 */ 1650 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1651 } 1652 1653 /* 1654 * ------------------------------------------------------------ 1655 * Function : trm_MsgInPhase1 1656 * Purpose : Clear the FIFO 1657 * Inputs : 1658 * ------------------------------------------------------------ 1659 */ 1660 void 1661 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1662 { 1663 const bus_space_handle_t ioh = sc->sc_iohandle; 1664 const bus_space_tag_t iot = sc->sc_iotag; 1665 1666 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1667 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1668 1669 /* 1670 * it's important for atn stop 1671 */ 1672 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1673 /* 1674 * SCSI command 1675 */ 1676 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN); 1677 } 1678 1679 /* 1680 * ------------------------------------------------------------ 1681 * Function : trm_Nop 1682 * Purpose : EMPTY 1683 * Inputs : 1684 * ------------------------------------------------------------ 1685 */ 1686 void 1687 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1688 { 1689 } 1690 1691 /* 1692 * ------------------------------------------------------------ 1693 * Function : trm_SetXferParams 1694 * Purpose : Set the Sync period, offset and mode for each device that has 1695 * the same target as the given one (struct trm_dcb *) 1696 * Inputs : 1697 * ------------------------------------------------------------ 1698 */ 1699 void 1700 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info) 1701 { 1702 struct trm_dcb *pDCBTemp; 1703 int lun, target; 1704 1705 /* 1706 * set all lun device's period, offset 1707 */ 1708 #ifdef TRM_DEBUG0 1709 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname); 1710 #endif 1711 1712 target = pDCB->target; 1713 for(lun = 0; lun < TRM_MAX_LUNS; lun++) { 1714 pDCBTemp = sc->pDCB[target][lun]; 1715 if (pDCBTemp != NULL) { 1716 pDCBTemp->DevMode = pDCB->DevMode; 1717 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod; 1718 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 1719 pDCBTemp->SyncOffset = pDCB->SyncOffset; 1720 pDCBTemp->DCBFlag = pDCB->DCBFlag; 1721 } 1722 } 1723 1724 if (print_info) 1725 trm_print_info(sc, pDCB); 1726 } 1727 1728 /* 1729 * ------------------------------------------------------------ 1730 * Function : trm_Disconnect 1731 * Purpose : 1732 * Inputs : 1733 * 1734 * ---SCSI bus phase 1735 * PH_DATA_OUT 0x00 Data out phase 1736 * PH_DATA_IN 0x01 Data in phase 1737 * PH_COMMAND 0x02 Command phase 1738 * PH_STATUS 0x03 Status phase 1739 * PH_BUS_FREE 0x04 Invalid phase used as bus free 1740 * PH_BUS_FREE 0x05 Invalid phase used as bus free 1741 * PH_MSG_OUT 0x06 Message out phase 1742 * PH_MSG_IN 0x07 Message in phase 1743 * ------------------------------------------------------------ 1744 */ 1745 void 1746 trm_Disconnect(struct trm_softc *sc) 1747 { 1748 const bus_space_handle_t ioh = sc->sc_iohandle; 1749 struct trm_scsi_req_q *pSRB; 1750 const bus_space_tag_t iot = sc->sc_iotag; 1751 struct trm_dcb *pDCB; 1752 int j; 1753 1754 #ifdef TRM_DEBUG0 1755 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname); 1756 #endif 1757 1758 pDCB = sc->pActiveDCB; 1759 if (pDCB == NULL) { 1760 /* TODO: Why use a loop? Why not use DELAY(400)? */ 1761 for(j = 400; j > 0; --j) 1762 DELAY(1); /* 1 msec */ 1763 bus_space_write_2(iot, ioh, 1764 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1765 return; 1766 } 1767 1768 pSRB = pDCB->pActiveSRB; 1769 sc->pActiveDCB = NULL; 1770 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1771 bus_space_write_2(iot, ioh, 1772 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1773 DELAY(100); 1774 1775 switch (pSRB->SRBState) { 1776 case TRM_UNEXPECT_RESEL: 1777 pSRB->SRBState = TRM_FREE; 1778 break; 1779 1780 case TRM_ABORT_SENT: 1781 trm_GoingSRB_Done(sc, pDCB); 1782 break; 1783 1784 case TRM_START: 1785 case TRM_MSGOUT: 1786 /* 1787 * Selection time out 1788 */ 1789 /* If not polling just keep trying until xs->stimeout expires */ 1790 if ((pSRB->xs->flags & SCSI_POLL) == 0) { 1791 trm_RewaitSRB(sc, pSRB); 1792 } else { 1793 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT; 1794 goto disc1; 1795 } 1796 break; 1797 1798 case TRM_COMPLETED: 1799 disc1: 1800 /* 1801 * TRM_COMPLETED - remove id from mask of active tags 1802 */ 1803 pDCB->pActiveSRB = NULL; 1804 trm_FinishSRB(sc, pSRB); 1805 break; 1806 1807 default: 1808 break; 1809 } 1810 1811 trm_StartWaitingSRB(sc); 1812 } 1813 1814 /* 1815 * ------------------------------------------------------------ 1816 * Function : trm_Reselect 1817 * Purpose : 1818 * Inputs : 1819 * ------------------------------------------------------------ 1820 */ 1821 void 1822 trm_Reselect(struct trm_softc *sc) 1823 { 1824 const bus_space_handle_t ioh = sc->sc_iohandle; 1825 const bus_space_tag_t iot = sc->sc_iotag; 1826 struct trm_scsi_req_q *pSRB; 1827 struct trm_dcb *pDCB; 1828 u_int16_t RselTarLunId; 1829 u_int8_t target, lun; 1830 1831 #ifdef TRM_DEBUG0 1832 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname); 1833 #endif 1834 1835 pDCB = sc->pActiveDCB; 1836 if (pDCB != NULL) { 1837 /* 1838 * Arbitration lost but Reselection win 1839 */ 1840 pSRB = pDCB->pActiveSRB; 1841 trm_RewaitSRB(sc, pSRB); 1842 } 1843 1844 /* 1845 * Read Reselected Target Id and LUN 1846 */ 1847 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF; 1848 /* TODO XXXX: Make endian independent! */ 1849 target = RselTarLunId & 0xff; 1850 lun = (RselTarLunId >> 8) & 0xff; 1851 1852 #ifdef TRM_DEBUG0 1853 printf("%s: reselect - target = %d, lun = %d\n", 1854 sc->sc_device.dv_xname, target, lun); 1855 #endif 1856 1857 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS)) 1858 pDCB = sc->pDCB[target][lun]; 1859 else 1860 pDCB = NULL; 1861 1862 if (pDCB == NULL) 1863 printf("%s: reselect - target = %d, lun = %d not found\n", 1864 sc->sc_device.dv_xname, target, lun); 1865 1866 sc->pActiveDCB = pDCB; 1867 1868 /* TODO XXXX: This will crash if pDCB is ever NULL */ 1869 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) { 1870 pSRB = &sc->SRB[0]; 1871 pDCB->pActiveSRB = pSRB; 1872 } else { 1873 pSRB = pDCB->pActiveSRB; 1874 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) { 1875 /* 1876 * abort command 1877 */ 1878 pSRB = &sc->SRB[0]; 1879 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1880 pDCB->pActiveSRB = pSRB; 1881 trm_EnableMsgOut(sc, MSG_ABORT); 1882 } else 1883 pSRB->SRBState = TRM_DATA_XFER; 1884 } 1885 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1886 1887 /* 1888 * Program HA ID, target ID, period and offset 1889 */ 1890 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target); 1891 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 1892 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1893 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1894 1895 /* 1896 * it's important for atn stop 1897 */ 1898 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1899 DELAY(30); 1900 1901 /* 1902 * SCSI command 1903 * to rls the /ACK signal 1904 */ 1905 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1906 } 1907 1908 /* 1909 * ------------------------------------------------------------ 1910 * Function : trm_FinishSRB 1911 * Purpose : Complete execution of a SCSI command 1912 * Inputs : 1913 * ------------------------------------------------------------ 1914 */ 1915 void 1916 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 1917 { 1918 struct scsi_inquiry_data *ptr; 1919 struct scsi_sense_data *s1, *s2; 1920 struct scsi_xfer *xs = pSRB->xs; 1921 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1922 int target, lun, intflag; 1923 1924 #ifdef TRM_DEBUG0 1925 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n", 1926 sc->sc_device.dv_xname, sc, pSRB); 1927 #endif 1928 pDCB->DCBFlag &= ~TRM_QUEUE_FULL; 1929 1930 intflag = splbio(); 1931 if (pSRB->TagNumber != TRM_NO_TAG) { 1932 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber); 1933 pSRB->TagNumber = TRM_NO_TAG; 1934 } 1935 /* SRB may have started & finished, or be waiting and timed out */ 1936 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 1937 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 1938 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 1939 } 1940 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 1941 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 1942 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 1943 } 1944 splx(intflag); 1945 1946 if (xs == NULL) { 1947 return; 1948 } 1949 1950 timeout_del(&xs->stimeout); 1951 1952 xs->status = pSRB->TargetStatus; 1953 if (xs->datalen != 0) { 1954 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 1955 0, pSRB->dmamapxfer->dm_mapsize, 1956 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1957 BUS_DMASYNC_POSTWRITE); 1958 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer); 1959 } 1960 1961 switch (xs->status) { 1962 case SCSI_INTERM_COND_MET: 1963 case SCSI_COND_MET: 1964 case SCSI_INTERM: 1965 case SCSI_OK: 1966 switch (pSRB->AdaptStatus) { 1967 case TRM_STATUS_GOOD: 1968 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) { 1969 #ifdef TRM_DEBUG0 1970 sc_print_addr(xs->sc_link); 1971 printf(" trm_FinishSRB. TRM_PARITY_ERROR\n"); 1972 #endif 1973 xs->error = XS_DRIVER_STUFFUP; 1974 1975 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) { 1976 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) == 0) 1977 xs->error = XS_TIMEOUT; 1978 else { 1979 bzero(&xs->sense, sizeof(xs->sense)); 1980 xs->status = SCSI_CHECK; 1981 xs->error = XS_SENSE; 1982 } 1983 1984 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) { 1985 s1 = &pSRB->scsisense; 1986 s2 = &xs->sense; 1987 1988 *s2 = *s1; 1989 1990 xs->status = SCSI_CHECK; 1991 xs->error = XS_SENSE; 1992 1993 } else 1994 xs->error = XS_NOERROR; 1995 break; 1996 1997 case TRM_OVER_UNDER_RUN: 1998 #ifdef TRM_DEBUG0 1999 sc_print_addr(xs->sc_link); 2000 printf("trm_FinishSRB. TRM_OVER_UNDER_RUN\n"); 2001 #endif 2002 xs->error = XS_DRIVER_STUFFUP; 2003 break; 2004 2005 default: 2006 #ifdef TRM_DEBUG0 2007 sc_print_addr(xs->sc_link); 2008 printf("trm_FinishSRB. AdaptStatus Error = 0x%02x\n", 2009 pSRB->AdaptStatus); 2010 #endif 2011 xs->error = XS_DRIVER_STUFFUP; 2012 break; 2013 } 2014 break; 2015 2016 case SCSI_TERMINATED: 2017 case SCSI_ACA_ACTIVE: 2018 case SCSI_CHECK: 2019 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) 2020 xs->error = XS_DRIVER_STUFFUP; 2021 else { 2022 trm_RequestSense(sc, pSRB); 2023 return; 2024 } 2025 break; 2026 2027 case SCSI_QUEUE_FULL: 2028 /* this says no more until someone completes */ 2029 pDCB->DCBFlag |= TRM_QUEUE_FULL; 2030 trm_RewaitSRB(sc, pSRB); 2031 return; 2032 2033 case SCSI_RESV_CONFLICT: 2034 case SCSI_BUSY: 2035 xs->error = XS_BUSY; 2036 break; 2037 2038 case TRM_SCSI_UNEXP_BUS_FREE: 2039 xs->status = SCSI_OK; 2040 xs->error = XS_DRIVER_STUFFUP; 2041 break; 2042 2043 case TRM_SCSI_BUS_RST_DETECTED: 2044 xs->status = SCSI_OK; 2045 xs->error = XS_RESET; 2046 break; 2047 2048 case TRM_SCSI_SELECT_TIMEOUT: 2049 xs->status = SCSI_OK; 2050 xs->error = XS_SELTIMEOUT; 2051 break; 2052 2053 default: 2054 xs->error = XS_DRIVER_STUFFUP; 2055 break; 2056 } 2057 2058 target = xs->sc_link->target; 2059 lun = xs->sc_link->lun; 2060 2061 if ((xs->flags & SCSI_POLL) != 0) { 2062 2063 if (xs->cmd->opcode == INQUIRY && pDCB->sc_link == NULL) { 2064 2065 ptr = (struct scsi_inquiry_data *) xs->data; 2066 2067 if ((xs->error != XS_NOERROR) || 2068 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) { 2069 #ifdef TRM_DEBUG0 2070 sc_print_addr(xs->sc_link); 2071 printf("trm_FinishSRB NO Device\n"); 2072 #endif 2073 free(pDCB, M_DEVBUF); 2074 sc->pDCB[target][lun] = NULL; 2075 pDCB = NULL; 2076 2077 } else 2078 pDCB->sc_link = xs->sc_link; 2079 } 2080 } 2081 2082 /* 2083 * Notify cmd done 2084 */ 2085 #ifdef TRM_DEBUG0 2086 if ((xs->error != 0) || (xs->status != 0) || ((xs->flags & SCSI_POLL) != 0)) 2087 sc_print_addr(xs->sc_link); 2088 printf("trm_FinishSRB. xs->cmd->opcode = 0x%02x, xs->error = %d, xs->status = %d\n", 2089 xs->cmd->opcode, xs->error, xs->status); 2090 #endif 2091 2092 if (ISSET(xs->flags, SCSI_POLL)) 2093 SET(xs->flags, ITSDONE); 2094 else 2095 scsi_done(xs); 2096 } 2097 2098 /* 2099 * ------------------------------------------------------------ 2100 * Function : trm_srb_reinit 2101 * Purpose : 2102 * Inputs : 2103 * ------------------------------------------------------------ 2104 */ 2105 void 2106 trm_srb_reinit(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2107 { 2108 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX)); 2109 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2110 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense)); 2111 2112 pSRB->SRBTotalXferLength = 0; 2113 pSRB->SRBSGCount = 0; 2114 pSRB->SRBSGIndex = 0; 2115 pSRB->SRBFlag = 0; 2116 2117 pSRB->SRBState = TRM_FREE; 2118 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2119 pSRB->TargetStatus = SCSI_OK; 2120 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 2121 2122 pSRB->xs = NULL; 2123 pSRB->pSRBDCB = NULL; 2124 } 2125 2126 /* 2127 * ------------------------------------------------------------ 2128 * Function : trm_srb_free 2129 * Purpose : 2130 * Inputs : 2131 * ------------------------------------------------------------ 2132 */ 2133 void 2134 trm_srb_free(void *xsc, void *xpSRB) 2135 { 2136 struct trm_softc *sc = xsc; 2137 struct trm_scsi_req_q *pSRB = xpSRB; 2138 2139 trm_srb_reinit(sc, pSRB); 2140 2141 if (pSRB != &sc->SRB[0]) { 2142 mtx_enter(&sc->sc_srb_mtx); 2143 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2144 mtx_leave(&sc->sc_srb_mtx); 2145 } 2146 } 2147 2148 /* 2149 * ------------------------------------------------------------ 2150 * Function : trm_GoingSRB_Done 2151 * Purpose : 2152 * Inputs : 2153 * ------------------------------------------------------------ 2154 */ 2155 void 2156 trm_GoingSRB_Done(struct trm_softc *sc, struct trm_dcb *pDCB) 2157 { 2158 struct trm_scsi_req_q *pSRB, *pNextSRB; 2159 2160 /* ASSUME we are inside a splbio()/splx() pair */ 2161 2162 pSRB = TAILQ_FIRST(&sc->goingSRB); 2163 while (pSRB != NULL) { 2164 /* 2165 * Need to save pNextSRB because trm_FinishSRB() puts 2166 * pSRB in freeSRB queue, and thus its links no longer 2167 * point to members of the goingSRB queue. This is why 2168 * TAILQ_FOREACH() will not work for this traversal. 2169 */ 2170 pNextSRB = TAILQ_NEXT(pSRB, link); 2171 if (pDCB == NULL || pSRB->pSRBDCB == pDCB) { 2172 /* TODO XXXX: Is TIMED_OUT the best state to report? */ 2173 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 2174 trm_FinishSRB(sc, pSRB); 2175 } 2176 pSRB = pNextSRB; 2177 } 2178 } 2179 2180 /* 2181 * ------------------------------------------------------------ 2182 * Function : trm_ResetSCSIBus 2183 * Purpose : Reset the SCSI bus 2184 * Inputs : struct trm_softc * - 2185 * ------------------------------------------------------------ 2186 */ 2187 void 2188 trm_ResetSCSIBus(struct trm_softc *sc) 2189 { 2190 const bus_space_handle_t ioh = sc->sc_iohandle; 2191 const bus_space_tag_t iot = sc->sc_iotag; 2192 int intflag; 2193 2194 intflag = splbio(); 2195 2196 sc->sc_Flag |= RESET_DEV; 2197 2198 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI); 2199 while ((bus_space_read_2(iot, ioh, 2200 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0); 2201 2202 splx(intflag); 2203 } 2204 2205 /* 2206 * ------------------------------------------------------------ 2207 * Function : trm_ScsiRstDetect 2208 * Purpose : 2209 * Inputs : 2210 * ------------------------------------------------------------ 2211 */ 2212 void 2213 trm_ScsiRstDetect(struct trm_softc *sc) 2214 { 2215 const bus_space_handle_t ioh = sc->sc_iohandle; 2216 const bus_space_tag_t iot = sc->sc_iotag; 2217 int wlval; 2218 2219 #ifdef TRM_DEBUG0 2220 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname); 2221 #endif 2222 2223 wlval = 1000; 2224 /* 2225 * delay 1 sec 2226 */ 2227 while (--wlval != 0) 2228 DELAY(1000); 2229 2230 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 2231 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 2232 2233 if ((sc->sc_Flag & RESET_DEV) != 0) 2234 sc->sc_Flag |= RESET_DONE; 2235 else { 2236 sc->sc_Flag |= RESET_DETECT; 2237 trm_ResetAllDevParam(sc); 2238 trm_RecoverSRB(sc); 2239 sc->pActiveDCB = NULL; 2240 sc->sc_Flag = 0; 2241 trm_StartWaitingSRB(sc); 2242 } 2243 } 2244 2245 /* 2246 * ------------------------------------------------------------ 2247 * Function : trm_RequestSense 2248 * Purpose : 2249 * Inputs : 2250 * ------------------------------------------------------------ 2251 */ 2252 void 2253 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2254 { 2255 pSRB->SRBFlag |= TRM_AUTO_REQSENSE; 2256 2257 /* 2258 * Status of initiator/target 2259 */ 2260 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2261 pSRB->TargetStatus = SCSI_OK; 2262 /* 2263 * Status of initiator/target 2264 */ 2265 2266 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr; 2267 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data); 2268 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data); 2269 pSRB->SRBSGCount = 1; 2270 pSRB->SRBSGIndex = 0; 2271 2272 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2273 2274 pSRB->CmdBlock[0] = REQUEST_SENSE; 2275 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5; 2276 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data); 2277 2278 pSRB->ScsiCmdLen = 6; 2279 2280 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0)) 2281 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout); 2282 2283 if (trm_StartSRB(sc, pSRB) != 0) 2284 trm_RewaitSRB(sc, pSRB); 2285 } 2286 2287 /* 2288 * ------------------------------------------------------------ 2289 * Function : trm_EnableMsgOut 2290 * Purpose : set up MsgBuf to send out a single byte message 2291 * Inputs : 2292 * ------------------------------------------------------------ 2293 */ 2294 void 2295 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg) 2296 { 2297 sc->MsgBuf[0] = msg; 2298 sc->MsgCnt = 1; 2299 2300 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN); 2301 } 2302 2303 /* 2304 * ------------------------------------------------------------ 2305 * Function : trm_linkSRB 2306 * Purpose : 2307 * Inputs : 2308 * ------------------------------------------------------------ 2309 */ 2310 void 2311 trm_linkSRB(struct trm_softc *sc) 2312 { 2313 struct trm_scsi_req_q *pSRB; 2314 int i, intflag; 2315 2316 intflag = splbio(); 2317 2318 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2319 pSRB = &sc->SRB[i]; 2320 2321 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr 2322 + i * sizeof(struct trm_scsi_req_q); 2323 2324 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2325 + i * sizeof(struct trm_scsi_req_q) 2326 + offsetof(struct trm_scsi_req_q, SegmentX); 2327 2328 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2329 + i * sizeof(struct trm_scsi_req_q) 2330 + offsetof(struct trm_scsi_req_q, scsisense); 2331 2332 /* 2333 * map all SRB space 2334 */ 2335 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE, 2336 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0, 2337 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2338 &pSRB->dmamapxfer) != 0) { 2339 printf("%s: unable to create DMA transfer map\n", 2340 sc->sc_device.dv_xname); 2341 splx(intflag); 2342 return; 2343 } 2344 2345 if (i > 0) 2346 /* We use sc->SRB[0] directly, so *don't* link it */ 2347 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2348 #ifdef TRM_DEBUG0 2349 printf("pSRB = %p ", pSRB); 2350 #endif 2351 } 2352 #ifdef TRM_DEBUG0 2353 printf("\n "); 2354 #endif 2355 splx(intflag); 2356 } 2357 2358 /* 2359 * ------------------------------------------------------------ 2360 * Function : trm_minphys 2361 * Purpose : limited by the number of segments in the dma segment list 2362 * Inputs : *buf 2363 * ------------------------------------------------------------ 2364 */ 2365 void 2366 trm_minphys(struct buf *bp, struct scsi_link *sl) 2367 { 2368 if (bp->b_bcount > (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG) { 2369 bp->b_bcount = (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG; 2370 } 2371 minphys(bp); 2372 } 2373 2374 /* 2375 * ------------------------------------------------------------ 2376 * Function : trm_initACB 2377 * Purpose : initialize the internal structures for a given SCSI host 2378 * Inputs : 2379 * ------------------------------------------------------------ 2380 */ 2381 void 2382 trm_initACB(struct trm_softc *sc, int unit) 2383 { 2384 const bus_space_handle_t ioh = sc->sc_iohandle; 2385 const bus_space_tag_t iot = sc->sc_iotag; 2386 struct trm_adapter_nvram *pEEpromBuf; 2387 struct trm_dcb *pDCB; 2388 int target, lun; 2389 2390 pEEpromBuf = &trm_eepromBuf[unit]; 2391 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2392 2393 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0) 2394 sc->sc_config |= HCC_WIDE_CARD; 2395 2396 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0) 2397 sc->sc_config |= HCC_SCSI_RESET; 2398 2399 TAILQ_INIT(&sc->freeSRB); 2400 TAILQ_INIT(&sc->waitingSRB); 2401 TAILQ_INIT(&sc->goingSRB); 2402 2403 mtx_init(&sc->sc_srb_mtx, IPL_BIO); 2404 scsi_iopool_init(&sc->sc_iopool, sc, trm_srb_alloc, trm_srb_free); 2405 2406 sc->pActiveDCB = NULL; 2407 sc->sc_AdapterUnit = unit; 2408 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId; 2409 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2410 sc->sc_Flag = 0; 2411 2412 /* 2413 * put all SRB's (except [0]) onto the freeSRB list 2414 */ 2415 trm_linkSRB(sc); 2416 2417 /* 2418 * allocate DCB array 2419 */ 2420 for (target = 0; target < TRM_MAX_TARGETS; target++) { 2421 if (target == sc->sc_AdaptSCSIID) 2422 continue; 2423 2424 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2425 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), 2426 M_DEVBUF, M_NOWAIT | M_ZERO); 2427 sc->pDCB[target][lun] = pDCB; 2428 2429 if (pDCB == NULL) 2430 continue; 2431 2432 pDCB->target = target; 2433 pDCB->lun = lun; 2434 pDCB->pActiveSRB = NULL; 2435 } 2436 } 2437 2438 sc->sc_adapter.scsi_cmd = trm_scsi_cmd; 2439 sc->sc_adapter.scsi_minphys = trm_minphys; 2440 2441 sc->sc_link.adapter_softc = sc; 2442 sc->sc_link.adapter_target = sc->sc_AdaptSCSIID; 2443 sc->sc_link.openings = 30; /* So TagMask (32 bit integer) always has space */ 2444 sc->sc_link.adapter = &sc->sc_adapter; 2445 sc->sc_link.adapter_buswidth = ((sc->sc_config & HCC_WIDE_CARD) == 0) ? 8:16; 2446 sc->sc_link.pool = &sc->sc_iopool; 2447 2448 trm_reset(sc); 2449 } 2450 2451 /* 2452 * ------------------------------------------------------------ 2453 * Function : trm_write_all 2454 * Description : write pEEpromBuf 128 bytes to seeprom 2455 * Input : iot, ioh - chip's base address 2456 * Output : none 2457 * ------------------------------------------------------------ 2458 */ 2459 void 2460 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2461 bus_space_handle_t ioh) 2462 { 2463 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2464 u_int8_t bAddr; 2465 2466 /* 2467 * Enable SEEPROM 2468 */ 2469 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2470 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2471 /* 2472 * Write enable 2473 */ 2474 trm_write_cmd(iot, ioh, 0x04, 0xFF); 2475 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2476 trm_wait_30us(iot, ioh); 2477 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2478 trm_set_data(iot, ioh, bAddr, *bpEeprom); 2479 /* 2480 * Write disable 2481 */ 2482 trm_write_cmd(iot, ioh, 0x04, 0x00); 2483 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2484 trm_wait_30us(iot, ioh); 2485 /* 2486 * Disable SEEPROM 2487 */ 2488 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2489 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2490 } 2491 2492 /* 2493 * ------------------------------------------------------------ 2494 * Function : trm_set_data 2495 * Description : write one byte to seeprom 2496 * Input : iot, ioh - chip's base address 2497 * bAddr - address of SEEPROM 2498 * bData - data of SEEPROM 2499 * Output : none 2500 * ------------------------------------------------------------ 2501 */ 2502 void 2503 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr, 2504 u_int8_t bData) 2505 { 2506 u_int8_t bSendData; 2507 int i; 2508 2509 /* 2510 * Send write command & address 2511 */ 2512 trm_write_cmd(iot, ioh, 0x05, bAddr); 2513 /* 2514 * Write data 2515 */ 2516 for (i = 0; i < 8; i++, bData <<= 1) { 2517 bSendData = NVR_SELECT; 2518 if ((bData & 0x80) != 0) { /* Start from bit 7 */ 2519 bSendData |= NVR_BITOUT; 2520 } 2521 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2522 trm_wait_30us(iot, ioh); 2523 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2524 (bSendData | NVR_CLOCK)); 2525 trm_wait_30us(iot, ioh); 2526 } 2527 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2528 trm_wait_30us(iot, ioh); 2529 /* 2530 * Disable chip select 2531 */ 2532 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2533 trm_wait_30us(iot, ioh); 2534 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2535 trm_wait_30us(iot, ioh); 2536 /* 2537 * Wait for write ready 2538 */ 2539 for (;;) { 2540 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2541 (NVR_SELECT | NVR_CLOCK)); 2542 trm_wait_30us(iot, ioh); 2543 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2544 trm_wait_30us(iot, ioh); 2545 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN) 2546 break; 2547 } 2548 /* 2549 * Disable chip select 2550 */ 2551 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2552 } 2553 2554 /* 2555 * ------------------------------------------------------------ 2556 * Function : trm_read_all 2557 * Description : read seeprom 128 bytes to pEEpromBuf 2558 * Input : pEEpromBuf, iot, ioh - chip's base address 2559 * Output : none 2560 * ------------------------------------------------------------ 2561 */ 2562 void 2563 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2564 bus_space_handle_t ioh) 2565 { 2566 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2567 u_int8_t bAddr; 2568 2569 /* 2570 * Enable SEEPROM 2571 */ 2572 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2573 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2574 2575 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2576 *bpEeprom = trm_get_data(iot, ioh, bAddr); 2577 2578 /* 2579 * Disable SEEPROM 2580 */ 2581 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2582 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2583 } 2584 2585 /* 2586 * ------------------------------------------------------------ 2587 * Function : trm_get_data 2588 * Description : read one byte from seeprom 2589 * Input : iot, ioh - chip's base address 2590 * bAddr - address of SEEPROM 2591 * Output : bData - data of SEEPROM 2592 * ------------------------------------------------------------ 2593 */ 2594 u_int8_t 2595 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr) 2596 { 2597 u_int8_t bReadData, bData; 2598 int i; 2599 2600 bData = 0; 2601 2602 /* 2603 * Send read command & address 2604 */ 2605 trm_write_cmd(iot, ioh, 0x06, bAddr); 2606 2607 for (i = 0; i < 8; i++) { 2608 /* 2609 * Read data 2610 */ 2611 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2612 (NVR_SELECT | NVR_CLOCK)); 2613 trm_wait_30us(iot, ioh); 2614 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2615 /* 2616 * Get data bit while falling edge 2617 */ 2618 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM); 2619 bData <<= 1; 2620 if ((bReadData & NVR_BITIN) != 0) 2621 bData |= 1; 2622 trm_wait_30us(iot, ioh); 2623 } 2624 /* 2625 * Disable chip select 2626 */ 2627 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2628 2629 return bData; 2630 } 2631 2632 /* 2633 * ------------------------------------------------------------ 2634 * Function : trm_wait_30us 2635 * Description : wait 30 us 2636 * Input : iot, ioh - chip's base address 2637 * Output : none 2638 * ------------------------------------------------------------ 2639 */ 2640 void 2641 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh) 2642 { 2643 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5); 2644 2645 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT) 2646 == 0); 2647 } 2648 2649 /* 2650 * ------------------------------------------------------------ 2651 * Function : trm_write_cmd 2652 * Description : write SB and Op Code into seeprom 2653 * Input : iot, ioh - chip's base address 2654 * bCmd - SB + Op Code 2655 * bAddr - address of SEEPROM 2656 * Output : none 2657 * ------------------------------------------------------------ 2658 */ 2659 void 2660 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd, 2661 u_int8_t bAddr) 2662 { 2663 u_int8_t bSendData; 2664 int i; 2665 2666 for (i = 0; i < 3; i++, bCmd <<= 1) { 2667 /* 2668 * Program SB + OP code 2669 */ 2670 bSendData = NVR_SELECT; 2671 if (bCmd & 0x04) /* Start from bit 2 */ 2672 bSendData |= NVR_BITOUT; 2673 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2674 trm_wait_30us(iot, ioh); 2675 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2676 (bSendData | NVR_CLOCK)); 2677 trm_wait_30us(iot, ioh); 2678 } 2679 2680 for (i = 0; i < 7; i++, bAddr <<= 1) { 2681 /* 2682 * Program address 2683 */ 2684 bSendData = NVR_SELECT; 2685 if (bAddr & 0x40) { /* Start from bit 6 */ 2686 bSendData |= NVR_BITOUT; 2687 } 2688 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2689 trm_wait_30us(iot, ioh); 2690 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2691 (bSendData | NVR_CLOCK)); 2692 trm_wait_30us(iot, ioh); 2693 } 2694 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2695 trm_wait_30us(iot, ioh); 2696 } 2697 2698 /* 2699 * ------------------------------------------------------------ 2700 * Function : trm_check_eeprom 2701 * Description : read eeprom 128 bytes to pEEpromBuf and check 2702 * checksum. If it is wrong, updated with default value. 2703 * Input : eeprom, iot, ioh - chip's base address 2704 * Output : none 2705 * ------------------------------------------------------------ 2706 */ 2707 void 2708 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2709 bus_space_handle_t ioh) 2710 { 2711 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget; 2712 u_int32_t dAddr; 2713 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf; 2714 u_int16_t wAddr, wCheckSum; 2715 2716 #ifdef TRM_DEBUG0 2717 printf("\ntrm_check_eeprom\n"); 2718 #endif 2719 trm_read_all(pEEpromBuf, iot, ioh); 2720 wCheckSum = 0; 2721 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++) 2722 wCheckSum += *wpEeprom; 2723 2724 if (wCheckSum != 0x1234) { 2725 #ifdef TRM_DEBUG0 2726 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n"); 2727 #endif 2728 /* 2729 * Checksum error, load default 2730 */ 2731 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2732 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2733 >> 8); 2734 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) 2735 PCI_PRODUCT_TEKRAM2_DC3X5U; 2736 pEEpromBuf->NvramSubSysID[1] = (u_int8_t) 2737 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2738 pEEpromBuf->NvramSubClass = 0; 2739 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2740 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2741 >> 8); 2742 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) 2743 PCI_PRODUCT_TEKRAM2_DC3X5U; 2744 pEEpromBuf->NvramDeviceID[1] = (u_int8_t) 2745 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2746 pEEpromBuf->NvramReserved = 0; 2747 2748 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++) 2749 /* 2750 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 2751 */ 2752 *dpEeprom = 0x00000077; 2753 2754 /* 2755 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId 2756 */ 2757 *dpEeprom++ = 0x04000F07; 2758 2759 /* 2760 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 2761 */ 2762 *dpEeprom++ = 0x00000015; 2763 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 2764 *dpEeprom = 0; 2765 2766 pEEpromBuf->NvramCheckSum = 0; 2767 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++) 2768 wCheckSum += *wpEeprom; 2769 2770 *wpEeprom = 0x1234 - wCheckSum; 2771 trm_write_all(pEEpromBuf, iot, ioh); 2772 } 2773 } 2774 2775 /* 2776 * ------------------------------------------------------------ 2777 * Function : trm_initAdapter 2778 * Purpose : initialize the SCSI chip ctrl registers 2779 * Inputs : psh - pointer to this host adapter's structure 2780 * ------------------------------------------------------------ 2781 */ 2782 void 2783 trm_initAdapter(struct trm_softc *sc) 2784 { 2785 const bus_space_handle_t ioh = sc->sc_iohandle; 2786 const bus_space_tag_t iot = sc->sc_iotag; 2787 u_int16_t wval; 2788 u_int8_t bval; 2789 2790 /* 2791 * program configuration 0 2792 */ 2793 if ((sc->sc_config & HCC_PARITY) != 0) { 2794 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 2795 } else { 2796 bval = PHASELATCH | INITIATOR | BLOCKRST; 2797 } 2798 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval); 2799 /* 2800 * program configuration 1 2801 */ 2802 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13); 2803 /* 2804 * 250ms selection timeout 2805 */ 2806 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT); 2807 /* 2808 * Mask all the interrupt 2809 */ 2810 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 2811 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 2812 /* 2813 * Reset SCSI module 2814 */ 2815 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE); 2816 /* 2817 * program Host ID 2818 */ 2819 bval = sc->sc_AdaptSCSIID; 2820 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval); 2821 /* 2822 * set ansynchronous transfer 2823 */ 2824 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0); 2825 /* 2826 * Turn LED control off 2827 */ 2828 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F; 2829 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval); 2830 /* 2831 * DMA config 2832 */ 2833 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE; 2834 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval); 2835 /* 2836 * Clear pending interrupt status 2837 */ 2838 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 2839 /* 2840 * Enable SCSI interrupts 2841 */ 2842 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 2843 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 2844 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 2845 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 2846 } 2847 2848 /* 2849 * ------------------------------------------------------------ 2850 * Function : trm_init 2851 * Purpose : initialize the internal structures for a given SCSI host 2852 * Inputs : host - pointer to this host adapter's structure 2853 * Preconditions : when this function is called, the chip_type field of 2854 * the ACB structure MUST have been set. 2855 * ------------------------------------------------------------ 2856 */ 2857 int 2858 trm_init(struct trm_softc *sc, int unit) 2859 { 2860 const bus_space_handle_t ioh = sc->sc_iohandle; 2861 const bus_space_tag_t iot = sc->sc_iotag; 2862 bus_dma_segment_t seg; 2863 int error, rseg, all_srbs_size; 2864 2865 /* 2866 * EEPROM CHECKSUM 2867 */ 2868 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh); 2869 2870 /* 2871 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 2872 */ 2873 /* 2874 * allocate the space for all SCSI control blocks (SRB) for DMA memory. 2875 */ 2876 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q); 2877 2878 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg, 2879 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 2880 if (error != 0) { 2881 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n", 2882 sc->sc_device.dv_xname, error); 2883 /*errx(error, "%s: unable to allocate SCSI request blocks", 2884 sc->sc_device.dv_xname);*/ 2885 return -1; 2886 } 2887 2888 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size, 2889 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 2890 if (error != 0) { 2891 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n", 2892 sc->sc_device.dv_xname, error); 2893 /*errx(error, "unable to map SCSI request blocks");*/ 2894 return -1; 2895 } 2896 2897 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1, 2898 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control); 2899 if (error != 0) { 2900 printf("%s: unable to create SRB DMA maps, error = %d\n", 2901 sc->sc_device.dv_xname, error); 2902 /*errx(error, "unable to create SRB DMA maps");*/ 2903 return -1; 2904 } 2905 2906 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control, 2907 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT); 2908 if (error != 0) { 2909 printf("%s: unable to load SRB DMA maps, error = %d\n", 2910 sc->sc_device.dv_xname, error); 2911 /*errx(error, "unable to load SRB DMA maps");*/ 2912 return -1; 2913 } 2914 #ifdef TRM_DEBUG0 2915 printf("\n\n%s: all_srbs_size=%x\n", 2916 sc->sc_device.dv_xname, all_srbs_size); 2917 #endif 2918 trm_initACB(sc, unit); 2919 trm_initAdapter(sc); 2920 2921 return 0; 2922 } 2923 2924 /* ------------------------------------------------------------ 2925 * Function : trm_print_info 2926 * Purpose : Print the DCB negotiation information 2927 * Inputs : 2928 * ------------------------------------------------------------ 2929 */ 2930 void 2931 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB) 2932 { 2933 int syncXfer, index; 2934 2935 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC); 2936 2937 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target); 2938 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0) 2939 printf("16 bit "); 2940 else 2941 printf("8 bit "); 2942 2943 if (pDCB->SyncOffset == 0) 2944 printf("Asynchronous "); 2945 else { 2946 syncXfer = 100000 / (trm_clock_period[index] * 4); 2947 printf("%d.%01d MHz, Offset %d ", 2948 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset); 2949 } 2950 printf("data transfers "); 2951 2952 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) 2953 printf("with Tag Queuing"); 2954 2955 printf("\n"); 2956 } 2957