1 /* $OpenBSD: trm.c,v 1.12 2009/02/16 21:19:07 miod Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.c 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * HISTORY: 13 * 14 * REV# DATE NAME DESCRIPTION 15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x 16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8 17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting 18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic 19 * ------------------------------------------------------------ 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 3. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * ------------------------------------------------------------ 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/buf.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <scsi/scsi_message.h> 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/ic/trm.h> 61 62 /* #define TRM_DEBUG0 */ 63 64 void trm_minphys(struct buf *, struct scsi_link *); 65 66 void trm_initSRB(struct trm_scsi_req_q *); 67 68 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 69 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 70 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 71 72 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 73 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 74 75 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t); 76 77 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t); 78 79 int trm_scsi_cmd(struct scsi_xfer *); 80 81 struct trm_scsi_req_q *trm_GetFreeSRB(struct trm_softc *); 82 83 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 84 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 85 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 86 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 87 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 88 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 89 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 90 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 91 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 92 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 93 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 94 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 95 96 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int); 97 98 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t); 99 100 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *); 101 void trm_ReleaseSRB (struct trm_softc *, struct trm_scsi_req_q *); 102 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *); 103 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *); 104 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *); 105 106 void trm_initAdapter (struct trm_softc *); 107 void trm_Disconnect (struct trm_softc *); 108 void trm_Reselect (struct trm_softc *); 109 void trm_GoingSRB_Done (struct trm_softc *); 110 void trm_ScsiRstDetect (struct trm_softc *); 111 void trm_ResetSCSIBus (struct trm_softc *); 112 void trm_reset (struct trm_softc *); 113 void trm_StartWaitingSRB (struct trm_softc *); 114 void trm_ResetAllDevParam(struct trm_softc *); 115 void trm_RecoverSRB (struct trm_softc *); 116 void trm_linkSRB (struct trm_softc *); 117 118 void trm_initACB(struct trm_softc *, int); 119 120 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t); 121 122 void trm_EnableMsgOut(struct trm_softc *, u_int8_t); 123 124 void trm_timeout(void *); 125 126 void trm_print_info(struct trm_softc *, struct trm_dcb *); 127 128 /* 129 * Define structures 130 */ 131 struct cfdriver trm_cd = { 132 NULL, "trm", DV_DULL 133 }; 134 135 struct scsi_adapter trm_switch = { 136 trm_scsi_cmd, 137 trm_minphys, 138 NULL, 139 NULL 140 }; 141 142 static struct scsi_device trm_device = { 143 NULL, /* Use default error handler */ 144 NULL, /* have a queue, served by this */ 145 NULL, /* have no async handler */ 146 NULL, /* Use default 'done' routine */ 147 }; 148 149 /* 150 * ------------------------------------------------------------ 151 * 152 * stateV = (void *) trm_SCSI_phase0[phase] 153 * 154 * ------------------------------------------------------------ 155 */ 156 static void *trm_SCSI_phase0[8] = { 157 trm_DataOutPhase0, /* phase:0 */ 158 trm_DataInPhase0, /* phase:1 */ 159 trm_Nop, /* phase:2 */ 160 trm_StatusPhase0, /* phase:3 */ 161 trm_Nop, /* phase:4 */ 162 trm_Nop, /* phase:5 */ 163 trm_MsgOutPhase0, /* phase:6 */ 164 trm_MsgInPhase0, /* phase:7 */ 165 }; 166 167 /* 168 * ------------------------------------------------------------ 169 * 170 * stateV = (void *) trm_SCSI_phase1[phase] 171 * 172 * ------------------------------------------------------------ 173 */ 174 static void *trm_SCSI_phase1[8] = { 175 trm_DataOutPhase1, /* phase:0 */ 176 trm_DataInPhase1, /* phase:1 */ 177 trm_CommandPhase1, /* phase:2 */ 178 trm_StatusPhase1, /* phase:3 */ 179 trm_Nop, /* phase:4 */ 180 trm_Nop, /* phase:5 */ 181 trm_MsgOutPhase1, /* phase:6 */ 182 trm_MsgInPhase1, /* phase:7 */ 183 }; 184 185 186 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 187 /* 188 *Fast20: 000 50ns, 20.0 Mbytes/s 189 * 001 75ns, 13.3 Mbytes/s 190 * 010 100ns, 10.0 Mbytes/s 191 * 011 125ns, 8.0 Mbytes/s 192 * 100 150ns, 6.6 Mbytes/s 193 * 101 175ns, 5.7 Mbytes/s 194 * 110 200ns, 5.0 Mbytes/s 195 * 111 250ns, 4.0 Mbytes/s 196 * 197 *Fast40: 000 25ns, 40.0 Mbytes/s 198 * 001 50ns, 20.0 Mbytes/s 199 * 010 75ns, 13.3 Mbytes/s 200 * 011 100ns, 10.0 Mbytes/s 201 * 100 125ns, 8.0 Mbytes/s 202 * 101 150ns, 6.6 Mbytes/s 203 * 110 175ns, 5.7 Mbytes/s 204 * 111 200ns, 5.0 Mbytes/s 205 */ 206 207 /* 208 * real period: 209 */ 210 u_int8_t trm_clock_period[8] = { 211 /* nanosecond divided by 4 */ 212 12, /* 48 ns 20 MB/sec */ 213 18, /* 72 ns 13.3 MB/sec */ 214 25, /* 100 ns 10.0 MB/sec */ 215 31, /* 124 ns 8.0 MB/sec */ 216 37, /* 148 ns 6.6 MB/sec */ 217 43, /* 172 ns 5.7 MB/sec */ 218 50, /* 200 ns 5.0 MB/sec */ 219 62 /* 248 ns 4.0 MB/sec */ 220 }; 221 222 /* 223 * ------------------------------------------------------------ 224 * Function : trm_GetFreeSRB 225 * Purpose : Get the first free SRB 226 * Inputs : 227 * Return : NULL or a free SCSI Request block 228 * ------------------------------------------------------------ 229 */ 230 struct trm_scsi_req_q * 231 trm_GetFreeSRB(struct trm_softc *sc) 232 { 233 struct trm_scsi_req_q *pSRB; 234 235 /* ASSUME we are called from inside a splbio()/splx() region */ 236 237 pSRB = TAILQ_FIRST(&sc->freeSRB); 238 239 if (pSRB != NULL) 240 TAILQ_REMOVE(&sc->freeSRB, pSRB, link); 241 242 #ifdef TRM_DEBUG0 243 printf("%s: trm_GetFreeSRB. pSRB = %p, next pSRB = %p\n", 244 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB)); 245 #endif 246 247 return pSRB; 248 } 249 250 /* 251 * ------------------------------------------------------------ 252 * Function : trm_RewaitSRB 253 * Purpose : Q back to pending Q 254 * Inputs : struct trm_dcb * - 255 * struct trm_scsi_req_q * - 256 * ------------------------------------------------------------ 257 */ 258 void 259 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 260 { 261 int intflag; 262 263 intflag = splbio(); 264 265 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 266 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 267 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 268 } 269 270 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 271 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 272 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 273 } 274 275 pSRB->SRBState = TRM_READY; 276 pSRB->TargetStatus = SCSI_OK; 277 pSRB->AdaptStatus = TRM_STATUS_GOOD; 278 279 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 280 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 281 282 splx(intflag); 283 } 284 285 /* 286 * ------------------------------------------------------------ 287 * Function : trm_StartWaitingSRB 288 * Purpose : If there is no active DCB then run robin through 289 * the DCB's to find the next waiting SRB 290 * and move it to the going list. 291 * Inputs : struct trm_softc * - 292 * ------------------------------------------------------------ 293 */ 294 void 295 trm_StartWaitingSRB(struct trm_softc *sc) 296 { 297 struct trm_scsi_req_q *pSRB, *next; 298 int intflag; 299 300 intflag = splbio(); 301 302 if ((sc->pActiveDCB != NULL) || 303 (TAILQ_EMPTY(&sc->waitingSRB)) || 304 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0) 305 return; 306 307 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) { 308 next = TAILQ_NEXT(pSRB, link); 309 if (trm_StartSRB(sc, pSRB) == 0) { 310 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 311 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 312 pSRB->SRBFlag |= TRM_ON_GOING_SRB; 313 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link); 314 break; 315 } 316 } 317 318 splx(intflag); 319 } 320 321 /* 322 * ------------------------------------------------------------ 323 * Function : trm_scsi_cmd 324 * Purpose : enqueues a SCSI command 325 * Inputs : 326 * Call By : GENERIC SCSI driver 327 * ------------------------------------------------------------ 328 */ 329 int 330 trm_scsi_cmd(struct scsi_xfer *xs) 331 { 332 struct trm_scsi_req_q *pSRB; 333 bus_space_handle_t ioh; 334 struct trm_softc *sc; 335 bus_space_tag_t iot; 336 struct trm_dcb *pDCB; 337 u_int8_t target, lun; 338 int i, error, intflag, xferflags; 339 340 target = xs->sc_link->target; 341 lun = xs->sc_link->lun; 342 343 sc = (struct trm_softc *)xs->sc_link->adapter_softc; 344 ioh = sc->sc_iohandle; 345 iot = sc->sc_iotag; 346 347 #ifdef TRM_DEBUG0 348 if ((xs->flags & SCSI_POLL) != 0) 349 printf("%s: trm_scsi_cmd. sc = %p, xs = %p, targ/lun = %d/%d opcode = 0x%02x\n", 350 sc->sc_device.dv_xname, sc, xs, target, lun, xs->cmd->opcode); 351 #endif 352 353 if (target >= TRM_MAX_TARGETS) { 354 printf("%s: target=%d >= %d\n", 355 sc->sc_device.dv_xname, target, TRM_MAX_TARGETS); 356 xs->error = XS_DRIVER_STUFFUP; 357 return COMPLETE; 358 } 359 if (lun >= TRM_MAX_LUNS) { 360 printf("%s: lun=%d >= %d\n", 361 sc->sc_device.dv_xname, lun, TRM_MAX_LUNS); 362 xs->error = XS_DRIVER_STUFFUP; 363 return COMPLETE; 364 } 365 366 pDCB = sc->pDCB[target][lun]; 367 if (pDCB == NULL) { 368 /* Removed as a result of INQUIRY proving no device present */ 369 xs->error = XS_DRIVER_STUFFUP; 370 return COMPLETE; 371 } 372 373 xferflags = xs->flags; 374 if (xferflags & SCSI_RESET) { 375 #ifdef TRM_DEBUG0 376 printf("%s: trm_reset\n", sc->sc_device.dv_xname); 377 #endif 378 trm_reset(sc); 379 xs->error = XS_NOERROR; 380 return COMPLETE; 381 } 382 383 if (xferflags & ITSDONE) { 384 #ifdef TRM_DEBUG0 385 printf("%s: Is it done?\n", sc->sc_device.dv_xname); 386 #endif 387 xs->flags &= ~ITSDONE; 388 } 389 390 xs->error = XS_NOERROR; 391 xs->status = SCSI_OK; 392 xs->resid = 0; 393 394 intflag = splbio(); 395 396 pSRB = trm_GetFreeSRB(sc); 397 398 if (pSRB == NULL) { 399 splx(intflag); 400 return (NO_CCB); 401 } 402 403 /* 404 * BuildSRB(pSRB,pDCB); 405 */ 406 if (xs->datalen != 0) { 407 #ifdef TRM_DEBUG0 408 printf("%s: xs->datalen=%x\n", sc->sc_device.dv_xname, 409 (u_int32_t)xs->datalen); 410 printf("%s: sc->sc_dmatag=0x%x\n", sc->sc_device.dv_xname, 411 (u_int32_t)sc->sc_dmatag); 412 printf("%s: pSRB->dmamapxfer=0x%x\n", sc->sc_device.dv_xname, 413 (u_int32_t)pSRB->dmamapxfer); 414 printf("%s: xs->data=0x%x\n", sc->sc_device.dv_xname, 415 (u_int32_t)xs->data); 416 #endif 417 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer, 418 xs->data, xs->datalen, NULL, 419 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : 420 BUS_DMA_WAITOK)) != 0) { 421 printf("%s: DMA transfer map unable to load, error = %d\n" 422 , sc->sc_device.dv_xname, error); 423 xs->error = XS_DRIVER_STUFFUP; 424 /* 425 * free SRB 426 */ 427 TAILQ_INSERT_HEAD(&sc->freeSRB, pSRB, link); 428 splx(intflag); 429 return COMPLETE; 430 } 431 432 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 433 0, pSRB->dmamapxfer->dm_mapsize, 434 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 435 436 /* 437 * Set up the scatter gather list 438 */ 439 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) { 440 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr; 441 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len; 442 } 443 pSRB->SRBTotalXferLength = xs->datalen; 444 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs; 445 } 446 447 pSRB->pSRBDCB = pDCB; 448 pSRB->xs = xs; 449 pSRB->ScsiCmdLen = xs->cmdlen; 450 451 memcpy(pSRB->CmdBlock, xs->cmd, xs->cmdlen); 452 453 splx (intflag); 454 455 timeout_set(&xs->stimeout, trm_timeout, pSRB); 456 457 intflag = splbio(); 458 459 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 460 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link); 461 trm_StartWaitingSRB(sc); 462 463 if ((xferflags & SCSI_POLL) == 0) { 464 timeout_add_msec(&xs->stimeout, xs->timeout); 465 splx(intflag); 466 return SUCCESSFULLY_QUEUED; 467 } 468 469 while ((--xs->timeout > 0) && ((xs->flags & ITSDONE) == 0)) { 470 trm_Interrupt(sc); 471 DELAY(1000); 472 } 473 474 if (xs->timeout == 0) 475 trm_timeout(pSRB); 476 477 splx(intflag); 478 return COMPLETE; 479 } 480 481 /* 482 * ------------------------------------------------------------ 483 * Function : trm_ResetAllDevParam 484 * Purpose : 485 * Inputs : struct trm_softc * 486 * ------------------------------------------------------------ 487 */ 488 void 489 trm_ResetAllDevParam(struct trm_softc *sc) 490 { 491 struct trm_adapter_nvram *pEEpromBuf; 492 int target, quirks; 493 494 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 495 496 for (target = 0; target < TRM_MAX_TARGETS; target++) { 497 if (target == sc->sc_AdaptSCSIID) 498 continue; 499 500 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0) 501 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS; 502 else 503 quirks = sc->pDCB[target][0]->sc_link->quirks; 504 505 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks); 506 } 507 } 508 509 /* 510 * ------------------------------------------------------------ 511 * Function : trm_ResetDevParam 512 * Purpose : 513 * Inputs : 514 * ------------------------------------------------------------ 515 */ 516 void 517 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks) 518 { 519 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 520 u_int8_t PeriodIndex; 521 const int target = pDCB->target; 522 523 pDCB->DCBFlag &= TRM_QUIRKS_VALID; 524 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE); 525 526 pDCB->SyncPeriod = 0; 527 pDCB->SyncOffset = 0; 528 pDCB->MaxNegoPeriod = 0; 529 530 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0; 531 532 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0)); 533 534 if (((quirks & SDEV_NOWIDE) == 0) && 535 (pDCB->DevMode & TRM_WIDE) && 536 ((sc->sc_config & HCC_WIDE_CARD) != 0)) 537 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT; 538 539 if (((quirks & SDEV_NOSYNC) == 0) && 540 ((pDCB->DevMode & TRM_SYNC) != 0)) { 541 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07; 542 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex]; 543 } 544 545 if (((quirks & SDEV_NOTAGS) == 0) && 546 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) && 547 ((pDCB->DevMode & TRM_DISCONNECT) != 0)) 548 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */ 549 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING; 550 551 trm_SetXferParams(sc, pDCB, 0); 552 } 553 554 /* 555 * ------------------------------------------------------------ 556 * Function : trm_RecoverSRB 557 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs 558 * Inputs : struct trm_softc * - 559 * ------------------------------------------------------------ 560 */ 561 void 562 trm_RecoverSRB(struct trm_softc *sc) 563 { 564 struct trm_scsi_req_q *pSRB; 565 566 /* ASSUME we are inside splbio()/splx() */ 567 568 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 569 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 570 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 571 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 572 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 573 } 574 } 575 576 /* 577 * ------------------------------------------------------------ 578 * Function : trm_reset 579 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip). 580 * Inputs : 581 * ------------------------------------------------------------ 582 */ 583 void 584 trm_reset (struct trm_softc *sc) 585 { 586 const bus_space_handle_t ioh = sc->sc_iohandle; 587 const bus_space_tag_t iot = sc->sc_iotag; 588 int i, intflag; 589 590 #ifdef TRM_DEBUG0 591 printf("%s: trm_reset", sc->sc_device.dv_xname); 592 #endif 593 594 intflag = splbio(); 595 596 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 597 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 598 599 trm_ResetSCSIBus(sc); 600 for (i = 0; i < 500; i++) 601 DELAY(1000); 602 603 /* 604 * Enable all SCSI interrupts except EN_SCAM 605 */ 606 bus_space_write_1(iot, ioh, 607 TRM_S1040_SCSI_INTEN, 608 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 609 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 610 /* 611 * Enable DMA interrupt 612 */ 613 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 614 /* 615 * Clear DMA FIFO 616 */ 617 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO); 618 /* 619 * Clear SCSI FIFO 620 */ 621 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 622 623 trm_ResetAllDevParam(sc); 624 trm_GoingSRB_Done(sc); 625 sc->pActiveDCB = NULL; 626 627 /* 628 * RESET_DETECT, RESET_DONE, RESET_DEV 629 */ 630 sc->sc_Flag = 0; 631 trm_StartWaitingSRB(sc); 632 633 splx(intflag); 634 } 635 636 /* 637 * ------------------------------------------------------------ 638 * Function : trm_timeout 639 * Purpose : Prints a timeout message and aborts the timed out SCSI request 640 * Inputs : void * - A struct trm_scsi_req_q * structure pointer 641 * ------------------------------------------------------------ 642 */ 643 void 644 trm_timeout(void *arg1) 645 { 646 struct trm_scsi_req_q *pSRB; 647 struct scsi_xfer *xs; 648 struct trm_softc *sc; 649 650 pSRB = (struct trm_scsi_req_q *)arg1; 651 xs = pSRB->xs; 652 653 if (xs != NULL) { 654 sc = xs->sc_link->adapter_softc; 655 sc_print_addr(xs->sc_link); 656 printf("SCSI OpCode 0x%02x timed out\n", 657 sc->sc_device.dv_xname, xs->cmd->opcode); 658 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 659 trm_FinishSRB(sc, pSRB); 660 trm_StartWaitingSRB(sc); 661 } 662 #ifdef TRM_DEBUG0 663 else 664 printf("%s: trm_timeout called with xs == NULL\n", 665 sc->sc_device.dv_xname); 666 #endif 667 } 668 669 /* 670 * ------------------------------------------------------------ 671 * Function : trm_StartSRB 672 * Purpose : Send the commands in the SRB to the device 673 * Inputs : struct trm_softc * - 674 * struct trm_scsi_req_q * - 675 * Return : 0 - SCSI processor is unoccupied 676 * 1 - SCSI processor is occupied with an SRB 677 * ------------------------------------------------------------ 678 */ 679 int 680 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 681 { 682 const bus_space_handle_t ioh = sc->sc_iohandle; 683 const bus_space_tag_t iot = sc->sc_iotag; 684 struct trm_dcb *pDCB = pSRB->pSRBDCB; 685 u_int32_t tag_mask; 686 u_int8_t tag_id, scsicommand; 687 688 #ifdef TRM_DEBUG0 689 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n", 690 sc->sc_device.dv_xname, sc, pDCB, pSRB); 691 #endif 692 /* 693 * If the queue is full or the SCSI processor has a pending interrupt 694 * then try again later. 695 */ 696 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh, 697 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT)) 698 return (1); 699 700 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 701 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target); 702 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 703 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 704 705 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) && 706 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) { 707 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID; 708 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks); 709 } 710 711 /* 712 * Flush FIFO 713 */ 714 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 715 716 sc->MsgCnt = 1; 717 sc->MsgBuf[0] = pDCB->IdentifyMsg; 718 if (((pSRB->xs->flags & SCSI_POLL) != 0) || 719 (pSRB->CmdBlock[0] == INQUIRY) || 720 (pSRB->CmdBlock[0] == REQUEST_SENSE)) 721 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG; 722 723 scsicommand = SCMD_SEL_ATN; 724 725 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) { 726 scsicommand = SCMD_SEL_ATNSTOP; 727 pSRB->SRBState = TRM_MSGOUT; 728 729 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) { 730 pDCB->DCBFlag |= TRM_QUEUE_FULL; 731 732 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) { 733 if (pSRB->TagNumber == TRM_NO_TAG) { 734 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1) 735 if ((tag_mask & pDCB->TagMask) == 0) { 736 pDCB->TagMask |= tag_mask; 737 pSRB->TagNumber = tag_id; 738 break; 739 } 740 741 if (tag_id >= 32) { 742 pDCB->DCBFlag |= TRM_QUEUE_FULL; 743 sc->MsgCnt = 0; 744 return 1; 745 } 746 } 747 748 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */ 749 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG; 750 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber; 751 752 scsicommand = SCMD_SEL_ATN3; 753 } 754 755 pSRB->SRBState = TRM_START; 756 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 757 sc->pActiveDCB = pDCB; 758 pDCB->pActiveSRB = pSRB; 759 760 if (sc->MsgCnt > 0) { 761 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]); 762 if (sc->MsgCnt > 1) { 763 DELAY(30); 764 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1); 765 } 766 sc->MsgCnt = 0; 767 } 768 769 /* 770 * it's important for atn stop 771 */ 772 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT); 773 /* 774 * SCSI command 775 */ 776 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand); 777 778 return 0; 779 } 780 781 /* 782 * ------------------------------------------------------------ 783 * Function : trm_Interrupt 784 * Purpose : Catch an interrupt from the adapter 785 * Process pending device interrupts. 786 * Inputs : void * - struct trm_softc * structure pointer 787 * ------------------------------------------------------------ 788 */ 789 int 790 trm_Interrupt(void *vsc) 791 { 792 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 793 struct trm_scsi_req_q *pSRB; 794 bus_space_handle_t ioh; 795 struct trm_softc *sc = (struct trm_softc *)vsc; 796 bus_space_tag_t iot; 797 u_int16_t phase; 798 u_int8_t scsi_status, scsi_intstatus; 799 int intflag; 800 801 intflag = splbio(); 802 803 if (sc == NULL) { 804 splx(intflag); 805 return 0; 806 } 807 808 ioh = sc->sc_iohandle; 809 iot = sc->sc_iotag; 810 811 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS); 812 if (!(scsi_status & SCSIINTERRUPT)) { 813 splx(intflag); 814 return 0; 815 } 816 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 817 818 #ifdef TRM_DEBUG0 819 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n", 820 sc->sc_device.dv_xname, scsi_status, scsi_intstatus); 821 #endif 822 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0) 823 trm_Disconnect(sc); 824 825 else if ((scsi_intstatus & INT_RESELECTED) != 0) 826 trm_Reselect(sc); 827 828 else if ((scsi_intstatus & INT_SCSIRESET) != 0) 829 trm_ScsiRstDetect(sc); 830 831 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) { 832 pSRB = sc->pActiveDCB->pActiveSRB; 833 /* 834 * software sequential machine 835 */ 836 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 837 /* 838 * 62037 or 62137 839 * call trm_SCSI_phase0[]... "phase entry" 840 * handle every phase before start transfer 841 */ 842 stateV = trm_SCSI_phase0[phase]; 843 stateV(sc, pSRB, &scsi_status); 844 /* 845 * if any exception occurred 846 * scsi_status will be modified to bus free phase 847 * new scsi_status transfer out from previous stateV 848 */ 849 /* 850 * phase:0,1,2,3,4,5,6,7 851 */ 852 pSRB->ScsiPhase = scsi_status & PHASEMASK; 853 phase = (u_int16_t) scsi_status & PHASEMASK; 854 /* 855 * call trm_SCSI_phase1[]... "phase entry" 856 * handle every phase do transfer 857 */ 858 stateV = trm_SCSI_phase1[phase]; 859 stateV(sc, pSRB, &scsi_status); 860 861 } else { 862 splx(intflag); 863 return 0; 864 } 865 866 splx(intflag); 867 return 1; 868 } 869 870 /* 871 * ------------------------------------------------------------ 872 * Function : trm_MsgOutPhase0 873 * Purpose : Check the state machine before sending a message out 874 * Inputs : struct trm_softc * - 875 * struct trm_scsi_req_q * - 876 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready 877 * ------------------------------------------------------------ 878 */ 879 void 880 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 881 { 882 switch (pSRB->SRBState) { 883 case TRM_UNEXPECT_RESEL: 884 case TRM_ABORT_SENT: 885 *pscsi_status = PH_BUS_FREE; /* initial phase */ 886 break; 887 888 default: 889 break; 890 } 891 } 892 893 /* 894 * ------------------------------------------------------------ 895 * Function : trm_MsgOutPhase1 896 * Purpose : Write the message out to the bus 897 * Inputs : struct trm_softc * - 898 * struct trm_scsi_req_q * - 899 * u_int8_t * - unused 900 * ------------------------------------------------------------ 901 */ 902 void 903 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 904 { 905 const bus_space_handle_t ioh = sc->sc_iohandle; 906 const bus_space_tag_t iot = sc->sc_iotag; 907 struct trm_dcb *pDCB = sc->pActiveDCB; 908 909 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 910 911 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) { 912 /* 913 * WIDE DATA TRANSFER REQUEST code (03h) 914 */ 915 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 916 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO; 917 918 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 919 sc->MsgBuf[1] = MSG_EXTENDED; 920 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN; 921 sc->MsgBuf[3] = MSG_EXT_WDTR; 922 923 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 924 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT; 925 else 926 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 927 928 sc->MsgCnt = 5; 929 930 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 931 932 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE; 933 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO; 934 935 sc->MsgCnt = 0; 936 937 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0) 938 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 939 940 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED; 941 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN; 942 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR; 943 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod; 944 945 if (pDCB->MaxNegoPeriod > 0) 946 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET; 947 else 948 sc->MsgBuf[sc->MsgCnt++] = 0; 949 } 950 951 if (sc->MsgCnt > 0) { 952 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt); 953 if (sc->MsgBuf[0] == MSG_ABORT) 954 pSRB->SRBState = TRM_ABORT_SENT; 955 sc->MsgCnt = 0; 956 } 957 /* 958 * it's important for atn stop 959 */ 960 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 961 /* 962 * Transfer information out 963 */ 964 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 965 } 966 967 /* 968 * ------------------------------------------------------------ 969 * Function : trm_CommandPhase1 970 * Purpose : Send commands to bus 971 * Inputs : 972 * ------------------------------------------------------------ 973 */ 974 void 975 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 976 { 977 const bus_space_handle_t ioh = sc->sc_iohandle; 978 const bus_space_tag_t iot = sc->sc_iotag; 979 980 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 981 982 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen); 983 984 pSRB->SRBState = TRM_COMMAND; 985 /* 986 * it's important for atn stop 987 */ 988 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 989 /* 990 * Transfer information out 991 */ 992 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 993 } 994 995 /* 996 * ------------------------------------------------------------ 997 * Function : trm_DataOutPhase0 998 * Purpose : Ready for Data Out, clear FIFO 999 * Inputs : u_int8_t * - SCSI status, used but not set 1000 * ------------------------------------------------------------ 1001 */ 1002 void 1003 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1004 { 1005 const bus_space_handle_t ioh = sc->sc_iohandle; 1006 const bus_space_tag_t iot = sc->sc_iotag; 1007 struct SGentry *pseg; 1008 struct trm_dcb *pDCB; 1009 u_int32_t dLeftCounter, TempSRBXferredLength; 1010 u_int16_t scsi_status; 1011 u_int8_t TempDMAstatus, SGIndexTemp; 1012 1013 dLeftCounter = 0; 1014 1015 pDCB = pSRB->pSRBDCB; 1016 scsi_status = *pscsi_status; 1017 1018 if (pSRB->SRBState != TRM_XFERPAD) { 1019 if ((scsi_status & PARITYERROR) != 0) 1020 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1021 if ((scsi_status & SCSIXFERDONE) == 0) { 1022 /* 1023 * when data transfer from DMA FIFO to SCSI FIFO 1024 * if there was some data left in SCSI FIFO 1025 */ 1026 dLeftCounter = (u_int32_t)(bus_space_read_1( 1027 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F); 1028 if (pDCB->SyncPeriod & WIDE_SYNC) { 1029 /* 1030 * if WIDE scsi SCSI FIFOCNT unit is word 1031 * so need to * 2 1032 */ 1033 dLeftCounter <<= 1; 1034 } 1035 } 1036 /* 1037 * calculate all the residue data that not yet transferred 1038 * SCSI transfer counter + left in SCSI FIFO data 1039 * 1040 * .....TRM_S1040_SCSI_COUNTER (24bits) 1041 * The counter always decrement by one for every SCSI byte 1042 * transfer. 1043 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits) 1044 * The counter is SCSI FIFO offset counter 1045 */ 1046 dLeftCounter += bus_space_read_4(iot, ioh, 1047 TRM_S1040_SCSI_COUNTER); 1048 if (dLeftCounter == 1) { 1049 dLeftCounter = 0; 1050 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1051 DO_CLRFIFO); 1052 } 1053 if (dLeftCounter == 0 || 1054 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1055 TempDMAstatus = bus_space_read_1(iot, 1056 ioh, TRM_S1040_DMA_STATUS); 1057 while ((TempDMAstatus & DMAXFERCOMP) == 0) { 1058 TempDMAstatus = bus_space_read_1(iot, 1059 ioh, TRM_S1040_DMA_STATUS); 1060 } 1061 pSRB->SRBTotalXferLength = 0; 1062 } else { 1063 /* 1064 * Update SG list 1065 */ 1066 /* 1067 * if transfer not yet complete 1068 * there were some data residue in SCSI FIFO or 1069 * SCSI transfer counter not empty 1070 */ 1071 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1072 /* 1073 * data that had transferred length 1074 */ 1075 TempSRBXferredLength = pSRB->SRBTotalXferLength 1076 - dLeftCounter; 1077 /* 1078 * next time to be transferred length 1079 */ 1080 pSRB->SRBTotalXferLength = dLeftCounter; 1081 /* 1082 * parsing from last time disconnect SRBSGIndex 1083 */ 1084 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1085 for (SGIndexTemp = pSRB->SRBSGIndex; 1086 SGIndexTemp < pSRB->SRBSGCount; 1087 SGIndexTemp++) { 1088 /* 1089 * find last time which SG transfer be 1090 * disconnect 1091 */ 1092 if (TempSRBXferredLength >= pseg->length) 1093 TempSRBXferredLength -= pseg->length; 1094 else { 1095 /* 1096 * update last time disconnected 1097 * SG list 1098 */ 1099 /* 1100 * residue data length 1101 */ 1102 pseg->length -= 1103 TempSRBXferredLength; 1104 /* 1105 * residue data pointer 1106 */ 1107 pseg->address += 1108 TempSRBXferredLength; 1109 pSRB->SRBSGIndex = SGIndexTemp; 1110 break; 1111 } 1112 pseg++; 1113 } 1114 } 1115 } 1116 } 1117 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 1118 } 1119 1120 /* 1121 * ------------------------------------------------------------ 1122 * Function : trm_DataOutPhase1 1123 * Purpose : Transfers data out, calls trm_DataIO_transfer 1124 * Inputs : 1125 * ------------------------------------------------------------ 1126 */ 1127 void 1128 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1129 { 1130 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT); 1131 } 1132 1133 /* 1134 * ------------------------------------------------------------ 1135 * Function : trm_DataInPhase0 1136 * Purpose : Prepare for reading data in from bus 1137 * Inputs : 1138 * ------------------------------------------------------------ 1139 */ 1140 void 1141 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1142 { 1143 const bus_space_handle_t ioh = sc->sc_iohandle; 1144 const bus_space_tag_t iot = sc->sc_iotag; 1145 struct SGentry *pseg; 1146 u_int32_t TempSRBXferredLength, dLeftCounter; 1147 u_int16_t scsi_status; 1148 u_int8_t SGIndexTemp; 1149 1150 dLeftCounter = 0; 1151 1152 scsi_status = *pscsi_status; 1153 if (pSRB->SRBState != TRM_XFERPAD) { 1154 if ((scsi_status & PARITYERROR) != 0) 1155 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1156 dLeftCounter += bus_space_read_4(iot, ioh, 1157 TRM_S1040_SCSI_COUNTER); 1158 if (dLeftCounter == 0 || 1159 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1160 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0) 1161 ; 1162 pSRB->SRBTotalXferLength = 0; 1163 } else { 1164 /* 1165 * phase changed 1166 * 1167 * parsing the case: 1168 * when a transfer not yet complete 1169 * but be disconnected by uper layer 1170 * if transfer not yet complete 1171 * there were some data residue in SCSI FIFO or 1172 * SCSI transfer counter not empty 1173 */ 1174 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1175 /* 1176 * data that had transferred length 1177 */ 1178 TempSRBXferredLength = pSRB->SRBTotalXferLength 1179 - dLeftCounter; 1180 /* 1181 * next time to be transferred length 1182 */ 1183 pSRB->SRBTotalXferLength = dLeftCounter; 1184 /* 1185 * parsing from last time disconnect SRBSGIndex 1186 */ 1187 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1188 for (SGIndexTemp = pSRB->SRBSGIndex; 1189 SGIndexTemp < pSRB->SRBSGCount; 1190 SGIndexTemp++) { 1191 /* 1192 * find last time which SG transfer be 1193 * disconnect 1194 */ 1195 if (TempSRBXferredLength >= 1196 pseg->length) { 1197 TempSRBXferredLength -= pseg->length; 1198 } else { 1199 /* 1200 * update last time disconnected 1201 * SG list 1202 * 1203 * residue data length 1204 */ 1205 pseg->length -= TempSRBXferredLength; 1206 /* 1207 * residue data pointer 1208 */ 1209 pseg->address += TempSRBXferredLength; 1210 pSRB->SRBSGIndex = SGIndexTemp; 1211 break; 1212 } 1213 pseg++; 1214 } 1215 } 1216 } 1217 } 1218 } 1219 1220 /* 1221 * ------------------------------------------------------------ 1222 * Function : trm_DataInPhase1 1223 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer 1224 * Inputs : 1225 * ------------------------------------------------------------ 1226 */ 1227 void 1228 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1229 { 1230 trm_DataIO_transfer(sc, pSRB, XFERDATAIN); 1231 } 1232 1233 /* 1234 * ------------------------------------------------------------ 1235 * Function : trm_DataIO_transfer 1236 * Purpose : 1237 * Inputs : 1238 * ------------------------------------------------------------ 1239 */ 1240 void 1241 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir) 1242 { 1243 const bus_space_handle_t ioh = sc->sc_iohandle; 1244 const bus_space_tag_t iot = sc->sc_iotag; 1245 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1246 u_int8_t bval; 1247 1248 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1249 if (pSRB->SRBTotalXferLength != 0) { 1250 /* 1251 * load what physical address of Scatter/Gather list 1252 * table want to be transfer 1253 */ 1254 pSRB->SRBState = TRM_DATA_XFER; 1255 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0); 1256 bus_space_write_4(iot, ioh, 1257 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr + 1258 ((u_int32_t)pSRB->SRBSGIndex << 3))); 1259 /* 1260 * load how many bytes in the Scatter/Gather list table 1261 */ 1262 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT, 1263 ((u_int32_t)(pSRB->SRBSGCount - 1264 pSRB->SRBSGIndex) << 3)); 1265 /* 1266 * load total transfer length (24bits, 1267 * pSRB->SRBTotalXferLength) max value 16Mbyte 1268 */ 1269 bus_space_write_4(iot, ioh, 1270 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength); 1271 /* 1272 * Start DMA transfer 1273 */ 1274 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir); 1275 /* bus_space_write_2(iot, ioh, 1276 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/ 1277 /* 1278 * Set the transfer bus and direction 1279 */ 1280 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN; 1281 } else { 1282 /* 1283 * xfer pad 1284 */ 1285 if (pSRB->SRBSGCount) 1286 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN; 1287 1288 if (pDCB->SyncPeriod & WIDE_SYNC) { 1289 bus_space_write_4(iot, ioh, 1290 TRM_S1040_SCSI_COUNTER, 2); 1291 } else { 1292 bus_space_write_4(iot, ioh, 1293 TRM_S1040_SCSI_COUNTER, 1); 1294 } 1295 1296 if (ioDir == XFERDATAOUT) { 1297 bus_space_write_2(iot, 1298 ioh, TRM_S1040_SCSI_FIFO, 0); 1299 } else { 1300 bus_space_read_2(iot, 1301 ioh, TRM_S1040_SCSI_FIFO); 1302 } 1303 pSRB->SRBState = TRM_XFERPAD; 1304 /* 1305 * Set the transfer bus and direction 1306 */ 1307 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN; 1308 } 1309 /* 1310 * it's important for atn stop 1311 */ 1312 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1313 /* 1314 * Tell the bus to do the transfer 1315 */ 1316 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval); 1317 } 1318 } 1319 1320 /* 1321 * ------------------------------------------------------------ 1322 * Function : trm_StatusPhase0 1323 * Purpose : Update Target Status with data from SCSI FIFO 1324 * Inputs : u_int8_t * - Set to PH_BUS_FREE 1325 * ------------------------------------------------------------ 1326 */ 1327 void 1328 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1329 { 1330 const bus_space_handle_t ioh = sc->sc_iohandle; 1331 const bus_space_tag_t iot = sc->sc_iotag; 1332 1333 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1334 1335 pSRB->SRBState = TRM_COMPLETED; 1336 /* 1337 * initial phase 1338 */ 1339 *pscsi_status = PH_BUS_FREE; 1340 /* 1341 * it's important for atn stop 1342 */ 1343 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1344 /* 1345 * Tell bus that the message was accepted 1346 */ 1347 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1348 } 1349 1350 /* 1351 * ------------------------------------------------------------ 1352 * Function : trm_StatusPhase1 1353 * Purpose : Clear FIFO of DMA and SCSI 1354 * Inputs : 1355 * ------------------------------------------------------------ 1356 */ 1357 void 1358 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1359 { 1360 const bus_space_handle_t ioh = sc->sc_iohandle; 1361 const bus_space_tag_t iot = sc->sc_iotag; 1362 1363 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) { 1364 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40) 1365 == 0) { 1366 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1367 DO_CLRFIFO); 1368 } 1369 if ((bus_space_read_2(iot, ioh, 1370 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1371 bus_space_write_1(iot, ioh, 1372 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1373 } 1374 } else { 1375 if ((bus_space_read_2(iot, ioh, 1376 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1377 bus_space_write_1(iot, ioh, 1378 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1379 } 1380 if ((bus_space_read_1(iot, ioh, 1381 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) { 1382 bus_space_write_2(iot, ioh, 1383 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1384 } 1385 } 1386 pSRB->SRBState = TRM_STATUS; 1387 /* 1388 * it's important for atn stop 1389 */ 1390 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1391 /* 1392 * Tell the bus that the command is complete 1393 */ 1394 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP); 1395 } 1396 1397 /* 1398 * ------------------------------------------------------------ 1399 * Function : trm_MsgInPhase0 1400 * Purpose : 1401 * Inputs : 1402 * 1403 * extended message codes: 1404 * code description 1405 * ---- ----------- 1406 * 02h Reserved 1407 * 00h MODIFY DATA POINTER 1408 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1409 * 03h WIDE DATA TRANSFER REQUEST 1410 * 04h - 7Fh Reserved 1411 * 80h - FFh Vendor specific 1412 * 1413 * ------------------------------------------------------------ 1414 */ 1415 void 1416 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1417 { 1418 const bus_space_handle_t ioh = sc->sc_iohandle; 1419 const bus_space_tag_t iot = sc->sc_iotag; 1420 struct trm_dcb *pDCB; 1421 u_int8_t message_in_code, bIndex, message_in_tag_id; 1422 1423 pDCB = sc->pActiveDCB; 1424 1425 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1426 1427 if (pSRB->SRBState != TRM_EXTEND_MSGIN) { 1428 switch (message_in_code) { 1429 case MSG_DISCONNECT: 1430 pSRB->SRBState = TRM_DISCONNECTED; 1431 break; 1432 1433 case MSG_EXTENDED: 1434 case MSG_SIMPLE_Q_TAG: 1435 case MSG_HEAD_OF_Q_TAG: 1436 case MSG_ORDERED_Q_TAG: 1437 pSRB->SRBState = TRM_EXTEND_MSGIN; 1438 /* 1439 * extended message (01h) 1440 */ 1441 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf)); 1442 sc->MsgBuf[0] = message_in_code; 1443 sc->MsgCnt = 1; 1444 /* 1445 * extended message length (n) 1446 */ 1447 break; 1448 1449 case MSG_MESSAGE_REJECT: 1450 /* 1451 * Reject message 1452 */ 1453 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) { 1454 /* 1455 * do wide nego reject 1456 */ 1457 pDCB = pSRB->pSRBDCB; 1458 1459 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO; 1460 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1461 1462 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 1463 /* 1464 * Set ATN, in case ATN was clear 1465 */ 1466 pSRB->SRBState = TRM_MSGOUT; 1467 bus_space_write_2(iot, ioh, 1468 TRM_S1040_SCSI_CONTROL, DO_SETATN); 1469 } else { 1470 /* 1471 * Clear ATN 1472 */ 1473 bus_space_write_2(iot, ioh, 1474 TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1475 } 1476 1477 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) { 1478 /* 1479 * do sync nego reject 1480 */ 1481 pDCB = pSRB->pSRBDCB; 1482 1483 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO; 1484 1485 pDCB->SyncPeriod = 0; 1486 pDCB->SyncOffset = 0; 1487 1488 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1489 goto re_prog; 1490 } 1491 break; 1492 1493 case MSG_IGN_WIDE_RESIDUE: 1494 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1495 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1496 break; 1497 1498 default: 1499 break; 1500 } 1501 1502 } else { 1503 1504 /* 1505 * We are collecting an extended message. Save the latest byte and then 1506 * check to see if the message is complete. If so, process it. 1507 */ 1508 sc->MsgBuf[sc->MsgCnt++] = message_in_code; 1509 #ifdef TRM_DEBUG0 1510 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 1511 sc->sc_device.dv_xname, 1512 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] ); 1513 #endif 1514 switch (sc->MsgBuf[0]) { 1515 case MSG_SIMPLE_Q_TAG: 1516 case MSG_HEAD_OF_Q_TAG: 1517 case MSG_ORDERED_Q_TAG: 1518 if (sc->MsgCnt == 2) { 1519 pSRB->SRBState = TRM_FREE; 1520 message_in_tag_id = sc->MsgBuf[1]; 1521 sc->MsgCnt = 0; 1522 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) { 1523 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id)) 1524 break; 1525 } 1526 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) { 1527 pDCB->pActiveSRB = pSRB; 1528 pSRB->SRBState = TRM_DATA_XFER; 1529 } else { 1530 pSRB = &sc->SRB[0]; 1531 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1532 pDCB->pActiveSRB = pSRB; 1533 trm_EnableMsgOut(sc, MSG_ABORT_TAG); 1534 } 1535 } 1536 break; 1537 1538 case MSG_EXTENDED: 1539 /* TODO XXXX: Correctly handling target initiated negotiations? */ 1540 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) { 1541 /* 1542 * ====================================== 1543 * WIDE DATA TRANSFER REQUEST 1544 * ====================================== 1545 * byte 0 : Extended message (01h) 1546 * byte 1 : Extended message length (02h) 1547 * byte 2 : WIDE DATA TRANSFER code (03h) 1548 * byte 3 : Transfer width exponent 1549 */ 1550 1551 pSRB->SRBState = TRM_FREE; 1552 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO); 1553 1554 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN) 1555 goto reject_offer; 1556 1557 switch (sc->MsgBuf[3]) { 1558 case MSG_EXT_WDTR_BUS_32_BIT: 1559 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 1560 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1561 else 1562 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT; 1563 break; 1564 1565 case MSG_EXT_WDTR_BUS_16_BIT: 1566 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) { 1567 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1568 break; 1569 } 1570 pDCB->SyncPeriod |= WIDE_SYNC; 1571 /* FALL THROUGH == ACCEPT OFFER */ 1572 1573 case MSG_EXT_WDTR_BUS_8_BIT: 1574 pSRB->SRBState = TRM_MSGOUT; 1575 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE); 1576 1577 if (pDCB->MaxNegoPeriod == 0) { 1578 pDCB->SyncPeriod = 0; 1579 pDCB->SyncOffset = 0; 1580 goto re_prog; 1581 } 1582 break; 1583 1584 default: 1585 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 1586 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1587 reject_offer: 1588 sc->MsgCnt = 1; 1589 sc->MsgBuf[0] = MSG_MESSAGE_REJECT; 1590 break; 1591 } 1592 1593 /* Echo accepted offer, or send revised offer */ 1594 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN); 1595 1596 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) { 1597 /* 1598 * ================================= 1599 * SYNCHRONOUS DATA TRANSFER REQUEST 1600 * ================================= 1601 * byte 0 : Extended message (01h) 1602 * byte 1 : Extended message length (03) 1603 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1604 * byte 3 : Transfer period factor 1605 * byte 4 : REQ/ACK offset 1606 */ 1607 1608 pSRB->SRBState = TRM_FREE; 1609 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO); 1610 1611 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN) 1612 goto reject_offer; 1613 1614 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) { 1615 /* 1616 * Asynchronous transfers 1617 */ 1618 pDCB->SyncPeriod = 0; 1619 pDCB->SyncOffset = 0; 1620 1621 } else { 1622 /* 1623 * Synchronous transfers 1624 */ 1625 /* 1626 * REQ/ACK offset 1627 */ 1628 pDCB->SyncOffset = sc->MsgBuf[4]; 1629 1630 for (bIndex = 0; bIndex < 7; bIndex++) 1631 if (sc->MsgBuf[3] <= trm_clock_period[bIndex]) 1632 break; 1633 1634 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 1635 } 1636 1637 re_prog: /* 1638 * program SCSI control register 1639 */ 1640 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1641 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1642 1643 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID)); 1644 } 1645 break; 1646 1647 default: 1648 break; 1649 } 1650 } 1651 1652 /* 1653 * initial phase 1654 */ 1655 *pscsi_status = PH_BUS_FREE; 1656 /* 1657 * it's important for atn stop 1658 */ 1659 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1660 /* 1661 * Tell bus that the message was accepted 1662 */ 1663 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1664 } 1665 1666 /* 1667 * ------------------------------------------------------------ 1668 * Function : trm_MsgInPhase1 1669 * Purpose : Clear the FIFO 1670 * Inputs : 1671 * ------------------------------------------------------------ 1672 */ 1673 void 1674 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1675 { 1676 const bus_space_handle_t ioh = sc->sc_iohandle; 1677 const bus_space_tag_t iot = sc->sc_iotag; 1678 1679 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1680 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1681 1682 /* 1683 * it's important for atn stop 1684 */ 1685 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1686 /* 1687 * SCSI command 1688 */ 1689 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN); 1690 } 1691 1692 /* 1693 * ------------------------------------------------------------ 1694 * Function : trm_Nop 1695 * Purpose : EMPTY 1696 * Inputs : 1697 * ------------------------------------------------------------ 1698 */ 1699 void 1700 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1701 { 1702 } 1703 1704 /* 1705 * ------------------------------------------------------------ 1706 * Function : trm_SetXferParams 1707 * Purpose : Set the Sync period, offset and mode for each device that has 1708 * the same target as the given one (struct trm_dcb *) 1709 * Inputs : 1710 * ------------------------------------------------------------ 1711 */ 1712 void 1713 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info) 1714 { 1715 struct trm_dcb *pDCBTemp; 1716 int lun, target; 1717 1718 /* 1719 * set all lun device's period, offset 1720 */ 1721 #ifdef TRM_DEBUG0 1722 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname); 1723 #endif 1724 1725 target = pDCB->target; 1726 for(lun = 0; lun < TRM_MAX_LUNS; lun++) { 1727 pDCBTemp = sc->pDCB[target][lun]; 1728 if (pDCBTemp != NULL) { 1729 pDCBTemp->DevMode = pDCB->DevMode; 1730 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod; 1731 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 1732 pDCBTemp->SyncOffset = pDCB->SyncOffset; 1733 pDCBTemp->DCBFlag = pDCB->DCBFlag; 1734 } 1735 } 1736 1737 if (print_info) 1738 trm_print_info(sc, pDCB); 1739 } 1740 1741 /* 1742 * ------------------------------------------------------------ 1743 * Function : trm_Disconnect 1744 * Purpose : 1745 * Inputs : 1746 * 1747 * ---SCSI bus phase 1748 * PH_DATA_OUT 0x00 Data out phase 1749 * PH_DATA_IN 0x01 Data in phase 1750 * PH_COMMAND 0x02 Command phase 1751 * PH_STATUS 0x03 Status phase 1752 * PH_BUS_FREE 0x04 Invalid phase used as bus free 1753 * PH_BUS_FREE 0x05 Invalid phase used as bus free 1754 * PH_MSG_OUT 0x06 Message out phase 1755 * PH_MSG_IN 0x07 Message in phase 1756 * ------------------------------------------------------------ 1757 */ 1758 void 1759 trm_Disconnect(struct trm_softc *sc) 1760 { 1761 const bus_space_handle_t ioh = sc->sc_iohandle; 1762 struct trm_scsi_req_q *pSRB, *pNextSRB; 1763 const bus_space_tag_t iot = sc->sc_iotag; 1764 struct trm_dcb *pDCB; 1765 int j; 1766 1767 #ifdef TRM_DEBUG0 1768 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname); 1769 #endif 1770 1771 pDCB = sc->pActiveDCB; 1772 if (pDCB == NULL) { 1773 /* TODO: Why use a loop? Why not use DELAY(400)? */ 1774 for(j = 400; j > 0; --j) 1775 DELAY(1); /* 1 msec */ 1776 bus_space_write_2(iot, ioh, 1777 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1778 return; 1779 } 1780 1781 pSRB = pDCB->pActiveSRB; 1782 sc->pActiveDCB = NULL; 1783 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1784 bus_space_write_2(iot, ioh, 1785 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1786 DELAY(100); 1787 1788 switch (pSRB->SRBState) { 1789 case TRM_UNEXPECT_RESEL: 1790 pSRB->SRBState = TRM_FREE; 1791 break; 1792 1793 case TRM_ABORT_SENT: 1794 pSRB = TAILQ_FIRST(&sc->goingSRB); 1795 while (pSRB != NULL) { 1796 /* 1797 * Need to save pNextSRB because trm_FinishSRB() puts 1798 * pSRB in freeSRB queue, and thus its links no longer 1799 * point to members of the goingSRB queue. This is why 1800 * TAILQ_FOREACH() will not work for this traversal. 1801 */ 1802 pNextSRB = TAILQ_NEXT(pSRB, link); 1803 if (pSRB->pSRBDCB == pDCB) { 1804 /* TODO XXXX: Is TIMED_OUT the best state to report? */ 1805 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 1806 trm_FinishSRB(sc, pSRB); 1807 } 1808 pSRB = pNextSRB; 1809 } 1810 break; 1811 1812 case TRM_START: 1813 case TRM_MSGOUT: 1814 /* 1815 * Selection time out 1816 */ 1817 /* If not polling just keep trying until xs->stimeout expires */ 1818 if ((pSRB->xs->flags & SCSI_POLL) == 0) { 1819 trm_RewaitSRB(sc, pSRB); 1820 } else { 1821 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT; 1822 goto disc1; 1823 } 1824 break; 1825 1826 case TRM_COMPLETED: 1827 disc1: 1828 /* 1829 * TRM_COMPLETED - remove id from mask of active tags 1830 */ 1831 pDCB->pActiveSRB = NULL; 1832 trm_FinishSRB(sc, pSRB); 1833 break; 1834 1835 default: 1836 break; 1837 } 1838 1839 trm_StartWaitingSRB(sc); 1840 } 1841 1842 /* 1843 * ------------------------------------------------------------ 1844 * Function : trm_Reselect 1845 * Purpose : 1846 * Inputs : 1847 * ------------------------------------------------------------ 1848 */ 1849 void 1850 trm_Reselect(struct trm_softc *sc) 1851 { 1852 const bus_space_handle_t ioh = sc->sc_iohandle; 1853 const bus_space_tag_t iot = sc->sc_iotag; 1854 struct trm_scsi_req_q *pSRB; 1855 struct trm_dcb *pDCB; 1856 u_int16_t RselTarLunId; 1857 u_int8_t target, lun; 1858 1859 #ifdef TRM_DEBUG0 1860 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname); 1861 #endif 1862 1863 pDCB = sc->pActiveDCB; 1864 if (pDCB != NULL) { 1865 /* 1866 * Arbitration lost but Reselection win 1867 */ 1868 pSRB = pDCB->pActiveSRB; 1869 trm_RewaitSRB(sc, pSRB); 1870 } 1871 1872 /* 1873 * Read Reselected Target Id and LUN 1874 */ 1875 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF; 1876 /* TODO XXXX: Make endian independent! */ 1877 target = RselTarLunId & 0xff; 1878 lun = (RselTarLunId >> 8) & 0xff; 1879 1880 #ifdef TRM_DEBUG0 1881 printf("%s: reselect - target = %d, lun = %d\n", 1882 sc->sc_device.dv_xname, target, lun); 1883 #endif 1884 1885 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS)) 1886 pDCB = sc->pDCB[target][lun]; 1887 else 1888 pDCB = NULL; 1889 1890 if (pDCB == NULL) 1891 printf("%s: reselect - target = %d, lun = %d not found\n", 1892 sc->sc_device.dv_xname, target, lun); 1893 1894 sc->pActiveDCB = pDCB; 1895 1896 /* TODO XXXX: This will crash if pDCB is ever NULL */ 1897 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) { 1898 pSRB = &sc->SRB[0]; 1899 pDCB->pActiveSRB = pSRB; 1900 } else { 1901 pSRB = pDCB->pActiveSRB; 1902 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) { 1903 /* 1904 * abort command 1905 */ 1906 pSRB = &sc->SRB[0]; 1907 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1908 pDCB->pActiveSRB = pSRB; 1909 trm_EnableMsgOut(sc, MSG_ABORT); 1910 } else 1911 pSRB->SRBState = TRM_DATA_XFER; 1912 } 1913 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1914 1915 /* 1916 * Program HA ID, target ID, period and offset 1917 */ 1918 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target); 1919 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 1920 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1921 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1922 1923 /* 1924 * it's important for atn stop 1925 */ 1926 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1927 DELAY(30); 1928 1929 /* 1930 * SCSI command 1931 * to rls the /ACK signal 1932 */ 1933 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1934 } 1935 1936 /* 1937 * ------------------------------------------------------------ 1938 * Function : trm_FinishSRB 1939 * Purpose : Complete execution of a SCSI command 1940 * Signal completion to the generic SCSI driver 1941 * Inputs : 1942 * ------------------------------------------------------------ 1943 */ 1944 void 1945 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 1946 { 1947 struct scsi_inquiry_data *ptr; 1948 struct scsi_sense_data *s1, *s2; 1949 struct scsi_xfer *xs = pSRB->xs; 1950 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1951 int target, lun; 1952 1953 #ifdef TRM_DEBUG0 1954 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n", 1955 sc->sc_device.dv_xname, sc, pSRB); 1956 #endif 1957 pDCB->DCBFlag &= ~TRM_QUEUE_FULL; 1958 1959 if (xs == NULL) { 1960 trm_ReleaseSRB(sc, pSRB); 1961 return; 1962 } 1963 1964 timeout_del(&xs->stimeout); 1965 1966 xs->status = pSRB->TargetStatus; 1967 1968 switch (xs->status) { 1969 case SCSI_INTERM_COND_MET: 1970 case SCSI_COND_MET: 1971 case SCSI_INTERM: 1972 case SCSI_OK: 1973 switch (pSRB->AdaptStatus) { 1974 case TRM_STATUS_GOOD: 1975 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) { 1976 #ifdef TRM_DEBUG0 1977 printf("%s: trm_FinishSRB. TRM_PARITY_ERROR\n", 1978 sc->sc_device.dv_xname); 1979 #endif 1980 xs->error = XS_DRIVER_STUFFUP; 1981 1982 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) { 1983 xs->error = XS_TIMEOUT; 1984 1985 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) { 1986 s1 = &pSRB->scsisense; 1987 s2 = &xs->sense; 1988 1989 *s2 = *s1; 1990 1991 xs->status = SCSI_CHECK; 1992 xs->error = XS_SENSE; 1993 1994 } else 1995 xs->error = XS_NOERROR; 1996 break; 1997 1998 case TRM_OVER_UNDER_RUN: 1999 #ifdef TRM_DEBUG0 2000 printf("%s: trm_FinishSRB. TRM_OVER_UNDER_RUN\n", 2001 sc->sc_device.dv_xname); 2002 #endif 2003 xs->error = XS_DRIVER_STUFFUP; 2004 break; 2005 2006 default: 2007 #ifdef TRM_DEBUG0 2008 printf("%s: trm_FinishSRB. AdaptStatus Error = 0x%02x\n", 2009 sc->sc_device.dv_xname, pSRB->AdaptStatus); 2010 #endif 2011 xs->error = XS_DRIVER_STUFFUP; 2012 break; 2013 } 2014 break; 2015 2016 case SCSI_TERMINATED: 2017 case SCSI_ACA_ACTIVE: 2018 case SCSI_CHECK: 2019 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) 2020 xs->error = XS_DRIVER_STUFFUP; 2021 else { 2022 trm_RequestSense(sc, pSRB); 2023 return; 2024 } 2025 break; 2026 2027 case SCSI_QUEUE_FULL: 2028 /* this says no more until someone completes */ 2029 pDCB->DCBFlag |= TRM_QUEUE_FULL; 2030 trm_RewaitSRB(sc, pSRB); 2031 return; 2032 2033 case SCSI_RESV_CONFLICT: 2034 case SCSI_BUSY: 2035 xs->error = XS_BUSY; 2036 break; 2037 2038 case TRM_SCSI_UNEXP_BUS_FREE: 2039 xs->status = SCSI_OK; 2040 xs->error = XS_DRIVER_STUFFUP; 2041 break; 2042 2043 case TRM_SCSI_BUS_RST_DETECTED: 2044 xs->status = SCSI_OK; 2045 xs->error = XS_RESET; 2046 break; 2047 2048 case TRM_SCSI_SELECT_TIMEOUT: 2049 xs->status = SCSI_OK; 2050 xs->error = XS_SELTIMEOUT; 2051 break; 2052 2053 default: 2054 xs->error = XS_DRIVER_STUFFUP; 2055 break; 2056 } 2057 2058 target = xs->sc_link->target; 2059 lun = xs->sc_link->lun; 2060 2061 if ((xs->flags & SCSI_POLL) != 0) { 2062 2063 if (xs->cmd->opcode == INQUIRY) { 2064 2065 ptr = (struct scsi_inquiry_data *) xs->data; 2066 2067 if ((xs->error != XS_NOERROR) || 2068 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) { 2069 #ifdef TRM_DEBUG0 2070 printf("%s: trm_FinishSRB NO Device:target= %d,lun= %d\n", 2071 sc->sc_device.dv_xname, target, lun); 2072 #endif 2073 free(pDCB, M_DEVBUF); 2074 sc->pDCB[target][lun] = NULL; 2075 pDCB = NULL; 2076 2077 } else 2078 pDCB->sc_link = xs->sc_link; 2079 } 2080 } 2081 2082 trm_ReleaseSRB(sc, pSRB); 2083 2084 xs->flags |= ITSDONE; 2085 2086 /* 2087 * Notify cmd done 2088 */ 2089 #ifdef TRM_DEBUG0 2090 if ((xs->error != 0) || (xs->status != 0) || ((xs->flags & SCSI_POLL) != 0)) 2091 printf("%s: trm_FinishSRB. %d/%d xs->cmd->opcode = 0x%02x, xs->error = %d, xs->status = %d\n", 2092 sc->sc_device.dv_xname, target, lun, xs->cmd->opcode, xs->error, xs->status); 2093 #endif 2094 2095 scsi_done(xs); 2096 } 2097 2098 /* 2099 * ------------------------------------------------------------ 2100 * Function : trm_ReleaseSRB 2101 * Purpose : 2102 * Inputs : 2103 * ------------------------------------------------------------ 2104 */ 2105 void 2106 trm_ReleaseSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2107 { 2108 struct scsi_xfer *xs = pSRB->xs; 2109 int intflag; 2110 2111 intflag = splbio(); 2112 2113 if (pSRB->TagNumber != TRM_NO_TAG) { 2114 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber); 2115 pSRB->TagNumber = TRM_NO_TAG; 2116 } 2117 2118 if (xs != NULL) { 2119 timeout_del(&xs->stimeout); 2120 2121 if (xs->datalen != 0) { 2122 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 2123 0, pSRB->dmamapxfer->dm_mapsize, 2124 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 2125 BUS_DMASYNC_POSTWRITE); 2126 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer); 2127 } 2128 } 2129 2130 /* SRB may have started & finished, or be waiting and timed out */ 2131 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 2132 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 2133 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 2134 } 2135 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 2136 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 2137 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 2138 } 2139 2140 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX)); 2141 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2142 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense)); 2143 2144 pSRB->SRBTotalXferLength = 0; 2145 pSRB->SRBSGCount = 0; 2146 pSRB->SRBSGIndex = 0; 2147 pSRB->SRBFlag = 0; 2148 2149 pSRB->SRBState = TRM_FREE; 2150 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2151 pSRB->TargetStatus = SCSI_OK; 2152 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 2153 2154 pSRB->xs = NULL; 2155 pSRB->pSRBDCB = NULL; 2156 2157 if (pSRB != &sc->SRB[0]) 2158 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2159 2160 splx(intflag); 2161 } 2162 2163 /* 2164 * ------------------------------------------------------------ 2165 * Function : trm_GoingSRB_Done 2166 * Purpose : 2167 * Inputs : 2168 * ------------------------------------------------------------ 2169 */ 2170 void 2171 trm_GoingSRB_Done(struct trm_softc *sc) 2172 { 2173 struct trm_scsi_req_q *pSRB; 2174 2175 /* ASSUME we are inside a splbio()/splx() pair */ 2176 2177 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 2178 /* TODO XXXX: Is TIMED_OUT the best status? */ 2179 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 2180 trm_FinishSRB(sc, pSRB); 2181 } 2182 } 2183 2184 /* 2185 * ------------------------------------------------------------ 2186 * Function : trm_ResetSCSIBus 2187 * Purpose : Reset the SCSI bus 2188 * Inputs : struct trm_softc * - 2189 * ------------------------------------------------------------ 2190 */ 2191 void 2192 trm_ResetSCSIBus(struct trm_softc *sc) 2193 { 2194 const bus_space_handle_t ioh = sc->sc_iohandle; 2195 const bus_space_tag_t iot = sc->sc_iotag; 2196 int intflag; 2197 2198 intflag = splbio(); 2199 2200 sc->sc_Flag |= RESET_DEV; 2201 2202 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI); 2203 while ((bus_space_read_2(iot, ioh, 2204 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0); 2205 2206 splx(intflag); 2207 } 2208 2209 /* 2210 * ------------------------------------------------------------ 2211 * Function : trm_ScsiRstDetect 2212 * Purpose : 2213 * Inputs : 2214 * ------------------------------------------------------------ 2215 */ 2216 void 2217 trm_ScsiRstDetect(struct trm_softc *sc) 2218 { 2219 const bus_space_handle_t ioh = sc->sc_iohandle; 2220 const bus_space_tag_t iot = sc->sc_iotag; 2221 int wlval; 2222 2223 #ifdef TRM_DEBUG0 2224 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname); 2225 #endif 2226 2227 wlval = 1000; 2228 /* 2229 * delay 1 sec 2230 */ 2231 while (--wlval != 0) 2232 DELAY(1000); 2233 2234 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 2235 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 2236 2237 if ((sc->sc_Flag & RESET_DEV) != 0) 2238 sc->sc_Flag |= RESET_DONE; 2239 else { 2240 sc->sc_Flag |= RESET_DETECT; 2241 trm_ResetAllDevParam(sc); 2242 trm_RecoverSRB(sc); 2243 sc->pActiveDCB = NULL; 2244 sc->sc_Flag = 0; 2245 trm_StartWaitingSRB(sc); 2246 } 2247 } 2248 2249 /* 2250 * ------------------------------------------------------------ 2251 * Function : trm_RequestSense 2252 * Purpose : 2253 * Inputs : 2254 * ------------------------------------------------------------ 2255 */ 2256 void 2257 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2258 { 2259 pSRB->SRBFlag |= TRM_AUTO_REQSENSE; 2260 2261 /* 2262 * Status of initiator/target 2263 */ 2264 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2265 pSRB->TargetStatus = SCSI_OK; 2266 /* 2267 * Status of initiator/target 2268 */ 2269 2270 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr; 2271 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data); 2272 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data); 2273 pSRB->SRBSGCount = 1; 2274 pSRB->SRBSGIndex = 0; 2275 2276 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2277 2278 pSRB->CmdBlock[0] = REQUEST_SENSE; 2279 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5; 2280 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data); 2281 2282 pSRB->ScsiCmdLen = 6; 2283 2284 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0)) 2285 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout); 2286 2287 if (trm_StartSRB(sc, pSRB) != 0) 2288 trm_RewaitSRB(sc, pSRB); 2289 } 2290 2291 /* 2292 * ------------------------------------------------------------ 2293 * Function : trm_EnableMsgOut 2294 * Purpose : set up MsgBuf to send out a single byte message 2295 * Inputs : 2296 * ------------------------------------------------------------ 2297 */ 2298 void 2299 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg) 2300 { 2301 sc->MsgBuf[0] = msg; 2302 sc->MsgCnt = 1; 2303 2304 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN); 2305 } 2306 2307 /* 2308 * ------------------------------------------------------------ 2309 * Function : trm_linkSRB 2310 * Purpose : 2311 * Inputs : 2312 * ------------------------------------------------------------ 2313 */ 2314 void 2315 trm_linkSRB(struct trm_softc *sc) 2316 { 2317 struct trm_scsi_req_q *pSRB; 2318 int i, intflag; 2319 2320 intflag = splbio(); 2321 2322 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2323 pSRB = &sc->SRB[i]; 2324 2325 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr 2326 + i * sizeof(struct trm_scsi_req_q); 2327 2328 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2329 + i * sizeof(struct trm_scsi_req_q) 2330 + offsetof(struct trm_scsi_req_q, SegmentX); 2331 2332 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2333 + i * sizeof(struct trm_scsi_req_q) 2334 + offsetof(struct trm_scsi_req_q, scsisense); 2335 2336 /* 2337 * map all SRB space 2338 */ 2339 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE, 2340 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0, 2341 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2342 &pSRB->dmamapxfer) != 0) { 2343 printf("%s: unable to create DMA transfer map\n", 2344 sc->sc_device.dv_xname); 2345 splx(intflag); 2346 return; 2347 } 2348 2349 if (i > 0) 2350 /* We use sc->SRB[0] directly, so *don't* link it */ 2351 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2352 #ifdef TRM_DEBUG0 2353 printf("pSRB = %p ", pSRB); 2354 #endif 2355 } 2356 #ifdef TRM_DEBUG0 2357 printf("\n "); 2358 #endif 2359 splx(intflag); 2360 } 2361 2362 /* 2363 * ------------------------------------------------------------ 2364 * Function : trm_minphys 2365 * Purpose : limited by the number of segments in the dma segment list 2366 * Inputs : *buf 2367 * ------------------------------------------------------------ 2368 */ 2369 void 2370 trm_minphys(struct buf *bp, struct scsi_link *sl) 2371 { 2372 if (bp->b_bcount > (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG) { 2373 bp->b_bcount = (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG; 2374 } 2375 minphys(bp); 2376 } 2377 2378 /* 2379 * ------------------------------------------------------------ 2380 * Function : trm_initACB 2381 * Purpose : initialize the internal structures for a given SCSI host 2382 * Inputs : 2383 * ------------------------------------------------------------ 2384 */ 2385 void 2386 trm_initACB(struct trm_softc *sc, int unit) 2387 { 2388 const bus_space_handle_t ioh = sc->sc_iohandle; 2389 const bus_space_tag_t iot = sc->sc_iotag; 2390 struct trm_adapter_nvram *pEEpromBuf; 2391 struct trm_dcb *pDCB; 2392 int target, lun; 2393 2394 pEEpromBuf = &trm_eepromBuf[unit]; 2395 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2396 2397 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0) 2398 sc->sc_config |= HCC_WIDE_CARD; 2399 2400 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0) 2401 sc->sc_config |= HCC_SCSI_RESET; 2402 2403 TAILQ_INIT(&sc->freeSRB); 2404 TAILQ_INIT(&sc->waitingSRB); 2405 TAILQ_INIT(&sc->goingSRB); 2406 2407 sc->pActiveDCB = NULL; 2408 sc->sc_AdapterUnit = unit; 2409 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId; 2410 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2411 sc->sc_Flag = 0; 2412 2413 /* 2414 * put all SRB's (except [0]) onto the freeSRB list 2415 */ 2416 trm_linkSRB(sc); 2417 2418 /* 2419 * allocate DCB array 2420 */ 2421 for (target = 0; target < TRM_MAX_TARGETS; target++) { 2422 if (target == sc->sc_AdaptSCSIID) 2423 continue; 2424 2425 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2426 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), 2427 M_DEVBUF, M_NOWAIT | M_ZERO); 2428 sc->pDCB[target][lun] = pDCB; 2429 2430 if (pDCB == NULL) 2431 continue; 2432 2433 pDCB->target = target; 2434 pDCB->lun = lun; 2435 pDCB->pActiveSRB = NULL; 2436 } 2437 } 2438 2439 sc->sc_adapter.scsi_cmd = trm_scsi_cmd; 2440 sc->sc_adapter.scsi_minphys = trm_minphys; 2441 2442 sc->sc_link.adapter_softc = sc; 2443 sc->sc_link.adapter_target = sc->sc_AdaptSCSIID; 2444 sc->sc_link.openings = 30; /* So TagMask (32 bit integer) always has space */ 2445 sc->sc_link.device = &trm_device; 2446 sc->sc_link.adapter = &sc->sc_adapter; 2447 sc->sc_link.adapter_buswidth = ((sc->sc_config & HCC_WIDE_CARD) == 0) ? 8:16; 2448 2449 trm_reset(sc); 2450 } 2451 2452 /* 2453 * ------------------------------------------------------------ 2454 * Function : trm_write_all 2455 * Description : write pEEpromBuf 128 bytes to seeprom 2456 * Input : iot, ioh - chip's base address 2457 * Output : none 2458 * ------------------------------------------------------------ 2459 */ 2460 void 2461 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2462 bus_space_handle_t ioh) 2463 { 2464 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2465 u_int8_t bAddr; 2466 2467 /* 2468 * Enable SEEPROM 2469 */ 2470 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2471 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2472 /* 2473 * Write enable 2474 */ 2475 trm_write_cmd(iot, ioh, 0x04, 0xFF); 2476 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2477 trm_wait_30us(iot, ioh); 2478 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2479 trm_set_data(iot, ioh, bAddr, *bpEeprom); 2480 /* 2481 * Write disable 2482 */ 2483 trm_write_cmd(iot, ioh, 0x04, 0x00); 2484 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2485 trm_wait_30us(iot, ioh); 2486 /* 2487 * Disable SEEPROM 2488 */ 2489 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2490 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2491 } 2492 2493 /* 2494 * ------------------------------------------------------------ 2495 * Function : trm_set_data 2496 * Description : write one byte to seeprom 2497 * Input : iot, ioh - chip's base address 2498 * bAddr - address of SEEPROM 2499 * bData - data of SEEPROM 2500 * Output : none 2501 * ------------------------------------------------------------ 2502 */ 2503 void 2504 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr, 2505 u_int8_t bData) 2506 { 2507 u_int8_t bSendData; 2508 int i; 2509 2510 /* 2511 * Send write command & address 2512 */ 2513 trm_write_cmd(iot, ioh, 0x05, bAddr); 2514 /* 2515 * Write data 2516 */ 2517 for (i = 0; i < 8; i++, bData <<= 1) { 2518 bSendData = NVR_SELECT; 2519 if ((bData & 0x80) != 0) { /* Start from bit 7 */ 2520 bSendData |= NVR_BITOUT; 2521 } 2522 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2523 trm_wait_30us(iot, ioh); 2524 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2525 (bSendData | NVR_CLOCK)); 2526 trm_wait_30us(iot, ioh); 2527 } 2528 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2529 trm_wait_30us(iot, ioh); 2530 /* 2531 * Disable chip select 2532 */ 2533 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2534 trm_wait_30us(iot, ioh); 2535 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2536 trm_wait_30us(iot, ioh); 2537 /* 2538 * Wait for write ready 2539 */ 2540 for (;;) { 2541 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2542 (NVR_SELECT | NVR_CLOCK)); 2543 trm_wait_30us(iot, ioh); 2544 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2545 trm_wait_30us(iot, ioh); 2546 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN) 2547 break; 2548 } 2549 /* 2550 * Disable chip select 2551 */ 2552 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2553 } 2554 2555 /* 2556 * ------------------------------------------------------------ 2557 * Function : trm_read_all 2558 * Description : read seeprom 128 bytes to pEEpromBuf 2559 * Input : pEEpromBuf, iot, ioh - chip's base address 2560 * Output : none 2561 * ------------------------------------------------------------ 2562 */ 2563 void 2564 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2565 bus_space_handle_t ioh) 2566 { 2567 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2568 u_int8_t bAddr; 2569 2570 /* 2571 * Enable SEEPROM 2572 */ 2573 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2574 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2575 2576 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2577 *bpEeprom = trm_get_data(iot, ioh, bAddr); 2578 2579 /* 2580 * Disable SEEPROM 2581 */ 2582 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2583 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2584 } 2585 2586 /* 2587 * ------------------------------------------------------------ 2588 * Function : trm_get_data 2589 * Description : read one byte from seeprom 2590 * Input : iot, ioh - chip's base address 2591 * bAddr - address of SEEPROM 2592 * Output : bData - data of SEEPROM 2593 * ------------------------------------------------------------ 2594 */ 2595 u_int8_t 2596 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr) 2597 { 2598 u_int8_t bReadData, bData; 2599 int i; 2600 2601 bData = 0; 2602 2603 /* 2604 * Send read command & address 2605 */ 2606 trm_write_cmd(iot, ioh, 0x06, bAddr); 2607 2608 for (i = 0; i < 8; i++) { 2609 /* 2610 * Read data 2611 */ 2612 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2613 (NVR_SELECT | NVR_CLOCK)); 2614 trm_wait_30us(iot, ioh); 2615 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2616 /* 2617 * Get data bit while falling edge 2618 */ 2619 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM); 2620 bData <<= 1; 2621 if ((bReadData & NVR_BITIN) != 0) 2622 bData |= 1; 2623 trm_wait_30us(iot, ioh); 2624 } 2625 /* 2626 * Disable chip select 2627 */ 2628 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2629 2630 return bData; 2631 } 2632 2633 /* 2634 * ------------------------------------------------------------ 2635 * Function : trm_wait_30us 2636 * Description : wait 30 us 2637 * Input : iot, ioh - chip's base address 2638 * Output : none 2639 * ------------------------------------------------------------ 2640 */ 2641 void 2642 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh) 2643 { 2644 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5); 2645 2646 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT) 2647 == 0); 2648 } 2649 2650 /* 2651 * ------------------------------------------------------------ 2652 * Function : trm_write_cmd 2653 * Description : write SB and Op Code into seeprom 2654 * Input : iot, ioh - chip's base address 2655 * bCmd - SB + Op Code 2656 * bAddr - address of SEEPROM 2657 * Output : none 2658 * ------------------------------------------------------------ 2659 */ 2660 void 2661 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd, 2662 u_int8_t bAddr) 2663 { 2664 u_int8_t bSendData; 2665 int i; 2666 2667 for (i = 0; i < 3; i++, bCmd <<= 1) { 2668 /* 2669 * Program SB + OP code 2670 */ 2671 bSendData = NVR_SELECT; 2672 if (bCmd & 0x04) /* Start from bit 2 */ 2673 bSendData |= NVR_BITOUT; 2674 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2675 trm_wait_30us(iot, ioh); 2676 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2677 (bSendData | NVR_CLOCK)); 2678 trm_wait_30us(iot, ioh); 2679 } 2680 2681 for (i = 0; i < 7; i++, bAddr <<= 1) { 2682 /* 2683 * Program address 2684 */ 2685 bSendData = NVR_SELECT; 2686 if (bAddr & 0x40) { /* Start from bit 6 */ 2687 bSendData |= NVR_BITOUT; 2688 } 2689 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2690 trm_wait_30us(iot, ioh); 2691 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2692 (bSendData | NVR_CLOCK)); 2693 trm_wait_30us(iot, ioh); 2694 } 2695 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2696 trm_wait_30us(iot, ioh); 2697 } 2698 2699 /* 2700 * ------------------------------------------------------------ 2701 * Function : trm_check_eeprom 2702 * Description : read eeprom 128 bytes to pEEpromBuf and check 2703 * checksum. If it is wrong, updated with default value. 2704 * Input : eeprom, iot, ioh - chip's base address 2705 * Output : none 2706 * ------------------------------------------------------------ 2707 */ 2708 void 2709 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2710 bus_space_handle_t ioh) 2711 { 2712 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget; 2713 u_int32_t dAddr; 2714 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf; 2715 u_int16_t wAddr, wCheckSum; 2716 2717 #ifdef TRM_DEBUG0 2718 printf("\ntrm_check_eeprom\n"); 2719 #endif 2720 trm_read_all(pEEpromBuf, iot, ioh); 2721 wCheckSum = 0; 2722 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++) 2723 wCheckSum += *wpEeprom; 2724 2725 if (wCheckSum != 0x1234) { 2726 #ifdef TRM_DEBUG0 2727 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n"); 2728 #endif 2729 /* 2730 * Checksum error, load default 2731 */ 2732 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2733 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2734 >> 8); 2735 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) 2736 PCI_PRODUCT_TEKRAM2_DC3X5U; 2737 pEEpromBuf->NvramSubSysID[1] = (u_int8_t) 2738 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2739 pEEpromBuf->NvramSubClass = 0; 2740 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2741 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2742 >> 8); 2743 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) 2744 PCI_PRODUCT_TEKRAM2_DC3X5U; 2745 pEEpromBuf->NvramDeviceID[1] = (u_int8_t) 2746 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2747 pEEpromBuf->NvramReserved = 0; 2748 2749 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++) 2750 /* 2751 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 2752 */ 2753 *dpEeprom = 0x00000077; 2754 2755 /* 2756 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId 2757 */ 2758 *dpEeprom++ = 0x04000F07; 2759 2760 /* 2761 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 2762 */ 2763 *dpEeprom++ = 0x00000015; 2764 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 2765 *dpEeprom = 0; 2766 2767 pEEpromBuf->NvramCheckSum = 0; 2768 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++) 2769 wCheckSum += *wpEeprom; 2770 2771 *wpEeprom = 0x1234 - wCheckSum; 2772 trm_write_all(pEEpromBuf, iot, ioh); 2773 } 2774 } 2775 2776 /* 2777 * ------------------------------------------------------------ 2778 * Function : trm_initAdapter 2779 * Purpose : initialize the SCSI chip ctrl registers 2780 * Inputs : psh - pointer to this host adapter's structure 2781 * ------------------------------------------------------------ 2782 */ 2783 void 2784 trm_initAdapter(struct trm_softc *sc) 2785 { 2786 const bus_space_handle_t ioh = sc->sc_iohandle; 2787 const bus_space_tag_t iot = sc->sc_iotag; 2788 u_int16_t wval; 2789 u_int8_t bval; 2790 2791 /* 2792 * program configuration 0 2793 */ 2794 if ((sc->sc_config & HCC_PARITY) != 0) { 2795 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 2796 } else { 2797 bval = PHASELATCH | INITIATOR | BLOCKRST; 2798 } 2799 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval); 2800 /* 2801 * program configuration 1 2802 */ 2803 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13); 2804 /* 2805 * 250ms selection timeout 2806 */ 2807 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT); 2808 /* 2809 * Mask all the interrupt 2810 */ 2811 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 2812 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 2813 /* 2814 * Reset SCSI module 2815 */ 2816 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE); 2817 /* 2818 * program Host ID 2819 */ 2820 bval = sc->sc_AdaptSCSIID; 2821 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval); 2822 /* 2823 * set ansynchronous transfer 2824 */ 2825 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0); 2826 /* 2827 * Turn LED control off 2828 */ 2829 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F; 2830 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval); 2831 /* 2832 * DMA config 2833 */ 2834 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE; 2835 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval); 2836 /* 2837 * Clear pending interrupt status 2838 */ 2839 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 2840 /* 2841 * Enable SCSI interrupts 2842 */ 2843 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 2844 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 2845 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 2846 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 2847 } 2848 2849 /* 2850 * ------------------------------------------------------------ 2851 * Function : trm_init 2852 * Purpose : initialize the internal structures for a given SCSI host 2853 * Inputs : host - pointer to this host adapter's structure 2854 * Preconditions : when this function is called, the chip_type field of 2855 * the ACB structure MUST have been set. 2856 * ------------------------------------------------------------ 2857 */ 2858 int 2859 trm_init(struct trm_softc *sc, int unit) 2860 { 2861 const bus_space_handle_t ioh = sc->sc_iohandle; 2862 const bus_space_tag_t iot = sc->sc_iotag; 2863 bus_dma_segment_t seg; 2864 int error, rseg, all_srbs_size; 2865 2866 /* 2867 * EEPROM CHECKSUM 2868 */ 2869 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh); 2870 2871 /* 2872 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 2873 */ 2874 /* 2875 * allocate the space for all SCSI control blocks (SRB) for DMA memory. 2876 */ 2877 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q); 2878 2879 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg, 2880 1, &rseg, BUS_DMA_NOWAIT); 2881 if (error != 0) { 2882 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n", 2883 sc->sc_device.dv_xname, error); 2884 /*errx(error, "%s: unable to allocate SCSI request blocks", 2885 sc->sc_device.dv_xname);*/ 2886 return -1; 2887 } 2888 2889 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size, 2890 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 2891 if (error != 0) { 2892 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n", 2893 sc->sc_device.dv_xname, error); 2894 /*errx(error, "unable to map SCSI request blocks");*/ 2895 return -1; 2896 } 2897 2898 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1, 2899 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control); 2900 if (error != 0) { 2901 printf("%s: unable to create SRB DMA maps, error = %d\n", 2902 sc->sc_device.dv_xname, error); 2903 /*errx(error, "unable to create SRB DMA maps");*/ 2904 return -1; 2905 } 2906 2907 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control, 2908 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT); 2909 if (error != 0) { 2910 printf("%s: unable to load SRB DMA maps, error = %d\n", 2911 sc->sc_device.dv_xname, error); 2912 /*errx(error, "unable to load SRB DMA maps");*/ 2913 return -1; 2914 } 2915 #ifdef TRM_DEBUG0 2916 printf("\n\n%s: all_srbs_size=%x\n", 2917 sc->sc_device.dv_xname, all_srbs_size); 2918 #endif 2919 bzero(sc->SRB, all_srbs_size); 2920 trm_initACB(sc, unit); 2921 trm_initAdapter(sc); 2922 2923 return 0; 2924 } 2925 2926 /* ------------------------------------------------------------ 2927 * Function : trm_print_info 2928 * Purpose : Print the DCB negotiation information 2929 * Inputs : 2930 * ------------------------------------------------------------ 2931 */ 2932 void 2933 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB) 2934 { 2935 int syncXfer, index; 2936 2937 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC); 2938 2939 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target); 2940 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0) 2941 printf("16 bit "); 2942 else 2943 printf("8 bit "); 2944 2945 if (pDCB->SyncOffset == 0) 2946 printf("Asynchronous "); 2947 else { 2948 syncXfer = 100000 / (trm_clock_period[index] * 4); 2949 printf("%d.%01d MHz, Offset %d ", 2950 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset); 2951 } 2952 printf("data transfers "); 2953 2954 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) 2955 printf("with Tag Queuing"); 2956 2957 printf("\n"); 2958 } 2959