1 /* $OpenBSD: trm.c,v 1.39 2020/02/15 18:02:00 krw Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.c 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * HISTORY: 13 * 14 * REV# DATE NAME DESCRIPTION 15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x 16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8 17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting 18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic 19 * ------------------------------------------------------------ 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 3. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * ------------------------------------------------------------ 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/buf.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <scsi/scsi_message.h> 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/ic/trm.h> 61 62 /* #define TRM_DEBUG0 */ 63 64 void trm_initSRB(struct trm_scsi_req_q *); 65 66 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 67 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 68 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 69 70 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 71 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 72 73 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t); 74 75 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t); 76 77 void trm_scsi_cmd(struct scsi_xfer *); 78 79 void *trm_srb_alloc(void *); 80 81 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 82 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 83 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 84 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 85 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 86 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 87 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 88 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 89 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 90 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 91 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 92 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 93 94 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int); 95 96 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t); 97 98 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *); 99 void trm_srb_reinit (struct trm_softc *, struct trm_scsi_req_q *); 100 void trm_srb_free (void *, void *); 101 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *); 102 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *); 103 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *); 104 105 void trm_initAdapter (struct trm_softc *); 106 void trm_Disconnect (struct trm_softc *); 107 void trm_Reselect (struct trm_softc *); 108 void trm_GoingSRB_Done (struct trm_softc *, struct trm_dcb *); 109 void trm_ScsiRstDetect (struct trm_softc *); 110 void trm_ResetSCSIBus (struct trm_softc *); 111 void trm_reset (struct trm_softc *); 112 void trm_StartWaitingSRB (struct trm_softc *); 113 void trm_ResetAllDevParam(struct trm_softc *); 114 void trm_RecoverSRB (struct trm_softc *); 115 void trm_linkSRB (struct trm_softc *); 116 117 void trm_initACB(struct trm_softc *, int); 118 119 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t); 120 121 void trm_EnableMsgOut(struct trm_softc *, u_int8_t); 122 123 void trm_timeout(void *); 124 125 void trm_print_info(struct trm_softc *, struct trm_dcb *); 126 127 /* 128 * Define structures 129 */ 130 struct cfdriver trm_cd = { 131 NULL, "trm", DV_DULL 132 }; 133 134 struct scsi_adapter trm_switch = { 135 trm_scsi_cmd, NULL, NULL, NULL, NULL 136 }; 137 138 /* 139 * ------------------------------------------------------------ 140 * 141 * stateV = (void *) trm_SCSI_phase0[phase] 142 * 143 * ------------------------------------------------------------ 144 */ 145 static void *trm_SCSI_phase0[8] = { 146 trm_DataOutPhase0, /* phase:0 */ 147 trm_DataInPhase0, /* phase:1 */ 148 trm_Nop, /* phase:2 */ 149 trm_StatusPhase0, /* phase:3 */ 150 trm_Nop, /* phase:4 */ 151 trm_Nop, /* phase:5 */ 152 trm_MsgOutPhase0, /* phase:6 */ 153 trm_MsgInPhase0, /* phase:7 */ 154 }; 155 156 /* 157 * ------------------------------------------------------------ 158 * 159 * stateV = (void *) trm_SCSI_phase1[phase] 160 * 161 * ------------------------------------------------------------ 162 */ 163 static void *trm_SCSI_phase1[8] = { 164 trm_DataOutPhase1, /* phase:0 */ 165 trm_DataInPhase1, /* phase:1 */ 166 trm_CommandPhase1, /* phase:2 */ 167 trm_StatusPhase1, /* phase:3 */ 168 trm_Nop, /* phase:4 */ 169 trm_Nop, /* phase:5 */ 170 trm_MsgOutPhase1, /* phase:6 */ 171 trm_MsgInPhase1, /* phase:7 */ 172 }; 173 174 175 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 176 /* 177 *Fast20: 000 50ns, 20.0 Mbytes/s 178 * 001 75ns, 13.3 Mbytes/s 179 * 010 100ns, 10.0 Mbytes/s 180 * 011 125ns, 8.0 Mbytes/s 181 * 100 150ns, 6.6 Mbytes/s 182 * 101 175ns, 5.7 Mbytes/s 183 * 110 200ns, 5.0 Mbytes/s 184 * 111 250ns, 4.0 Mbytes/s 185 * 186 *Fast40: 000 25ns, 40.0 Mbytes/s 187 * 001 50ns, 20.0 Mbytes/s 188 * 010 75ns, 13.3 Mbytes/s 189 * 011 100ns, 10.0 Mbytes/s 190 * 100 125ns, 8.0 Mbytes/s 191 * 101 150ns, 6.6 Mbytes/s 192 * 110 175ns, 5.7 Mbytes/s 193 * 111 200ns, 5.0 Mbytes/s 194 */ 195 196 /* 197 * real period: 198 */ 199 u_int8_t trm_clock_period[8] = { 200 /* nanosecond divided by 4 */ 201 12, /* 48 ns 20 MB/sec */ 202 18, /* 72 ns 13.3 MB/sec */ 203 25, /* 100 ns 10.0 MB/sec */ 204 31, /* 124 ns 8.0 MB/sec */ 205 37, /* 148 ns 6.6 MB/sec */ 206 43, /* 172 ns 5.7 MB/sec */ 207 50, /* 200 ns 5.0 MB/sec */ 208 62 /* 248 ns 4.0 MB/sec */ 209 }; 210 211 /* 212 * ------------------------------------------------------------ 213 * Function : trm_srb_alloc 214 * Purpose : Get the first free SRB 215 * Inputs : 216 * Return : NULL or a free SCSI Request block 217 * ------------------------------------------------------------ 218 */ 219 void * 220 trm_srb_alloc(void *xsc) 221 { 222 struct trm_softc *sc = xsc; 223 struct trm_scsi_req_q *pSRB; 224 225 mtx_enter(&sc->sc_srb_mtx); 226 pSRB = TAILQ_FIRST(&sc->freeSRB); 227 if (pSRB != NULL) 228 TAILQ_REMOVE(&sc->freeSRB, pSRB, link); 229 mtx_leave(&sc->sc_srb_mtx); 230 231 #ifdef TRM_DEBUG0 232 printf("%s: trm_srb_alloc. pSRB = %p, next pSRB = %p\n", 233 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB)); 234 #endif 235 236 return pSRB; 237 } 238 239 /* 240 * ------------------------------------------------------------ 241 * Function : trm_RewaitSRB 242 * Purpose : Q back to pending Q 243 * Inputs : struct trm_dcb * - 244 * struct trm_scsi_req_q * - 245 * ------------------------------------------------------------ 246 */ 247 void 248 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 249 { 250 int intflag; 251 252 intflag = splbio(); 253 254 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 255 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 256 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 257 } 258 259 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 260 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 261 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 262 } 263 264 pSRB->SRBState = TRM_READY; 265 pSRB->TargetStatus = SCSI_OK; 266 pSRB->AdaptStatus = TRM_STATUS_GOOD; 267 268 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 269 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 270 271 splx(intflag); 272 } 273 274 /* 275 * ------------------------------------------------------------ 276 * Function : trm_StartWaitingSRB 277 * Purpose : If there is no active DCB then run robin through 278 * the DCB's to find the next waiting SRB 279 * and move it to the going list. 280 * Inputs : struct trm_softc * - 281 * ------------------------------------------------------------ 282 */ 283 void 284 trm_StartWaitingSRB(struct trm_softc *sc) 285 { 286 struct trm_scsi_req_q *pSRB, *next; 287 int intflag; 288 289 intflag = splbio(); 290 291 if ((sc->pActiveDCB != NULL) || 292 (TAILQ_EMPTY(&sc->waitingSRB)) || 293 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0) 294 goto out; 295 296 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) { 297 next = TAILQ_NEXT(pSRB, link); 298 if (trm_StartSRB(sc, pSRB) == 0) { 299 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 300 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 301 pSRB->SRBFlag |= TRM_ON_GOING_SRB; 302 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link); 303 break; 304 } 305 } 306 307 out: 308 splx(intflag); 309 } 310 311 /* 312 * ------------------------------------------------------------ 313 * Function : trm_scsi_cmd 314 * Purpose : enqueues a SCSI command 315 * Inputs : 316 * Call By : GENERIC SCSI driver 317 * ------------------------------------------------------------ 318 */ 319 void 320 trm_scsi_cmd(struct scsi_xfer *xs) 321 { 322 struct trm_scsi_req_q *pSRB; 323 bus_space_handle_t ioh; 324 struct trm_softc *sc; 325 bus_space_tag_t iot; 326 struct trm_dcb *pDCB; 327 u_int8_t target, lun; 328 int i, error, intflag, timeout, xferflags; 329 330 target = xs->sc_link->target; 331 lun = xs->sc_link->lun; 332 333 sc = (struct trm_softc *)xs->sc_link->adapter_softc; 334 ioh = sc->sc_iohandle; 335 iot = sc->sc_iotag; 336 337 #ifdef TRM_DEBUG0 338 if ((xs->flags & SCSI_POLL) != 0) { 339 sc_print_addr(xs->sc_link); 340 printf("trm_scsi_cmd. sc = %p, xs = %p, opcode = 0x%02x\n", 341 sc, xs, lun, xs->cmd->opcode); 342 } 343 #endif 344 345 if (target >= TRM_MAX_TARGETS) { 346 sc_print_addr(xs->sc_link); 347 printf("target >= %d\n", TRM_MAX_TARGETS); 348 xs->error = XS_DRIVER_STUFFUP; 349 scsi_done(xs); 350 return; 351 } 352 if (lun >= TRM_MAX_LUNS) { 353 sc_print_addr(xs->sc_link); 354 printf("lun >= %d\n", TRM_MAX_LUNS); 355 xs->error = XS_DRIVER_STUFFUP; 356 scsi_done(xs); 357 return; 358 } 359 360 pDCB = sc->pDCB[target][lun]; 361 if (pDCB == NULL) { 362 /* Removed as a result of INQUIRY proving no device present */ 363 xs->error = XS_DRIVER_STUFFUP; 364 scsi_done(xs); 365 return; 366 } 367 368 xferflags = xs->flags; 369 if (xferflags & SCSI_RESET) { 370 #ifdef TRM_DEBUG0 371 sc_print_addr(xs->sc_link); 372 printf("trm_reset via SCSI_RESET\n"); 373 #endif 374 trm_reset(sc); 375 xs->error = XS_NOERROR; 376 scsi_done(xs); 377 return; 378 } 379 380 pSRB = xs->io; 381 trm_srb_reinit(sc, pSRB); 382 383 xs->error = XS_NOERROR; 384 xs->status = SCSI_OK; 385 xs->resid = 0; 386 387 intflag = splbio(); 388 389 /* 390 * BuildSRB(pSRB,pDCB); 391 */ 392 if (xs->datalen != 0) { 393 #ifdef TRM_DEBUG0 394 sc_print_addr(xs->sc_link); 395 printf("xs->datalen=%x\n", (u_int32_t)xs->datalen); 396 sc_print_addr(xs->sc_link); 397 printf("sc->sc_dmatag=0x%x\n", (u_int32_t)sc->sc_dmatag); 398 sc_print_addr(xs->sc_link); 399 printf("pSRB->dmamapxfer=0x%x\n", (u_int32_t)pSRB->dmamapxfer); 400 sc_print_addr(xs->sc_link); 401 printf("xs->data=0x%x\n", (u_int32_t)xs->data); 402 #endif 403 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer, 404 xs->data, xs->datalen, NULL, 405 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : 406 BUS_DMA_WAITOK)) != 0) { 407 sc_print_addr(xs->sc_link); 408 printf("DMA transfer map unable to load, error = %d\n", 409 error); 410 xs->error = XS_DRIVER_STUFFUP; 411 splx(intflag); 412 scsi_done(xs); 413 return; 414 } 415 416 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 417 0, pSRB->dmamapxfer->dm_mapsize, 418 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 419 420 /* 421 * Set up the scatter gather list 422 */ 423 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) { 424 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr; 425 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len; 426 } 427 pSRB->SRBTotalXferLength = xs->datalen; 428 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs; 429 } 430 431 pSRB->pSRBDCB = pDCB; 432 pSRB->xs = xs; 433 pSRB->ScsiCmdLen = xs->cmdlen; 434 435 memcpy(pSRB->CmdBlock, xs->cmd, xs->cmdlen); 436 437 timeout_set(&xs->stimeout, trm_timeout, pSRB); 438 439 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 440 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link); 441 trm_StartWaitingSRB(sc); 442 443 if ((xferflags & SCSI_POLL) == 0) { 444 timeout_add_msec(&xs->stimeout, xs->timeout); 445 splx(intflag); 446 return; 447 } 448 449 splx(intflag); 450 for (timeout = xs->timeout; timeout > 0; timeout--) { 451 intflag = splbio(); 452 trm_Interrupt(sc); 453 splx(intflag); 454 if (ISSET(xs->flags, ITSDONE)) 455 break; 456 DELAY(1000); 457 } 458 459 if (!ISSET(xs->flags, ITSDONE) && timeout == 0) 460 trm_timeout(pSRB); 461 462 scsi_done(xs); 463 } 464 465 /* 466 * ------------------------------------------------------------ 467 * Function : trm_ResetAllDevParam 468 * Purpose : 469 * Inputs : struct trm_softc * 470 * ------------------------------------------------------------ 471 */ 472 void 473 trm_ResetAllDevParam(struct trm_softc *sc) 474 { 475 struct trm_adapter_nvram *pEEpromBuf; 476 int target, quirks; 477 478 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 479 480 for (target = 0; target < TRM_MAX_TARGETS; target++) { 481 if (target == sc->sc_AdaptSCSIID || sc->pDCB[target][0] == NULL) 482 continue; 483 484 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0) 485 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS; 486 else if (sc->pDCB[target][0]->sc_link != NULL) 487 quirks = sc->pDCB[target][0]->sc_link->quirks; 488 489 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks); 490 } 491 } 492 493 /* 494 * ------------------------------------------------------------ 495 * Function : trm_ResetDevParam 496 * Purpose : 497 * Inputs : 498 * ------------------------------------------------------------ 499 */ 500 void 501 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks) 502 { 503 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 504 u_int8_t PeriodIndex; 505 const int target = pDCB->target; 506 507 pDCB->DCBFlag &= TRM_QUIRKS_VALID; 508 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE); 509 510 pDCB->SyncPeriod = 0; 511 pDCB->SyncOffset = 0; 512 pDCB->MaxNegoPeriod = 0; 513 514 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0; 515 516 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0)); 517 518 if (((quirks & SDEV_NOWIDE) == 0) && 519 (pDCB->DevMode & TRM_WIDE) && 520 ((sc->sc_config & HCC_WIDE_CARD) != 0)) 521 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT; 522 523 if (((quirks & SDEV_NOSYNC) == 0) && 524 ((pDCB->DevMode & TRM_SYNC) != 0)) { 525 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07; 526 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex]; 527 } 528 529 if (((quirks & SDEV_NOTAGS) == 0) && 530 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) && 531 ((pDCB->DevMode & TRM_DISCONNECT) != 0)) 532 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */ 533 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING; 534 535 trm_SetXferParams(sc, pDCB, 0); 536 } 537 538 /* 539 * ------------------------------------------------------------ 540 * Function : trm_RecoverSRB 541 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs 542 * Inputs : struct trm_softc * - 543 * ------------------------------------------------------------ 544 */ 545 void 546 trm_RecoverSRB(struct trm_softc *sc) 547 { 548 struct trm_scsi_req_q *pSRB; 549 550 /* ASSUME we are inside splbio()/splx() */ 551 552 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 553 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 554 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 555 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 556 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 557 } 558 } 559 560 /* 561 * ------------------------------------------------------------ 562 * Function : trm_reset 563 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip). 564 * Inputs : 565 * ------------------------------------------------------------ 566 */ 567 void 568 trm_reset (struct trm_softc *sc) 569 { 570 const bus_space_handle_t ioh = sc->sc_iohandle; 571 const bus_space_tag_t iot = sc->sc_iotag; 572 int i, intflag; 573 574 intflag = splbio(); 575 576 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 577 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 578 579 trm_ResetSCSIBus(sc); 580 for (i = 0; i < 500; i++) 581 DELAY(1000); 582 583 /* 584 * Enable all SCSI interrupts except EN_SCAM 585 */ 586 bus_space_write_1(iot, ioh, 587 TRM_S1040_SCSI_INTEN, 588 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 589 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 590 /* 591 * Enable DMA interrupt 592 */ 593 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 594 /* 595 * Clear DMA FIFO 596 */ 597 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO); 598 /* 599 * Clear SCSI FIFO 600 */ 601 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 602 603 trm_ResetAllDevParam(sc); 604 trm_GoingSRB_Done(sc, NULL); 605 sc->pActiveDCB = NULL; 606 607 /* 608 * RESET_DETECT, RESET_DONE, RESET_DEV 609 */ 610 sc->sc_Flag = 0; 611 trm_StartWaitingSRB(sc); 612 613 splx(intflag); 614 } 615 616 /* 617 * ------------------------------------------------------------ 618 * Function : trm_timeout 619 * Purpose : Prints a timeout message and aborts the timed out SCSI request 620 * Inputs : void * - A struct trm_scsi_req_q * structure pointer 621 * ------------------------------------------------------------ 622 */ 623 void 624 trm_timeout(void *arg1) 625 { 626 struct trm_scsi_req_q *pSRB; 627 struct scsi_xfer *xs; 628 struct trm_softc *sc; 629 630 pSRB = (struct trm_scsi_req_q *)arg1; 631 xs = pSRB->xs; 632 633 if (xs != NULL) { 634 sc = xs->sc_link->adapter_softc; 635 sc_print_addr(xs->sc_link); 636 printf("SCSI OpCode 0x%02x ", xs->cmd->opcode); 637 if (pSRB->SRBFlag & TRM_AUTO_REQSENSE) 638 printf("REQUEST SENSE "); 639 printf("timed out\n"); 640 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 641 trm_FinishSRB(sc, pSRB); 642 #ifdef TRM_DEBUG0 643 sc_print_addr(xs->sc_link); 644 printf("trm_reset via trm_timeout()\n"); 645 #endif 646 trm_reset(sc); 647 trm_StartWaitingSRB(sc); 648 } 649 } 650 651 /* 652 * ------------------------------------------------------------ 653 * Function : trm_StartSRB 654 * Purpose : Send the commands in the SRB to the device 655 * Inputs : struct trm_softc * - 656 * struct trm_scsi_req_q * - 657 * Return : 0 - SCSI processor is unoccupied 658 * 1 - SCSI processor is occupied with an SRB 659 * ------------------------------------------------------------ 660 */ 661 int 662 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 663 { 664 const bus_space_handle_t ioh = sc->sc_iohandle; 665 const bus_space_tag_t iot = sc->sc_iotag; 666 struct trm_dcb *pDCB = pSRB->pSRBDCB; 667 u_int32_t tag_mask; 668 u_int8_t tag_id, scsicommand; 669 670 #ifdef TRM_DEBUG0 671 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n", 672 sc->sc_device.dv_xname, sc, pDCB, pSRB); 673 #endif 674 /* 675 * If the queue is full or the SCSI processor has a pending interrupt 676 * then try again later. 677 */ 678 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh, 679 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT)) 680 return (1); 681 682 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 683 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target); 684 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 685 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 686 687 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) && 688 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) { 689 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID; 690 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks); 691 } 692 693 /* 694 * Flush FIFO 695 */ 696 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 697 698 sc->MsgCnt = 1; 699 sc->MsgBuf[0] = pDCB->IdentifyMsg; 700 if (((pSRB->xs->flags & SCSI_POLL) != 0) || 701 (pSRB->CmdBlock[0] == INQUIRY) || 702 (pSRB->CmdBlock[0] == REQUEST_SENSE)) 703 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG; 704 705 scsicommand = SCMD_SEL_ATN; 706 707 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) { 708 scsicommand = SCMD_SEL_ATNSTOP; 709 pSRB->SRBState = TRM_MSGOUT; 710 711 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) { 712 pDCB->DCBFlag |= TRM_QUEUE_FULL; 713 714 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) { 715 if (pSRB->TagNumber == TRM_NO_TAG) { 716 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1) 717 if ((tag_mask & pDCB->TagMask) == 0) { 718 pDCB->TagMask |= tag_mask; 719 pSRB->TagNumber = tag_id; 720 break; 721 } 722 723 if (tag_id >= 32) { 724 pDCB->DCBFlag |= TRM_QUEUE_FULL; 725 sc->MsgCnt = 0; 726 return 1; 727 } 728 } 729 730 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */ 731 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG; 732 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber; 733 734 scsicommand = SCMD_SEL_ATN3; 735 } 736 737 pSRB->SRBState = TRM_START; 738 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 739 sc->pActiveDCB = pDCB; 740 pDCB->pActiveSRB = pSRB; 741 742 if (sc->MsgCnt > 0) { 743 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]); 744 if (sc->MsgCnt > 1) { 745 DELAY(30); 746 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1); 747 } 748 sc->MsgCnt = 0; 749 } 750 751 /* 752 * it's important for atn stop 753 */ 754 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT); 755 /* 756 * SCSI command 757 */ 758 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand); 759 760 return 0; 761 } 762 763 /* 764 * ------------------------------------------------------------ 765 * Function : trm_Interrupt 766 * Purpose : Catch an interrupt from the adapter 767 * Process pending device interrupts. 768 * Inputs : void * - struct trm_softc * structure pointer 769 * ------------------------------------------------------------ 770 */ 771 int 772 trm_Interrupt(void *vsc) 773 { 774 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 775 struct trm_scsi_req_q *pSRB; 776 bus_space_handle_t ioh; 777 struct trm_softc *sc = (struct trm_softc *)vsc; 778 bus_space_tag_t iot; 779 u_int16_t phase; 780 u_int8_t scsi_status, scsi_intstatus; 781 782 if (sc == NULL) 783 return 0; 784 785 ioh = sc->sc_iohandle; 786 iot = sc->sc_iotag; 787 788 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS); 789 if (!(scsi_status & SCSIINTERRUPT)) 790 return 0; 791 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 792 793 #ifdef TRM_DEBUG0 794 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n", 795 sc->sc_device.dv_xname, scsi_status, scsi_intstatus); 796 #endif 797 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0) 798 trm_Disconnect(sc); 799 800 else if ((scsi_intstatus & INT_RESELECTED) != 0) 801 trm_Reselect(sc); 802 803 else if ((scsi_intstatus & INT_SCSIRESET) != 0) 804 trm_ScsiRstDetect(sc); 805 806 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) { 807 pSRB = sc->pActiveDCB->pActiveSRB; 808 /* 809 * software sequential machine 810 */ 811 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 812 /* 813 * 62037 or 62137 814 * call trm_SCSI_phase0[]... "phase entry" 815 * handle every phase before start transfer 816 */ 817 stateV = trm_SCSI_phase0[phase]; 818 stateV(sc, pSRB, &scsi_status); 819 /* 820 * if any exception occurred 821 * scsi_status will be modified to bus free phase 822 * new scsi_status transfer out from previous stateV 823 */ 824 /* 825 * phase:0,1,2,3,4,5,6,7 826 */ 827 pSRB->ScsiPhase = scsi_status & PHASEMASK; 828 phase = (u_int16_t) scsi_status & PHASEMASK; 829 /* 830 * call trm_SCSI_phase1[]... "phase entry" 831 * handle every phase do transfer 832 */ 833 stateV = trm_SCSI_phase1[phase]; 834 stateV(sc, pSRB, &scsi_status); 835 836 } else { 837 return 0; 838 } 839 840 return 1; 841 } 842 843 /* 844 * ------------------------------------------------------------ 845 * Function : trm_MsgOutPhase0 846 * Purpose : Check the state machine before sending a message out 847 * Inputs : struct trm_softc * - 848 * struct trm_scsi_req_q * - 849 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready 850 * ------------------------------------------------------------ 851 */ 852 void 853 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 854 { 855 switch (pSRB->SRBState) { 856 case TRM_UNEXPECT_RESEL: 857 case TRM_ABORT_SENT: 858 *pscsi_status = PH_BUS_FREE; /* initial phase */ 859 break; 860 861 default: 862 break; 863 } 864 } 865 866 /* 867 * ------------------------------------------------------------ 868 * Function : trm_MsgOutPhase1 869 * Purpose : Write the message out to the bus 870 * Inputs : struct trm_softc * - 871 * struct trm_scsi_req_q * - 872 * u_int8_t * - unused 873 * ------------------------------------------------------------ 874 */ 875 void 876 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 877 { 878 const bus_space_handle_t ioh = sc->sc_iohandle; 879 const bus_space_tag_t iot = sc->sc_iotag; 880 struct trm_dcb *pDCB = sc->pActiveDCB; 881 882 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 883 884 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) { 885 /* 886 * WIDE DATA TRANSFER REQUEST code (03h) 887 */ 888 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 889 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO; 890 891 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 892 sc->MsgBuf[1] = MSG_EXTENDED; 893 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN; 894 sc->MsgBuf[3] = MSG_EXT_WDTR; 895 896 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 897 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT; 898 else 899 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 900 901 sc->MsgCnt = 5; 902 903 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 904 905 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE; 906 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO; 907 908 sc->MsgCnt = 0; 909 910 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0) 911 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 912 913 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED; 914 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN; 915 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR; 916 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod; 917 918 if (pDCB->MaxNegoPeriod > 0) 919 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET; 920 else 921 sc->MsgBuf[sc->MsgCnt++] = 0; 922 } 923 924 if (sc->MsgCnt > 0) { 925 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt); 926 if (sc->MsgBuf[0] == MSG_ABORT) 927 pSRB->SRBState = TRM_ABORT_SENT; 928 sc->MsgCnt = 0; 929 } 930 /* 931 * it's important for atn stop 932 */ 933 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 934 /* 935 * Transfer information out 936 */ 937 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 938 } 939 940 /* 941 * ------------------------------------------------------------ 942 * Function : trm_CommandPhase1 943 * Purpose : Send commands to bus 944 * Inputs : 945 * ------------------------------------------------------------ 946 */ 947 void 948 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 949 { 950 const bus_space_handle_t ioh = sc->sc_iohandle; 951 const bus_space_tag_t iot = sc->sc_iotag; 952 953 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 954 955 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen); 956 957 pSRB->SRBState = TRM_COMMAND; 958 /* 959 * it's important for atn stop 960 */ 961 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 962 /* 963 * Transfer information out 964 */ 965 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 966 } 967 968 /* 969 * ------------------------------------------------------------ 970 * Function : trm_DataOutPhase0 971 * Purpose : Ready for Data Out, clear FIFO 972 * Inputs : u_int8_t * - SCSI status, used but not set 973 * ------------------------------------------------------------ 974 */ 975 void 976 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 977 { 978 const bus_space_handle_t ioh = sc->sc_iohandle; 979 const bus_space_tag_t iot = sc->sc_iotag; 980 struct SGentry *pseg; 981 struct trm_dcb *pDCB; 982 u_int32_t dLeftCounter, TempSRBXferredLength; 983 u_int16_t scsi_status; 984 u_int8_t TempDMAstatus, SGIndexTemp; 985 986 dLeftCounter = 0; 987 988 pDCB = pSRB->pSRBDCB; 989 scsi_status = *pscsi_status; 990 991 if (pSRB->SRBState != TRM_XFERPAD) { 992 if ((scsi_status & PARITYERROR) != 0) 993 pSRB->SRBFlag |= TRM_PARITY_ERROR; 994 if ((scsi_status & SCSIXFERDONE) == 0) { 995 /* 996 * when data transfer from DMA FIFO to SCSI FIFO 997 * if there was some data left in SCSI FIFO 998 */ 999 dLeftCounter = (u_int32_t)(bus_space_read_1( 1000 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F); 1001 if (pDCB->SyncPeriod & WIDE_SYNC) { 1002 /* 1003 * if WIDE scsi SCSI FIFOCNT unit is word 1004 * so need to * 2 1005 */ 1006 dLeftCounter <<= 1; 1007 } 1008 } 1009 /* 1010 * calculate all the residue data that not yet transferred 1011 * SCSI transfer counter + left in SCSI FIFO data 1012 * 1013 * .....TRM_S1040_SCSI_COUNTER (24bits) 1014 * The counter always decrement by one for every SCSI byte 1015 * transfer. 1016 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits) 1017 * The counter is SCSI FIFO offset counter 1018 */ 1019 dLeftCounter += bus_space_read_4(iot, ioh, 1020 TRM_S1040_SCSI_COUNTER); 1021 if (dLeftCounter == 1) { 1022 dLeftCounter = 0; 1023 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1024 DO_CLRFIFO); 1025 } 1026 if (dLeftCounter == 0 || 1027 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1028 TempDMAstatus = bus_space_read_1(iot, 1029 ioh, TRM_S1040_DMA_STATUS); 1030 while ((TempDMAstatus & DMAXFERCOMP) == 0) { 1031 TempDMAstatus = bus_space_read_1(iot, 1032 ioh, TRM_S1040_DMA_STATUS); 1033 } 1034 pSRB->SRBTotalXferLength = 0; 1035 } else { 1036 /* 1037 * Update SG list 1038 */ 1039 /* 1040 * if transfer not yet complete 1041 * there were some data residue in SCSI FIFO or 1042 * SCSI transfer counter not empty 1043 */ 1044 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1045 /* 1046 * data that had transferred length 1047 */ 1048 TempSRBXferredLength = pSRB->SRBTotalXferLength 1049 - dLeftCounter; 1050 /* 1051 * next time to be transferred length 1052 */ 1053 pSRB->SRBTotalXferLength = dLeftCounter; 1054 /* 1055 * parsing from last time disconnect SRBSGIndex 1056 */ 1057 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1058 for (SGIndexTemp = pSRB->SRBSGIndex; 1059 SGIndexTemp < pSRB->SRBSGCount; 1060 SGIndexTemp++) { 1061 /* 1062 * find last time which SG transfer be 1063 * disconnect 1064 */ 1065 if (TempSRBXferredLength >= pseg->length) 1066 TempSRBXferredLength -= pseg->length; 1067 else { 1068 /* 1069 * update last time disconnected 1070 * SG list 1071 */ 1072 /* 1073 * residue data length 1074 */ 1075 pseg->length -= 1076 TempSRBXferredLength; 1077 /* 1078 * residue data pointer 1079 */ 1080 pseg->address += 1081 TempSRBXferredLength; 1082 pSRB->SRBSGIndex = SGIndexTemp; 1083 break; 1084 } 1085 pseg++; 1086 } 1087 } 1088 } 1089 } 1090 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 1091 } 1092 1093 /* 1094 * ------------------------------------------------------------ 1095 * Function : trm_DataOutPhase1 1096 * Purpose : Transfers data out, calls trm_DataIO_transfer 1097 * Inputs : 1098 * ------------------------------------------------------------ 1099 */ 1100 void 1101 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1102 { 1103 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT); 1104 } 1105 1106 /* 1107 * ------------------------------------------------------------ 1108 * Function : trm_DataInPhase0 1109 * Purpose : Prepare for reading data in from bus 1110 * Inputs : 1111 * ------------------------------------------------------------ 1112 */ 1113 void 1114 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1115 { 1116 const bus_space_handle_t ioh = sc->sc_iohandle; 1117 const bus_space_tag_t iot = sc->sc_iotag; 1118 struct SGentry *pseg; 1119 u_int32_t TempSRBXferredLength, dLeftCounter; 1120 u_int16_t scsi_status; 1121 u_int8_t SGIndexTemp; 1122 1123 dLeftCounter = 0; 1124 1125 scsi_status = *pscsi_status; 1126 if (pSRB->SRBState != TRM_XFERPAD) { 1127 if ((scsi_status & PARITYERROR) != 0) 1128 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1129 dLeftCounter += bus_space_read_4(iot, ioh, 1130 TRM_S1040_SCSI_COUNTER); 1131 if (dLeftCounter == 0 || 1132 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1133 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0) 1134 ; 1135 pSRB->SRBTotalXferLength = 0; 1136 } else { 1137 /* 1138 * phase changed 1139 * 1140 * parsing the case: 1141 * when a transfer not yet complete 1142 * but be disconnected by uper layer 1143 * if transfer not yet complete 1144 * there were some data residue in SCSI FIFO or 1145 * SCSI transfer counter not empty 1146 */ 1147 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1148 /* 1149 * data that had transferred length 1150 */ 1151 TempSRBXferredLength = pSRB->SRBTotalXferLength 1152 - dLeftCounter; 1153 /* 1154 * next time to be transferred length 1155 */ 1156 pSRB->SRBTotalXferLength = dLeftCounter; 1157 /* 1158 * parsing from last time disconnect SRBSGIndex 1159 */ 1160 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1161 for (SGIndexTemp = pSRB->SRBSGIndex; 1162 SGIndexTemp < pSRB->SRBSGCount; 1163 SGIndexTemp++) { 1164 /* 1165 * find last time which SG transfer be 1166 * disconnect 1167 */ 1168 if (TempSRBXferredLength >= 1169 pseg->length) { 1170 TempSRBXferredLength -= pseg->length; 1171 } else { 1172 /* 1173 * update last time disconnected 1174 * SG list 1175 * 1176 * residue data length 1177 */ 1178 pseg->length -= TempSRBXferredLength; 1179 /* 1180 * residue data pointer 1181 */ 1182 pseg->address += TempSRBXferredLength; 1183 pSRB->SRBSGIndex = SGIndexTemp; 1184 break; 1185 } 1186 pseg++; 1187 } 1188 } 1189 } 1190 } 1191 } 1192 1193 /* 1194 * ------------------------------------------------------------ 1195 * Function : trm_DataInPhase1 1196 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer 1197 * Inputs : 1198 * ------------------------------------------------------------ 1199 */ 1200 void 1201 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1202 { 1203 trm_DataIO_transfer(sc, pSRB, XFERDATAIN); 1204 } 1205 1206 /* 1207 * ------------------------------------------------------------ 1208 * Function : trm_DataIO_transfer 1209 * Purpose : 1210 * Inputs : 1211 * ------------------------------------------------------------ 1212 */ 1213 void 1214 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir) 1215 { 1216 const bus_space_handle_t ioh = sc->sc_iohandle; 1217 const bus_space_tag_t iot = sc->sc_iotag; 1218 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1219 u_int8_t bval; 1220 1221 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1222 if (pSRB->SRBTotalXferLength != 0) { 1223 /* 1224 * load what physical address of Scatter/Gather list 1225 * table want to be transfer 1226 */ 1227 pSRB->SRBState = TRM_DATA_XFER; 1228 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0); 1229 bus_space_write_4(iot, ioh, 1230 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr + 1231 ((u_int32_t)pSRB->SRBSGIndex << 3))); 1232 /* 1233 * load how many bytes in the Scatter/Gather list table 1234 */ 1235 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT, 1236 ((u_int32_t)(pSRB->SRBSGCount - 1237 pSRB->SRBSGIndex) << 3)); 1238 /* 1239 * load total transfer length (24bits, 1240 * pSRB->SRBTotalXferLength) max value 16Mbyte 1241 */ 1242 bus_space_write_4(iot, ioh, 1243 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength); 1244 /* 1245 * Start DMA transfer 1246 */ 1247 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir); 1248 /* bus_space_write_2(iot, ioh, 1249 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/ 1250 /* 1251 * Set the transfer bus and direction 1252 */ 1253 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN; 1254 } else { 1255 /* 1256 * xfer pad 1257 */ 1258 if (pSRB->SRBSGCount) 1259 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN; 1260 1261 if (pDCB->SyncPeriod & WIDE_SYNC) { 1262 bus_space_write_4(iot, ioh, 1263 TRM_S1040_SCSI_COUNTER, 2); 1264 } else { 1265 bus_space_write_4(iot, ioh, 1266 TRM_S1040_SCSI_COUNTER, 1); 1267 } 1268 1269 if (ioDir == XFERDATAOUT) { 1270 bus_space_write_2(iot, 1271 ioh, TRM_S1040_SCSI_FIFO, 0); 1272 } else { 1273 bus_space_read_2(iot, 1274 ioh, TRM_S1040_SCSI_FIFO); 1275 } 1276 pSRB->SRBState = TRM_XFERPAD; 1277 /* 1278 * Set the transfer bus and direction 1279 */ 1280 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN; 1281 } 1282 /* 1283 * it's important for atn stop 1284 */ 1285 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1286 /* 1287 * Tell the bus to do the transfer 1288 */ 1289 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval); 1290 } 1291 } 1292 1293 /* 1294 * ------------------------------------------------------------ 1295 * Function : trm_StatusPhase0 1296 * Purpose : Update Target Status with data from SCSI FIFO 1297 * Inputs : u_int8_t * - Set to PH_BUS_FREE 1298 * ------------------------------------------------------------ 1299 */ 1300 void 1301 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1302 { 1303 const bus_space_handle_t ioh = sc->sc_iohandle; 1304 const bus_space_tag_t iot = sc->sc_iotag; 1305 1306 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1307 1308 pSRB->SRBState = TRM_COMPLETED; 1309 /* 1310 * initial phase 1311 */ 1312 *pscsi_status = PH_BUS_FREE; 1313 /* 1314 * it's important for atn stop 1315 */ 1316 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1317 /* 1318 * Tell bus that the message was accepted 1319 */ 1320 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1321 } 1322 1323 /* 1324 * ------------------------------------------------------------ 1325 * Function : trm_StatusPhase1 1326 * Purpose : Clear FIFO of DMA and SCSI 1327 * Inputs : 1328 * ------------------------------------------------------------ 1329 */ 1330 void 1331 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1332 { 1333 const bus_space_handle_t ioh = sc->sc_iohandle; 1334 const bus_space_tag_t iot = sc->sc_iotag; 1335 1336 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) { 1337 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40) 1338 == 0) { 1339 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1340 DO_CLRFIFO); 1341 } 1342 if ((bus_space_read_2(iot, ioh, 1343 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1344 bus_space_write_1(iot, ioh, 1345 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1346 } 1347 } else { 1348 if ((bus_space_read_2(iot, ioh, 1349 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1350 bus_space_write_1(iot, ioh, 1351 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1352 } 1353 if ((bus_space_read_1(iot, ioh, 1354 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) { 1355 bus_space_write_2(iot, ioh, 1356 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1357 } 1358 } 1359 pSRB->SRBState = TRM_STATUS; 1360 /* 1361 * it's important for atn stop 1362 */ 1363 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1364 /* 1365 * Tell the bus that the command is complete 1366 */ 1367 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP); 1368 } 1369 1370 /* 1371 * ------------------------------------------------------------ 1372 * Function : trm_MsgInPhase0 1373 * Purpose : 1374 * Inputs : 1375 * 1376 * extended message codes: 1377 * code description 1378 * ---- ----------- 1379 * 02h Reserved 1380 * 00h MODIFY DATA POINTER 1381 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1382 * 03h WIDE DATA TRANSFER REQUEST 1383 * 04h - 7Fh Reserved 1384 * 80h - FFh Vendor specific 1385 * 1386 * ------------------------------------------------------------ 1387 */ 1388 void 1389 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1390 { 1391 const bus_space_handle_t ioh = sc->sc_iohandle; 1392 const bus_space_tag_t iot = sc->sc_iotag; 1393 struct trm_dcb *pDCB; 1394 u_int8_t message_in_code, bIndex, message_in_tag_id; 1395 1396 pDCB = sc->pActiveDCB; 1397 1398 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1399 1400 if (pSRB->SRBState != TRM_EXTEND_MSGIN) { 1401 switch (message_in_code) { 1402 case MSG_DISCONNECT: 1403 pSRB->SRBState = TRM_DISCONNECTED; 1404 break; 1405 1406 case MSG_EXTENDED: 1407 case MSG_SIMPLE_Q_TAG: 1408 case MSG_HEAD_OF_Q_TAG: 1409 case MSG_ORDERED_Q_TAG: 1410 pSRB->SRBState = TRM_EXTEND_MSGIN; 1411 /* 1412 * extended message (01h) 1413 */ 1414 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf)); 1415 sc->MsgBuf[0] = message_in_code; 1416 sc->MsgCnt = 1; 1417 /* 1418 * extended message length (n) 1419 */ 1420 break; 1421 1422 case MSG_MESSAGE_REJECT: 1423 /* 1424 * Reject message 1425 */ 1426 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) { 1427 /* 1428 * do wide nego reject 1429 */ 1430 pDCB = pSRB->pSRBDCB; 1431 1432 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO; 1433 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1434 1435 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 1436 /* 1437 * Set ATN, in case ATN was clear 1438 */ 1439 pSRB->SRBState = TRM_MSGOUT; 1440 bus_space_write_2(iot, ioh, 1441 TRM_S1040_SCSI_CONTROL, DO_SETATN); 1442 } else { 1443 /* 1444 * Clear ATN 1445 */ 1446 bus_space_write_2(iot, ioh, 1447 TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1448 } 1449 1450 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) { 1451 /* 1452 * do sync nego reject 1453 */ 1454 pDCB = pSRB->pSRBDCB; 1455 1456 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO; 1457 1458 pDCB->SyncPeriod = 0; 1459 pDCB->SyncOffset = 0; 1460 1461 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1462 goto re_prog; 1463 } 1464 break; 1465 1466 case MSG_IGN_WIDE_RESIDUE: 1467 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1468 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1469 break; 1470 1471 default: 1472 break; 1473 } 1474 1475 } else { 1476 1477 /* 1478 * We are collecting an extended message. Save the latest byte and then 1479 * check to see if the message is complete. If so, process it. 1480 */ 1481 sc->MsgBuf[sc->MsgCnt++] = message_in_code; 1482 #ifdef TRM_DEBUG0 1483 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 1484 sc->sc_device.dv_xname, 1485 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] ); 1486 #endif 1487 switch (sc->MsgBuf[0]) { 1488 case MSG_SIMPLE_Q_TAG: 1489 case MSG_HEAD_OF_Q_TAG: 1490 case MSG_ORDERED_Q_TAG: 1491 if (sc->MsgCnt == 2) { 1492 pSRB->SRBState = TRM_FREE; 1493 message_in_tag_id = sc->MsgBuf[1]; 1494 sc->MsgCnt = 0; 1495 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) { 1496 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id)) 1497 break; 1498 } 1499 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) { 1500 pDCB->pActiveSRB = pSRB; 1501 pSRB->SRBState = TRM_DATA_XFER; 1502 } else { 1503 #ifdef TRM_DEBUG0 1504 printf("%s: TRM_UNEXPECT_RESEL!\n", 1505 sc->sc_device.dv_xname); 1506 #endif 1507 pSRB = &sc->SRB[0]; 1508 trm_srb_reinit(sc, pSRB); 1509 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1510 pDCB->pActiveSRB = pSRB; 1511 trm_EnableMsgOut(sc, MSG_ABORT_TAG); 1512 } 1513 } 1514 break; 1515 1516 case MSG_EXTENDED: 1517 /* TODO XXXX: Correctly handling target initiated negotiations? */ 1518 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) { 1519 /* 1520 * ====================================== 1521 * WIDE DATA TRANSFER REQUEST 1522 * ====================================== 1523 * byte 0 : Extended message (01h) 1524 * byte 1 : Extended message length (02h) 1525 * byte 2 : WIDE DATA TRANSFER code (03h) 1526 * byte 3 : Transfer width exponent 1527 */ 1528 1529 pSRB->SRBState = TRM_FREE; 1530 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO); 1531 1532 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN) 1533 goto reject_offer; 1534 1535 switch (sc->MsgBuf[3]) { 1536 case MSG_EXT_WDTR_BUS_32_BIT: 1537 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 1538 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1539 else 1540 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT; 1541 break; 1542 1543 case MSG_EXT_WDTR_BUS_16_BIT: 1544 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) { 1545 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1546 break; 1547 } 1548 pDCB->SyncPeriod |= WIDE_SYNC; 1549 /* FALL THROUGH == ACCEPT OFFER */ 1550 1551 case MSG_EXT_WDTR_BUS_8_BIT: 1552 pSRB->SRBState = TRM_MSGOUT; 1553 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE); 1554 1555 if (pDCB->MaxNegoPeriod == 0) { 1556 pDCB->SyncPeriod = 0; 1557 pDCB->SyncOffset = 0; 1558 goto re_prog; 1559 } 1560 break; 1561 1562 default: 1563 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 1564 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1565 reject_offer: 1566 sc->MsgCnt = 1; 1567 sc->MsgBuf[0] = MSG_MESSAGE_REJECT; 1568 break; 1569 } 1570 1571 /* Echo accepted offer, or send revised offer */ 1572 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN); 1573 1574 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) { 1575 /* 1576 * ================================= 1577 * SYNCHRONOUS DATA TRANSFER REQUEST 1578 * ================================= 1579 * byte 0 : Extended message (01h) 1580 * byte 1 : Extended message length (03) 1581 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1582 * byte 3 : Transfer period factor 1583 * byte 4 : REQ/ACK offset 1584 */ 1585 1586 pSRB->SRBState = TRM_FREE; 1587 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO); 1588 1589 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN) 1590 goto reject_offer; 1591 1592 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) { 1593 /* 1594 * Asynchronous transfers 1595 */ 1596 pDCB->SyncPeriod = 0; 1597 pDCB->SyncOffset = 0; 1598 1599 } else { 1600 /* 1601 * Synchronous transfers 1602 */ 1603 /* 1604 * REQ/ACK offset 1605 */ 1606 pDCB->SyncOffset = sc->MsgBuf[4]; 1607 1608 for (bIndex = 0; bIndex < 7; bIndex++) 1609 if (sc->MsgBuf[3] <= trm_clock_period[bIndex]) 1610 break; 1611 1612 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 1613 } 1614 1615 re_prog: /* 1616 * program SCSI control register 1617 */ 1618 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1619 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1620 1621 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID)); 1622 } 1623 break; 1624 1625 default: 1626 break; 1627 } 1628 } 1629 1630 /* 1631 * initial phase 1632 */ 1633 *pscsi_status = PH_BUS_FREE; 1634 /* 1635 * it's important for atn stop 1636 */ 1637 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1638 /* 1639 * Tell bus that the message was accepted 1640 */ 1641 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1642 } 1643 1644 /* 1645 * ------------------------------------------------------------ 1646 * Function : trm_MsgInPhase1 1647 * Purpose : Clear the FIFO 1648 * Inputs : 1649 * ------------------------------------------------------------ 1650 */ 1651 void 1652 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1653 { 1654 const bus_space_handle_t ioh = sc->sc_iohandle; 1655 const bus_space_tag_t iot = sc->sc_iotag; 1656 1657 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1658 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1659 1660 /* 1661 * it's important for atn stop 1662 */ 1663 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1664 /* 1665 * SCSI command 1666 */ 1667 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN); 1668 } 1669 1670 /* 1671 * ------------------------------------------------------------ 1672 * Function : trm_Nop 1673 * Purpose : EMPTY 1674 * Inputs : 1675 * ------------------------------------------------------------ 1676 */ 1677 void 1678 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1679 { 1680 } 1681 1682 /* 1683 * ------------------------------------------------------------ 1684 * Function : trm_SetXferParams 1685 * Purpose : Set the Sync period, offset and mode for each device that has 1686 * the same target as the given one (struct trm_dcb *) 1687 * Inputs : 1688 * ------------------------------------------------------------ 1689 */ 1690 void 1691 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info) 1692 { 1693 struct trm_dcb *pDCBTemp; 1694 int lun, target; 1695 1696 /* 1697 * set all lun device's period, offset 1698 */ 1699 #ifdef TRM_DEBUG0 1700 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname); 1701 #endif 1702 1703 target = pDCB->target; 1704 for(lun = 0; lun < TRM_MAX_LUNS; lun++) { 1705 pDCBTemp = sc->pDCB[target][lun]; 1706 if (pDCBTemp != NULL) { 1707 pDCBTemp->DevMode = pDCB->DevMode; 1708 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod; 1709 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 1710 pDCBTemp->SyncOffset = pDCB->SyncOffset; 1711 pDCBTemp->DCBFlag = pDCB->DCBFlag; 1712 } 1713 } 1714 1715 if (print_info) 1716 trm_print_info(sc, pDCB); 1717 } 1718 1719 /* 1720 * ------------------------------------------------------------ 1721 * Function : trm_Disconnect 1722 * Purpose : 1723 * Inputs : 1724 * 1725 * ---SCSI bus phase 1726 * PH_DATA_OUT 0x00 Data out phase 1727 * PH_DATA_IN 0x01 Data in phase 1728 * PH_COMMAND 0x02 Command phase 1729 * PH_STATUS 0x03 Status phase 1730 * PH_BUS_FREE 0x04 Invalid phase used as bus free 1731 * PH_BUS_FREE 0x05 Invalid phase used as bus free 1732 * PH_MSG_OUT 0x06 Message out phase 1733 * PH_MSG_IN 0x07 Message in phase 1734 * ------------------------------------------------------------ 1735 */ 1736 void 1737 trm_Disconnect(struct trm_softc *sc) 1738 { 1739 const bus_space_handle_t ioh = sc->sc_iohandle; 1740 struct trm_scsi_req_q *pSRB; 1741 const bus_space_tag_t iot = sc->sc_iotag; 1742 struct trm_dcb *pDCB; 1743 int j; 1744 1745 #ifdef TRM_DEBUG0 1746 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname); 1747 #endif 1748 1749 pDCB = sc->pActiveDCB; 1750 if (pDCB == NULL) { 1751 /* TODO: Why use a loop? Why not use DELAY(400)? */ 1752 for(j = 400; j > 0; --j) 1753 DELAY(1); /* 1 msec */ 1754 bus_space_write_2(iot, ioh, 1755 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1756 return; 1757 } 1758 1759 pSRB = pDCB->pActiveSRB; 1760 sc->pActiveDCB = NULL; 1761 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1762 bus_space_write_2(iot, ioh, 1763 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1764 DELAY(100); 1765 1766 switch (pSRB->SRBState) { 1767 case TRM_UNEXPECT_RESEL: 1768 pSRB->SRBState = TRM_FREE; 1769 break; 1770 1771 case TRM_ABORT_SENT: 1772 trm_GoingSRB_Done(sc, pDCB); 1773 break; 1774 1775 case TRM_START: 1776 case TRM_MSGOUT: 1777 /* 1778 * Selection time out 1779 */ 1780 /* If not polling just keep trying until xs->stimeout expires */ 1781 if ((pSRB->xs->flags & SCSI_POLL) == 0) { 1782 trm_RewaitSRB(sc, pSRB); 1783 } else { 1784 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT; 1785 goto disc1; 1786 } 1787 break; 1788 1789 case TRM_COMPLETED: 1790 disc1: 1791 /* 1792 * TRM_COMPLETED - remove id from mask of active tags 1793 */ 1794 pDCB->pActiveSRB = NULL; 1795 trm_FinishSRB(sc, pSRB); 1796 break; 1797 1798 default: 1799 break; 1800 } 1801 1802 trm_StartWaitingSRB(sc); 1803 } 1804 1805 /* 1806 * ------------------------------------------------------------ 1807 * Function : trm_Reselect 1808 * Purpose : 1809 * Inputs : 1810 * ------------------------------------------------------------ 1811 */ 1812 void 1813 trm_Reselect(struct trm_softc *sc) 1814 { 1815 const bus_space_handle_t ioh = sc->sc_iohandle; 1816 const bus_space_tag_t iot = sc->sc_iotag; 1817 struct trm_scsi_req_q *pSRB; 1818 struct trm_dcb *pDCB; 1819 u_int16_t RselTarLunId; 1820 u_int8_t target, lun; 1821 1822 #ifdef TRM_DEBUG0 1823 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname); 1824 #endif 1825 1826 pDCB = sc->pActiveDCB; 1827 if (pDCB != NULL) { 1828 /* 1829 * Arbitration lost but Reselection win 1830 */ 1831 pSRB = pDCB->pActiveSRB; 1832 trm_RewaitSRB(sc, pSRB); 1833 } 1834 1835 /* 1836 * Read Reselected Target Id and LUN 1837 */ 1838 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF; 1839 /* TODO XXXX: Make endian independent! */ 1840 target = RselTarLunId & 0xff; 1841 lun = (RselTarLunId >> 8) & 0xff; 1842 1843 #ifdef TRM_DEBUG0 1844 printf("%s: reselect - target = %d, lun = %d\n", 1845 sc->sc_device.dv_xname, target, lun); 1846 #endif 1847 1848 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS)) 1849 pDCB = sc->pDCB[target][lun]; 1850 else 1851 pDCB = NULL; 1852 1853 if (pDCB == NULL) 1854 printf("%s: reselect - target = %d, lun = %d not found\n", 1855 sc->sc_device.dv_xname, target, lun); 1856 1857 sc->pActiveDCB = pDCB; 1858 1859 /* TODO XXXX: This will crash if pDCB is ever NULL */ 1860 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) { 1861 pSRB = &sc->SRB[0]; 1862 pDCB->pActiveSRB = pSRB; 1863 } else { 1864 pSRB = pDCB->pActiveSRB; 1865 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) { 1866 /* 1867 * abort command 1868 */ 1869 pSRB = &sc->SRB[0]; 1870 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1871 pDCB->pActiveSRB = pSRB; 1872 trm_EnableMsgOut(sc, MSG_ABORT); 1873 } else 1874 pSRB->SRBState = TRM_DATA_XFER; 1875 } 1876 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1877 1878 /* 1879 * Program HA ID, target ID, period and offset 1880 */ 1881 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target); 1882 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 1883 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1884 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1885 1886 /* 1887 * it's important for atn stop 1888 */ 1889 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1890 DELAY(30); 1891 1892 /* 1893 * SCSI command 1894 * to rls the /ACK signal 1895 */ 1896 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1897 } 1898 1899 /* 1900 * ------------------------------------------------------------ 1901 * Function : trm_FinishSRB 1902 * Purpose : Complete execution of a SCSI command 1903 * Inputs : 1904 * ------------------------------------------------------------ 1905 */ 1906 void 1907 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 1908 { 1909 struct scsi_inquiry_data *ptr; 1910 struct scsi_sense_data *s1, *s2; 1911 struct scsi_xfer *xs = pSRB->xs; 1912 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1913 int target, lun, intflag; 1914 1915 #ifdef TRM_DEBUG0 1916 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n", 1917 sc->sc_device.dv_xname, sc, pSRB); 1918 #endif 1919 pDCB->DCBFlag &= ~TRM_QUEUE_FULL; 1920 1921 intflag = splbio(); 1922 if (pSRB->TagNumber != TRM_NO_TAG) { 1923 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber); 1924 pSRB->TagNumber = TRM_NO_TAG; 1925 } 1926 /* SRB may have started & finished, or be waiting and timed out */ 1927 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 1928 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 1929 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 1930 } 1931 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 1932 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 1933 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 1934 } 1935 splx(intflag); 1936 1937 if (xs == NULL) { 1938 return; 1939 } 1940 1941 timeout_del(&xs->stimeout); 1942 1943 xs->status = pSRB->TargetStatus; 1944 if (xs->datalen != 0) { 1945 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 1946 0, pSRB->dmamapxfer->dm_mapsize, 1947 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1948 BUS_DMASYNC_POSTWRITE); 1949 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer); 1950 } 1951 1952 switch (xs->status) { 1953 case SCSI_INTERM_COND_MET: 1954 case SCSI_COND_MET: 1955 case SCSI_INTERM: 1956 case SCSI_OK: 1957 switch (pSRB->AdaptStatus) { 1958 case TRM_STATUS_GOOD: 1959 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) { 1960 #ifdef TRM_DEBUG0 1961 sc_print_addr(xs->sc_link); 1962 printf(" trm_FinishSRB. TRM_PARITY_ERROR\n"); 1963 #endif 1964 xs->error = XS_DRIVER_STUFFUP; 1965 1966 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) { 1967 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) == 0) 1968 xs->error = XS_TIMEOUT; 1969 else { 1970 bzero(&xs->sense, sizeof(xs->sense)); 1971 xs->status = SCSI_CHECK; 1972 xs->error = XS_SENSE; 1973 } 1974 1975 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) { 1976 s1 = &pSRB->scsisense; 1977 s2 = &xs->sense; 1978 1979 *s2 = *s1; 1980 1981 xs->status = SCSI_CHECK; 1982 xs->error = XS_SENSE; 1983 1984 } else 1985 xs->error = XS_NOERROR; 1986 break; 1987 1988 case TRM_OVER_UNDER_RUN: 1989 #ifdef TRM_DEBUG0 1990 sc_print_addr(xs->sc_link); 1991 printf("trm_FinishSRB. TRM_OVER_UNDER_RUN\n"); 1992 #endif 1993 xs->error = XS_DRIVER_STUFFUP; 1994 break; 1995 1996 default: 1997 #ifdef TRM_DEBUG0 1998 sc_print_addr(xs->sc_link); 1999 printf("trm_FinishSRB. AdaptStatus Error = 0x%02x\n", 2000 pSRB->AdaptStatus); 2001 #endif 2002 xs->error = XS_DRIVER_STUFFUP; 2003 break; 2004 } 2005 break; 2006 2007 case SCSI_TERMINATED: 2008 case SCSI_ACA_ACTIVE: 2009 case SCSI_CHECK: 2010 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) 2011 xs->error = XS_DRIVER_STUFFUP; 2012 else { 2013 trm_RequestSense(sc, pSRB); 2014 return; 2015 } 2016 break; 2017 2018 case SCSI_QUEUE_FULL: 2019 /* this says no more until someone completes */ 2020 pDCB->DCBFlag |= TRM_QUEUE_FULL; 2021 trm_RewaitSRB(sc, pSRB); 2022 return; 2023 2024 case SCSI_RESV_CONFLICT: 2025 case SCSI_BUSY: 2026 xs->error = XS_BUSY; 2027 break; 2028 2029 case TRM_SCSI_UNEXP_BUS_FREE: 2030 xs->status = SCSI_OK; 2031 xs->error = XS_DRIVER_STUFFUP; 2032 break; 2033 2034 case TRM_SCSI_BUS_RST_DETECTED: 2035 xs->status = SCSI_OK; 2036 xs->error = XS_RESET; 2037 break; 2038 2039 case TRM_SCSI_SELECT_TIMEOUT: 2040 xs->status = SCSI_OK; 2041 xs->error = XS_SELTIMEOUT; 2042 break; 2043 2044 default: 2045 xs->error = XS_DRIVER_STUFFUP; 2046 break; 2047 } 2048 2049 target = xs->sc_link->target; 2050 lun = xs->sc_link->lun; 2051 2052 if ((xs->flags & SCSI_POLL) != 0) { 2053 2054 if (xs->cmd->opcode == INQUIRY && pDCB->sc_link == NULL) { 2055 2056 ptr = (struct scsi_inquiry_data *) xs->data; 2057 2058 if ((xs->error != XS_NOERROR) || 2059 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) { 2060 #ifdef TRM_DEBUG0 2061 sc_print_addr(xs->sc_link); 2062 printf("trm_FinishSRB NO Device\n"); 2063 #endif 2064 free(pDCB, M_DEVBUF, 0); 2065 sc->pDCB[target][lun] = NULL; 2066 pDCB = NULL; 2067 2068 } else 2069 pDCB->sc_link = xs->sc_link; 2070 } 2071 } 2072 2073 /* 2074 * Notify cmd done 2075 */ 2076 #ifdef TRM_DEBUG0 2077 if ((xs->error != 0) || (xs->status != 0) || 2078 ((xs->flags & SCSI_POLL) != 0)) { 2079 sc_print_addr(xs->sc_link); 2080 printf("trm_FinishSRB. xs->cmd->opcode = 0x%02x, xs->error = %d, xs->status = %d\n", 2081 xs->cmd->opcode, xs->error, xs->status); 2082 } 2083 #endif 2084 2085 if (ISSET(xs->flags, SCSI_POLL)) 2086 SET(xs->flags, ITSDONE); 2087 else 2088 scsi_done(xs); 2089 } 2090 2091 /* 2092 * ------------------------------------------------------------ 2093 * Function : trm_srb_reinit 2094 * Purpose : 2095 * Inputs : 2096 * ------------------------------------------------------------ 2097 */ 2098 void 2099 trm_srb_reinit(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2100 { 2101 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX)); 2102 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2103 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense)); 2104 2105 pSRB->SRBTotalXferLength = 0; 2106 pSRB->SRBSGCount = 0; 2107 pSRB->SRBSGIndex = 0; 2108 pSRB->SRBFlag = 0; 2109 2110 pSRB->SRBState = TRM_FREE; 2111 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2112 pSRB->TargetStatus = SCSI_OK; 2113 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 2114 2115 pSRB->xs = NULL; 2116 pSRB->pSRBDCB = NULL; 2117 } 2118 2119 /* 2120 * ------------------------------------------------------------ 2121 * Function : trm_srb_free 2122 * Purpose : 2123 * Inputs : 2124 * ------------------------------------------------------------ 2125 */ 2126 void 2127 trm_srb_free(void *xsc, void *xpSRB) 2128 { 2129 struct trm_softc *sc = xsc; 2130 struct trm_scsi_req_q *pSRB = xpSRB; 2131 2132 trm_srb_reinit(sc, pSRB); 2133 2134 if (pSRB != &sc->SRB[0]) { 2135 mtx_enter(&sc->sc_srb_mtx); 2136 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2137 mtx_leave(&sc->sc_srb_mtx); 2138 } 2139 } 2140 2141 /* 2142 * ------------------------------------------------------------ 2143 * Function : trm_GoingSRB_Done 2144 * Purpose : 2145 * Inputs : 2146 * ------------------------------------------------------------ 2147 */ 2148 void 2149 trm_GoingSRB_Done(struct trm_softc *sc, struct trm_dcb *pDCB) 2150 { 2151 struct trm_scsi_req_q *pSRB, *pNextSRB; 2152 2153 /* ASSUME we are inside a splbio()/splx() pair */ 2154 2155 pSRB = TAILQ_FIRST(&sc->goingSRB); 2156 while (pSRB != NULL) { 2157 /* 2158 * Need to save pNextSRB because trm_FinishSRB() puts 2159 * pSRB in freeSRB queue, and thus its links no longer 2160 * point to members of the goingSRB queue. This is why 2161 * TAILQ_FOREACH() will not work for this traversal. 2162 */ 2163 pNextSRB = TAILQ_NEXT(pSRB, link); 2164 if (pDCB == NULL || pSRB->pSRBDCB == pDCB) { 2165 /* TODO XXXX: Is TIMED_OUT the best state to report? */ 2166 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 2167 trm_FinishSRB(sc, pSRB); 2168 } 2169 pSRB = pNextSRB; 2170 } 2171 } 2172 2173 /* 2174 * ------------------------------------------------------------ 2175 * Function : trm_ResetSCSIBus 2176 * Purpose : Reset the SCSI bus 2177 * Inputs : struct trm_softc * - 2178 * ------------------------------------------------------------ 2179 */ 2180 void 2181 trm_ResetSCSIBus(struct trm_softc *sc) 2182 { 2183 const bus_space_handle_t ioh = sc->sc_iohandle; 2184 const bus_space_tag_t iot = sc->sc_iotag; 2185 int intflag; 2186 2187 intflag = splbio(); 2188 2189 sc->sc_Flag |= RESET_DEV; 2190 2191 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI); 2192 while ((bus_space_read_2(iot, ioh, 2193 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0); 2194 2195 splx(intflag); 2196 } 2197 2198 /* 2199 * ------------------------------------------------------------ 2200 * Function : trm_ScsiRstDetect 2201 * Purpose : 2202 * Inputs : 2203 * ------------------------------------------------------------ 2204 */ 2205 void 2206 trm_ScsiRstDetect(struct trm_softc *sc) 2207 { 2208 const bus_space_handle_t ioh = sc->sc_iohandle; 2209 const bus_space_tag_t iot = sc->sc_iotag; 2210 int wlval; 2211 2212 #ifdef TRM_DEBUG0 2213 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname); 2214 #endif 2215 2216 wlval = 1000; 2217 /* 2218 * delay 1 sec 2219 */ 2220 while (--wlval != 0) 2221 DELAY(1000); 2222 2223 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 2224 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 2225 2226 if ((sc->sc_Flag & RESET_DEV) != 0) 2227 sc->sc_Flag |= RESET_DONE; 2228 else { 2229 sc->sc_Flag |= RESET_DETECT; 2230 trm_ResetAllDevParam(sc); 2231 trm_RecoverSRB(sc); 2232 sc->pActiveDCB = NULL; 2233 sc->sc_Flag = 0; 2234 trm_StartWaitingSRB(sc); 2235 } 2236 } 2237 2238 /* 2239 * ------------------------------------------------------------ 2240 * Function : trm_RequestSense 2241 * Purpose : 2242 * Inputs : 2243 * ------------------------------------------------------------ 2244 */ 2245 void 2246 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2247 { 2248 pSRB->SRBFlag |= TRM_AUTO_REQSENSE; 2249 2250 /* 2251 * Status of initiator/target 2252 */ 2253 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2254 pSRB->TargetStatus = SCSI_OK; 2255 /* 2256 * Status of initiator/target 2257 */ 2258 2259 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr; 2260 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data); 2261 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data); 2262 pSRB->SRBSGCount = 1; 2263 pSRB->SRBSGIndex = 0; 2264 2265 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2266 2267 pSRB->CmdBlock[0] = REQUEST_SENSE; 2268 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5; 2269 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data); 2270 2271 pSRB->ScsiCmdLen = 6; 2272 2273 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0)) 2274 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout); 2275 2276 if (trm_StartSRB(sc, pSRB) != 0) 2277 trm_RewaitSRB(sc, pSRB); 2278 } 2279 2280 /* 2281 * ------------------------------------------------------------ 2282 * Function : trm_EnableMsgOut 2283 * Purpose : set up MsgBuf to send out a single byte message 2284 * Inputs : 2285 * ------------------------------------------------------------ 2286 */ 2287 void 2288 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg) 2289 { 2290 sc->MsgBuf[0] = msg; 2291 sc->MsgCnt = 1; 2292 2293 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN); 2294 } 2295 2296 /* 2297 * ------------------------------------------------------------ 2298 * Function : trm_linkSRB 2299 * Purpose : 2300 * Inputs : 2301 * ------------------------------------------------------------ 2302 */ 2303 void 2304 trm_linkSRB(struct trm_softc *sc) 2305 { 2306 struct trm_scsi_req_q *pSRB; 2307 int i, intflag; 2308 2309 intflag = splbio(); 2310 2311 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2312 pSRB = &sc->SRB[i]; 2313 2314 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr 2315 + i * sizeof(struct trm_scsi_req_q); 2316 2317 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2318 + i * sizeof(struct trm_scsi_req_q) 2319 + offsetof(struct trm_scsi_req_q, SegmentX); 2320 2321 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2322 + i * sizeof(struct trm_scsi_req_q) 2323 + offsetof(struct trm_scsi_req_q, scsisense); 2324 2325 /* 2326 * map all SRB space 2327 */ 2328 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE, 2329 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0, 2330 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2331 &pSRB->dmamapxfer) != 0) { 2332 printf("%s: unable to create DMA transfer map\n", 2333 sc->sc_device.dv_xname); 2334 splx(intflag); 2335 return; 2336 } 2337 2338 if (i > 0) 2339 /* We use sc->SRB[0] directly, so *don't* link it */ 2340 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2341 #ifdef TRM_DEBUG0 2342 printf("pSRB = %p ", pSRB); 2343 #endif 2344 } 2345 #ifdef TRM_DEBUG0 2346 printf("\n "); 2347 #endif 2348 splx(intflag); 2349 } 2350 2351 /* 2352 * ------------------------------------------------------------ 2353 * Function : trm_initACB 2354 * Purpose : initialize the internal structures for a given SCSI host 2355 * Inputs : 2356 * ------------------------------------------------------------ 2357 */ 2358 void 2359 trm_initACB(struct trm_softc *sc, int unit) 2360 { 2361 const bus_space_handle_t ioh = sc->sc_iohandle; 2362 const bus_space_tag_t iot = sc->sc_iotag; 2363 struct trm_adapter_nvram *pEEpromBuf; 2364 struct trm_dcb *pDCB; 2365 int target, lun; 2366 2367 pEEpromBuf = &trm_eepromBuf[unit]; 2368 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2369 2370 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0) 2371 sc->sc_config |= HCC_WIDE_CARD; 2372 2373 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0) 2374 sc->sc_config |= HCC_SCSI_RESET; 2375 2376 TAILQ_INIT(&sc->freeSRB); 2377 TAILQ_INIT(&sc->waitingSRB); 2378 TAILQ_INIT(&sc->goingSRB); 2379 2380 mtx_init(&sc->sc_srb_mtx, IPL_BIO); 2381 scsi_iopool_init(&sc->sc_iopool, sc, trm_srb_alloc, trm_srb_free); 2382 2383 sc->pActiveDCB = NULL; 2384 sc->sc_AdapterUnit = unit; 2385 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId; 2386 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2387 sc->sc_Flag = 0; 2388 2389 /* 2390 * put all SRB's (except [0]) onto the freeSRB list 2391 */ 2392 trm_linkSRB(sc); 2393 2394 /* 2395 * allocate DCB array 2396 */ 2397 for (target = 0; target < TRM_MAX_TARGETS; target++) { 2398 if (target == sc->sc_AdaptSCSIID) 2399 continue; 2400 2401 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2402 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), 2403 M_DEVBUF, M_NOWAIT | M_ZERO); 2404 sc->pDCB[target][lun] = pDCB; 2405 2406 if (pDCB == NULL) 2407 continue; 2408 2409 pDCB->target = target; 2410 pDCB->lun = lun; 2411 pDCB->pActiveSRB = NULL; 2412 } 2413 } 2414 2415 sc->sc_link.adapter_softc = sc; 2416 sc->sc_link.adapter_target = sc->sc_AdaptSCSIID; 2417 sc->sc_link.openings = 30; /* So TagMask (32 bit integer) always has space */ 2418 sc->sc_link.adapter = &trm_switch; 2419 sc->sc_link.adapter_buswidth = ((sc->sc_config & HCC_WIDE_CARD) == 0) ? 8:16; 2420 sc->sc_link.pool = &sc->sc_iopool; 2421 2422 trm_reset(sc); 2423 } 2424 2425 /* 2426 * ------------------------------------------------------------ 2427 * Function : trm_write_all 2428 * Description : write pEEpromBuf 128 bytes to seeprom 2429 * Input : iot, ioh - chip's base address 2430 * Output : none 2431 * ------------------------------------------------------------ 2432 */ 2433 void 2434 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2435 bus_space_handle_t ioh) 2436 { 2437 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2438 u_int8_t bAddr; 2439 2440 /* 2441 * Enable SEEPROM 2442 */ 2443 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2444 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2445 /* 2446 * Write enable 2447 */ 2448 trm_write_cmd(iot, ioh, 0x04, 0xFF); 2449 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2450 trm_wait_30us(iot, ioh); 2451 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2452 trm_set_data(iot, ioh, bAddr, *bpEeprom); 2453 /* 2454 * Write disable 2455 */ 2456 trm_write_cmd(iot, ioh, 0x04, 0x00); 2457 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2458 trm_wait_30us(iot, ioh); 2459 /* 2460 * Disable SEEPROM 2461 */ 2462 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2463 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2464 } 2465 2466 /* 2467 * ------------------------------------------------------------ 2468 * Function : trm_set_data 2469 * Description : write one byte to seeprom 2470 * Input : iot, ioh - chip's base address 2471 * bAddr - address of SEEPROM 2472 * bData - data of SEEPROM 2473 * Output : none 2474 * ------------------------------------------------------------ 2475 */ 2476 void 2477 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr, 2478 u_int8_t bData) 2479 { 2480 u_int8_t bSendData; 2481 int i; 2482 2483 /* 2484 * Send write command & address 2485 */ 2486 trm_write_cmd(iot, ioh, 0x05, bAddr); 2487 /* 2488 * Write data 2489 */ 2490 for (i = 0; i < 8; i++, bData <<= 1) { 2491 bSendData = NVR_SELECT; 2492 if ((bData & 0x80) != 0) { /* Start from bit 7 */ 2493 bSendData |= NVR_BITOUT; 2494 } 2495 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2496 trm_wait_30us(iot, ioh); 2497 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2498 (bSendData | NVR_CLOCK)); 2499 trm_wait_30us(iot, ioh); 2500 } 2501 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2502 trm_wait_30us(iot, ioh); 2503 /* 2504 * Disable chip select 2505 */ 2506 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2507 trm_wait_30us(iot, ioh); 2508 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2509 trm_wait_30us(iot, ioh); 2510 /* 2511 * Wait for write ready 2512 */ 2513 for (;;) { 2514 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2515 (NVR_SELECT | NVR_CLOCK)); 2516 trm_wait_30us(iot, ioh); 2517 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2518 trm_wait_30us(iot, ioh); 2519 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN) 2520 break; 2521 } 2522 /* 2523 * Disable chip select 2524 */ 2525 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2526 } 2527 2528 /* 2529 * ------------------------------------------------------------ 2530 * Function : trm_read_all 2531 * Description : read seeprom 128 bytes to pEEpromBuf 2532 * Input : pEEpromBuf, iot, ioh - chip's base address 2533 * Output : none 2534 * ------------------------------------------------------------ 2535 */ 2536 void 2537 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2538 bus_space_handle_t ioh) 2539 { 2540 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2541 u_int8_t bAddr; 2542 2543 /* 2544 * Enable SEEPROM 2545 */ 2546 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2547 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2548 2549 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2550 *bpEeprom = trm_get_data(iot, ioh, bAddr); 2551 2552 /* 2553 * Disable SEEPROM 2554 */ 2555 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2556 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2557 } 2558 2559 /* 2560 * ------------------------------------------------------------ 2561 * Function : trm_get_data 2562 * Description : read one byte from seeprom 2563 * Input : iot, ioh - chip's base address 2564 * bAddr - address of SEEPROM 2565 * Output : bData - data of SEEPROM 2566 * ------------------------------------------------------------ 2567 */ 2568 u_int8_t 2569 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr) 2570 { 2571 u_int8_t bReadData, bData; 2572 int i; 2573 2574 bData = 0; 2575 2576 /* 2577 * Send read command & address 2578 */ 2579 trm_write_cmd(iot, ioh, 0x06, bAddr); 2580 2581 for (i = 0; i < 8; i++) { 2582 /* 2583 * Read data 2584 */ 2585 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2586 (NVR_SELECT | NVR_CLOCK)); 2587 trm_wait_30us(iot, ioh); 2588 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2589 /* 2590 * Get data bit while falling edge 2591 */ 2592 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM); 2593 bData <<= 1; 2594 if ((bReadData & NVR_BITIN) != 0) 2595 bData |= 1; 2596 trm_wait_30us(iot, ioh); 2597 } 2598 /* 2599 * Disable chip select 2600 */ 2601 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2602 2603 return bData; 2604 } 2605 2606 /* 2607 * ------------------------------------------------------------ 2608 * Function : trm_wait_30us 2609 * Description : wait 30 us 2610 * Input : iot, ioh - chip's base address 2611 * Output : none 2612 * ------------------------------------------------------------ 2613 */ 2614 void 2615 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh) 2616 { 2617 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5); 2618 2619 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT) 2620 == 0); 2621 } 2622 2623 /* 2624 * ------------------------------------------------------------ 2625 * Function : trm_write_cmd 2626 * Description : write SB and Op Code into seeprom 2627 * Input : iot, ioh - chip's base address 2628 * bCmd - SB + Op Code 2629 * bAddr - address of SEEPROM 2630 * Output : none 2631 * ------------------------------------------------------------ 2632 */ 2633 void 2634 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd, 2635 u_int8_t bAddr) 2636 { 2637 u_int8_t bSendData; 2638 int i; 2639 2640 for (i = 0; i < 3; i++, bCmd <<= 1) { 2641 /* 2642 * Program SB + OP code 2643 */ 2644 bSendData = NVR_SELECT; 2645 if (bCmd & 0x04) /* Start from bit 2 */ 2646 bSendData |= NVR_BITOUT; 2647 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2648 trm_wait_30us(iot, ioh); 2649 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2650 (bSendData | NVR_CLOCK)); 2651 trm_wait_30us(iot, ioh); 2652 } 2653 2654 for (i = 0; i < 7; i++, bAddr <<= 1) { 2655 /* 2656 * Program address 2657 */ 2658 bSendData = NVR_SELECT; 2659 if (bAddr & 0x40) { /* Start from bit 6 */ 2660 bSendData |= NVR_BITOUT; 2661 } 2662 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2663 trm_wait_30us(iot, ioh); 2664 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2665 (bSendData | NVR_CLOCK)); 2666 trm_wait_30us(iot, ioh); 2667 } 2668 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2669 trm_wait_30us(iot, ioh); 2670 } 2671 2672 /* 2673 * ------------------------------------------------------------ 2674 * Function : trm_check_eeprom 2675 * Description : read eeprom 128 bytes to pEEpromBuf and check 2676 * checksum. If it is wrong, updated with default value. 2677 * Input : eeprom, iot, ioh - chip's base address 2678 * Output : none 2679 * ------------------------------------------------------------ 2680 */ 2681 void 2682 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2683 bus_space_handle_t ioh) 2684 { 2685 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget; 2686 u_int32_t dAddr; 2687 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf; 2688 u_int16_t wAddr, wCheckSum; 2689 2690 #ifdef TRM_DEBUG0 2691 printf("\ntrm_check_eeprom\n"); 2692 #endif 2693 trm_read_all(pEEpromBuf, iot, ioh); 2694 wCheckSum = 0; 2695 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++) 2696 wCheckSum += *wpEeprom; 2697 2698 if (wCheckSum != 0x1234) { 2699 #ifdef TRM_DEBUG0 2700 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n"); 2701 #endif 2702 /* 2703 * Checksum error, load default 2704 */ 2705 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2706 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2707 >> 8); 2708 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) 2709 PCI_PRODUCT_TEKRAM2_DC3X5U; 2710 pEEpromBuf->NvramSubSysID[1] = (u_int8_t) 2711 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2712 pEEpromBuf->NvramSubClass = 0; 2713 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2714 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2715 >> 8); 2716 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) 2717 PCI_PRODUCT_TEKRAM2_DC3X5U; 2718 pEEpromBuf->NvramDeviceID[1] = (u_int8_t) 2719 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2720 pEEpromBuf->NvramReserved = 0; 2721 2722 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++) 2723 /* 2724 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 2725 */ 2726 *dpEeprom = 0x00000077; 2727 2728 /* 2729 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId 2730 */ 2731 *dpEeprom++ = 0x04000F07; 2732 2733 /* 2734 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 2735 */ 2736 *dpEeprom++ = 0x00000015; 2737 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 2738 *dpEeprom = 0; 2739 2740 pEEpromBuf->NvramCheckSum = 0; 2741 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++) 2742 wCheckSum += *wpEeprom; 2743 2744 *wpEeprom = 0x1234 - wCheckSum; 2745 trm_write_all(pEEpromBuf, iot, ioh); 2746 } 2747 } 2748 2749 /* 2750 * ------------------------------------------------------------ 2751 * Function : trm_initAdapter 2752 * Purpose : initialize the SCSI chip ctrl registers 2753 * Inputs : psh - pointer to this host adapter's structure 2754 * ------------------------------------------------------------ 2755 */ 2756 void 2757 trm_initAdapter(struct trm_softc *sc) 2758 { 2759 const bus_space_handle_t ioh = sc->sc_iohandle; 2760 const bus_space_tag_t iot = sc->sc_iotag; 2761 u_int16_t wval; 2762 u_int8_t bval; 2763 2764 /* 2765 * program configuration 0 2766 */ 2767 if ((sc->sc_config & HCC_PARITY) != 0) { 2768 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 2769 } else { 2770 bval = PHASELATCH | INITIATOR | BLOCKRST; 2771 } 2772 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval); 2773 /* 2774 * program configuration 1 2775 */ 2776 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13); 2777 /* 2778 * 250ms selection timeout 2779 */ 2780 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT); 2781 /* 2782 * Mask all the interrupt 2783 */ 2784 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 2785 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 2786 /* 2787 * Reset SCSI module 2788 */ 2789 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE); 2790 /* 2791 * program Host ID 2792 */ 2793 bval = sc->sc_AdaptSCSIID; 2794 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval); 2795 /* 2796 * set ansynchronous transfer 2797 */ 2798 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0); 2799 /* 2800 * Turn LED control off 2801 */ 2802 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F; 2803 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval); 2804 /* 2805 * DMA config 2806 */ 2807 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE; 2808 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval); 2809 /* 2810 * Clear pending interrupt status 2811 */ 2812 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 2813 /* 2814 * Enable SCSI interrupts 2815 */ 2816 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 2817 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 2818 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 2819 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 2820 } 2821 2822 /* 2823 * ------------------------------------------------------------ 2824 * Function : trm_init 2825 * Purpose : initialize the internal structures for a given SCSI host 2826 * Inputs : host - pointer to this host adapter's structure 2827 * Preconditions : when this function is called, the chip_type field of 2828 * the ACB structure MUST have been set. 2829 * ------------------------------------------------------------ 2830 */ 2831 int 2832 trm_init(struct trm_softc *sc, int unit) 2833 { 2834 const bus_space_handle_t ioh = sc->sc_iohandle; 2835 const bus_space_tag_t iot = sc->sc_iotag; 2836 bus_dma_segment_t seg; 2837 int error, rseg, all_srbs_size; 2838 2839 /* 2840 * EEPROM CHECKSUM 2841 */ 2842 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh); 2843 2844 /* 2845 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 2846 */ 2847 /* 2848 * allocate the space for all SCSI control blocks (SRB) for DMA memory. 2849 */ 2850 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q); 2851 2852 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg, 2853 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 2854 if (error != 0) { 2855 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n", 2856 sc->sc_device.dv_xname, error); 2857 /*errx(error, "%s: unable to allocate SCSI request blocks", 2858 sc->sc_device.dv_xname);*/ 2859 return -1; 2860 } 2861 2862 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size, 2863 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 2864 if (error != 0) { 2865 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n", 2866 sc->sc_device.dv_xname, error); 2867 /*errx(error, "unable to map SCSI request blocks");*/ 2868 return -1; 2869 } 2870 2871 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1, 2872 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control); 2873 if (error != 0) { 2874 printf("%s: unable to create SRB DMA maps, error = %d\n", 2875 sc->sc_device.dv_xname, error); 2876 /*errx(error, "unable to create SRB DMA maps");*/ 2877 return -1; 2878 } 2879 2880 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control, 2881 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT); 2882 if (error != 0) { 2883 printf("%s: unable to load SRB DMA maps, error = %d\n", 2884 sc->sc_device.dv_xname, error); 2885 /*errx(error, "unable to load SRB DMA maps");*/ 2886 return -1; 2887 } 2888 #ifdef TRM_DEBUG0 2889 printf("\n\n%s: all_srbs_size=%x\n", 2890 sc->sc_device.dv_xname, all_srbs_size); 2891 #endif 2892 trm_initACB(sc, unit); 2893 trm_initAdapter(sc); 2894 2895 return 0; 2896 } 2897 2898 /* ------------------------------------------------------------ 2899 * Function : trm_print_info 2900 * Purpose : Print the DCB negotiation information 2901 * Inputs : 2902 * ------------------------------------------------------------ 2903 */ 2904 void 2905 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB) 2906 { 2907 int syncXfer, index; 2908 2909 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC); 2910 2911 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target); 2912 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0) 2913 printf("16 bit "); 2914 else 2915 printf("8 bit "); 2916 2917 if (pDCB->SyncOffset == 0) 2918 printf("Asynchronous "); 2919 else { 2920 syncXfer = 100000 / (trm_clock_period[index] * 4); 2921 printf("%d.%01d MHz, Offset %d ", 2922 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset); 2923 } 2924 printf("data transfers "); 2925 2926 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) 2927 printf("with Tag Queuing"); 2928 2929 printf("\n"); 2930 } 2931