1 /* $OpenBSD: trm.c,v 1.30 2011/12/03 03:29:13 krw Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.c 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * HISTORY: 13 * 14 * REV# DATE NAME DESCRIPTION 15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x 16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8 17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting 18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic 19 * ------------------------------------------------------------ 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 3. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * ------------------------------------------------------------ 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/buf.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <scsi/scsi_message.h> 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/ic/trm.h> 61 62 /* #define TRM_DEBUG0 */ 63 64 void trm_minphys(struct buf *, struct scsi_link *); 65 66 void trm_initSRB(struct trm_scsi_req_q *); 67 68 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 69 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 70 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 71 72 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 73 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 74 75 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t); 76 77 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t); 78 79 void trm_scsi_cmd(struct scsi_xfer *); 80 81 void *trm_srb_alloc(void *); 82 83 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 84 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 85 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 86 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 87 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 88 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 89 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 90 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 91 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 92 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 93 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 94 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 95 96 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int); 97 98 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t); 99 100 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *); 101 void trm_srb_reinit (struct trm_softc *, struct trm_scsi_req_q *); 102 void trm_srb_free (void *, void *); 103 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *); 104 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *); 105 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *); 106 107 void trm_initAdapter (struct trm_softc *); 108 void trm_Disconnect (struct trm_softc *); 109 void trm_Reselect (struct trm_softc *); 110 void trm_GoingSRB_Done (struct trm_softc *, struct trm_dcb *); 111 void trm_ScsiRstDetect (struct trm_softc *); 112 void trm_ResetSCSIBus (struct trm_softc *); 113 void trm_reset (struct trm_softc *); 114 void trm_StartWaitingSRB (struct trm_softc *); 115 void trm_ResetAllDevParam(struct trm_softc *); 116 void trm_RecoverSRB (struct trm_softc *); 117 void trm_linkSRB (struct trm_softc *); 118 119 void trm_initACB(struct trm_softc *, int); 120 121 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t); 122 123 void trm_EnableMsgOut(struct trm_softc *, u_int8_t); 124 125 void trm_timeout(void *); 126 127 void trm_print_info(struct trm_softc *, struct trm_dcb *); 128 129 /* 130 * Define structures 131 */ 132 struct cfdriver trm_cd = { 133 NULL, "trm", DV_DULL 134 }; 135 136 struct scsi_adapter trm_switch = { 137 trm_scsi_cmd, 138 trm_minphys, 139 NULL, 140 NULL 141 }; 142 143 /* 144 * ------------------------------------------------------------ 145 * 146 * stateV = (void *) trm_SCSI_phase0[phase] 147 * 148 * ------------------------------------------------------------ 149 */ 150 static void *trm_SCSI_phase0[8] = { 151 trm_DataOutPhase0, /* phase:0 */ 152 trm_DataInPhase0, /* phase:1 */ 153 trm_Nop, /* phase:2 */ 154 trm_StatusPhase0, /* phase:3 */ 155 trm_Nop, /* phase:4 */ 156 trm_Nop, /* phase:5 */ 157 trm_MsgOutPhase0, /* phase:6 */ 158 trm_MsgInPhase0, /* phase:7 */ 159 }; 160 161 /* 162 * ------------------------------------------------------------ 163 * 164 * stateV = (void *) trm_SCSI_phase1[phase] 165 * 166 * ------------------------------------------------------------ 167 */ 168 static void *trm_SCSI_phase1[8] = { 169 trm_DataOutPhase1, /* phase:0 */ 170 trm_DataInPhase1, /* phase:1 */ 171 trm_CommandPhase1, /* phase:2 */ 172 trm_StatusPhase1, /* phase:3 */ 173 trm_Nop, /* phase:4 */ 174 trm_Nop, /* phase:5 */ 175 trm_MsgOutPhase1, /* phase:6 */ 176 trm_MsgInPhase1, /* phase:7 */ 177 }; 178 179 180 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 181 /* 182 *Fast20: 000 50ns, 20.0 Mbytes/s 183 * 001 75ns, 13.3 Mbytes/s 184 * 010 100ns, 10.0 Mbytes/s 185 * 011 125ns, 8.0 Mbytes/s 186 * 100 150ns, 6.6 Mbytes/s 187 * 101 175ns, 5.7 Mbytes/s 188 * 110 200ns, 5.0 Mbytes/s 189 * 111 250ns, 4.0 Mbytes/s 190 * 191 *Fast40: 000 25ns, 40.0 Mbytes/s 192 * 001 50ns, 20.0 Mbytes/s 193 * 010 75ns, 13.3 Mbytes/s 194 * 011 100ns, 10.0 Mbytes/s 195 * 100 125ns, 8.0 Mbytes/s 196 * 101 150ns, 6.6 Mbytes/s 197 * 110 175ns, 5.7 Mbytes/s 198 * 111 200ns, 5.0 Mbytes/s 199 */ 200 201 /* 202 * real period: 203 */ 204 u_int8_t trm_clock_period[8] = { 205 /* nanosecond divided by 4 */ 206 12, /* 48 ns 20 MB/sec */ 207 18, /* 72 ns 13.3 MB/sec */ 208 25, /* 100 ns 10.0 MB/sec */ 209 31, /* 124 ns 8.0 MB/sec */ 210 37, /* 148 ns 6.6 MB/sec */ 211 43, /* 172 ns 5.7 MB/sec */ 212 50, /* 200 ns 5.0 MB/sec */ 213 62 /* 248 ns 4.0 MB/sec */ 214 }; 215 216 /* 217 * ------------------------------------------------------------ 218 * Function : trm_srb_alloc 219 * Purpose : Get the first free SRB 220 * Inputs : 221 * Return : NULL or a free SCSI Request block 222 * ------------------------------------------------------------ 223 */ 224 void * 225 trm_srb_alloc(void *xsc) 226 { 227 struct trm_softc *sc = xsc; 228 struct trm_scsi_req_q *pSRB; 229 230 mtx_enter(&sc->sc_srb_mtx); 231 pSRB = TAILQ_FIRST(&sc->freeSRB); 232 if (pSRB != NULL) 233 TAILQ_REMOVE(&sc->freeSRB, pSRB, link); 234 mtx_leave(&sc->sc_srb_mtx); 235 236 #ifdef TRM_DEBUG0 237 printf("%s: trm_srb_alloc. pSRB = %p, next pSRB = %p\n", 238 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB)); 239 #endif 240 241 return pSRB; 242 } 243 244 /* 245 * ------------------------------------------------------------ 246 * Function : trm_RewaitSRB 247 * Purpose : Q back to pending Q 248 * Inputs : struct trm_dcb * - 249 * struct trm_scsi_req_q * - 250 * ------------------------------------------------------------ 251 */ 252 void 253 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 254 { 255 int intflag; 256 257 intflag = splbio(); 258 259 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 260 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 261 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 262 } 263 264 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 265 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 266 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 267 } 268 269 pSRB->SRBState = TRM_READY; 270 pSRB->TargetStatus = SCSI_OK; 271 pSRB->AdaptStatus = TRM_STATUS_GOOD; 272 273 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 274 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 275 276 splx(intflag); 277 } 278 279 /* 280 * ------------------------------------------------------------ 281 * Function : trm_StartWaitingSRB 282 * Purpose : If there is no active DCB then run robin through 283 * the DCB's to find the next waiting SRB 284 * and move it to the going list. 285 * Inputs : struct trm_softc * - 286 * ------------------------------------------------------------ 287 */ 288 void 289 trm_StartWaitingSRB(struct trm_softc *sc) 290 { 291 struct trm_scsi_req_q *pSRB, *next; 292 int intflag; 293 294 intflag = splbio(); 295 296 if ((sc->pActiveDCB != NULL) || 297 (TAILQ_EMPTY(&sc->waitingSRB)) || 298 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0) 299 goto out; 300 301 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) { 302 next = TAILQ_NEXT(pSRB, link); 303 if (trm_StartSRB(sc, pSRB) == 0) { 304 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 305 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 306 pSRB->SRBFlag |= TRM_ON_GOING_SRB; 307 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link); 308 break; 309 } 310 } 311 312 out: 313 splx(intflag); 314 } 315 316 /* 317 * ------------------------------------------------------------ 318 * Function : trm_scsi_cmd 319 * Purpose : enqueues a SCSI command 320 * Inputs : 321 * Call By : GENERIC SCSI driver 322 * ------------------------------------------------------------ 323 */ 324 void 325 trm_scsi_cmd(struct scsi_xfer *xs) 326 { 327 struct trm_scsi_req_q *pSRB; 328 bus_space_handle_t ioh; 329 struct trm_softc *sc; 330 bus_space_tag_t iot; 331 struct trm_dcb *pDCB; 332 u_int8_t target, lun; 333 int i, error, intflag, timeout, xferflags; 334 335 target = xs->sc_link->target; 336 lun = xs->sc_link->lun; 337 338 sc = (struct trm_softc *)xs->sc_link->adapter_softc; 339 ioh = sc->sc_iohandle; 340 iot = sc->sc_iotag; 341 342 #ifdef TRM_DEBUG0 343 if ((xs->flags & SCSI_POLL) != 0) { 344 sc_print_addr(xs->sc_link); 345 printf("trm_scsi_cmd. sc = %p, xs = %p, opcode = 0x%02x\n", 346 sc, xs, lun, xs->cmd->opcode); 347 } 348 #endif 349 350 if (target >= TRM_MAX_TARGETS) { 351 sc_print_addr(xs->sc_link); 352 printf("target >= %d\n", TRM_MAX_TARGETS); 353 xs->error = XS_DRIVER_STUFFUP; 354 scsi_done(xs); 355 return; 356 } 357 if (lun >= TRM_MAX_LUNS) { 358 sc_print_addr(xs->sc_link); 359 printf("lun >= %d\n", TRM_MAX_LUNS); 360 xs->error = XS_DRIVER_STUFFUP; 361 scsi_done(xs); 362 return; 363 } 364 365 pDCB = sc->pDCB[target][lun]; 366 if (pDCB == NULL) { 367 /* Removed as a result of INQUIRY proving no device present */ 368 xs->error = XS_DRIVER_STUFFUP; 369 scsi_done(xs); 370 return; 371 } 372 373 xferflags = xs->flags; 374 if (xferflags & SCSI_RESET) { 375 #ifdef TRM_DEBUG0 376 sc_print_addr(xs->sc_link); 377 printf("trm_reset via SCSI_RESET\n"); 378 #endif 379 trm_reset(sc); 380 xs->error = XS_NOERROR; 381 scsi_done(xs); 382 return; 383 } 384 385 pSRB = xs->io; 386 trm_srb_reinit(sc, pSRB); 387 388 xs->error = XS_NOERROR; 389 xs->status = SCSI_OK; 390 xs->resid = 0; 391 392 intflag = splbio(); 393 394 /* 395 * BuildSRB(pSRB,pDCB); 396 */ 397 if (xs->datalen != 0) { 398 #ifdef TRM_DEBUG0 399 sc_print_addr(xs->sc_link); 400 printf("xs->datalen=%x\n", (u_int32_t)xs->datalen); 401 sc_print_addr(xs->sc_link); 402 printf("sc->sc_dmatag=0x%x\n", (u_int32_t)sc->sc_dmatag); 403 sc_print_addr(xs->sc_link); 404 printf("pSRB->dmamapxfer=0x%x\n", (u_int32_t)pSRB->dmamapxfer); 405 sc_print_addr(xs->sc_link); 406 printf("xs->data=0x%x\n", (u_int32_t)xs->data); 407 #endif 408 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer, 409 xs->data, xs->datalen, NULL, 410 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : 411 BUS_DMA_WAITOK)) != 0) { 412 sc_print_addr(xs->sc_link); 413 printf("DMA transfer map unable to load, error = %d\n", 414 error); 415 xs->error = XS_DRIVER_STUFFUP; 416 splx(intflag); 417 scsi_done(xs); 418 return; 419 } 420 421 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 422 0, pSRB->dmamapxfer->dm_mapsize, 423 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 424 425 /* 426 * Set up the scatter gather list 427 */ 428 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) { 429 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr; 430 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len; 431 } 432 pSRB->SRBTotalXferLength = xs->datalen; 433 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs; 434 } 435 436 pSRB->pSRBDCB = pDCB; 437 pSRB->xs = xs; 438 pSRB->ScsiCmdLen = xs->cmdlen; 439 440 memcpy(pSRB->CmdBlock, xs->cmd, xs->cmdlen); 441 442 timeout_set(&xs->stimeout, trm_timeout, pSRB); 443 444 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 445 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link); 446 trm_StartWaitingSRB(sc); 447 448 if ((xferflags & SCSI_POLL) == 0) { 449 timeout_add_msec(&xs->stimeout, xs->timeout); 450 splx(intflag); 451 return; 452 } 453 454 splx(intflag); 455 for (timeout = xs->timeout; timeout > 0; timeout--) { 456 intflag = splbio(); 457 trm_Interrupt(sc); 458 splx(intflag); 459 if (ISSET(xs->flags, ITSDONE)) 460 break; 461 DELAY(1000); 462 } 463 464 if (!ISSET(xs->flags, ITSDONE) && timeout == 0) 465 trm_timeout(pSRB); 466 467 scsi_done(xs); 468 } 469 470 /* 471 * ------------------------------------------------------------ 472 * Function : trm_ResetAllDevParam 473 * Purpose : 474 * Inputs : struct trm_softc * 475 * ------------------------------------------------------------ 476 */ 477 void 478 trm_ResetAllDevParam(struct trm_softc *sc) 479 { 480 struct trm_adapter_nvram *pEEpromBuf; 481 int target, quirks; 482 483 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 484 485 for (target = 0; target < TRM_MAX_TARGETS; target++) { 486 if (target == sc->sc_AdaptSCSIID || sc->pDCB[target][0] == NULL) 487 continue; 488 489 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0) 490 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS; 491 else if (sc->pDCB[target][0]->sc_link != NULL) 492 quirks = sc->pDCB[target][0]->sc_link->quirks; 493 494 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks); 495 } 496 } 497 498 /* 499 * ------------------------------------------------------------ 500 * Function : trm_ResetDevParam 501 * Purpose : 502 * Inputs : 503 * ------------------------------------------------------------ 504 */ 505 void 506 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks) 507 { 508 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 509 u_int8_t PeriodIndex; 510 const int target = pDCB->target; 511 512 pDCB->DCBFlag &= TRM_QUIRKS_VALID; 513 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE); 514 515 pDCB->SyncPeriod = 0; 516 pDCB->SyncOffset = 0; 517 pDCB->MaxNegoPeriod = 0; 518 519 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0; 520 521 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0)); 522 523 if (((quirks & SDEV_NOWIDE) == 0) && 524 (pDCB->DevMode & TRM_WIDE) && 525 ((sc->sc_config & HCC_WIDE_CARD) != 0)) 526 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT; 527 528 if (((quirks & SDEV_NOSYNC) == 0) && 529 ((pDCB->DevMode & TRM_SYNC) != 0)) { 530 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07; 531 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex]; 532 } 533 534 if (((quirks & SDEV_NOTAGS) == 0) && 535 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) && 536 ((pDCB->DevMode & TRM_DISCONNECT) != 0)) 537 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */ 538 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING; 539 540 trm_SetXferParams(sc, pDCB, 0); 541 } 542 543 /* 544 * ------------------------------------------------------------ 545 * Function : trm_RecoverSRB 546 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs 547 * Inputs : struct trm_softc * - 548 * ------------------------------------------------------------ 549 */ 550 void 551 trm_RecoverSRB(struct trm_softc *sc) 552 { 553 struct trm_scsi_req_q *pSRB; 554 555 /* ASSUME we are inside splbio()/splx() */ 556 557 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 558 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 559 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 560 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 561 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 562 } 563 } 564 565 /* 566 * ------------------------------------------------------------ 567 * Function : trm_reset 568 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip). 569 * Inputs : 570 * ------------------------------------------------------------ 571 */ 572 void 573 trm_reset (struct trm_softc *sc) 574 { 575 const bus_space_handle_t ioh = sc->sc_iohandle; 576 const bus_space_tag_t iot = sc->sc_iotag; 577 int i, intflag; 578 579 intflag = splbio(); 580 581 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 582 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 583 584 trm_ResetSCSIBus(sc); 585 for (i = 0; i < 500; i++) 586 DELAY(1000); 587 588 /* 589 * Enable all SCSI interrupts except EN_SCAM 590 */ 591 bus_space_write_1(iot, ioh, 592 TRM_S1040_SCSI_INTEN, 593 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 594 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 595 /* 596 * Enable DMA interrupt 597 */ 598 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 599 /* 600 * Clear DMA FIFO 601 */ 602 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO); 603 /* 604 * Clear SCSI FIFO 605 */ 606 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 607 608 trm_ResetAllDevParam(sc); 609 trm_GoingSRB_Done(sc, NULL); 610 sc->pActiveDCB = NULL; 611 612 /* 613 * RESET_DETECT, RESET_DONE, RESET_DEV 614 */ 615 sc->sc_Flag = 0; 616 trm_StartWaitingSRB(sc); 617 618 splx(intflag); 619 } 620 621 /* 622 * ------------------------------------------------------------ 623 * Function : trm_timeout 624 * Purpose : Prints a timeout message and aborts the timed out SCSI request 625 * Inputs : void * - A struct trm_scsi_req_q * structure pointer 626 * ------------------------------------------------------------ 627 */ 628 void 629 trm_timeout(void *arg1) 630 { 631 struct trm_scsi_req_q *pSRB; 632 struct scsi_xfer *xs; 633 struct trm_softc *sc; 634 635 pSRB = (struct trm_scsi_req_q *)arg1; 636 xs = pSRB->xs; 637 638 if (xs != NULL) { 639 sc = xs->sc_link->adapter_softc; 640 sc_print_addr(xs->sc_link); 641 printf("SCSI OpCode 0x%02x ", xs->cmd->opcode); 642 if (pSRB->SRBFlag & TRM_AUTO_REQSENSE) 643 printf("REQUEST SENSE "); 644 printf("timed out\n"); 645 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 646 trm_FinishSRB(sc, pSRB); 647 #ifdef TRM_DEBUG0 648 sc_print_addr(xs->sc_link); 649 printf("trm_reset via trm_timeout()\n"); 650 #endif 651 trm_reset(sc); 652 trm_StartWaitingSRB(sc); 653 } 654 #ifdef TRM_DEBUG0 655 else 656 printf("%s: trm_timeout called with xs == NULL\n", 657 sc->sc_device.dv_xname); 658 #endif 659 } 660 661 /* 662 * ------------------------------------------------------------ 663 * Function : trm_StartSRB 664 * Purpose : Send the commands in the SRB to the device 665 * Inputs : struct trm_softc * - 666 * struct trm_scsi_req_q * - 667 * Return : 0 - SCSI processor is unoccupied 668 * 1 - SCSI processor is occupied with an SRB 669 * ------------------------------------------------------------ 670 */ 671 int 672 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 673 { 674 const bus_space_handle_t ioh = sc->sc_iohandle; 675 const bus_space_tag_t iot = sc->sc_iotag; 676 struct trm_dcb *pDCB = pSRB->pSRBDCB; 677 u_int32_t tag_mask; 678 u_int8_t tag_id, scsicommand; 679 680 #ifdef TRM_DEBUG0 681 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n", 682 sc->sc_device.dv_xname, sc, pDCB, pSRB); 683 #endif 684 /* 685 * If the queue is full or the SCSI processor has a pending interrupt 686 * then try again later. 687 */ 688 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh, 689 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT)) 690 return (1); 691 692 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 693 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target); 694 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 695 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 696 697 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) && 698 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) { 699 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID; 700 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks); 701 } 702 703 /* 704 * Flush FIFO 705 */ 706 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 707 708 sc->MsgCnt = 1; 709 sc->MsgBuf[0] = pDCB->IdentifyMsg; 710 if (((pSRB->xs->flags & SCSI_POLL) != 0) || 711 (pSRB->CmdBlock[0] == INQUIRY) || 712 (pSRB->CmdBlock[0] == REQUEST_SENSE)) 713 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG; 714 715 scsicommand = SCMD_SEL_ATN; 716 717 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) { 718 scsicommand = SCMD_SEL_ATNSTOP; 719 pSRB->SRBState = TRM_MSGOUT; 720 721 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) { 722 pDCB->DCBFlag |= TRM_QUEUE_FULL; 723 724 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) { 725 if (pSRB->TagNumber == TRM_NO_TAG) { 726 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1) 727 if ((tag_mask & pDCB->TagMask) == 0) { 728 pDCB->TagMask |= tag_mask; 729 pSRB->TagNumber = tag_id; 730 break; 731 } 732 733 if (tag_id >= 32) { 734 pDCB->DCBFlag |= TRM_QUEUE_FULL; 735 sc->MsgCnt = 0; 736 return 1; 737 } 738 } 739 740 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */ 741 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG; 742 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber; 743 744 scsicommand = SCMD_SEL_ATN3; 745 } 746 747 pSRB->SRBState = TRM_START; 748 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 749 sc->pActiveDCB = pDCB; 750 pDCB->pActiveSRB = pSRB; 751 752 if (sc->MsgCnt > 0) { 753 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]); 754 if (sc->MsgCnt > 1) { 755 DELAY(30); 756 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1); 757 } 758 sc->MsgCnt = 0; 759 } 760 761 /* 762 * it's important for atn stop 763 */ 764 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT); 765 /* 766 * SCSI command 767 */ 768 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand); 769 770 return 0; 771 } 772 773 /* 774 * ------------------------------------------------------------ 775 * Function : trm_Interrupt 776 * Purpose : Catch an interrupt from the adapter 777 * Process pending device interrupts. 778 * Inputs : void * - struct trm_softc * structure pointer 779 * ------------------------------------------------------------ 780 */ 781 int 782 trm_Interrupt(void *vsc) 783 { 784 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 785 struct trm_scsi_req_q *pSRB; 786 bus_space_handle_t ioh; 787 struct trm_softc *sc = (struct trm_softc *)vsc; 788 bus_space_tag_t iot; 789 u_int16_t phase; 790 u_int8_t scsi_status, scsi_intstatus; 791 792 if (sc == NULL) 793 return 0; 794 795 ioh = sc->sc_iohandle; 796 iot = sc->sc_iotag; 797 798 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS); 799 if (!(scsi_status & SCSIINTERRUPT)) 800 return 0; 801 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 802 803 #ifdef TRM_DEBUG0 804 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n", 805 sc->sc_device.dv_xname, scsi_status, scsi_intstatus); 806 #endif 807 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0) 808 trm_Disconnect(sc); 809 810 else if ((scsi_intstatus & INT_RESELECTED) != 0) 811 trm_Reselect(sc); 812 813 else if ((scsi_intstatus & INT_SCSIRESET) != 0) 814 trm_ScsiRstDetect(sc); 815 816 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) { 817 pSRB = sc->pActiveDCB->pActiveSRB; 818 /* 819 * software sequential machine 820 */ 821 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 822 /* 823 * 62037 or 62137 824 * call trm_SCSI_phase0[]... "phase entry" 825 * handle every phase before start transfer 826 */ 827 stateV = trm_SCSI_phase0[phase]; 828 stateV(sc, pSRB, &scsi_status); 829 /* 830 * if any exception occurred 831 * scsi_status will be modified to bus free phase 832 * new scsi_status transfer out from previous stateV 833 */ 834 /* 835 * phase:0,1,2,3,4,5,6,7 836 */ 837 pSRB->ScsiPhase = scsi_status & PHASEMASK; 838 phase = (u_int16_t) scsi_status & PHASEMASK; 839 /* 840 * call trm_SCSI_phase1[]... "phase entry" 841 * handle every phase do transfer 842 */ 843 stateV = trm_SCSI_phase1[phase]; 844 stateV(sc, pSRB, &scsi_status); 845 846 } else { 847 return 0; 848 } 849 850 return 1; 851 } 852 853 /* 854 * ------------------------------------------------------------ 855 * Function : trm_MsgOutPhase0 856 * Purpose : Check the state machine before sending a message out 857 * Inputs : struct trm_softc * - 858 * struct trm_scsi_req_q * - 859 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready 860 * ------------------------------------------------------------ 861 */ 862 void 863 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 864 { 865 switch (pSRB->SRBState) { 866 case TRM_UNEXPECT_RESEL: 867 case TRM_ABORT_SENT: 868 *pscsi_status = PH_BUS_FREE; /* initial phase */ 869 break; 870 871 default: 872 break; 873 } 874 } 875 876 /* 877 * ------------------------------------------------------------ 878 * Function : trm_MsgOutPhase1 879 * Purpose : Write the message out to the bus 880 * Inputs : struct trm_softc * - 881 * struct trm_scsi_req_q * - 882 * u_int8_t * - unused 883 * ------------------------------------------------------------ 884 */ 885 void 886 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 887 { 888 const bus_space_handle_t ioh = sc->sc_iohandle; 889 const bus_space_tag_t iot = sc->sc_iotag; 890 struct trm_dcb *pDCB = sc->pActiveDCB; 891 892 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 893 894 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) { 895 /* 896 * WIDE DATA TRANSFER REQUEST code (03h) 897 */ 898 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 899 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO; 900 901 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 902 sc->MsgBuf[1] = MSG_EXTENDED; 903 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN; 904 sc->MsgBuf[3] = MSG_EXT_WDTR; 905 906 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 907 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT; 908 else 909 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 910 911 sc->MsgCnt = 5; 912 913 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 914 915 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE; 916 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO; 917 918 sc->MsgCnt = 0; 919 920 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0) 921 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 922 923 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED; 924 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN; 925 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR; 926 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod; 927 928 if (pDCB->MaxNegoPeriod > 0) 929 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET; 930 else 931 sc->MsgBuf[sc->MsgCnt++] = 0; 932 } 933 934 if (sc->MsgCnt > 0) { 935 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt); 936 if (sc->MsgBuf[0] == MSG_ABORT) 937 pSRB->SRBState = TRM_ABORT_SENT; 938 sc->MsgCnt = 0; 939 } 940 /* 941 * it's important for atn stop 942 */ 943 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 944 /* 945 * Transfer information out 946 */ 947 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 948 } 949 950 /* 951 * ------------------------------------------------------------ 952 * Function : trm_CommandPhase1 953 * Purpose : Send commands to bus 954 * Inputs : 955 * ------------------------------------------------------------ 956 */ 957 void 958 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 959 { 960 const bus_space_handle_t ioh = sc->sc_iohandle; 961 const bus_space_tag_t iot = sc->sc_iotag; 962 963 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 964 965 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen); 966 967 pSRB->SRBState = TRM_COMMAND; 968 /* 969 * it's important for atn stop 970 */ 971 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 972 /* 973 * Transfer information out 974 */ 975 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 976 } 977 978 /* 979 * ------------------------------------------------------------ 980 * Function : trm_DataOutPhase0 981 * Purpose : Ready for Data Out, clear FIFO 982 * Inputs : u_int8_t * - SCSI status, used but not set 983 * ------------------------------------------------------------ 984 */ 985 void 986 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 987 { 988 const bus_space_handle_t ioh = sc->sc_iohandle; 989 const bus_space_tag_t iot = sc->sc_iotag; 990 struct SGentry *pseg; 991 struct trm_dcb *pDCB; 992 u_int32_t dLeftCounter, TempSRBXferredLength; 993 u_int16_t scsi_status; 994 u_int8_t TempDMAstatus, SGIndexTemp; 995 996 dLeftCounter = 0; 997 998 pDCB = pSRB->pSRBDCB; 999 scsi_status = *pscsi_status; 1000 1001 if (pSRB->SRBState != TRM_XFERPAD) { 1002 if ((scsi_status & PARITYERROR) != 0) 1003 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1004 if ((scsi_status & SCSIXFERDONE) == 0) { 1005 /* 1006 * when data transfer from DMA FIFO to SCSI FIFO 1007 * if there was some data left in SCSI FIFO 1008 */ 1009 dLeftCounter = (u_int32_t)(bus_space_read_1( 1010 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F); 1011 if (pDCB->SyncPeriod & WIDE_SYNC) { 1012 /* 1013 * if WIDE scsi SCSI FIFOCNT unit is word 1014 * so need to * 2 1015 */ 1016 dLeftCounter <<= 1; 1017 } 1018 } 1019 /* 1020 * calculate all the residue data that not yet transferred 1021 * SCSI transfer counter + left in SCSI FIFO data 1022 * 1023 * .....TRM_S1040_SCSI_COUNTER (24bits) 1024 * The counter always decrement by one for every SCSI byte 1025 * transfer. 1026 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits) 1027 * The counter is SCSI FIFO offset counter 1028 */ 1029 dLeftCounter += bus_space_read_4(iot, ioh, 1030 TRM_S1040_SCSI_COUNTER); 1031 if (dLeftCounter == 1) { 1032 dLeftCounter = 0; 1033 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1034 DO_CLRFIFO); 1035 } 1036 if (dLeftCounter == 0 || 1037 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1038 TempDMAstatus = bus_space_read_1(iot, 1039 ioh, TRM_S1040_DMA_STATUS); 1040 while ((TempDMAstatus & DMAXFERCOMP) == 0) { 1041 TempDMAstatus = bus_space_read_1(iot, 1042 ioh, TRM_S1040_DMA_STATUS); 1043 } 1044 pSRB->SRBTotalXferLength = 0; 1045 } else { 1046 /* 1047 * Update SG list 1048 */ 1049 /* 1050 * if transfer not yet complete 1051 * there were some data residue in SCSI FIFO or 1052 * SCSI transfer counter not empty 1053 */ 1054 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1055 /* 1056 * data that had transferred length 1057 */ 1058 TempSRBXferredLength = pSRB->SRBTotalXferLength 1059 - dLeftCounter; 1060 /* 1061 * next time to be transferred length 1062 */ 1063 pSRB->SRBTotalXferLength = dLeftCounter; 1064 /* 1065 * parsing from last time disconnect SRBSGIndex 1066 */ 1067 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1068 for (SGIndexTemp = pSRB->SRBSGIndex; 1069 SGIndexTemp < pSRB->SRBSGCount; 1070 SGIndexTemp++) { 1071 /* 1072 * find last time which SG transfer be 1073 * disconnect 1074 */ 1075 if (TempSRBXferredLength >= pseg->length) 1076 TempSRBXferredLength -= pseg->length; 1077 else { 1078 /* 1079 * update last time disconnected 1080 * SG list 1081 */ 1082 /* 1083 * residue data length 1084 */ 1085 pseg->length -= 1086 TempSRBXferredLength; 1087 /* 1088 * residue data pointer 1089 */ 1090 pseg->address += 1091 TempSRBXferredLength; 1092 pSRB->SRBSGIndex = SGIndexTemp; 1093 break; 1094 } 1095 pseg++; 1096 } 1097 } 1098 } 1099 } 1100 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 1101 } 1102 1103 /* 1104 * ------------------------------------------------------------ 1105 * Function : trm_DataOutPhase1 1106 * Purpose : Transfers data out, calls trm_DataIO_transfer 1107 * Inputs : 1108 * ------------------------------------------------------------ 1109 */ 1110 void 1111 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1112 { 1113 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT); 1114 } 1115 1116 /* 1117 * ------------------------------------------------------------ 1118 * Function : trm_DataInPhase0 1119 * Purpose : Prepare for reading data in from bus 1120 * Inputs : 1121 * ------------------------------------------------------------ 1122 */ 1123 void 1124 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1125 { 1126 const bus_space_handle_t ioh = sc->sc_iohandle; 1127 const bus_space_tag_t iot = sc->sc_iotag; 1128 struct SGentry *pseg; 1129 u_int32_t TempSRBXferredLength, dLeftCounter; 1130 u_int16_t scsi_status; 1131 u_int8_t SGIndexTemp; 1132 1133 dLeftCounter = 0; 1134 1135 scsi_status = *pscsi_status; 1136 if (pSRB->SRBState != TRM_XFERPAD) { 1137 if ((scsi_status & PARITYERROR) != 0) 1138 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1139 dLeftCounter += bus_space_read_4(iot, ioh, 1140 TRM_S1040_SCSI_COUNTER); 1141 if (dLeftCounter == 0 || 1142 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1143 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0) 1144 ; 1145 pSRB->SRBTotalXferLength = 0; 1146 } else { 1147 /* 1148 * phase changed 1149 * 1150 * parsing the case: 1151 * when a transfer not yet complete 1152 * but be disconnected by uper layer 1153 * if transfer not yet complete 1154 * there were some data residue in SCSI FIFO or 1155 * SCSI transfer counter not empty 1156 */ 1157 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1158 /* 1159 * data that had transferred length 1160 */ 1161 TempSRBXferredLength = pSRB->SRBTotalXferLength 1162 - dLeftCounter; 1163 /* 1164 * next time to be transferred length 1165 */ 1166 pSRB->SRBTotalXferLength = dLeftCounter; 1167 /* 1168 * parsing from last time disconnect SRBSGIndex 1169 */ 1170 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1171 for (SGIndexTemp = pSRB->SRBSGIndex; 1172 SGIndexTemp < pSRB->SRBSGCount; 1173 SGIndexTemp++) { 1174 /* 1175 * find last time which SG transfer be 1176 * disconnect 1177 */ 1178 if (TempSRBXferredLength >= 1179 pseg->length) { 1180 TempSRBXferredLength -= pseg->length; 1181 } else { 1182 /* 1183 * update last time disconnected 1184 * SG list 1185 * 1186 * residue data length 1187 */ 1188 pseg->length -= TempSRBXferredLength; 1189 /* 1190 * residue data pointer 1191 */ 1192 pseg->address += TempSRBXferredLength; 1193 pSRB->SRBSGIndex = SGIndexTemp; 1194 break; 1195 } 1196 pseg++; 1197 } 1198 } 1199 } 1200 } 1201 } 1202 1203 /* 1204 * ------------------------------------------------------------ 1205 * Function : trm_DataInPhase1 1206 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer 1207 * Inputs : 1208 * ------------------------------------------------------------ 1209 */ 1210 void 1211 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1212 { 1213 trm_DataIO_transfer(sc, pSRB, XFERDATAIN); 1214 } 1215 1216 /* 1217 * ------------------------------------------------------------ 1218 * Function : trm_DataIO_transfer 1219 * Purpose : 1220 * Inputs : 1221 * ------------------------------------------------------------ 1222 */ 1223 void 1224 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir) 1225 { 1226 const bus_space_handle_t ioh = sc->sc_iohandle; 1227 const bus_space_tag_t iot = sc->sc_iotag; 1228 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1229 u_int8_t bval; 1230 1231 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1232 if (pSRB->SRBTotalXferLength != 0) { 1233 /* 1234 * load what physical address of Scatter/Gather list 1235 * table want to be transfer 1236 */ 1237 pSRB->SRBState = TRM_DATA_XFER; 1238 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0); 1239 bus_space_write_4(iot, ioh, 1240 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr + 1241 ((u_int32_t)pSRB->SRBSGIndex << 3))); 1242 /* 1243 * load how many bytes in the Scatter/Gather list table 1244 */ 1245 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT, 1246 ((u_int32_t)(pSRB->SRBSGCount - 1247 pSRB->SRBSGIndex) << 3)); 1248 /* 1249 * load total transfer length (24bits, 1250 * pSRB->SRBTotalXferLength) max value 16Mbyte 1251 */ 1252 bus_space_write_4(iot, ioh, 1253 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength); 1254 /* 1255 * Start DMA transfer 1256 */ 1257 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir); 1258 /* bus_space_write_2(iot, ioh, 1259 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/ 1260 /* 1261 * Set the transfer bus and direction 1262 */ 1263 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN; 1264 } else { 1265 /* 1266 * xfer pad 1267 */ 1268 if (pSRB->SRBSGCount) 1269 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN; 1270 1271 if (pDCB->SyncPeriod & WIDE_SYNC) { 1272 bus_space_write_4(iot, ioh, 1273 TRM_S1040_SCSI_COUNTER, 2); 1274 } else { 1275 bus_space_write_4(iot, ioh, 1276 TRM_S1040_SCSI_COUNTER, 1); 1277 } 1278 1279 if (ioDir == XFERDATAOUT) { 1280 bus_space_write_2(iot, 1281 ioh, TRM_S1040_SCSI_FIFO, 0); 1282 } else { 1283 bus_space_read_2(iot, 1284 ioh, TRM_S1040_SCSI_FIFO); 1285 } 1286 pSRB->SRBState = TRM_XFERPAD; 1287 /* 1288 * Set the transfer bus and direction 1289 */ 1290 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN; 1291 } 1292 /* 1293 * it's important for atn stop 1294 */ 1295 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1296 /* 1297 * Tell the bus to do the transfer 1298 */ 1299 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval); 1300 } 1301 } 1302 1303 /* 1304 * ------------------------------------------------------------ 1305 * Function : trm_StatusPhase0 1306 * Purpose : Update Target Status with data from SCSI FIFO 1307 * Inputs : u_int8_t * - Set to PH_BUS_FREE 1308 * ------------------------------------------------------------ 1309 */ 1310 void 1311 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1312 { 1313 const bus_space_handle_t ioh = sc->sc_iohandle; 1314 const bus_space_tag_t iot = sc->sc_iotag; 1315 1316 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1317 1318 pSRB->SRBState = TRM_COMPLETED; 1319 /* 1320 * initial phase 1321 */ 1322 *pscsi_status = PH_BUS_FREE; 1323 /* 1324 * it's important for atn stop 1325 */ 1326 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1327 /* 1328 * Tell bus that the message was accepted 1329 */ 1330 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1331 } 1332 1333 /* 1334 * ------------------------------------------------------------ 1335 * Function : trm_StatusPhase1 1336 * Purpose : Clear FIFO of DMA and SCSI 1337 * Inputs : 1338 * ------------------------------------------------------------ 1339 */ 1340 void 1341 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1342 { 1343 const bus_space_handle_t ioh = sc->sc_iohandle; 1344 const bus_space_tag_t iot = sc->sc_iotag; 1345 1346 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) { 1347 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40) 1348 == 0) { 1349 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1350 DO_CLRFIFO); 1351 } 1352 if ((bus_space_read_2(iot, ioh, 1353 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1354 bus_space_write_1(iot, ioh, 1355 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1356 } 1357 } else { 1358 if ((bus_space_read_2(iot, ioh, 1359 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1360 bus_space_write_1(iot, ioh, 1361 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1362 } 1363 if ((bus_space_read_1(iot, ioh, 1364 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) { 1365 bus_space_write_2(iot, ioh, 1366 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1367 } 1368 } 1369 pSRB->SRBState = TRM_STATUS; 1370 /* 1371 * it's important for atn stop 1372 */ 1373 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1374 /* 1375 * Tell the bus that the command is complete 1376 */ 1377 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP); 1378 } 1379 1380 /* 1381 * ------------------------------------------------------------ 1382 * Function : trm_MsgInPhase0 1383 * Purpose : 1384 * Inputs : 1385 * 1386 * extended message codes: 1387 * code description 1388 * ---- ----------- 1389 * 02h Reserved 1390 * 00h MODIFY DATA POINTER 1391 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1392 * 03h WIDE DATA TRANSFER REQUEST 1393 * 04h - 7Fh Reserved 1394 * 80h - FFh Vendor specific 1395 * 1396 * ------------------------------------------------------------ 1397 */ 1398 void 1399 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1400 { 1401 const bus_space_handle_t ioh = sc->sc_iohandle; 1402 const bus_space_tag_t iot = sc->sc_iotag; 1403 struct trm_dcb *pDCB; 1404 u_int8_t message_in_code, bIndex, message_in_tag_id; 1405 1406 pDCB = sc->pActiveDCB; 1407 1408 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1409 1410 if (pSRB->SRBState != TRM_EXTEND_MSGIN) { 1411 switch (message_in_code) { 1412 case MSG_DISCONNECT: 1413 pSRB->SRBState = TRM_DISCONNECTED; 1414 break; 1415 1416 case MSG_EXTENDED: 1417 case MSG_SIMPLE_Q_TAG: 1418 case MSG_HEAD_OF_Q_TAG: 1419 case MSG_ORDERED_Q_TAG: 1420 pSRB->SRBState = TRM_EXTEND_MSGIN; 1421 /* 1422 * extended message (01h) 1423 */ 1424 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf)); 1425 sc->MsgBuf[0] = message_in_code; 1426 sc->MsgCnt = 1; 1427 /* 1428 * extended message length (n) 1429 */ 1430 break; 1431 1432 case MSG_MESSAGE_REJECT: 1433 /* 1434 * Reject message 1435 */ 1436 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) { 1437 /* 1438 * do wide nego reject 1439 */ 1440 pDCB = pSRB->pSRBDCB; 1441 1442 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO; 1443 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1444 1445 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 1446 /* 1447 * Set ATN, in case ATN was clear 1448 */ 1449 pSRB->SRBState = TRM_MSGOUT; 1450 bus_space_write_2(iot, ioh, 1451 TRM_S1040_SCSI_CONTROL, DO_SETATN); 1452 } else { 1453 /* 1454 * Clear ATN 1455 */ 1456 bus_space_write_2(iot, ioh, 1457 TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1458 } 1459 1460 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) { 1461 /* 1462 * do sync nego reject 1463 */ 1464 pDCB = pSRB->pSRBDCB; 1465 1466 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO; 1467 1468 pDCB->SyncPeriod = 0; 1469 pDCB->SyncOffset = 0; 1470 1471 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1472 goto re_prog; 1473 } 1474 break; 1475 1476 case MSG_IGN_WIDE_RESIDUE: 1477 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1478 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1479 break; 1480 1481 default: 1482 break; 1483 } 1484 1485 } else { 1486 1487 /* 1488 * We are collecting an extended message. Save the latest byte and then 1489 * check to see if the message is complete. If so, process it. 1490 */ 1491 sc->MsgBuf[sc->MsgCnt++] = message_in_code; 1492 #ifdef TRM_DEBUG0 1493 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 1494 sc->sc_device.dv_xname, 1495 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] ); 1496 #endif 1497 switch (sc->MsgBuf[0]) { 1498 case MSG_SIMPLE_Q_TAG: 1499 case MSG_HEAD_OF_Q_TAG: 1500 case MSG_ORDERED_Q_TAG: 1501 if (sc->MsgCnt == 2) { 1502 pSRB->SRBState = TRM_FREE; 1503 message_in_tag_id = sc->MsgBuf[1]; 1504 sc->MsgCnt = 0; 1505 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) { 1506 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id)) 1507 break; 1508 } 1509 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) { 1510 pDCB->pActiveSRB = pSRB; 1511 pSRB->SRBState = TRM_DATA_XFER; 1512 } else { 1513 #ifdef TRM_DEBUG0 1514 printf("%s: TRM_UNEXPECT_RESEL!\n", 1515 sc->sc_device.dv_xname); 1516 #endif 1517 pSRB = &sc->SRB[0]; 1518 trm_srb_reinit(sc, pSRB); 1519 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1520 pDCB->pActiveSRB = pSRB; 1521 trm_EnableMsgOut(sc, MSG_ABORT_TAG); 1522 } 1523 } 1524 break; 1525 1526 case MSG_EXTENDED: 1527 /* TODO XXXX: Correctly handling target initiated negotiations? */ 1528 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) { 1529 /* 1530 * ====================================== 1531 * WIDE DATA TRANSFER REQUEST 1532 * ====================================== 1533 * byte 0 : Extended message (01h) 1534 * byte 1 : Extended message length (02h) 1535 * byte 2 : WIDE DATA TRANSFER code (03h) 1536 * byte 3 : Transfer width exponent 1537 */ 1538 1539 pSRB->SRBState = TRM_FREE; 1540 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO); 1541 1542 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN) 1543 goto reject_offer; 1544 1545 switch (sc->MsgBuf[3]) { 1546 case MSG_EXT_WDTR_BUS_32_BIT: 1547 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 1548 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1549 else 1550 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT; 1551 break; 1552 1553 case MSG_EXT_WDTR_BUS_16_BIT: 1554 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) { 1555 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1556 break; 1557 } 1558 pDCB->SyncPeriod |= WIDE_SYNC; 1559 /* FALL THROUGH == ACCEPT OFFER */ 1560 1561 case MSG_EXT_WDTR_BUS_8_BIT: 1562 pSRB->SRBState = TRM_MSGOUT; 1563 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE); 1564 1565 if (pDCB->MaxNegoPeriod == 0) { 1566 pDCB->SyncPeriod = 0; 1567 pDCB->SyncOffset = 0; 1568 goto re_prog; 1569 } 1570 break; 1571 1572 default: 1573 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 1574 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1575 reject_offer: 1576 sc->MsgCnt = 1; 1577 sc->MsgBuf[0] = MSG_MESSAGE_REJECT; 1578 break; 1579 } 1580 1581 /* Echo accepted offer, or send revised offer */ 1582 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN); 1583 1584 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) { 1585 /* 1586 * ================================= 1587 * SYNCHRONOUS DATA TRANSFER REQUEST 1588 * ================================= 1589 * byte 0 : Extended message (01h) 1590 * byte 1 : Extended message length (03) 1591 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1592 * byte 3 : Transfer period factor 1593 * byte 4 : REQ/ACK offset 1594 */ 1595 1596 pSRB->SRBState = TRM_FREE; 1597 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO); 1598 1599 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN) 1600 goto reject_offer; 1601 1602 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) { 1603 /* 1604 * Asynchronous transfers 1605 */ 1606 pDCB->SyncPeriod = 0; 1607 pDCB->SyncOffset = 0; 1608 1609 } else { 1610 /* 1611 * Synchronous transfers 1612 */ 1613 /* 1614 * REQ/ACK offset 1615 */ 1616 pDCB->SyncOffset = sc->MsgBuf[4]; 1617 1618 for (bIndex = 0; bIndex < 7; bIndex++) 1619 if (sc->MsgBuf[3] <= trm_clock_period[bIndex]) 1620 break; 1621 1622 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 1623 } 1624 1625 re_prog: /* 1626 * program SCSI control register 1627 */ 1628 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1629 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1630 1631 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID)); 1632 } 1633 break; 1634 1635 default: 1636 break; 1637 } 1638 } 1639 1640 /* 1641 * initial phase 1642 */ 1643 *pscsi_status = PH_BUS_FREE; 1644 /* 1645 * it's important for atn stop 1646 */ 1647 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1648 /* 1649 * Tell bus that the message was accepted 1650 */ 1651 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1652 } 1653 1654 /* 1655 * ------------------------------------------------------------ 1656 * Function : trm_MsgInPhase1 1657 * Purpose : Clear the FIFO 1658 * Inputs : 1659 * ------------------------------------------------------------ 1660 */ 1661 void 1662 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1663 { 1664 const bus_space_handle_t ioh = sc->sc_iohandle; 1665 const bus_space_tag_t iot = sc->sc_iotag; 1666 1667 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1668 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1669 1670 /* 1671 * it's important for atn stop 1672 */ 1673 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1674 /* 1675 * SCSI command 1676 */ 1677 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN); 1678 } 1679 1680 /* 1681 * ------------------------------------------------------------ 1682 * Function : trm_Nop 1683 * Purpose : EMPTY 1684 * Inputs : 1685 * ------------------------------------------------------------ 1686 */ 1687 void 1688 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1689 { 1690 } 1691 1692 /* 1693 * ------------------------------------------------------------ 1694 * Function : trm_SetXferParams 1695 * Purpose : Set the Sync period, offset and mode for each device that has 1696 * the same target as the given one (struct trm_dcb *) 1697 * Inputs : 1698 * ------------------------------------------------------------ 1699 */ 1700 void 1701 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info) 1702 { 1703 struct trm_dcb *pDCBTemp; 1704 int lun, target; 1705 1706 /* 1707 * set all lun device's period, offset 1708 */ 1709 #ifdef TRM_DEBUG0 1710 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname); 1711 #endif 1712 1713 target = pDCB->target; 1714 for(lun = 0; lun < TRM_MAX_LUNS; lun++) { 1715 pDCBTemp = sc->pDCB[target][lun]; 1716 if (pDCBTemp != NULL) { 1717 pDCBTemp->DevMode = pDCB->DevMode; 1718 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod; 1719 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 1720 pDCBTemp->SyncOffset = pDCB->SyncOffset; 1721 pDCBTemp->DCBFlag = pDCB->DCBFlag; 1722 } 1723 } 1724 1725 if (print_info) 1726 trm_print_info(sc, pDCB); 1727 } 1728 1729 /* 1730 * ------------------------------------------------------------ 1731 * Function : trm_Disconnect 1732 * Purpose : 1733 * Inputs : 1734 * 1735 * ---SCSI bus phase 1736 * PH_DATA_OUT 0x00 Data out phase 1737 * PH_DATA_IN 0x01 Data in phase 1738 * PH_COMMAND 0x02 Command phase 1739 * PH_STATUS 0x03 Status phase 1740 * PH_BUS_FREE 0x04 Invalid phase used as bus free 1741 * PH_BUS_FREE 0x05 Invalid phase used as bus free 1742 * PH_MSG_OUT 0x06 Message out phase 1743 * PH_MSG_IN 0x07 Message in phase 1744 * ------------------------------------------------------------ 1745 */ 1746 void 1747 trm_Disconnect(struct trm_softc *sc) 1748 { 1749 const bus_space_handle_t ioh = sc->sc_iohandle; 1750 struct trm_scsi_req_q *pSRB; 1751 const bus_space_tag_t iot = sc->sc_iotag; 1752 struct trm_dcb *pDCB; 1753 int j; 1754 1755 #ifdef TRM_DEBUG0 1756 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname); 1757 #endif 1758 1759 pDCB = sc->pActiveDCB; 1760 if (pDCB == NULL) { 1761 /* TODO: Why use a loop? Why not use DELAY(400)? */ 1762 for(j = 400; j > 0; --j) 1763 DELAY(1); /* 1 msec */ 1764 bus_space_write_2(iot, ioh, 1765 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1766 return; 1767 } 1768 1769 pSRB = pDCB->pActiveSRB; 1770 sc->pActiveDCB = NULL; 1771 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1772 bus_space_write_2(iot, ioh, 1773 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1774 DELAY(100); 1775 1776 switch (pSRB->SRBState) { 1777 case TRM_UNEXPECT_RESEL: 1778 pSRB->SRBState = TRM_FREE; 1779 break; 1780 1781 case TRM_ABORT_SENT: 1782 trm_GoingSRB_Done(sc, pDCB); 1783 break; 1784 1785 case TRM_START: 1786 case TRM_MSGOUT: 1787 /* 1788 * Selection time out 1789 */ 1790 /* If not polling just keep trying until xs->stimeout expires */ 1791 if ((pSRB->xs->flags & SCSI_POLL) == 0) { 1792 trm_RewaitSRB(sc, pSRB); 1793 } else { 1794 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT; 1795 goto disc1; 1796 } 1797 break; 1798 1799 case TRM_COMPLETED: 1800 disc1: 1801 /* 1802 * TRM_COMPLETED - remove id from mask of active tags 1803 */ 1804 pDCB->pActiveSRB = NULL; 1805 trm_FinishSRB(sc, pSRB); 1806 break; 1807 1808 default: 1809 break; 1810 } 1811 1812 trm_StartWaitingSRB(sc); 1813 } 1814 1815 /* 1816 * ------------------------------------------------------------ 1817 * Function : trm_Reselect 1818 * Purpose : 1819 * Inputs : 1820 * ------------------------------------------------------------ 1821 */ 1822 void 1823 trm_Reselect(struct trm_softc *sc) 1824 { 1825 const bus_space_handle_t ioh = sc->sc_iohandle; 1826 const bus_space_tag_t iot = sc->sc_iotag; 1827 struct trm_scsi_req_q *pSRB; 1828 struct trm_dcb *pDCB; 1829 u_int16_t RselTarLunId; 1830 u_int8_t target, lun; 1831 1832 #ifdef TRM_DEBUG0 1833 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname); 1834 #endif 1835 1836 pDCB = sc->pActiveDCB; 1837 if (pDCB != NULL) { 1838 /* 1839 * Arbitration lost but Reselection win 1840 */ 1841 pSRB = pDCB->pActiveSRB; 1842 trm_RewaitSRB(sc, pSRB); 1843 } 1844 1845 /* 1846 * Read Reselected Target Id and LUN 1847 */ 1848 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF; 1849 /* TODO XXXX: Make endian independent! */ 1850 target = RselTarLunId & 0xff; 1851 lun = (RselTarLunId >> 8) & 0xff; 1852 1853 #ifdef TRM_DEBUG0 1854 printf("%s: reselect - target = %d, lun = %d\n", 1855 sc->sc_device.dv_xname, target, lun); 1856 #endif 1857 1858 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS)) 1859 pDCB = sc->pDCB[target][lun]; 1860 else 1861 pDCB = NULL; 1862 1863 if (pDCB == NULL) 1864 printf("%s: reselect - target = %d, lun = %d not found\n", 1865 sc->sc_device.dv_xname, target, lun); 1866 1867 sc->pActiveDCB = pDCB; 1868 1869 /* TODO XXXX: This will crash if pDCB is ever NULL */ 1870 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) { 1871 pSRB = &sc->SRB[0]; 1872 pDCB->pActiveSRB = pSRB; 1873 } else { 1874 pSRB = pDCB->pActiveSRB; 1875 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) { 1876 /* 1877 * abort command 1878 */ 1879 pSRB = &sc->SRB[0]; 1880 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1881 pDCB->pActiveSRB = pSRB; 1882 trm_EnableMsgOut(sc, MSG_ABORT); 1883 } else 1884 pSRB->SRBState = TRM_DATA_XFER; 1885 } 1886 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1887 1888 /* 1889 * Program HA ID, target ID, period and offset 1890 */ 1891 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target); 1892 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 1893 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1894 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1895 1896 /* 1897 * it's important for atn stop 1898 */ 1899 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1900 DELAY(30); 1901 1902 /* 1903 * SCSI command 1904 * to rls the /ACK signal 1905 */ 1906 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1907 } 1908 1909 /* 1910 * ------------------------------------------------------------ 1911 * Function : trm_FinishSRB 1912 * Purpose : Complete execution of a SCSI command 1913 * Inputs : 1914 * ------------------------------------------------------------ 1915 */ 1916 void 1917 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 1918 { 1919 struct scsi_inquiry_data *ptr; 1920 struct scsi_sense_data *s1, *s2; 1921 struct scsi_xfer *xs = pSRB->xs; 1922 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1923 int target, lun, intflag; 1924 1925 #ifdef TRM_DEBUG0 1926 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n", 1927 sc->sc_device.dv_xname, sc, pSRB); 1928 #endif 1929 pDCB->DCBFlag &= ~TRM_QUEUE_FULL; 1930 1931 intflag = splbio(); 1932 if (pSRB->TagNumber != TRM_NO_TAG) { 1933 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber); 1934 pSRB->TagNumber = TRM_NO_TAG; 1935 } 1936 /* SRB may have started & finished, or be waiting and timed out */ 1937 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 1938 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 1939 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 1940 } 1941 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 1942 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 1943 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 1944 } 1945 splx(intflag); 1946 1947 if (xs == NULL) { 1948 return; 1949 } 1950 1951 timeout_del(&xs->stimeout); 1952 1953 xs->status = pSRB->TargetStatus; 1954 if (xs->datalen != 0) { 1955 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 1956 0, pSRB->dmamapxfer->dm_mapsize, 1957 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1958 BUS_DMASYNC_POSTWRITE); 1959 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer); 1960 } 1961 1962 switch (xs->status) { 1963 case SCSI_INTERM_COND_MET: 1964 case SCSI_COND_MET: 1965 case SCSI_INTERM: 1966 case SCSI_OK: 1967 switch (pSRB->AdaptStatus) { 1968 case TRM_STATUS_GOOD: 1969 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) { 1970 #ifdef TRM_DEBUG0 1971 sc_print_addr(xs->sc_link); 1972 printf(" trm_FinishSRB. TRM_PARITY_ERROR\n"); 1973 #endif 1974 xs->error = XS_DRIVER_STUFFUP; 1975 1976 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) { 1977 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) == 0) 1978 xs->error = XS_TIMEOUT; 1979 else { 1980 bzero(&xs->sense, sizeof(xs->sense)); 1981 xs->status = SCSI_CHECK; 1982 xs->error = XS_SENSE; 1983 } 1984 1985 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) { 1986 s1 = &pSRB->scsisense; 1987 s2 = &xs->sense; 1988 1989 *s2 = *s1; 1990 1991 xs->status = SCSI_CHECK; 1992 xs->error = XS_SENSE; 1993 1994 } else 1995 xs->error = XS_NOERROR; 1996 break; 1997 1998 case TRM_OVER_UNDER_RUN: 1999 #ifdef TRM_DEBUG0 2000 sc_print_addr(xs->sc_link); 2001 printf("trm_FinishSRB. TRM_OVER_UNDER_RUN\n"); 2002 #endif 2003 xs->error = XS_DRIVER_STUFFUP; 2004 break; 2005 2006 default: 2007 #ifdef TRM_DEBUG0 2008 sc_print_addr(xs->sc_link); 2009 printf("trm_FinishSRB. AdaptStatus Error = 0x%02x\n", 2010 pSRB->AdaptStatus); 2011 #endif 2012 xs->error = XS_DRIVER_STUFFUP; 2013 break; 2014 } 2015 break; 2016 2017 case SCSI_TERMINATED: 2018 case SCSI_ACA_ACTIVE: 2019 case SCSI_CHECK: 2020 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) 2021 xs->error = XS_DRIVER_STUFFUP; 2022 else { 2023 trm_RequestSense(sc, pSRB); 2024 return; 2025 } 2026 break; 2027 2028 case SCSI_QUEUE_FULL: 2029 /* this says no more until someone completes */ 2030 pDCB->DCBFlag |= TRM_QUEUE_FULL; 2031 trm_RewaitSRB(sc, pSRB); 2032 return; 2033 2034 case SCSI_RESV_CONFLICT: 2035 case SCSI_BUSY: 2036 xs->error = XS_BUSY; 2037 break; 2038 2039 case TRM_SCSI_UNEXP_BUS_FREE: 2040 xs->status = SCSI_OK; 2041 xs->error = XS_DRIVER_STUFFUP; 2042 break; 2043 2044 case TRM_SCSI_BUS_RST_DETECTED: 2045 xs->status = SCSI_OK; 2046 xs->error = XS_RESET; 2047 break; 2048 2049 case TRM_SCSI_SELECT_TIMEOUT: 2050 xs->status = SCSI_OK; 2051 xs->error = XS_SELTIMEOUT; 2052 break; 2053 2054 default: 2055 xs->error = XS_DRIVER_STUFFUP; 2056 break; 2057 } 2058 2059 target = xs->sc_link->target; 2060 lun = xs->sc_link->lun; 2061 2062 if ((xs->flags & SCSI_POLL) != 0) { 2063 2064 if (xs->cmd->opcode == INQUIRY && pDCB->sc_link == NULL) { 2065 2066 ptr = (struct scsi_inquiry_data *) xs->data; 2067 2068 if ((xs->error != XS_NOERROR) || 2069 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) { 2070 #ifdef TRM_DEBUG0 2071 sc_print_addr(xs->sc_link); 2072 printf("trm_FinishSRB NO Device\n"); 2073 #endif 2074 free(pDCB, M_DEVBUF); 2075 sc->pDCB[target][lun] = NULL; 2076 pDCB = NULL; 2077 2078 } else 2079 pDCB->sc_link = xs->sc_link; 2080 } 2081 } 2082 2083 /* 2084 * Notify cmd done 2085 */ 2086 #ifdef TRM_DEBUG0 2087 if ((xs->error != 0) || (xs->status != 0) || ((xs->flags & SCSI_POLL) != 0)) 2088 sc_print_addr(xs->sc_link); 2089 printf("trm_FinishSRB. xs->cmd->opcode = 0x%02x, xs->error = %d, xs->status = %d\n", 2090 xs->cmd->opcode, xs->error, xs->status); 2091 #endif 2092 2093 if (ISSET(xs->flags, SCSI_POLL)) 2094 SET(xs->flags, ITSDONE); 2095 else 2096 scsi_done(xs); 2097 } 2098 2099 /* 2100 * ------------------------------------------------------------ 2101 * Function : trm_srb_reinit 2102 * Purpose : 2103 * Inputs : 2104 * ------------------------------------------------------------ 2105 */ 2106 void 2107 trm_srb_reinit(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2108 { 2109 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX)); 2110 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2111 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense)); 2112 2113 pSRB->SRBTotalXferLength = 0; 2114 pSRB->SRBSGCount = 0; 2115 pSRB->SRBSGIndex = 0; 2116 pSRB->SRBFlag = 0; 2117 2118 pSRB->SRBState = TRM_FREE; 2119 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2120 pSRB->TargetStatus = SCSI_OK; 2121 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 2122 2123 pSRB->xs = NULL; 2124 pSRB->pSRBDCB = NULL; 2125 } 2126 2127 /* 2128 * ------------------------------------------------------------ 2129 * Function : trm_srb_free 2130 * Purpose : 2131 * Inputs : 2132 * ------------------------------------------------------------ 2133 */ 2134 void 2135 trm_srb_free(void *xsc, void *xpSRB) 2136 { 2137 struct trm_softc *sc = xsc; 2138 struct trm_scsi_req_q *pSRB = xpSRB; 2139 2140 trm_srb_reinit(sc, pSRB); 2141 2142 if (pSRB != &sc->SRB[0]) { 2143 mtx_enter(&sc->sc_srb_mtx); 2144 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2145 mtx_leave(&sc->sc_srb_mtx); 2146 } 2147 } 2148 2149 /* 2150 * ------------------------------------------------------------ 2151 * Function : trm_GoingSRB_Done 2152 * Purpose : 2153 * Inputs : 2154 * ------------------------------------------------------------ 2155 */ 2156 void 2157 trm_GoingSRB_Done(struct trm_softc *sc, struct trm_dcb *pDCB) 2158 { 2159 struct trm_scsi_req_q *pSRB, *pNextSRB; 2160 2161 /* ASSUME we are inside a splbio()/splx() pair */ 2162 2163 pSRB = TAILQ_FIRST(&sc->goingSRB); 2164 while (pSRB != NULL) { 2165 /* 2166 * Need to save pNextSRB because trm_FinishSRB() puts 2167 * pSRB in freeSRB queue, and thus its links no longer 2168 * point to members of the goingSRB queue. This is why 2169 * TAILQ_FOREACH() will not work for this traversal. 2170 */ 2171 pNextSRB = TAILQ_NEXT(pSRB, link); 2172 if (pDCB == NULL || pSRB->pSRBDCB == pDCB) { 2173 /* TODO XXXX: Is TIMED_OUT the best state to report? */ 2174 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 2175 trm_FinishSRB(sc, pSRB); 2176 } 2177 pSRB = pNextSRB; 2178 } 2179 } 2180 2181 /* 2182 * ------------------------------------------------------------ 2183 * Function : trm_ResetSCSIBus 2184 * Purpose : Reset the SCSI bus 2185 * Inputs : struct trm_softc * - 2186 * ------------------------------------------------------------ 2187 */ 2188 void 2189 trm_ResetSCSIBus(struct trm_softc *sc) 2190 { 2191 const bus_space_handle_t ioh = sc->sc_iohandle; 2192 const bus_space_tag_t iot = sc->sc_iotag; 2193 int intflag; 2194 2195 intflag = splbio(); 2196 2197 sc->sc_Flag |= RESET_DEV; 2198 2199 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI); 2200 while ((bus_space_read_2(iot, ioh, 2201 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0); 2202 2203 splx(intflag); 2204 } 2205 2206 /* 2207 * ------------------------------------------------------------ 2208 * Function : trm_ScsiRstDetect 2209 * Purpose : 2210 * Inputs : 2211 * ------------------------------------------------------------ 2212 */ 2213 void 2214 trm_ScsiRstDetect(struct trm_softc *sc) 2215 { 2216 const bus_space_handle_t ioh = sc->sc_iohandle; 2217 const bus_space_tag_t iot = sc->sc_iotag; 2218 int wlval; 2219 2220 #ifdef TRM_DEBUG0 2221 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname); 2222 #endif 2223 2224 wlval = 1000; 2225 /* 2226 * delay 1 sec 2227 */ 2228 while (--wlval != 0) 2229 DELAY(1000); 2230 2231 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 2232 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 2233 2234 if ((sc->sc_Flag & RESET_DEV) != 0) 2235 sc->sc_Flag |= RESET_DONE; 2236 else { 2237 sc->sc_Flag |= RESET_DETECT; 2238 trm_ResetAllDevParam(sc); 2239 trm_RecoverSRB(sc); 2240 sc->pActiveDCB = NULL; 2241 sc->sc_Flag = 0; 2242 trm_StartWaitingSRB(sc); 2243 } 2244 } 2245 2246 /* 2247 * ------------------------------------------------------------ 2248 * Function : trm_RequestSense 2249 * Purpose : 2250 * Inputs : 2251 * ------------------------------------------------------------ 2252 */ 2253 void 2254 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2255 { 2256 pSRB->SRBFlag |= TRM_AUTO_REQSENSE; 2257 2258 /* 2259 * Status of initiator/target 2260 */ 2261 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2262 pSRB->TargetStatus = SCSI_OK; 2263 /* 2264 * Status of initiator/target 2265 */ 2266 2267 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr; 2268 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data); 2269 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data); 2270 pSRB->SRBSGCount = 1; 2271 pSRB->SRBSGIndex = 0; 2272 2273 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2274 2275 pSRB->CmdBlock[0] = REQUEST_SENSE; 2276 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5; 2277 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data); 2278 2279 pSRB->ScsiCmdLen = 6; 2280 2281 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0)) 2282 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout); 2283 2284 if (trm_StartSRB(sc, pSRB) != 0) 2285 trm_RewaitSRB(sc, pSRB); 2286 } 2287 2288 /* 2289 * ------------------------------------------------------------ 2290 * Function : trm_EnableMsgOut 2291 * Purpose : set up MsgBuf to send out a single byte message 2292 * Inputs : 2293 * ------------------------------------------------------------ 2294 */ 2295 void 2296 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg) 2297 { 2298 sc->MsgBuf[0] = msg; 2299 sc->MsgCnt = 1; 2300 2301 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN); 2302 } 2303 2304 /* 2305 * ------------------------------------------------------------ 2306 * Function : trm_linkSRB 2307 * Purpose : 2308 * Inputs : 2309 * ------------------------------------------------------------ 2310 */ 2311 void 2312 trm_linkSRB(struct trm_softc *sc) 2313 { 2314 struct trm_scsi_req_q *pSRB; 2315 int i, intflag; 2316 2317 intflag = splbio(); 2318 2319 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2320 pSRB = &sc->SRB[i]; 2321 2322 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr 2323 + i * sizeof(struct trm_scsi_req_q); 2324 2325 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2326 + i * sizeof(struct trm_scsi_req_q) 2327 + offsetof(struct trm_scsi_req_q, SegmentX); 2328 2329 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2330 + i * sizeof(struct trm_scsi_req_q) 2331 + offsetof(struct trm_scsi_req_q, scsisense); 2332 2333 /* 2334 * map all SRB space 2335 */ 2336 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE, 2337 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0, 2338 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2339 &pSRB->dmamapxfer) != 0) { 2340 printf("%s: unable to create DMA transfer map\n", 2341 sc->sc_device.dv_xname); 2342 splx(intflag); 2343 return; 2344 } 2345 2346 if (i > 0) 2347 /* We use sc->SRB[0] directly, so *don't* link it */ 2348 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2349 #ifdef TRM_DEBUG0 2350 printf("pSRB = %p ", pSRB); 2351 #endif 2352 } 2353 #ifdef TRM_DEBUG0 2354 printf("\n "); 2355 #endif 2356 splx(intflag); 2357 } 2358 2359 /* 2360 * ------------------------------------------------------------ 2361 * Function : trm_minphys 2362 * Purpose : limited by the number of segments in the dma segment list 2363 * Inputs : *buf 2364 * ------------------------------------------------------------ 2365 */ 2366 void 2367 trm_minphys(struct buf *bp, struct scsi_link *sl) 2368 { 2369 if (bp->b_bcount > (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG) { 2370 bp->b_bcount = (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG; 2371 } 2372 minphys(bp); 2373 } 2374 2375 /* 2376 * ------------------------------------------------------------ 2377 * Function : trm_initACB 2378 * Purpose : initialize the internal structures for a given SCSI host 2379 * Inputs : 2380 * ------------------------------------------------------------ 2381 */ 2382 void 2383 trm_initACB(struct trm_softc *sc, int unit) 2384 { 2385 const bus_space_handle_t ioh = sc->sc_iohandle; 2386 const bus_space_tag_t iot = sc->sc_iotag; 2387 struct trm_adapter_nvram *pEEpromBuf; 2388 struct trm_dcb *pDCB; 2389 int target, lun; 2390 2391 pEEpromBuf = &trm_eepromBuf[unit]; 2392 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2393 2394 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0) 2395 sc->sc_config |= HCC_WIDE_CARD; 2396 2397 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0) 2398 sc->sc_config |= HCC_SCSI_RESET; 2399 2400 TAILQ_INIT(&sc->freeSRB); 2401 TAILQ_INIT(&sc->waitingSRB); 2402 TAILQ_INIT(&sc->goingSRB); 2403 2404 mtx_init(&sc->sc_srb_mtx, IPL_BIO); 2405 scsi_iopool_init(&sc->sc_iopool, sc, trm_srb_alloc, trm_srb_free); 2406 2407 sc->pActiveDCB = NULL; 2408 sc->sc_AdapterUnit = unit; 2409 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId; 2410 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2411 sc->sc_Flag = 0; 2412 2413 /* 2414 * put all SRB's (except [0]) onto the freeSRB list 2415 */ 2416 trm_linkSRB(sc); 2417 2418 /* 2419 * allocate DCB array 2420 */ 2421 for (target = 0; target < TRM_MAX_TARGETS; target++) { 2422 if (target == sc->sc_AdaptSCSIID) 2423 continue; 2424 2425 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2426 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), 2427 M_DEVBUF, M_NOWAIT | M_ZERO); 2428 sc->pDCB[target][lun] = pDCB; 2429 2430 if (pDCB == NULL) 2431 continue; 2432 2433 pDCB->target = target; 2434 pDCB->lun = lun; 2435 pDCB->pActiveSRB = NULL; 2436 } 2437 } 2438 2439 sc->sc_adapter.scsi_cmd = trm_scsi_cmd; 2440 sc->sc_adapter.scsi_minphys = trm_minphys; 2441 2442 sc->sc_link.adapter_softc = sc; 2443 sc->sc_link.adapter_target = sc->sc_AdaptSCSIID; 2444 sc->sc_link.openings = 30; /* So TagMask (32 bit integer) always has space */ 2445 sc->sc_link.adapter = &sc->sc_adapter; 2446 sc->sc_link.adapter_buswidth = ((sc->sc_config & HCC_WIDE_CARD) == 0) ? 8:16; 2447 sc->sc_link.pool = &sc->sc_iopool; 2448 2449 trm_reset(sc); 2450 } 2451 2452 /* 2453 * ------------------------------------------------------------ 2454 * Function : trm_write_all 2455 * Description : write pEEpromBuf 128 bytes to seeprom 2456 * Input : iot, ioh - chip's base address 2457 * Output : none 2458 * ------------------------------------------------------------ 2459 */ 2460 void 2461 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2462 bus_space_handle_t ioh) 2463 { 2464 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2465 u_int8_t bAddr; 2466 2467 /* 2468 * Enable SEEPROM 2469 */ 2470 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2471 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2472 /* 2473 * Write enable 2474 */ 2475 trm_write_cmd(iot, ioh, 0x04, 0xFF); 2476 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2477 trm_wait_30us(iot, ioh); 2478 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2479 trm_set_data(iot, ioh, bAddr, *bpEeprom); 2480 /* 2481 * Write disable 2482 */ 2483 trm_write_cmd(iot, ioh, 0x04, 0x00); 2484 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2485 trm_wait_30us(iot, ioh); 2486 /* 2487 * Disable SEEPROM 2488 */ 2489 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2490 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2491 } 2492 2493 /* 2494 * ------------------------------------------------------------ 2495 * Function : trm_set_data 2496 * Description : write one byte to seeprom 2497 * Input : iot, ioh - chip's base address 2498 * bAddr - address of SEEPROM 2499 * bData - data of SEEPROM 2500 * Output : none 2501 * ------------------------------------------------------------ 2502 */ 2503 void 2504 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr, 2505 u_int8_t bData) 2506 { 2507 u_int8_t bSendData; 2508 int i; 2509 2510 /* 2511 * Send write command & address 2512 */ 2513 trm_write_cmd(iot, ioh, 0x05, bAddr); 2514 /* 2515 * Write data 2516 */ 2517 for (i = 0; i < 8; i++, bData <<= 1) { 2518 bSendData = NVR_SELECT; 2519 if ((bData & 0x80) != 0) { /* Start from bit 7 */ 2520 bSendData |= NVR_BITOUT; 2521 } 2522 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2523 trm_wait_30us(iot, ioh); 2524 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2525 (bSendData | NVR_CLOCK)); 2526 trm_wait_30us(iot, ioh); 2527 } 2528 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2529 trm_wait_30us(iot, ioh); 2530 /* 2531 * Disable chip select 2532 */ 2533 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2534 trm_wait_30us(iot, ioh); 2535 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2536 trm_wait_30us(iot, ioh); 2537 /* 2538 * Wait for write ready 2539 */ 2540 for (;;) { 2541 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2542 (NVR_SELECT | NVR_CLOCK)); 2543 trm_wait_30us(iot, ioh); 2544 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2545 trm_wait_30us(iot, ioh); 2546 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN) 2547 break; 2548 } 2549 /* 2550 * Disable chip select 2551 */ 2552 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2553 } 2554 2555 /* 2556 * ------------------------------------------------------------ 2557 * Function : trm_read_all 2558 * Description : read seeprom 128 bytes to pEEpromBuf 2559 * Input : pEEpromBuf, iot, ioh - chip's base address 2560 * Output : none 2561 * ------------------------------------------------------------ 2562 */ 2563 void 2564 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2565 bus_space_handle_t ioh) 2566 { 2567 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2568 u_int8_t bAddr; 2569 2570 /* 2571 * Enable SEEPROM 2572 */ 2573 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2574 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2575 2576 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2577 *bpEeprom = trm_get_data(iot, ioh, bAddr); 2578 2579 /* 2580 * Disable SEEPROM 2581 */ 2582 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2583 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2584 } 2585 2586 /* 2587 * ------------------------------------------------------------ 2588 * Function : trm_get_data 2589 * Description : read one byte from seeprom 2590 * Input : iot, ioh - chip's base address 2591 * bAddr - address of SEEPROM 2592 * Output : bData - data of SEEPROM 2593 * ------------------------------------------------------------ 2594 */ 2595 u_int8_t 2596 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr) 2597 { 2598 u_int8_t bReadData, bData; 2599 int i; 2600 2601 bData = 0; 2602 2603 /* 2604 * Send read command & address 2605 */ 2606 trm_write_cmd(iot, ioh, 0x06, bAddr); 2607 2608 for (i = 0; i < 8; i++) { 2609 /* 2610 * Read data 2611 */ 2612 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2613 (NVR_SELECT | NVR_CLOCK)); 2614 trm_wait_30us(iot, ioh); 2615 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2616 /* 2617 * Get data bit while falling edge 2618 */ 2619 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM); 2620 bData <<= 1; 2621 if ((bReadData & NVR_BITIN) != 0) 2622 bData |= 1; 2623 trm_wait_30us(iot, ioh); 2624 } 2625 /* 2626 * Disable chip select 2627 */ 2628 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2629 2630 return bData; 2631 } 2632 2633 /* 2634 * ------------------------------------------------------------ 2635 * Function : trm_wait_30us 2636 * Description : wait 30 us 2637 * Input : iot, ioh - chip's base address 2638 * Output : none 2639 * ------------------------------------------------------------ 2640 */ 2641 void 2642 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh) 2643 { 2644 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5); 2645 2646 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT) 2647 == 0); 2648 } 2649 2650 /* 2651 * ------------------------------------------------------------ 2652 * Function : trm_write_cmd 2653 * Description : write SB and Op Code into seeprom 2654 * Input : iot, ioh - chip's base address 2655 * bCmd - SB + Op Code 2656 * bAddr - address of SEEPROM 2657 * Output : none 2658 * ------------------------------------------------------------ 2659 */ 2660 void 2661 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd, 2662 u_int8_t bAddr) 2663 { 2664 u_int8_t bSendData; 2665 int i; 2666 2667 for (i = 0; i < 3; i++, bCmd <<= 1) { 2668 /* 2669 * Program SB + OP code 2670 */ 2671 bSendData = NVR_SELECT; 2672 if (bCmd & 0x04) /* Start from bit 2 */ 2673 bSendData |= NVR_BITOUT; 2674 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2675 trm_wait_30us(iot, ioh); 2676 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2677 (bSendData | NVR_CLOCK)); 2678 trm_wait_30us(iot, ioh); 2679 } 2680 2681 for (i = 0; i < 7; i++, bAddr <<= 1) { 2682 /* 2683 * Program address 2684 */ 2685 bSendData = NVR_SELECT; 2686 if (bAddr & 0x40) { /* Start from bit 6 */ 2687 bSendData |= NVR_BITOUT; 2688 } 2689 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2690 trm_wait_30us(iot, ioh); 2691 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2692 (bSendData | NVR_CLOCK)); 2693 trm_wait_30us(iot, ioh); 2694 } 2695 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2696 trm_wait_30us(iot, ioh); 2697 } 2698 2699 /* 2700 * ------------------------------------------------------------ 2701 * Function : trm_check_eeprom 2702 * Description : read eeprom 128 bytes to pEEpromBuf and check 2703 * checksum. If it is wrong, updated with default value. 2704 * Input : eeprom, iot, ioh - chip's base address 2705 * Output : none 2706 * ------------------------------------------------------------ 2707 */ 2708 void 2709 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2710 bus_space_handle_t ioh) 2711 { 2712 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget; 2713 u_int32_t dAddr; 2714 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf; 2715 u_int16_t wAddr, wCheckSum; 2716 2717 #ifdef TRM_DEBUG0 2718 printf("\ntrm_check_eeprom\n"); 2719 #endif 2720 trm_read_all(pEEpromBuf, iot, ioh); 2721 wCheckSum = 0; 2722 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++) 2723 wCheckSum += *wpEeprom; 2724 2725 if (wCheckSum != 0x1234) { 2726 #ifdef TRM_DEBUG0 2727 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n"); 2728 #endif 2729 /* 2730 * Checksum error, load default 2731 */ 2732 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2733 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2734 >> 8); 2735 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) 2736 PCI_PRODUCT_TEKRAM2_DC3X5U; 2737 pEEpromBuf->NvramSubSysID[1] = (u_int8_t) 2738 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2739 pEEpromBuf->NvramSubClass = 0; 2740 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2741 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2742 >> 8); 2743 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) 2744 PCI_PRODUCT_TEKRAM2_DC3X5U; 2745 pEEpromBuf->NvramDeviceID[1] = (u_int8_t) 2746 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2747 pEEpromBuf->NvramReserved = 0; 2748 2749 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++) 2750 /* 2751 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 2752 */ 2753 *dpEeprom = 0x00000077; 2754 2755 /* 2756 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId 2757 */ 2758 *dpEeprom++ = 0x04000F07; 2759 2760 /* 2761 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 2762 */ 2763 *dpEeprom++ = 0x00000015; 2764 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 2765 *dpEeprom = 0; 2766 2767 pEEpromBuf->NvramCheckSum = 0; 2768 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++) 2769 wCheckSum += *wpEeprom; 2770 2771 *wpEeprom = 0x1234 - wCheckSum; 2772 trm_write_all(pEEpromBuf, iot, ioh); 2773 } 2774 } 2775 2776 /* 2777 * ------------------------------------------------------------ 2778 * Function : trm_initAdapter 2779 * Purpose : initialize the SCSI chip ctrl registers 2780 * Inputs : psh - pointer to this host adapter's structure 2781 * ------------------------------------------------------------ 2782 */ 2783 void 2784 trm_initAdapter(struct trm_softc *sc) 2785 { 2786 const bus_space_handle_t ioh = sc->sc_iohandle; 2787 const bus_space_tag_t iot = sc->sc_iotag; 2788 u_int16_t wval; 2789 u_int8_t bval; 2790 2791 /* 2792 * program configuration 0 2793 */ 2794 if ((sc->sc_config & HCC_PARITY) != 0) { 2795 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 2796 } else { 2797 bval = PHASELATCH | INITIATOR | BLOCKRST; 2798 } 2799 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval); 2800 /* 2801 * program configuration 1 2802 */ 2803 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13); 2804 /* 2805 * 250ms selection timeout 2806 */ 2807 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT); 2808 /* 2809 * Mask all the interrupt 2810 */ 2811 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 2812 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 2813 /* 2814 * Reset SCSI module 2815 */ 2816 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE); 2817 /* 2818 * program Host ID 2819 */ 2820 bval = sc->sc_AdaptSCSIID; 2821 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval); 2822 /* 2823 * set ansynchronous transfer 2824 */ 2825 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0); 2826 /* 2827 * Turn LED control off 2828 */ 2829 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F; 2830 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval); 2831 /* 2832 * DMA config 2833 */ 2834 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE; 2835 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval); 2836 /* 2837 * Clear pending interrupt status 2838 */ 2839 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 2840 /* 2841 * Enable SCSI interrupts 2842 */ 2843 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 2844 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 2845 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 2846 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 2847 } 2848 2849 /* 2850 * ------------------------------------------------------------ 2851 * Function : trm_init 2852 * Purpose : initialize the internal structures for a given SCSI host 2853 * Inputs : host - pointer to this host adapter's structure 2854 * Preconditions : when this function is called, the chip_type field of 2855 * the ACB structure MUST have been set. 2856 * ------------------------------------------------------------ 2857 */ 2858 int 2859 trm_init(struct trm_softc *sc, int unit) 2860 { 2861 const bus_space_handle_t ioh = sc->sc_iohandle; 2862 const bus_space_tag_t iot = sc->sc_iotag; 2863 bus_dma_segment_t seg; 2864 int error, rseg, all_srbs_size; 2865 2866 /* 2867 * EEPROM CHECKSUM 2868 */ 2869 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh); 2870 2871 /* 2872 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 2873 */ 2874 /* 2875 * allocate the space for all SCSI control blocks (SRB) for DMA memory. 2876 */ 2877 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q); 2878 2879 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg, 2880 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 2881 if (error != 0) { 2882 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n", 2883 sc->sc_device.dv_xname, error); 2884 /*errx(error, "%s: unable to allocate SCSI request blocks", 2885 sc->sc_device.dv_xname);*/ 2886 return -1; 2887 } 2888 2889 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size, 2890 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 2891 if (error != 0) { 2892 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n", 2893 sc->sc_device.dv_xname, error); 2894 /*errx(error, "unable to map SCSI request blocks");*/ 2895 return -1; 2896 } 2897 2898 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1, 2899 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control); 2900 if (error != 0) { 2901 printf("%s: unable to create SRB DMA maps, error = %d\n", 2902 sc->sc_device.dv_xname, error); 2903 /*errx(error, "unable to create SRB DMA maps");*/ 2904 return -1; 2905 } 2906 2907 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control, 2908 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT); 2909 if (error != 0) { 2910 printf("%s: unable to load SRB DMA maps, error = %d\n", 2911 sc->sc_device.dv_xname, error); 2912 /*errx(error, "unable to load SRB DMA maps");*/ 2913 return -1; 2914 } 2915 #ifdef TRM_DEBUG0 2916 printf("\n\n%s: all_srbs_size=%x\n", 2917 sc->sc_device.dv_xname, all_srbs_size); 2918 #endif 2919 trm_initACB(sc, unit); 2920 trm_initAdapter(sc); 2921 2922 return 0; 2923 } 2924 2925 /* ------------------------------------------------------------ 2926 * Function : trm_print_info 2927 * Purpose : Print the DCB negotiation information 2928 * Inputs : 2929 * ------------------------------------------------------------ 2930 */ 2931 void 2932 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB) 2933 { 2934 int syncXfer, index; 2935 2936 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC); 2937 2938 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target); 2939 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0) 2940 printf("16 bit "); 2941 else 2942 printf("8 bit "); 2943 2944 if (pDCB->SyncOffset == 0) 2945 printf("Asynchronous "); 2946 else { 2947 syncXfer = 100000 / (trm_clock_period[index] * 4); 2948 printf("%d.%01d MHz, Offset %d ", 2949 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset); 2950 } 2951 printf("data transfers "); 2952 2953 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) 2954 printf("with Tag Queuing"); 2955 2956 printf("\n"); 2957 } 2958