1 /* $OpenBSD: smc91cxx.c,v 1.48 2016/07/13 15:40:26 deraadt Exp $ */ 2 /* $NetBSD: smc91cxx.c,v 1.11 1998/08/08 23:51:41 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Gardner Buchanan. 49 * 4. The name of Gardner Buchanan may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 65 */ 66 67 /* 68 * Core driver for the SMC 91Cxx family of Ethernet chips. 69 * 70 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 71 * written for NetBSD/amiga by Michael Hitch. 72 */ 73 74 #include "bpfilter.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/mbuf.h> 79 #include <sys/syslog.h> 80 #include <sys/socket.h> 81 #include <sys/device.h> 82 #include <sys/timeout.h> 83 #include <sys/kernel.h> 84 #include <sys/malloc.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 91 #include <net/if.h> 92 #include <net/if_media.h> 93 94 #include <netinet/in.h> 95 #include <netinet/if_ether.h> 96 97 #if NBPFILTER > 0 98 #include <net/bpf.h> 99 #endif 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/ic/smc91cxxreg.h> 106 #include <dev/ic/smc91cxxvar.h> 107 108 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 109 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 110 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 111 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 112 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 113 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 114 115 /* XXX Hardware padding doesn't work yet(?) */ 116 #define SMC91CXX_SW_PAD 117 118 const char *smc91cxx_idstrs[] = { 119 NULL, /* 0 */ 120 NULL, /* 1 */ 121 NULL, /* 2 */ 122 "SMC91C90/91C92", /* 3 */ 123 "SMC91C94/91C96", /* 4 */ 124 "SMC91C95", /* 5 */ 125 NULL, /* 6 */ 126 "SMC91C100", /* 7 */ 127 "SMC91C100FD", /* 8 */ 128 NULL, /* 9 */ 129 NULL, /* 10 */ 130 NULL, /* 11 */ 131 NULL, /* 12 */ 132 NULL, /* 13 */ 133 NULL, /* 14 */ 134 NULL, /* 15 */ 135 }; 136 137 /* Supported media types. */ 138 const uint64_t smc91cxx_media[] = { 139 IFM_ETHER|IFM_10_T, 140 IFM_ETHER|IFM_10_5, 141 }; 142 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 143 144 /* 145 * MII bit-bang glue. 146 */ 147 u_int32_t smc91cxx_mii_bitbang_read(struct device *); 148 void smc91cxx_mii_bitbang_write(struct device *, u_int32_t); 149 150 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 151 smc91cxx_mii_bitbang_read, 152 smc91cxx_mii_bitbang_write, 153 { 154 MR_MDO, /* MII_BIT_MDO */ 155 MR_MDI, /* MII_BIT_MDI */ 156 MR_MCLK, /* MII_BIT_MDC */ 157 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 158 0, /* MII_BIT_DIR_PHY_HOST */ 159 } 160 }; 161 162 struct cfdriver sm_cd = { 163 NULL, "sm", DV_IFNET 164 }; 165 166 /* MII callbacks */ 167 int smc91cxx_mii_readreg(struct device *, int, int); 168 void smc91cxx_mii_writereg(struct device *, int, int, int); 169 void smc91cxx_statchg(struct device *); 170 void smc91cxx_tick(void *); 171 172 int smc91cxx_mediachange(struct ifnet *); 173 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 int smc91cxx_set_media(struct smc91cxx_softc *, uint64_t); 176 177 void smc91cxx_read(struct smc91cxx_softc *); 178 void smc91cxx_reset(struct smc91cxx_softc *); 179 void smc91cxx_start(struct ifnet *); 180 void smc91cxx_resume(struct smc91cxx_softc *); 181 void smc91cxx_watchdog(struct ifnet *); 182 int smc91cxx_ioctl(struct ifnet *, u_long, caddr_t); 183 184 void 185 smc91cxx_attach(sc, myea) 186 struct smc91cxx_softc *sc; 187 u_int8_t *myea; 188 { 189 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 190 bus_space_tag_t bst = sc->sc_bst; 191 bus_space_handle_t bsh = sc->sc_bsh; 192 struct ifmedia *ifm = &sc->sc_mii.mii_media; 193 u_int32_t miicapabilities; 194 u_int16_t tmp; 195 int i, aui; 196 const char *idstr; 197 198 /* Make sure the chip is stopped. */ 199 smc91cxx_stop(sc); 200 201 SMC_SELECT_BANK(sc, 3); 202 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 203 sc->sc_chipid = RR_ID(tmp); 204 /* check magic number */ 205 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 206 idstr = NULL; 207 printf("%s: invalid BSR 0x%04x\n", sc->sc_dev.dv_xname, tmp); 208 } else 209 idstr = smc91cxx_idstrs[RR_ID(tmp)]; 210 #ifdef SMC_DEBUG 211 printf("\n%s: ", sc->sc_dev.dv_xname); 212 if (idstr != NULL) 213 printf("%s, ", idstr); 214 else 215 printf("unknown chip id %d, ", sc->sc_chipid); 216 printf("revision %d", RR_REV(tmp)); 217 #endif 218 219 /* Read the station address from the chip. */ 220 SMC_SELECT_BANK(sc, 1); 221 if (myea == NULL) { 222 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 223 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 224 sc->sc_arpcom.ac_enaddr[i + 1] = (tmp >>8) & 0xff; 225 sc->sc_arpcom.ac_enaddr[i] = tmp & 0xff; 226 } 227 } else { 228 bcopy(myea, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 229 } 230 231 printf(": address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 232 233 /* Initialize the ifnet structure. */ 234 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 235 ifp->if_softc = sc; 236 ifp->if_start = smc91cxx_start; 237 ifp->if_ioctl = smc91cxx_ioctl; 238 ifp->if_watchdog = smc91cxx_watchdog; 239 ifp->if_flags = 240 IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 241 242 /* Attach the interface. */ 243 if_attach(ifp); 244 ether_ifattach(ifp); 245 246 /* 247 * Initialize our media structures and MII info. We will 248 * probe the MII if we are on the SMC91Cxx 249 */ 250 sc->sc_mii.mii_ifp = ifp; 251 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 252 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 253 sc->sc_mii.mii_statchg = smc91cxx_statchg; 254 ifmedia_init(ifm, 0, smc91cxx_mediachange, smc91cxx_mediastatus); 255 256 SMC_SELECT_BANK(sc, 1); 257 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 258 259 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 260 switch (sc->sc_chipid) { 261 case CHIP_91100: 262 /* 263 * The 91100 does not have full-duplex capabilities, 264 * even if the PHY does. 265 */ 266 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 267 /* FALLTHROUGH */ 268 case CHIP_91100FD: 269 if (tmp & CR_MII_SELECT) { 270 #ifdef SMC_DEBUG 271 printf("%s: default media MII\n", 272 sc->sc_dev.dv_xname); 273 #endif 274 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 275 MII_PHY_ANY, MII_OFFSET_ANY, 0); 276 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 277 ifmedia_add(&sc->sc_mii.mii_media, 278 IFM_ETHER|IFM_NONE, 0, NULL); 279 ifmedia_set(&sc->sc_mii.mii_media, 280 IFM_ETHER|IFM_NONE); 281 } else { 282 ifmedia_set(&sc->sc_mii.mii_media, 283 IFM_ETHER|IFM_AUTO); 284 } 285 sc->sc_flags |= SMC_FLAGS_HAS_MII; 286 break; 287 } 288 /* FALLTHROUGH */ 289 default: 290 aui = tmp & CR_AUI_SELECT; 291 #ifdef SMC_DEBUG 292 printf("%s: default media %s\n", sc->sc_dev.dv_xname, 293 aui ? "AUI" : "UTP"); 294 #endif 295 for (i = 0; i < NSMC91CxxMEDIA; i++) 296 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 297 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 298 break; 299 } 300 301 /* The attach is successful. */ 302 sc->sc_flags |= SMC_FLAGS_ATTACHED; 303 } 304 305 /* 306 * Change media according to request. 307 */ 308 int 309 smc91cxx_mediachange(ifp) 310 struct ifnet *ifp; 311 { 312 struct smc91cxx_softc *sc = ifp->if_softc; 313 314 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 315 } 316 317 int 318 smc91cxx_set_media(sc, media) 319 struct smc91cxx_softc *sc; 320 uint64_t media; 321 { 322 bus_space_tag_t bst = sc->sc_bst; 323 bus_space_handle_t bsh = sc->sc_bsh; 324 u_int16_t tmp; 325 326 /* 327 * If the interface is not currently powered on, just return. 328 * When it is enabled later, smc91cxx_init() will properly set 329 * up the media for us. 330 */ 331 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 332 return (0); 333 334 if (IFM_TYPE(media) != IFM_ETHER) 335 return (EINVAL); 336 337 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 338 return (mii_mediachg(&sc->sc_mii)); 339 340 switch (IFM_SUBTYPE(media)) { 341 case IFM_10_T: 342 case IFM_10_5: 343 SMC_SELECT_BANK(sc, 1); 344 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 345 if (IFM_SUBTYPE(media) == IFM_10_5) 346 tmp |= CR_AUI_SELECT; 347 else 348 tmp &= ~CR_AUI_SELECT; 349 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 350 delay(20000); /* XXX is this needed? */ 351 break; 352 353 default: 354 return (EINVAL); 355 } 356 357 return (0); 358 } 359 360 /* 361 * Notify the world which media we're using. 362 */ 363 void 364 smc91cxx_mediastatus(ifp, ifmr) 365 struct ifnet *ifp; 366 struct ifmediareq *ifmr; 367 { 368 struct smc91cxx_softc *sc = ifp->if_softc; 369 bus_space_tag_t bst = sc->sc_bst; 370 bus_space_handle_t bsh = sc->sc_bsh; 371 u_int16_t tmp; 372 373 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 374 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 375 ifmr->ifm_status = 0; 376 return; 377 } 378 379 /* 380 * If we have MII, go ask the PHY what's going on. 381 */ 382 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 383 mii_pollstat(&sc->sc_mii); 384 ifmr->ifm_active = sc->sc_mii.mii_media_active; 385 ifmr->ifm_status = sc->sc_mii.mii_media_status; 386 return; 387 } 388 389 SMC_SELECT_BANK(sc, 1); 390 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 391 ifmr->ifm_active = 392 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 393 } 394 395 /* 396 * Reset and initialize the chip. 397 */ 398 void 399 smc91cxx_init(sc) 400 struct smc91cxx_softc *sc; 401 { 402 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 403 bus_space_tag_t bst = sc->sc_bst; 404 bus_space_handle_t bsh = sc->sc_bsh; 405 u_int16_t tmp; 406 int s, i; 407 408 s = splnet(); 409 410 /* 411 * This resets the registers mostly to defaults, but doesn't 412 * affect the EEPROM. After the reset cycle, we pause briefly 413 * for the chip to recover. 414 * 415 * XXX how long are we really supposed to delay? --thorpej 416 */ 417 SMC_SELECT_BANK(sc, 0); 418 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 419 delay(100); 420 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 421 delay(200); 422 423 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 424 425 /* Set the Ethernet address. */ 426 SMC_SELECT_BANK(sc, 1); 427 for (i = 0; i < ETHER_ADDR_LEN; i++ ) 428 bus_space_write_1(bst, bsh, IAR_ADDR0_REG_W + i, 429 sc->sc_arpcom.ac_enaddr[i]); 430 431 /* 432 * Set the control register to automatically release successfully 433 * transmitted packets (making the best use of our limited memory) 434 * and enable the EPH interrupt on certain TX errors. 435 */ 436 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 437 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 438 439 /* 440 * Reset the MMU and wait for it to be un-busy. 441 */ 442 SMC_SELECT_BANK(sc, 2); 443 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 444 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 445 /* XXX bound this loop! */ ; 446 447 /* 448 * Disable all interrupts. 449 */ 450 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 451 452 /* 453 * Set current media. 454 */ 455 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 456 457 /* 458 * Set the receive filter. We want receive enable and auto 459 * strip of CRC from received packet. If we are in promisc. mode, 460 * then set that bit as well. 461 * 462 * XXX Initialize multicast filter. For now, we just accept 463 * XXX all multicast. 464 */ 465 SMC_SELECT_BANK(sc, 0); 466 467 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 468 if (ifp->if_flags & IFF_PROMISC) 469 tmp |= RCR_PROMISC; 470 471 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 472 473 /* 474 * Set transmitter control to "enabled". 475 */ 476 tmp = TCR_ENABLE; 477 478 #ifndef SMC91CXX_SW_PAD 479 /* 480 * Enable hardware padding of transmitted packets. 481 * XXX doesn't work? 482 */ 483 tmp |= TCR_PAD_ENABLE; 484 #endif 485 486 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 487 488 /* 489 * Now, enable interrupts. 490 */ 491 SMC_SELECT_BANK(sc, 2); 492 493 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 494 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 495 496 /* Interface is now running, with no output active. */ 497 ifp->if_flags |= IFF_RUNNING; 498 ifq_clr_oactive(&ifp->if_snd); 499 500 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 501 /* Start the one second clock. */ 502 timeout_set(&sc->sc_mii_timeout, smc91cxx_tick, sc); 503 timeout_add_sec(&sc->sc_mii_timeout, 1); 504 } 505 506 /* 507 * Attempt to start any pending transmission. 508 */ 509 smc91cxx_start(ifp); 510 511 splx(s); 512 } 513 514 /* 515 * Start output on an interface. 516 * Must be called at splnet or interrupt level. 517 */ 518 void 519 smc91cxx_start(ifp) 520 struct ifnet *ifp; 521 { 522 struct smc91cxx_softc *sc = ifp->if_softc; 523 bus_space_tag_t bst = sc->sc_bst; 524 bus_space_handle_t bsh = sc->sc_bsh; 525 u_int len; 526 struct mbuf *m, *top; 527 u_int16_t length, npages; 528 u_int8_t packetno; 529 int timo, pad; 530 531 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 532 return; 533 534 again: 535 /* 536 * Peek at the next packet. 537 */ 538 m = ifq_deq_begin(&ifp->if_snd); 539 if (m == NULL) 540 return; 541 542 /* 543 * Compute the frame length and set pad to give an overall even 544 * number of bytes. Below, we assume that the packet length 545 * is even. 546 */ 547 for (len = 0, top = m; m != NULL; m = m->m_next) 548 len += m->m_len; 549 pad = (len & 1); 550 551 /* 552 * We drop packets that are too large. Perhaps we should 553 * truncate them instead? 554 */ 555 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 556 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 557 ifp->if_oerrors++; 558 ifq_deq_commit(&ifp->if_snd, m); 559 m_freem(m); 560 goto readcheck; 561 } 562 563 #ifdef SMC91CXX_SW_PAD 564 /* 565 * Not using hardware padding; pad to ETHER_MIN_LEN. 566 */ 567 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 568 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 569 #endif 570 571 length = pad + len; 572 573 /* 574 * The MMU has a 256 byte page size. The MMU expects us to 575 * ask for "npages - 1". We include space for the status word, 576 * byte count, and control bytes in the allocation request. 577 */ 578 npages = (length + 6) >> 8; 579 580 /* 581 * Now allocate the memory. 582 */ 583 SMC_SELECT_BANK(sc, 2); 584 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 585 586 timo = MEMORY_WAIT_TIME; 587 do { 588 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 589 break; 590 delay(1); 591 } while (--timo); 592 593 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 594 595 if (packetno & ARR_FAILED || timo == 0) { 596 /* 597 * No transmit memory is available. Record the number 598 * of requestd pages and enable the allocation completion 599 * interrupt. Set up the watchdog timer in case we miss 600 * the interrupt. Mark the interface as active so that 601 * no one else attempts to transmit while we're allocating 602 * memory. 603 */ 604 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 605 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 606 607 ifp->if_timer = 5; 608 ifq_deq_rollback(&ifp->if_snd, m); 609 ifq_set_oactive(&ifp->if_snd); 610 return; 611 } 612 613 /* 614 * We have a packet number - set the data window. 615 */ 616 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 617 618 /* 619 * Point to the beginning of the packet. 620 */ 621 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 622 623 /* 624 * Send the packet length (+6 for stats, length, and control bytes) 625 * and the status word (set to zeros). 626 */ 627 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 628 bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff); 629 bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff); 630 631 /* 632 * Get the packet from the kernel. This will include the Ethernet 633 * frame header, MAC address, etc. 634 */ 635 ifq_deq_commit(&ifp->if_snd, m); 636 637 /* 638 * Push the packet out to the card. 639 */ 640 for (top = m; m != NULL; m = m->m_next) { 641 /* Words... */ 642 if (m->m_len > 1) 643 bus_space_write_multi_stream_2(bst, bsh, DATA_REG_W, 644 mtod(m, u_int16_t *), m->m_len >> 1); 645 646 /* ...and the remaining byte, if any. */ 647 if (m->m_len & 1) 648 bus_space_write_1(bst, bsh, DATA_REG_B, 649 *(u_int8_t *)(mtod(m, u_int8_t *) + (m->m_len - 1))); 650 } 651 652 #ifdef SMC91CXX_SW_PAD 653 /* 654 * Push out padding. 655 */ 656 while (pad > 1) { 657 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 658 pad -= 2; 659 } 660 if (pad) 661 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 662 #endif 663 664 /* 665 * Push out control byte and unused packet byte. The control byte 666 * is 0, meaning the packet is even lengthed and no special 667 * CRC handling is necessary. 668 */ 669 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 670 671 /* 672 * Enable transmit interrupts and let the chip go. Set a watchdog 673 * in case we miss the interrupt. 674 */ 675 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 676 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 677 IM_TX_INT | IM_TX_EMPTY_INT); 678 679 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 680 681 ifp->if_timer = 5; 682 683 #if NBPFILTER > 0 684 if (ifp->if_bpf) 685 bpf_mtap(ifp->if_bpf, top, BPF_DIRECTION_OUT); 686 #endif 687 688 ifp->if_opackets++; 689 m_freem(top); 690 691 readcheck: 692 /* 693 * Check for incoming packets. We don't want to overflow the small 694 * RX FIFO. If nothing has arrived, attempt to queue another 695 * transmit packet. 696 */ 697 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 698 goto again; 699 } 700 701 /* 702 * Interrupt service routine. 703 */ 704 int 705 smc91cxx_intr(arg) 706 void *arg; 707 { 708 struct smc91cxx_softc *sc = arg; 709 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 710 bus_space_tag_t bst = sc->sc_bst; 711 bus_space_handle_t bsh = sc->sc_bsh; 712 u_int8_t mask, interrupts, status; 713 u_int16_t packetno, tx_status, card_stats; 714 715 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 716 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 717 return (0); 718 719 SMC_SELECT_BANK(sc, 2); 720 721 /* 722 * Obtain the current interrupt mask. 723 */ 724 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 725 726 /* 727 * Get the set of interrupt which occurred and eliminate any 728 * which are not enabled. 729 */ 730 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 731 status = interrupts & mask; 732 733 /* Ours? */ 734 if (status == 0) 735 return (0); 736 737 /* 738 * It's ours; disable all interrupts while we process them. 739 */ 740 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 741 742 /* 743 * Receive overrun interrupts. 744 */ 745 if (status & IM_RX_OVRN_INT) { 746 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 747 ifp->if_ierrors++; 748 } 749 750 /* 751 * Receive interrupts. 752 */ 753 if (status & IM_RCV_INT) { 754 #if 1 /* DIAGNOSTIC */ 755 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 756 if (packetno & FIFO_REMPTY) { 757 printf("%s: receive interrupt on empty fifo\n", 758 sc->sc_dev.dv_xname); 759 goto out; 760 } else 761 #endif 762 smc91cxx_read(sc); 763 } 764 765 /* 766 * Memory allocation interrupts. 767 */ 768 if (status & IM_ALLOC_INT) { 769 /* Disable this interrupt. */ 770 mask &= ~IM_ALLOC_INT; 771 772 /* 773 * Release the just-allocated memory. We will reallocate 774 * it through the normal start logic. 775 */ 776 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 777 /* XXX bound this loop! */ ; 778 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 779 780 ifq_clr_oactive(&ifp->if_snd); 781 ifp->if_timer = 0; 782 } 783 784 /* 785 * Transmit complete interrupt. Handle transmission error messages. 786 * This will only be called on error condition because of AUTO RELEASE 787 * mode. 788 */ 789 if (status & IM_TX_INT) { 790 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 791 792 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 793 FIFO_TX_MASK; 794 795 /* 796 * Select this as the packet to read from. 797 */ 798 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 799 800 /* 801 * Position the pointer to the beginning of the packet. 802 */ 803 bus_space_write_2(bst, bsh, POINTER_REG_W, 804 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 805 806 /* 807 * Fetch the TX status word. This will be a copy of 808 * the EPH_STATUS_REG_W at the time of the transmission 809 * failure. 810 */ 811 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 812 813 if (tx_status & EPHSR_TX_SUC) 814 printf("%s: successful packet caused TX interrupt?!\n", 815 sc->sc_dev.dv_xname); 816 else 817 ifp->if_oerrors++; 818 819 if (tx_status & EPHSR_LATCOL) 820 ifp->if_collisions++; 821 822 /* 823 * Some of these errors disable the transmitter; reenable it. 824 */ 825 SMC_SELECT_BANK(sc, 0); 826 #ifdef SMC91CXX_SW_PAD 827 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 828 #else 829 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 830 TCR_ENABLE | TCR_PAD_ENABLE); 831 #endif 832 833 /* 834 * Kill the failed packet and wait for the MMU to unbusy. 835 */ 836 SMC_SELECT_BANK(sc, 2); 837 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 838 /* XXX bound this loop! */ ; 839 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 840 841 ifp->if_timer = 0; 842 } 843 844 /* 845 * Transmit underrun interrupts. We use this opportunity to 846 * update transmit statistics from the card. 847 */ 848 if (status & IM_TX_EMPTY_INT) { 849 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 850 851 /* Disable this interrupt. */ 852 mask &= ~IM_TX_EMPTY_INT; 853 854 SMC_SELECT_BANK(sc, 0); 855 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 856 857 /* Single collisions. */ 858 ifp->if_collisions += card_stats & ECR_COLN_MASK; 859 860 /* Multiple collisions. */ 861 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 862 863 SMC_SELECT_BANK(sc, 2); 864 865 ifp->if_timer = 0; 866 } 867 868 /* 869 * Other errors. Reset the interface. 870 */ 871 if (status & IM_EPH_INT) { 872 smc91cxx_stop(sc); 873 smc91cxx_init(sc); 874 } 875 876 /* 877 * Attempt to queue more packets for transmission. 878 */ 879 smc91cxx_start(ifp); 880 881 out: 882 /* 883 * Reenable the interrupts we wish to receive now that processing 884 * is complete. 885 */ 886 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 887 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 888 889 return (1); 890 } 891 892 /* 893 * Read a packet from the card and pass it up to the kernel. 894 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 895 */ 896 void 897 smc91cxx_read(sc) 898 struct smc91cxx_softc *sc; 899 { 900 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 901 bus_space_tag_t bst = sc->sc_bst; 902 bus_space_handle_t bsh = sc->sc_bsh; 903 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 904 struct mbuf *m; 905 u_int16_t status, packetno, packetlen; 906 u_int8_t *data; 907 908 again: 909 /* 910 * Set data pointer to the beginning of the packet. Since 911 * PTR_RCV is set, the packet number will be found automatically 912 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 913 */ 914 bus_space_write_2(bst, bsh, POINTER_REG_W, 915 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 916 917 /* 918 * First two words are status and packet length. 919 */ 920 status = bus_space_read_2(bst, bsh, DATA_REG_W); 921 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 922 923 /* 924 * The packet length includes 3 extra words: status, length, 925 * and an extra word that includes the control byte. 926 */ 927 packetlen -= 6; 928 929 /* 930 * Account for receive errors and discard. 931 */ 932 if (status & RS_ERRORS) { 933 ifp->if_ierrors++; 934 goto out; 935 } 936 937 /* 938 * Adjust for odd-length packet. 939 */ 940 if (status & RS_ODDFRAME) 941 packetlen++; 942 943 /* 944 * Allocate a header mbuf. 945 */ 946 MGETHDR(m, M_DONTWAIT, MT_DATA); 947 if (m == NULL) 948 goto out; 949 m->m_pkthdr.len = packetlen; 950 951 /* 952 * Always put the packet in a cluster. 953 * XXX should chain small mbufs if less than threshold. 954 */ 955 MCLGET(m, M_DONTWAIT); 956 if ((m->m_flags & M_EXT) == 0) { 957 m_freem(m); 958 ifp->if_ierrors++; 959 printf("%s: can't allocate cluster for incoming packet\n", 960 sc->sc_dev.dv_xname); 961 goto out; 962 } 963 964 /* 965 * Pull the packet off the interface. Make sure the payload 966 * is aligned. 967 */ 968 m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t) + 969 sizeof(struct ether_header)) - sizeof(struct ether_header); 970 971 data = mtod(m, u_int8_t *); 972 if (packetlen > 1) 973 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 974 (u_int16_t *)data, packetlen >> 1); 975 if (packetlen & 1) { 976 data += packetlen & ~1; 977 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 978 } 979 980 m->m_pkthdr.len = m->m_len = packetlen; 981 ml_enqueue(&ml, m); 982 983 out: 984 /* 985 * Tell the card to free the memory occupied by this packet. 986 */ 987 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 988 /* XXX bound this loop! */ ; 989 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 990 991 /* 992 * Check for another packet. 993 */ 994 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 995 if (packetno & FIFO_REMPTY) { 996 if_input(ifp, &ml); 997 return; 998 } 999 goto again; 1000 } 1001 1002 /* 1003 * Process an ioctl request. 1004 */ 1005 int 1006 smc91cxx_ioctl(ifp, cmd, data) 1007 struct ifnet *ifp; 1008 u_long cmd; 1009 caddr_t data; 1010 { 1011 struct smc91cxx_softc *sc = ifp->if_softc; 1012 struct ifreq *ifr = (struct ifreq *)data; 1013 int s, error = 0; 1014 1015 s = splnet(); 1016 1017 switch (cmd) { 1018 case SIOCSIFADDR: 1019 if ((error = smc91cxx_enable(sc)) != 0) 1020 break; 1021 ifp->if_flags |= IFF_UP; 1022 smc91cxx_init(sc); 1023 break; 1024 1025 case SIOCSIFFLAGS: 1026 if ((ifp->if_flags & IFF_UP) == 0 && 1027 (ifp->if_flags & IFF_RUNNING) != 0) { 1028 /* 1029 * If interface is marked down and it is running, 1030 * stop it. 1031 */ 1032 smc91cxx_stop(sc); 1033 ifp->if_flags &= ~IFF_RUNNING; 1034 smc91cxx_disable(sc); 1035 } else if ((ifp->if_flags & IFF_UP) != 0 && 1036 (ifp->if_flags & IFF_RUNNING) == 0) { 1037 /* 1038 * If interface is marked up and it is stopped, 1039 * start it. 1040 */ 1041 if ((error = smc91cxx_enable(sc)) != 0) 1042 break; 1043 smc91cxx_init(sc); 1044 } else if ((ifp->if_flags & IFF_UP) != 0) { 1045 /* 1046 * Reset the interface to pick up changes in any 1047 * other flags that affect hardware registers. 1048 */ 1049 smc91cxx_reset(sc); 1050 } 1051 break; 1052 1053 case SIOCGIFMEDIA: 1054 case SIOCSIFMEDIA: 1055 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1056 break; 1057 1058 default: 1059 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1060 } 1061 1062 if (error == ENETRESET) { 1063 if (ifp->if_flags & IFF_RUNNING) 1064 smc91cxx_reset(sc); 1065 error = 0; 1066 } 1067 1068 splx(s); 1069 return (error); 1070 } 1071 1072 /* 1073 * Reset the interface. 1074 */ 1075 void 1076 smc91cxx_reset(sc) 1077 struct smc91cxx_softc *sc; 1078 { 1079 int s; 1080 1081 s = splnet(); 1082 smc91cxx_stop(sc); 1083 smc91cxx_init(sc); 1084 splx(s); 1085 } 1086 1087 /* 1088 * Watchdog timer. 1089 */ 1090 void 1091 smc91cxx_watchdog(ifp) 1092 struct ifnet *ifp; 1093 { 1094 struct smc91cxx_softc *sc = ifp->if_softc; 1095 1096 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1097 ++sc->sc_arpcom.ac_if.if_oerrors; 1098 1099 smc91cxx_reset(sc); 1100 } 1101 1102 /* 1103 * Stop output on the interface. 1104 */ 1105 void 1106 smc91cxx_stop(sc) 1107 struct smc91cxx_softc *sc; 1108 { 1109 bus_space_tag_t bst = sc->sc_bst; 1110 bus_space_handle_t bsh = sc->sc_bsh; 1111 1112 /* 1113 * Clear interrupt mask; disable all interrupts. 1114 */ 1115 SMC_SELECT_BANK(sc, 2); 1116 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1117 1118 /* 1119 * Disable transmitter and receiver. 1120 */ 1121 SMC_SELECT_BANK(sc, 0); 1122 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1123 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1124 1125 /* 1126 * Cancel watchdog timer. 1127 */ 1128 sc->sc_arpcom.ac_if.if_timer = 0; 1129 } 1130 1131 /* 1132 * Enable power on the interface. 1133 */ 1134 int 1135 smc91cxx_enable(sc) 1136 struct smc91cxx_softc *sc; 1137 { 1138 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1139 if ((*sc->sc_enable)(sc) != 0) { 1140 printf("%s: device enable failed\n", 1141 sc->sc_dev.dv_xname); 1142 return (EIO); 1143 } 1144 } 1145 1146 sc->sc_flags |= SMC_FLAGS_ENABLED; 1147 return (0); 1148 } 1149 1150 /* 1151 * Disable power on the interface. 1152 */ 1153 void 1154 smc91cxx_disable(sc) 1155 struct smc91cxx_softc *sc; 1156 { 1157 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1158 (*sc->sc_disable)(sc); 1159 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1160 } 1161 } 1162 1163 int 1164 smc91cxx_activate(self, act) 1165 struct device *self; 1166 int act; 1167 { 1168 #if 0 1169 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1170 #endif 1171 int rv = 0, s; 1172 1173 s = splnet(); 1174 switch (act) { 1175 case DVACT_DEACTIVATE: 1176 #if 0 1177 if_deactivate(&sc->sc_ic.ic_if); 1178 #endif 1179 break; 1180 } 1181 splx(s); 1182 return(rv); 1183 } 1184 1185 int 1186 smc91cxx_detach(self, flags) 1187 struct device *self; 1188 int flags; 1189 { 1190 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1191 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1192 1193 /* Succeed now if there's no work to do. */ 1194 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1195 return(0); 1196 1197 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1198 smc91cxx_disable(sc); 1199 1200 /* smc91cxx_attach() never fails */ 1201 1202 /* Delete all media. */ 1203 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1204 1205 ether_ifdetach(ifp); 1206 if_detach(ifp); 1207 1208 return (0); 1209 } 1210 1211 u_int32_t 1212 smc91cxx_mii_bitbang_read(self) 1213 struct device *self; 1214 { 1215 struct smc91cxx_softc *sc = (void *) self; 1216 1217 /* We're already in bank 3. */ 1218 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1219 } 1220 1221 void 1222 smc91cxx_mii_bitbang_write(self, val) 1223 struct device *self; 1224 u_int32_t val; 1225 { 1226 struct smc91cxx_softc *sc = (void *) self; 1227 1228 /* We're already in bank 3. */ 1229 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1230 } 1231 1232 int 1233 smc91cxx_mii_readreg(self, phy, reg) 1234 struct device *self; 1235 int phy, reg; 1236 { 1237 struct smc91cxx_softc *sc = (void *) self; 1238 int val; 1239 1240 SMC_SELECT_BANK(sc, 3); 1241 1242 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1243 1244 SMC_SELECT_BANK(sc, 2); 1245 1246 return (val); 1247 } 1248 1249 void 1250 smc91cxx_mii_writereg(self, phy, reg, val) 1251 struct device *self; 1252 int phy, reg, val; 1253 { 1254 struct smc91cxx_softc *sc = (void *) self; 1255 1256 SMC_SELECT_BANK(sc, 3); 1257 1258 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1259 1260 SMC_SELECT_BANK(sc, 2); 1261 } 1262 1263 void 1264 smc91cxx_statchg(self) 1265 struct device *self; 1266 { 1267 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1268 bus_space_tag_t bst = sc->sc_bst; 1269 bus_space_handle_t bsh = sc->sc_bsh; 1270 int mctl; 1271 1272 SMC_SELECT_BANK(sc, 0); 1273 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1274 if (sc->sc_mii.mii_media_active & IFM_FDX) 1275 mctl |= TCR_SWFDUP; 1276 else 1277 mctl &= ~TCR_SWFDUP; 1278 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1279 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1280 } 1281 1282 /* 1283 * One second timer, used to tick the MII. 1284 */ 1285 void 1286 smc91cxx_tick(arg) 1287 void *arg; 1288 { 1289 struct smc91cxx_softc *sc = arg; 1290 int s; 1291 1292 #ifdef DIAGNOSTIC 1293 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1294 panic("smc91cxx_tick"); 1295 #endif 1296 1297 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1298 return; 1299 1300 s = splnet(); 1301 mii_tick(&sc->sc_mii); 1302 splx(s); 1303 1304 timeout_add_sec(&sc->sc_mii_timeout, 1); 1305 } 1306