1 /* $OpenBSD: smc83c170.c,v 1.13 2008/11/28 02:44:17 brad Exp $ */ 2 /* $NetBSD: smc83c170.c,v 1.59 2005/02/27 00:27:02 perry Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Device driver for the Standard Microsystems Corp. 83C170 36 * Ethernet PCI Integrated Controller (EPIC/100). 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/timeout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_ether.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <machine/bus.h> 70 #include <machine/intr.h> 71 72 #include <dev/mii/miivar.h> 73 #include <dev/mii/lxtphyreg.h> 74 75 #include <dev/ic/smc83c170reg.h> 76 #include <dev/ic/smc83c170var.h> 77 78 void epic_start(struct ifnet *); 79 void epic_watchdog(struct ifnet *); 80 int epic_ioctl(struct ifnet *, u_long, caddr_t); 81 int epic_init(struct ifnet *); 82 void epic_stop(struct ifnet *, int); 83 84 void epic_shutdown(void *); 85 86 void epic_reset(struct epic_softc *); 87 void epic_rxdrain(struct epic_softc *); 88 int epic_add_rxbuf(struct epic_softc *, int); 89 void epic_read_eeprom(struct epic_softc *, int, int, u_int16_t *); 90 void epic_set_mchash(struct epic_softc *); 91 void epic_fixup_clock_source(struct epic_softc *); 92 int epic_mii_read(struct device *, int, int); 93 void epic_mii_write(struct device *, int, int, int); 94 int epic_mii_wait(struct epic_softc *, u_int32_t); 95 void epic_tick(void *); 96 97 void epic_statchg(struct device *); 98 int epic_mediachange(struct ifnet *); 99 void epic_mediastatus(struct ifnet *, struct ifmediareq *); 100 101 struct cfdriver epic_cd = { 102 0, "epic", DV_IFNET 103 }; 104 105 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 106 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 107 108 int epic_copy_small = 0; 109 110 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 111 112 /* 113 * Attach an EPIC interface to the system. 114 */ 115 void 116 epic_attach(struct epic_softc *sc, const char *intrstr) 117 { 118 bus_space_tag_t st = sc->sc_st; 119 bus_space_handle_t sh = sc->sc_sh; 120 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 121 int rseg, error, miiflags; 122 u_int i; 123 bus_dma_segment_t seg; 124 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 125 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 126 char *nullbuf; 127 128 timeout_set(&sc->sc_mii_timeout, epic_tick, sc); 129 130 /* 131 * Allocate the control data structures, and create and load the 132 * DMA map for it. 133 */ 134 if ((error = bus_dmamem_alloc(sc->sc_dmat, 135 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 136 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 137 printf(": unable to allocate control data, error = %d\n", 138 error); 139 goto fail_0; 140 } 141 142 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 143 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 144 (caddr_t *)&sc->sc_control_data, 145 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 146 printf(": unable to map control data, error = %d\n", error); 147 goto fail_1; 148 } 149 nullbuf = 150 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 151 memset(nullbuf, 0, ETHER_PAD_LEN); 152 153 if ((error = bus_dmamap_create(sc->sc_dmat, 154 sizeof(struct epic_control_data), 1, 155 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 156 &sc->sc_cddmamap)) != 0) { 157 printf(": unable to create control data DMA map, error = %d\n", 158 error); 159 goto fail_2; 160 } 161 162 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 163 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 164 BUS_DMA_NOWAIT)) != 0) { 165 printf(": unable to load control data DMA map, error = %d\n", 166 error); 167 goto fail_3; 168 } 169 170 /* 171 * Create the transmit buffer DMA maps. 172 */ 173 for (i = 0; i < EPIC_NTXDESC; i++) { 174 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 175 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 176 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 177 printf(": unable to create tx DMA map %d, error = %d\n", 178 i, error); 179 goto fail_4; 180 } 181 } 182 183 /* 184 * Create the receive buffer DMA maps. 185 */ 186 for (i = 0; i < EPIC_NRXDESC; i++) { 187 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 188 MCLBYTES, 0, BUS_DMA_NOWAIT, 189 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 190 printf(": unable to create rx DMA map %d, error = %d\n", 191 i, error); 192 goto fail_5; 193 } 194 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 195 } 196 197 /* 198 * create and map the pad buffer 199 */ 200 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 201 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 202 printf(": unable to create pad buffer DMA map, error = %d\n", 203 error); 204 goto fail_5; 205 } 206 207 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 208 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 209 printf(": unable to load pad buffer DMA map, error = %d\n", 210 error); 211 goto fail_6; 212 } 213 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 214 BUS_DMASYNC_PREWRITE); 215 216 /* 217 * Bring the chip out of low-power mode and reset it to a known state. 218 */ 219 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 220 epic_reset(sc); 221 222 /* 223 * Read the Ethernet address from the EEPROM. 224 */ 225 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 226 for (i = 0; i < sizeof(myea)/ sizeof(myea[0]); i++) { 227 enaddr[i * 2] = myea[i] & 0xff; 228 enaddr[i * 2 + 1] = myea[i] >> 8; 229 } 230 231 /* 232 * ...and the device name. 233 */ 234 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 235 mydevname); 236 for (i = 0; i < sizeof(mydevname) / sizeof(mydevname[0]); i++) { 237 devname[i * 2] = mydevname[i] & 0xff; 238 devname[i * 2 + 1] = mydevname[i] >> 8; 239 } 240 241 devname[sizeof(devname) - 1] = ' '; 242 for (i = sizeof(devname) - 1; devname[i] == ' '; i--) { 243 devname[i] = '\0'; 244 if (i == 0) 245 break; 246 } 247 248 printf(", %s : %s, address %s\n", devname, intrstr, 249 ether_sprintf(enaddr)); 250 251 miiflags = 0; 252 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 253 miiflags |= MIIF_HAVEFIBER; 254 255 /* 256 * Initialize our media structures and probe the MII. 257 */ 258 sc->sc_mii.mii_ifp = ifp; 259 sc->sc_mii.mii_readreg = epic_mii_read; 260 sc->sc_mii.mii_writereg = epic_mii_write; 261 sc->sc_mii.mii_statchg = epic_statchg; 262 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 263 epic_mediastatus); 264 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 265 MII_OFFSET_ANY, miiflags); 266 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 267 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 268 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 269 } else 270 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 271 272 if (sc->sc_hwflags & EPIC_HAS_BNC) { 273 /* use the next free media instance */ 274 sc->sc_serinst = sc->sc_mii.mii_instance++; 275 ifmedia_add(&sc->sc_mii.mii_media, 276 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, 277 sc->sc_serinst), 278 0, NULL); 279 } else 280 sc->sc_serinst = -1; 281 282 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 283 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 284 ifp->if_softc = sc; 285 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 286 ifp->if_ioctl = epic_ioctl; 287 ifp->if_start = epic_start; 288 ifp->if_watchdog = epic_watchdog; 289 IFQ_SET_MAXLEN(&ifp->if_snd, EPIC_NTXDESC - 1); 290 IFQ_SET_READY(&ifp->if_snd); 291 292 ifp->if_capabilities = IFCAP_VLAN_MTU; 293 294 /* 295 * Attach the interface. 296 */ 297 if_attach(ifp); 298 ether_ifattach(ifp); 299 300 /* 301 * Make sure the interface is shutdown during reboot. 302 */ 303 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 304 if (sc->sc_sdhook == NULL) 305 printf("%s: WARNING: unable to establish shutdown hook\n", 306 sc->sc_dev.dv_xname); 307 return; 308 309 /* 310 * Free any resources we've allocated during the failed attach 311 * attempt. Do this in reverse order and fall through. 312 */ 313 fail_6: 314 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 315 fail_5: 316 for (i = 0; i < EPIC_NRXDESC; i++) { 317 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 318 bus_dmamap_destroy(sc->sc_dmat, 319 EPIC_DSRX(sc, i)->ds_dmamap); 320 } 321 fail_4: 322 for (i = 0; i < EPIC_NTXDESC; i++) { 323 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 324 bus_dmamap_destroy(sc->sc_dmat, 325 EPIC_DSTX(sc, i)->ds_dmamap); 326 } 327 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 328 fail_3: 329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 330 fail_2: 331 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 332 sizeof(struct epic_control_data)); 333 fail_1: 334 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 335 fail_0: 336 return; 337 } 338 339 /* 340 * Shutdown hook. Make sure the interface is stopped at reboot. 341 */ 342 void 343 epic_shutdown(void *arg) 344 { 345 struct epic_softc *sc = arg; 346 347 epic_stop(&sc->sc_arpcom.ac_if, 1); 348 } 349 350 /* 351 * Start packet transmission on the interface. 352 * [ifnet interface function] 353 */ 354 void 355 epic_start(struct ifnet *ifp) 356 { 357 struct epic_softc *sc = ifp->if_softc; 358 struct mbuf *m0, *m; 359 struct epic_txdesc *txd; 360 struct epic_descsoft *ds; 361 struct epic_fraglist *fr; 362 bus_dmamap_t dmamap; 363 int error, firsttx, nexttx, opending, seg; 364 u_int len; 365 366 /* 367 * Remember the previous txpending and the first transmit 368 * descriptor we use. 369 */ 370 opending = sc->sc_txpending; 371 firsttx = EPIC_NEXTTX(sc->sc_txlast); 372 373 /* 374 * Loop through the send queue, setting up transmit descriptors 375 * until we drain the queue, or use up all available transmit 376 * descriptors. 377 */ 378 while (sc->sc_txpending < EPIC_NTXDESC) { 379 /* 380 * Grab a packet off the queue. 381 */ 382 IFQ_POLL(&ifp->if_snd, m0); 383 if (m0 == NULL) 384 break; 385 m = NULL; 386 387 /* 388 * Get the last and next available transmit descriptor. 389 */ 390 nexttx = EPIC_NEXTTX(sc->sc_txlast); 391 txd = EPIC_CDTX(sc, nexttx); 392 fr = EPIC_CDFL(sc, nexttx); 393 ds = EPIC_DSTX(sc, nexttx); 394 dmamap = ds->ds_dmamap; 395 396 /* 397 * Load the DMA map. If this fails, the packet either 398 * didn't fit in the alloted number of frags, or we were 399 * short on resources. In this case, we'll copy and try 400 * again. 401 */ 402 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 403 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 404 (m0->m_pkthdr.len < ETHER_PAD_LEN && 405 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 406 if (error == 0) 407 bus_dmamap_unload(sc->sc_dmat, dmamap); 408 409 MGETHDR(m, M_DONTWAIT, MT_DATA); 410 if (m == NULL) 411 break; 412 if (m0->m_pkthdr.len > MHLEN) { 413 MCLGET(m, M_DONTWAIT); 414 if ((m->m_flags & M_EXT) == 0) { 415 m_freem(m); 416 break; 417 } 418 } 419 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 420 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 421 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 422 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 423 if (error) 424 break; 425 } 426 IFQ_DEQUEUE(&ifp->if_snd, m0); 427 if (m != NULL) { 428 m_freem(m0); 429 m0 = m; 430 } 431 432 /* Initialize the fraglist. */ 433 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 434 fr->ef_frags[seg].ef_addr = 435 dmamap->dm_segs[seg].ds_addr; 436 fr->ef_frags[seg].ef_length = 437 dmamap->dm_segs[seg].ds_len; 438 } 439 len = m0->m_pkthdr.len; 440 if (len < ETHER_PAD_LEN) { 441 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 442 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 443 len = ETHER_PAD_LEN; 444 seg++; 445 } 446 fr->ef_nfrags = seg; 447 448 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 449 450 /* Sync the DMA map. */ 451 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 452 BUS_DMASYNC_PREWRITE); 453 454 /* 455 * Store a pointer to the packet so we can free it later. 456 */ 457 ds->ds_mbuf = m0; 458 459 /* 460 * Fill in the transmit descriptor. 461 */ 462 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 463 464 /* 465 * If this is the first descriptor we're enqueueing, 466 * don't give it to the EPIC yet. That could cause 467 * a race condition. We'll do it below. 468 */ 469 if (nexttx == firsttx) 470 txd->et_txstatus = TXSTAT_TXLENGTH(len); 471 else 472 txd->et_txstatus = 473 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 474 475 EPIC_CDTXSYNC(sc, nexttx, 476 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 477 478 /* Advance the tx pointer. */ 479 sc->sc_txpending++; 480 sc->sc_txlast = nexttx; 481 482 #if NBPFILTER > 0 483 /* 484 * Pass the packet to any BPF listeners. 485 */ 486 if (ifp->if_bpf) 487 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 488 #endif 489 } 490 491 if (sc->sc_txpending == EPIC_NTXDESC) { 492 /* No more slots left; notify upper layer. */ 493 ifp->if_flags |= IFF_OACTIVE; 494 } 495 496 if (sc->sc_txpending != opending) { 497 /* 498 * We enqueued packets. If the transmitter was idle, 499 * reset the txdirty pointer. 500 */ 501 if (opending == 0) 502 sc->sc_txdirty = firsttx; 503 504 /* 505 * Cause a transmit interrupt to happen on the 506 * last packet we enqueued. 507 */ 508 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 509 EPIC_CDTXSYNC(sc, sc->sc_txlast, 510 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 511 512 /* 513 * The entire packet chain is set up. Give the 514 * first descriptor to the EPIC now. 515 */ 516 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 517 EPIC_CDTXSYNC(sc, firsttx, 518 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 519 520 /* Start the transmitter. */ 521 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 522 COMMAND_TXQUEUED); 523 524 /* Set a watchdog timer in case the chip flakes out. */ 525 ifp->if_timer = 5; 526 } 527 } 528 529 /* 530 * Watchdog timer handler. 531 * [ifnet interface function] 532 */ 533 void 534 epic_watchdog(struct ifnet *ifp) 535 { 536 struct epic_softc *sc = ifp->if_softc; 537 538 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 539 ifp->if_oerrors++; 540 541 (void) epic_init(ifp); 542 } 543 544 /* 545 * Handle control requests from the operator. 546 * [ifnet interface function] 547 */ 548 int 549 epic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 550 { 551 struct epic_softc *sc = ifp->if_softc; 552 struct ifaddr *ifa = (struct ifaddr *)data; 553 struct ifreq *ifr = (struct ifreq *)data; 554 int s, error = 0; 555 556 s = splnet(); 557 558 switch (cmd) { 559 case SIOCSIFADDR: 560 ifp->if_flags |= IFF_UP; 561 562 switch (ifa->ifa_addr->sa_family) { 563 #ifdef INET 564 case AF_INET: 565 epic_init(ifp); 566 arp_ifinit(&sc->sc_arpcom, ifa); 567 break; 568 #endif 569 default: 570 epic_init(ifp); 571 break; 572 } 573 break; 574 575 case SIOCSIFFLAGS: 576 /* 577 * If interface is marked up and not running, then start it. 578 * If it is marked down and running, stop it. 579 * XXX If it's up then re-initialize it. This is so flags 580 * such as IFF_PROMISC are handled. 581 */ 582 if (ifp->if_flags & IFF_UP) 583 epic_init(ifp); 584 else if (ifp->if_flags & IFF_RUNNING) 585 epic_stop(ifp, 1); 586 break; 587 588 case SIOCSIFMEDIA: 589 case SIOCGIFMEDIA: 590 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 591 break; 592 593 default: 594 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 595 } 596 597 if (error == ENETRESET) { 598 if (ifp->if_flags & IFF_RUNNING) { 599 mii_pollstat(&sc->sc_mii); 600 epic_set_mchash(sc); 601 } 602 error = 0; 603 } 604 605 splx(s); 606 return (error); 607 } 608 609 /* 610 * Interrupt handler. 611 */ 612 int 613 epic_intr(void *arg) 614 { 615 struct epic_softc *sc = arg; 616 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 617 struct epic_rxdesc *rxd; 618 struct epic_txdesc *txd; 619 struct epic_descsoft *ds; 620 struct mbuf *m; 621 u_int32_t intstat, rxstatus, txstatus; 622 int i, claimed = 0; 623 u_int len; 624 625 top: 626 /* 627 * Get the interrupt status from the EPIC. 628 */ 629 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 630 if ((intstat & INTSTAT_INT_ACTV) == 0) 631 return (claimed); 632 633 claimed = 1; 634 635 /* 636 * Acknowledge the interrupt. 637 */ 638 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 639 intstat & INTMASK); 640 641 /* 642 * Check for receive interrupts. 643 */ 644 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 645 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 646 rxd = EPIC_CDRX(sc, i); 647 ds = EPIC_DSRX(sc, i); 648 649 EPIC_CDRXSYNC(sc, i, 650 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 651 652 rxstatus = rxd->er_rxstatus; 653 if (rxstatus & ER_RXSTAT_OWNER) { 654 /* 655 * We have processed all of the 656 * receive buffers. 657 */ 658 break; 659 } 660 661 /* 662 * Make sure the packet arrived intact. If an error 663 * occurred, update stats and reset the descriptor. 664 * The buffer will be reused the next time the 665 * descriptor comes up in the ring. 666 */ 667 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 668 if (rxstatus & ER_RXSTAT_CRCERROR) 669 printf("%s: CRC error\n", 670 sc->sc_dev.dv_xname); 671 if (rxstatus & ER_RXSTAT_ALIGNERROR) 672 printf("%s: alignment error\n", 673 sc->sc_dev.dv_xname); 674 ifp->if_ierrors++; 675 EPIC_INIT_RXDESC(sc, i); 676 continue; 677 } 678 679 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 680 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 681 682 /* 683 * The EPIC includes the CRC with every packet; 684 * trim it. 685 */ 686 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 687 688 if (len < sizeof(struct ether_header)) { 689 /* 690 * Runt packet; drop it now. 691 */ 692 ifp->if_ierrors++; 693 EPIC_INIT_RXDESC(sc, i); 694 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 695 ds->ds_dmamap->dm_mapsize, 696 BUS_DMASYNC_PREREAD); 697 continue; 698 } 699 700 /* 701 * If the packet is small enough to fit in a 702 * single header mbuf, allocate one and copy 703 * the data into it. This greatly reduces 704 * memory consumption when we receive lots 705 * of small packets. 706 * 707 * Otherwise, we add a new buffer to the receive 708 * chain. If this fails, we drop the packet and 709 * recycle the old buffer. 710 */ 711 if (epic_copy_small != 0 && len <= MHLEN) { 712 MGETHDR(m, M_DONTWAIT, MT_DATA); 713 if (m == NULL) 714 goto dropit; 715 memcpy(mtod(m, caddr_t), 716 mtod(ds->ds_mbuf, caddr_t), len); 717 EPIC_INIT_RXDESC(sc, i); 718 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 719 ds->ds_dmamap->dm_mapsize, 720 BUS_DMASYNC_PREREAD); 721 } else { 722 m = ds->ds_mbuf; 723 if (epic_add_rxbuf(sc, i) != 0) { 724 dropit: 725 ifp->if_ierrors++; 726 EPIC_INIT_RXDESC(sc, i); 727 bus_dmamap_sync(sc->sc_dmat, 728 ds->ds_dmamap, 0, 729 ds->ds_dmamap->dm_mapsize, 730 BUS_DMASYNC_PREREAD); 731 continue; 732 } 733 } 734 735 m->m_pkthdr.rcvif = ifp; 736 m->m_pkthdr.len = m->m_len = len; 737 738 #if NBPFILTER > 0 739 /* 740 * Pass this up to any BPF listeners, but only 741 * pass it up the stack if its for us. 742 */ 743 if (ifp->if_bpf) 744 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 745 #endif 746 747 /* Pass it on. */ 748 ether_input_mbuf(ifp, m); 749 ifp->if_ipackets++; 750 } 751 752 /* Update the receive pointer. */ 753 sc->sc_rxptr = i; 754 755 /* 756 * Check for receive queue underflow. 757 */ 758 if (intstat & INTSTAT_RQE) { 759 printf("%s: receiver queue empty\n", 760 sc->sc_dev.dv_xname); 761 /* 762 * Ring is already built; just restart the 763 * receiver. 764 */ 765 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 766 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 767 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 768 COMMAND_RXQUEUED | COMMAND_START_RX); 769 } 770 } 771 772 /* 773 * Check for transmission complete interrupts. 774 */ 775 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 776 ifp->if_flags &= ~IFF_OACTIVE; 777 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 778 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 779 txd = EPIC_CDTX(sc, i); 780 ds = EPIC_DSTX(sc, i); 781 782 EPIC_CDTXSYNC(sc, i, 783 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 784 785 txstatus = txd->et_txstatus; 786 if (txstatus & ET_TXSTAT_OWNER) 787 break; 788 789 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 790 791 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 792 0, ds->ds_dmamap->dm_mapsize, 793 BUS_DMASYNC_POSTWRITE); 794 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 795 m_freem(ds->ds_mbuf); 796 ds->ds_mbuf = NULL; 797 798 /* 799 * Check for errors and collisions. 800 */ 801 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 802 ifp->if_oerrors++; 803 else 804 ifp->if_opackets++; 805 ifp->if_collisions += 806 TXSTAT_COLLISIONS(txstatus); 807 if (txstatus & ET_TXSTAT_CARSENSELOST) 808 printf("%s: lost carrier\n", 809 sc->sc_dev.dv_xname); 810 } 811 812 /* Update the dirty transmit buffer pointer. */ 813 sc->sc_txdirty = i; 814 815 /* 816 * Cancel the watchdog timer if there are no pending 817 * transmissions. 818 */ 819 if (sc->sc_txpending == 0) 820 ifp->if_timer = 0; 821 822 /* 823 * Kick the transmitter after a DMA underrun. 824 */ 825 if (intstat & INTSTAT_TXU) { 826 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 827 bus_space_write_4(sc->sc_st, sc->sc_sh, 828 EPIC_COMMAND, COMMAND_TXUGO); 829 if (sc->sc_txpending) 830 bus_space_write_4(sc->sc_st, sc->sc_sh, 831 EPIC_COMMAND, COMMAND_TXQUEUED); 832 } 833 834 /* 835 * Try to get more packets going. 836 */ 837 epic_start(ifp); 838 } 839 840 /* 841 * Check for fatal interrupts. 842 */ 843 if (intstat & INTSTAT_FATAL_INT) { 844 if (intstat & INTSTAT_PTA) 845 printf("%s: PCI target abort error\n", 846 sc->sc_dev.dv_xname); 847 else if (intstat & INTSTAT_PMA) 848 printf("%s: PCI master abort error\n", 849 sc->sc_dev.dv_xname); 850 else if (intstat & INTSTAT_APE) 851 printf("%s: PCI address parity error\n", 852 sc->sc_dev.dv_xname); 853 else if (intstat & INTSTAT_DPE) 854 printf("%s: PCI data parity error\n", 855 sc->sc_dev.dv_xname); 856 else 857 printf("%s: unknown fatal error\n", 858 sc->sc_dev.dv_xname); 859 (void) epic_init(ifp); 860 } 861 862 /* 863 * Check for more interrupts. 864 */ 865 goto top; 866 } 867 868 /* 869 * One second timer, used to tick the MII. 870 */ 871 void 872 epic_tick(void *arg) 873 { 874 struct epic_softc *sc = arg; 875 int s; 876 877 s = splnet(); 878 mii_tick(&sc->sc_mii); 879 splx(s); 880 881 timeout_add_sec(&sc->sc_mii_timeout, 1); 882 } 883 884 /* 885 * Fixup the clock source on the EPIC. 886 */ 887 void 888 epic_fixup_clock_source(struct epic_softc *sc) 889 { 890 int i; 891 892 /* 893 * According to SMC Application Note 7-15, the EPIC's clock 894 * source is incorrect following a reset. This manifests itself 895 * as failure to recognize when host software has written to 896 * a register on the EPIC. The appnote recommends issuing at 897 * least 16 consecutive writes to the CLOCK TEST bit to correctly 898 * configure the clock source. 899 */ 900 for (i = 0; i < 16; i++) 901 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 902 TEST_CLOCKTEST); 903 } 904 905 /* 906 * Perform a soft reset on the EPIC. 907 */ 908 void 909 epic_reset(struct epic_softc *sc) 910 { 911 912 epic_fixup_clock_source(sc); 913 914 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 915 delay(100); 916 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 917 delay(100); 918 919 epic_fixup_clock_source(sc); 920 } 921 922 /* 923 * Initialize the interface. Must be called at splnet(). 924 */ 925 int 926 epic_init(struct ifnet *ifp) 927 { 928 struct epic_softc *sc = ifp->if_softc; 929 bus_space_tag_t st = sc->sc_st; 930 bus_space_handle_t sh = sc->sc_sh; 931 struct epic_txdesc *txd; 932 struct epic_descsoft *ds; 933 u_int32_t genctl, reg0; 934 int i, error = 0; 935 936 /* 937 * Cancel any pending I/O. 938 */ 939 epic_stop(ifp, 0); 940 941 /* 942 * Reset the EPIC to a known state. 943 */ 944 epic_reset(sc); 945 946 /* 947 * Magical mystery initialization. 948 */ 949 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 950 951 /* 952 * Initialize the EPIC genctl register: 953 * 954 * - 64 byte receive FIFO threshold 955 * - automatic advance to next receive frame 956 */ 957 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 958 #if BYTE_ORDER == BIG_ENDIAN 959 genctl |= GENCTL_BIG_ENDIAN; 960 #endif 961 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 962 963 /* 964 * Reset the MII bus and PHY. 965 */ 966 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 967 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 968 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 969 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 970 delay(100); 971 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 972 delay(1000); 973 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 974 975 /* 976 * Initialize Ethernet address. 977 */ 978 reg0 = sc->sc_arpcom.ac_enaddr[1] << 8 | sc->sc_arpcom.ac_enaddr[0]; 979 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 980 reg0 = sc->sc_arpcom.ac_enaddr[3] << 8 | sc->sc_arpcom.ac_enaddr[2]; 981 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 982 reg0 = sc->sc_arpcom.ac_enaddr[5] << 8 | sc->sc_arpcom.ac_enaddr[4]; 983 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 984 985 /* 986 * Initialize receive control. Remember the external buffer 987 * size setting. 988 */ 989 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 990 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 991 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 992 if (ifp->if_flags & IFF_PROMISC) 993 reg0 |= RXCON_PROMISCMODE; 994 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 995 996 /* Set the current media. */ 997 epic_mediachange(ifp); 998 999 /* Set up the multicast hash table. */ 1000 epic_set_mchash(sc); 1001 1002 /* 1003 * Initialize the transmit descriptor ring. txlast is initialized 1004 * to the end of the list so that it will wrap around to the first 1005 * descriptor when the first packet is transmitted. 1006 */ 1007 for (i = 0; i < EPIC_NTXDESC; i++) { 1008 txd = EPIC_CDTX(sc, i); 1009 memset(txd, 0, sizeof(struct epic_txdesc)); 1010 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 1011 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 1012 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1013 } 1014 sc->sc_txpending = 0; 1015 sc->sc_txdirty = 0; 1016 sc->sc_txlast = EPIC_NTXDESC - 1; 1017 1018 /* 1019 * Initialize the receive descriptor ring. 1020 */ 1021 for (i = 0; i < EPIC_NRXDESC; i++) { 1022 ds = EPIC_DSRX(sc, i); 1023 if (ds->ds_mbuf == NULL) { 1024 if ((error = epic_add_rxbuf(sc, i)) != 0) { 1025 printf("%s: unable to allocate or map rx " 1026 "buffer %d error = %d\n", 1027 sc->sc_dev.dv_xname, i, error); 1028 /* 1029 * XXX Should attempt to run with fewer receive 1030 * XXX buffers instead of just failing. 1031 */ 1032 epic_rxdrain(sc); 1033 goto out; 1034 } 1035 } else 1036 EPIC_INIT_RXDESC(sc, i); 1037 } 1038 sc->sc_rxptr = 0; 1039 1040 /* 1041 * Initialize the interrupt mask and enable interrupts. 1042 */ 1043 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1044 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1045 1046 /* 1047 * Give the transmit and receive rings to the EPIC. 1048 */ 1049 bus_space_write_4(st, sh, EPIC_PTCDAR, 1050 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1051 bus_space_write_4(st, sh, EPIC_PRCDAR, 1052 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1053 1054 /* 1055 * Set the EPIC in motion. 1056 */ 1057 bus_space_write_4(st, sh, EPIC_COMMAND, 1058 COMMAND_RXQUEUED | COMMAND_START_RX); 1059 1060 /* 1061 * ...all done! 1062 */ 1063 ifp->if_flags |= IFF_RUNNING; 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 1066 /* 1067 * Start the one second clock. 1068 */ 1069 timeout_add_sec(&sc->sc_mii_timeout, 1); 1070 1071 /* 1072 * Attempt to start output on the interface. 1073 */ 1074 epic_start(ifp); 1075 1076 out: 1077 if (error) 1078 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1079 return (error); 1080 } 1081 1082 /* 1083 * Drain the receive queue. 1084 */ 1085 void 1086 epic_rxdrain(struct epic_softc *sc) 1087 { 1088 struct epic_descsoft *ds; 1089 int i; 1090 1091 for (i = 0; i < EPIC_NRXDESC; i++) { 1092 ds = EPIC_DSRX(sc, i); 1093 if (ds->ds_mbuf != NULL) { 1094 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1095 m_freem(ds->ds_mbuf); 1096 ds->ds_mbuf = NULL; 1097 } 1098 } 1099 } 1100 1101 /* 1102 * Stop transmission on the interface. 1103 */ 1104 void 1105 epic_stop(struct ifnet *ifp, int disable) 1106 { 1107 struct epic_softc *sc = ifp->if_softc; 1108 bus_space_tag_t st = sc->sc_st; 1109 bus_space_handle_t sh = sc->sc_sh; 1110 struct epic_descsoft *ds; 1111 u_int32_t reg; 1112 int i; 1113 1114 /* 1115 * Stop the one second clock. 1116 */ 1117 timeout_del(&sc->sc_mii_timeout); 1118 1119 /* 1120 * Mark the interface down and cancel the watchdog timer. 1121 */ 1122 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1123 ifp->if_timer = 0; 1124 1125 /* Down the MII. */ 1126 mii_down(&sc->sc_mii); 1127 1128 /* Paranoia... */ 1129 epic_fixup_clock_source(sc); 1130 1131 /* 1132 * Disable interrupts. 1133 */ 1134 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1135 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1136 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1137 1138 /* 1139 * Stop the DMA engine and take the receiver off-line. 1140 */ 1141 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1142 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1143 1144 /* 1145 * Release any queued transmit buffers. 1146 */ 1147 for (i = 0; i < EPIC_NTXDESC; i++) { 1148 ds = EPIC_DSTX(sc, i); 1149 if (ds->ds_mbuf != NULL) { 1150 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1151 m_freem(ds->ds_mbuf); 1152 ds->ds_mbuf = NULL; 1153 } 1154 } 1155 1156 if (disable) 1157 epic_rxdrain(sc); 1158 } 1159 1160 /* 1161 * Read the EPIC Serial EEPROM. 1162 */ 1163 void 1164 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, u_int16_t *data) 1165 { 1166 bus_space_tag_t st = sc->sc_st; 1167 bus_space_handle_t sh = sc->sc_sh; 1168 u_int16_t reg; 1169 int i, x; 1170 1171 #define EEPROM_WAIT_READY(st, sh) \ 1172 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1173 /* nothing */ 1174 1175 /* 1176 * Enable the EEPROM. 1177 */ 1178 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1179 EEPROM_WAIT_READY(st, sh); 1180 1181 for (i = 0; i < wordcnt; i++) { 1182 /* Send CHIP SELECT for one clock tick. */ 1183 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1184 EEPROM_WAIT_READY(st, sh); 1185 1186 /* Shift in the READ opcode. */ 1187 for (x = 3; x > 0; x--) { 1188 reg = EECTL_ENABLE|EECTL_EECS; 1189 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1190 reg |= EECTL_EEDI; 1191 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1192 EEPROM_WAIT_READY(st, sh); 1193 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1194 EEPROM_WAIT_READY(st, sh); 1195 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1196 EEPROM_WAIT_READY(st, sh); 1197 } 1198 1199 /* Shift in address. */ 1200 for (x = 6; x > 0; x--) { 1201 reg = EECTL_ENABLE|EECTL_EECS; 1202 if ((word + i) & (1 << (x - 1))) 1203 reg |= EECTL_EEDI; 1204 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1205 EEPROM_WAIT_READY(st, sh); 1206 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1207 EEPROM_WAIT_READY(st, sh); 1208 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1209 EEPROM_WAIT_READY(st, sh); 1210 } 1211 1212 /* Shift out data. */ 1213 reg = EECTL_ENABLE|EECTL_EECS; 1214 data[i] = 0; 1215 for (x = 16; x > 0; x--) { 1216 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1217 EEPROM_WAIT_READY(st, sh); 1218 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1219 data[i] |= (1 << (x - 1)); 1220 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1221 EEPROM_WAIT_READY(st, sh); 1222 } 1223 1224 /* Clear CHIP SELECT. */ 1225 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1226 EEPROM_WAIT_READY(st, sh); 1227 } 1228 1229 /* 1230 * Disable the EEPROM. 1231 */ 1232 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1233 1234 #undef EEPROM_WAIT_READY 1235 } 1236 1237 /* 1238 * Add a receive buffer to the indicated descriptor. 1239 */ 1240 int 1241 epic_add_rxbuf(struct epic_softc *sc, int idx) 1242 { 1243 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1244 struct mbuf *m; 1245 int error; 1246 1247 MGETHDR(m, M_DONTWAIT, MT_DATA); 1248 if (m == NULL) 1249 return (ENOBUFS); 1250 1251 MCLGET(m, M_DONTWAIT); 1252 if ((m->m_flags & M_EXT) == 0) { 1253 m_freem(m); 1254 return (ENOBUFS); 1255 } 1256 1257 if (ds->ds_mbuf != NULL) 1258 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1259 1260 ds->ds_mbuf = m; 1261 1262 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1263 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1264 BUS_DMA_READ|BUS_DMA_NOWAIT); 1265 if (error) { 1266 printf("%s: can't load rx DMA map %d, error = %d\n", 1267 sc->sc_dev.dv_xname, idx, error); 1268 panic("epic_add_rxbuf"); /* XXX */ 1269 } 1270 1271 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1272 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1273 1274 EPIC_INIT_RXDESC(sc, idx); 1275 1276 return (0); 1277 } 1278 1279 /* 1280 * Set the EPIC multicast hash table. 1281 * 1282 * NOTE: We rely on a recently-updated mii_media_active here! 1283 */ 1284 void 1285 epic_set_mchash(struct epic_softc *sc) 1286 { 1287 struct arpcom *ac = &sc->sc_arpcom; 1288 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1289 struct ether_multi *enm; 1290 struct ether_multistep step; 1291 u_int32_t hash, mchash[4]; 1292 1293 /* 1294 * Set up the multicast address filter by passing all multicast 1295 * addresses through a CRC generator, and then using the low-order 1296 * 6 bits as an index into the 64 bit multicast hash table (only 1297 * the lower 16 bits of each 32 bit multicast hash register are 1298 * valid). The high order bits select the register, while the 1299 * rest of the bits select the bit within the register. 1300 */ 1301 1302 if (ifp->if_flags & IFF_PROMISC) 1303 goto allmulti; 1304 1305 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1306 /* XXX hardware bug in 10Mbps mode. */ 1307 goto allmulti; 1308 } 1309 1310 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1311 1312 ETHER_FIRST_MULTI(step, ac, enm); 1313 while (enm != NULL) { 1314 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 1315 goto allmulti; 1316 1317 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1318 hash >>= 26; 1319 1320 /* Set the corresponding bit in the hash table. */ 1321 mchash[hash >> 4] |= 1 << (hash & 0xf); 1322 1323 ETHER_NEXT_MULTI(step, enm); 1324 } 1325 1326 ifp->if_flags &= ~IFF_ALLMULTI; 1327 goto sethash; 1328 1329 allmulti: 1330 ifp->if_flags |= IFF_ALLMULTI; 1331 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1332 1333 sethash: 1334 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1335 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1336 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1337 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1338 } 1339 1340 /* 1341 * Wait for the MII to become ready. 1342 */ 1343 int 1344 epic_mii_wait(struct epic_softc *sc, u_int32_t rw) 1345 { 1346 int i; 1347 1348 for (i = 0; i < 50; i++) { 1349 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1350 == 0) 1351 break; 1352 delay(2); 1353 } 1354 if (i == 50) { 1355 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1356 return (1); 1357 } 1358 1359 return (0); 1360 } 1361 1362 /* 1363 * Read from the MII. 1364 */ 1365 int 1366 epic_mii_read(struct device *self, int phy, int reg) 1367 { 1368 struct epic_softc *sc = (struct epic_softc *)self; 1369 1370 if (epic_mii_wait(sc, MMCTL_WRITE)) 1371 return (0); 1372 1373 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1374 MMCTL_ARG(phy, reg, MMCTL_READ)); 1375 1376 if (epic_mii_wait(sc, MMCTL_READ)) 1377 return (0); 1378 1379 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1380 MMDATA_MASK); 1381 } 1382 1383 /* 1384 * Write to the MII. 1385 */ 1386 void 1387 epic_mii_write(struct device *self, int phy, int reg, int val) 1388 { 1389 struct epic_softc *sc = (struct epic_softc *)self; 1390 1391 if (epic_mii_wait(sc, MMCTL_WRITE)) 1392 return; 1393 1394 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1395 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1396 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1397 } 1398 1399 /* 1400 * Callback from PHY when media changes. 1401 */ 1402 void 1403 epic_statchg(struct device *self) 1404 { 1405 struct epic_softc *sc = (struct epic_softc *)self; 1406 u_int32_t txcon, miicfg; 1407 1408 /* 1409 * Update loopback bits in TXCON to reflect duplex mode. 1410 */ 1411 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1412 if (sc->sc_mii.mii_media_active & IFM_FDX) 1413 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1414 else 1415 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1416 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1417 1418 /* On some cards we need manualy set fullduplex led */ 1419 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1420 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1421 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1422 miicfg |= MIICFG_ENABLE; 1423 else 1424 miicfg &= ~MIICFG_ENABLE; 1425 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1426 } 1427 1428 /* 1429 * There is a multicast filter bug in 10Mbps mode. Kick the 1430 * multicast filter in case the speed changed. 1431 */ 1432 epic_set_mchash(sc); 1433 } 1434 1435 /* 1436 * Callback from ifmedia to request current media status. 1437 */ 1438 void 1439 epic_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1440 { 1441 struct epic_softc *sc = ifp->if_softc; 1442 1443 mii_pollstat(&sc->sc_mii); 1444 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1445 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1446 } 1447 1448 /* 1449 * Callback from ifmedia to request new media setting. 1450 */ 1451 int 1452 epic_mediachange(struct ifnet *ifp) 1453 { 1454 struct epic_softc *sc = ifp->if_softc; 1455 struct mii_data *mii = &sc->sc_mii; 1456 struct ifmedia *ifm = &mii->mii_media; 1457 int media = ifm->ifm_cur->ifm_media; 1458 u_int32_t miicfg; 1459 struct mii_softc *miisc; 1460 int cfg; 1461 1462 if (!(ifp->if_flags & IFF_UP)) 1463 return (0); 1464 1465 if (IFM_INST(media) != sc->sc_serinst) { 1466 /* If we're not selecting serial interface, select MII mode */ 1467 #ifdef EPICMEDIADEBUG 1468 printf("%s: parallel mode\n", ifp->if_xname); 1469 #endif 1470 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1471 miicfg &= ~MIICFG_SERMODEENA; 1472 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1473 } 1474 1475 mii_mediachg(mii); 1476 1477 if (IFM_INST(media) == sc->sc_serinst) { 1478 /* select serial interface */ 1479 #ifdef EPICMEDIADEBUG 1480 printf("%s: serial mode\n", ifp->if_xname); 1481 #endif 1482 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1483 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1484 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1485 1486 /* There is no driver to fill this */ 1487 mii->mii_media_active = media; 1488 mii->mii_media_status = 0; 1489 1490 epic_statchg(&sc->sc_dev); 1491 return (0); 1492 } 1493 1494 /* Lookup selected PHY */ 1495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1496 miisc = LIST_NEXT(miisc, mii_list)) { 1497 if (IFM_INST(media) == miisc->mii_inst) 1498 break; 1499 } 1500 if (!miisc) { 1501 printf("epic_mediachange: can't happen\n"); /* ??? panic */ 1502 return (0); 1503 } 1504 #ifdef EPICMEDIADEBUG 1505 printf("%s: using phy %s\n", ifp->if_xname, 1506 miisc->mii_dev.dv_xname); 1507 #endif 1508 1509 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1510 /* XXX XXX assume it's a Level1 - should check */ 1511 1512 /* We have to powerup fiber transceivers */ 1513 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1514 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1515 #ifdef EPICMEDIADEBUG 1516 printf("%s: power up fiber\n", ifp->if_xname); 1517 #endif 1518 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1519 } else { 1520 #ifdef EPICMEDIADEBUG 1521 printf("%s: power down fiber\n", ifp->if_xname); 1522 #endif 1523 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1524 } 1525 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1526 } 1527 1528 return (0); 1529 } 1530