1 /* $OpenBSD: sili.c,v 1.51 2012/02/04 21:44:54 krw Exp $ */ 2 3 /* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * Copyright (c) 2010 Conformal Systems LLC <info@conformal.com> 6 * Copyright (c) 2010 Jonathan Matthew <jonathan@d14n.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/param.h> 22 #include <sys/systm.h> 23 #include <sys/buf.h> 24 #include <sys/device.h> 25 #include <sys/proc.h> 26 #include <sys/malloc.h> 27 #include <sys/kernel.h> 28 #include <sys/mutex.h> 29 30 #include <machine/bus.h> 31 32 #include <dev/ata/atascsi.h> 33 #include <dev/ata/pmreg.h> 34 35 #include <dev/ic/silireg.h> 36 #include <dev/ic/silivar.h> 37 38 /* use SILI_DEBUG for dmesg spam */ 39 #define NO_SILI_DEBUG 40 41 #ifdef SILI_DEBUG 42 #define SILI_D_VERBOSE (1<<0) 43 #define SILI_D_INTR (1<<1) 44 45 int silidebug = SILI_D_VERBOSE; 46 47 #define DPRINTF(m, a...) do { if ((m) & silidebug) printf(a); } while (0) 48 #else 49 #define DPRINTF(m, a...) 50 #endif 51 52 /* these can be used to simulate read and write errors on specific PMP ports */ 53 #undef SILI_ERROR_TEST 54 int sili_error_pmp_ports = 0; /* bitmask containing ports to fail*/ 55 int sili_error_test_inv_p = 500; /* 1/P(error) */ 56 int sili_error_restart_type = SILI_PREG_PCS_PORTINIT; /* or _DEVRESET */ 57 58 #ifdef SILI_ERROR_TEST 59 #include <dev/rndvar.h> 60 #endif 61 62 struct cfdriver sili_cd = { 63 NULL, "sili", DV_DULL 64 }; 65 66 /* wrapper around dma memory */ 67 struct sili_dmamem { 68 bus_dmamap_t sdm_map; 69 bus_dma_segment_t sdm_seg; 70 size_t sdm_size; 71 caddr_t sdm_kva; 72 }; 73 #define SILI_DMA_MAP(_sdm) ((_sdm)->sdm_map) 74 #define SILI_DMA_DVA(_sdm) ((_sdm)->sdm_map->dm_segs[0].ds_addr) 75 #define SILI_DMA_KVA(_sdm) ((_sdm)->sdm_kva) 76 77 struct sili_dmamem *sili_dmamem_alloc(struct sili_softc *, bus_size_t, 78 bus_size_t); 79 void sili_dmamem_free(struct sili_softc *, 80 struct sili_dmamem *); 81 82 /* per port goo */ 83 struct sili_ccb; 84 85 /* size of scratch space for use in error recovery. */ 86 #define SILI_SCRATCH_LEN 512 /* must be at least 1 sector */ 87 88 struct sili_port { 89 struct sili_softc *sp_sc; 90 bus_space_handle_t sp_ioh; 91 92 struct sili_ccb *sp_ccbs; 93 struct sili_dmamem *sp_cmds; 94 struct sili_dmamem *sp_scratch; 95 96 TAILQ_HEAD(, sili_ccb) sp_free_ccbs; 97 struct mutex sp_free_ccb_mtx; 98 99 volatile u_int32_t sp_active; 100 TAILQ_HEAD(, sili_ccb) sp_active_ccbs; 101 TAILQ_HEAD(, sili_ccb) sp_deferred_ccbs; 102 103 int sp_port; 104 int sp_pmp_ports; 105 int sp_active_pmp_ports; 106 int sp_pmp_error_recovery; /* port bitmask */ 107 volatile u_int32_t sp_err_active; /* cmd bitmask */ 108 volatile u_int32_t sp_err_cmds; /* cmd bitmask */ 109 110 #ifdef SILI_DEBUG 111 char sp_name[16]; 112 #define PORTNAME(_sp) ((_sp)->sp_name) 113 #else 114 #define PORTNAME(_sp) DEVNAME((_sp)->sp_sc) 115 #endif 116 }; 117 118 int sili_ports_alloc(struct sili_softc *); 119 void sili_ports_free(struct sili_softc *); 120 121 /* ccb shizz */ 122 123 /* 124 * the dma memory for each command will be made up of a prb followed by 125 * 7 sgts, this is a neat 512 bytes. 126 */ 127 #define SILI_CMD_LEN 512 128 129 /* 130 * you can fit 22 sge's into 7 sgts and a prb: 131 * there's 1 sgl in an atapi prb (two in the ata one, but we cant over 132 * advertise), but that's needed for the chain element. you get three sges 133 * per sgt cos you lose the 4th sge for the chaining, but you keep it in 134 * the last sgt. so 3 x 6 + 4 is 22. 135 */ 136 #define SILI_DMA_SEGS 22 137 138 struct sili_ccb { 139 struct ata_xfer ccb_xa; 140 141 void *ccb_cmd; 142 u_int64_t ccb_cmd_dva; 143 bus_dmamap_t ccb_dmamap; 144 145 struct sili_port *ccb_port; 146 147 TAILQ_ENTRY(sili_ccb) ccb_entry; 148 }; 149 150 int sili_ccb_alloc(struct sili_port *); 151 void sili_ccb_free(struct sili_port *); 152 struct sili_ccb *sili_get_ccb(struct sili_port *); 153 void sili_put_ccb(struct sili_ccb *); 154 155 /* bus space ops */ 156 u_int32_t sili_read(struct sili_softc *, bus_size_t); 157 void sili_write(struct sili_softc *, bus_size_t, u_int32_t); 158 u_int32_t sili_pread(struct sili_port *, bus_size_t); 159 void sili_pwrite(struct sili_port *, bus_size_t, u_int32_t); 160 int sili_pwait_eq(struct sili_port *, bus_size_t, 161 u_int32_t, u_int32_t, int); 162 int sili_pwait_ne(struct sili_port *, bus_size_t, 163 u_int32_t, u_int32_t, int); 164 165 /* command handling */ 166 void sili_post_direct(struct sili_port *, u_int, 167 void *, size_t buflen); 168 void sili_post_indirect(struct sili_port *, 169 struct sili_ccb *); 170 void sili_pread_fis(struct sili_port *, u_int, 171 struct ata_fis_d2h *); 172 u_int32_t sili_signature(struct sili_port *, u_int); 173 u_int32_t sili_port_softreset(struct sili_port *sp); 174 int sili_load(struct sili_ccb *, struct sili_sge *, int); 175 void sili_unload(struct sili_ccb *); 176 int sili_poll(struct sili_ccb *, int, void (*)(void *)); 177 void sili_start(struct sili_port *, struct sili_ccb *); 178 int sili_read_ncq_error(struct sili_port *, int *, int); 179 int sili_pmp_port_start_error_recovery(struct sili_port *, 180 int); 181 void sili_pmp_port_do_error_recovery(struct sili_port *, 182 int, u_int32_t *); 183 void sili_port_clear_commands(struct sili_port *sp); 184 185 /* pmp operations */ 186 int sili_pmp_read(struct sili_port *, int, int, 187 u_int32_t *); 188 int sili_pmp_write(struct sili_port *, int, int, u_int32_t); 189 int sili_pmp_phy_status(struct sili_port *, int, 190 u_int32_t *); 191 int sili_pmp_identify(struct sili_port *, int *); 192 193 /* port interrupt handler */ 194 u_int32_t sili_port_intr(struct sili_port *, int); 195 196 /* atascsi interface */ 197 int sili_ata_probe(void *, int, int); 198 void sili_ata_free(void *, int, int); 199 struct ata_xfer *sili_ata_get_xfer(void *, int); 200 void sili_ata_put_xfer(struct ata_xfer *); 201 void sili_ata_cmd(struct ata_xfer *); 202 int sili_pmp_portreset(struct sili_softc *, int, int); 203 int sili_pmp_softreset(struct sili_softc *, int, int); 204 205 #ifdef SILI_ERROR_TEST 206 void sili_simulate_error(struct sili_ccb *ccb, 207 int *need_restart, int *err_port); 208 #endif 209 210 struct atascsi_methods sili_atascsi_methods = { 211 sili_ata_probe, 212 sili_ata_free, 213 sili_ata_get_xfer, 214 sili_ata_put_xfer, 215 sili_ata_cmd 216 }; 217 218 /* completion paths */ 219 void sili_ata_cmd_done(struct sili_ccb *, int); 220 void sili_ata_cmd_timeout(void *); 221 void sili_dummy_done(struct ata_xfer *); 222 223 void sili_pmp_op_timeout(void *); 224 225 int 226 sili_attach(struct sili_softc *sc) 227 { 228 struct atascsi_attach_args aaa; 229 230 printf("\n"); 231 232 if (sili_ports_alloc(sc) != 0) { 233 /* error already printed by sili_port_alloc */ 234 return (1); 235 } 236 237 /* bounce the controller */ 238 sili_write(sc, SILI_REG_GC, SILI_REG_GC_GR); 239 sili_write(sc, SILI_REG_GC, 0x0); 240 241 bzero(&aaa, sizeof(aaa)); 242 aaa.aaa_cookie = sc; 243 aaa.aaa_methods = &sili_atascsi_methods; 244 aaa.aaa_minphys = NULL; 245 aaa.aaa_nports = sc->sc_nports; 246 aaa.aaa_ncmds = SILI_MAX_CMDS; 247 aaa.aaa_capability = ASAA_CAP_NCQ | ASAA_CAP_PMP_NCQ; 248 249 sc->sc_atascsi = atascsi_attach(&sc->sc_dev, &aaa); 250 251 return (0); 252 } 253 254 int 255 sili_detach(struct sili_softc *sc, int flags) 256 { 257 int rv; 258 259 if (sc->sc_atascsi != NULL) { 260 rv = atascsi_detach(sc->sc_atascsi, flags); 261 if (rv != 0) 262 return (rv); 263 } 264 265 if (sc->sc_ports != NULL) 266 sili_ports_free(sc); 267 268 return (0); 269 } 270 271 void 272 sili_resume(struct sili_softc *sc) 273 { 274 int i, j; 275 276 /* bounce the controller */ 277 sili_write(sc, SILI_REG_GC, SILI_REG_GC_GR); 278 sili_write(sc, SILI_REG_GC, 0x0); 279 280 for (i = 0; i < sc->sc_nports; i++) { 281 if (sili_ata_probe(sc, i, 0) == ATA_PORT_T_PM) { 282 struct sili_port *sp = &sc->sc_ports[i]; 283 for (j = 0; j < sp->sp_pmp_ports; j++) { 284 sili_ata_probe(sc, i, j); 285 } 286 } 287 } 288 } 289 290 int 291 sili_pmp_port_start_error_recovery(struct sili_port *sp, int err_port) 292 { 293 struct sili_ccb *ccb; 294 295 sp->sp_pmp_error_recovery |= (1 << err_port); 296 297 /* create a bitmask of active commands on non-error ports */ 298 sp->sp_err_active = 0; 299 TAILQ_FOREACH(ccb, &sp->sp_active_ccbs, ccb_entry) { 300 int bit = (1 << ccb->ccb_xa.pmp_port); 301 if ((sp->sp_pmp_error_recovery & bit) == 0) { 302 DPRINTF(SILI_D_VERBOSE, "%s: slot %d active on port " 303 "%d\n", PORTNAME(sp), ccb->ccb_xa.tag, 304 ccb->ccb_xa.pmp_port); 305 sp->sp_err_active |= (1 << ccb->ccb_xa.tag); 306 } 307 } 308 309 if (sp->sp_err_active == 0) { 310 DPRINTF(SILI_D_VERBOSE, "%s: no other PMP ports active\n", 311 PORTNAME(sp)); 312 sp->sp_pmp_error_recovery = 0; 313 return (0); 314 } 315 316 /* set port resume */ 317 sili_pwrite(sp, SILI_PREG_PCS, SILI_PREG_PCS_RESUME); 318 319 DPRINTF(SILI_D_VERBOSE, "%s: beginning error recovery (port %d); " 320 "error port mask %x, active slot mask %x\n", PORTNAME(sp), err_port, 321 sp->sp_pmp_error_recovery, sp->sp_err_active); 322 return (1); 323 } 324 325 void 326 sili_port_clear_commands(struct sili_port *sp) 327 { 328 int port; 329 330 DPRINTF(SILI_D_VERBOSE, "%s: clearing active commands\n", 331 PORTNAME(sp)); 332 333 /* clear port resume */ 334 sili_pwrite(sp, SILI_PREG_PCC, SILI_PREG_PCC_RESUME); 335 delay(10000); 336 337 /* clear port status and port active for all ports */ 338 for (port = 0; port < 16; port++) { 339 sili_pwrite(sp, SILI_PREG_PMP_STATUS(port), 0); 340 sili_pwrite(sp, SILI_PREG_PMP_QACTIVE(port), 0); 341 } 342 } 343 344 void 345 sili_pmp_port_do_error_recovery(struct sili_port *sp, int slot, 346 u_int32_t *need_restart) 347 { 348 if (sp->sp_pmp_error_recovery == 0) { 349 return; 350 } 351 352 /* have all outstanding commands finished yet? */ 353 if (sp->sp_err_active != 0) { 354 DPRINTF(SILI_D_VERBOSE, "%s: PMP error recovery still waiting " 355 "for %x\n", PORTNAME(sp), sp->sp_err_active); 356 *need_restart = 0; 357 return; 358 } 359 360 sili_port_clear_commands(sp); 361 362 /* get the main error recovery code to reset the port and 363 * resubmit commands. it will also reset the error recovery flags. 364 */ 365 *need_restart = SILI_PREG_PCS_PORTINIT; 366 DPRINTF(SILI_D_VERBOSE, "%s: PMP error recovery complete\n", 367 PORTNAME(sp)); 368 } 369 370 #ifdef SILI_ERROR_TEST 371 void 372 sili_simulate_error(struct sili_ccb *ccb, int *need_restart, int *err_port) 373 { 374 struct sili_port *sp = ccb->ccb_port; 375 376 if (*need_restart == 0 && 377 ((1 << ccb->ccb_xa.pmp_port) & sili_error_pmp_ports)) { 378 switch (ccb->ccb_xa.fis->command) { 379 case ATA_C_WRITE_FPDMA: 380 case ATA_C_READ_FPDMA: 381 case ATA_C_WRITEDMA_EXT: 382 case ATA_C_READDMA_EXT: 383 case ATA_C_WRITEDMA: 384 case ATA_C_READDMA: 385 if ((arc4random() % sili_error_test_inv_p) == 0) { 386 printf("%s: faking error on slot %d\n", 387 PORTNAME(sp), ccb->ccb_xa.tag); 388 ccb->ccb_xa.state = ATA_S_ERROR; 389 *need_restart = sili_error_restart_type; 390 *err_port = ccb->ccb_xa.pmp_port; 391 392 ccb->ccb_port->sp_err_cmds |= 393 (1 << ccb->ccb_xa.tag); 394 } 395 break; 396 397 default: 398 /* leave other commands alone, we only want to mess 399 * with normal read/write ops 400 */ 401 break; 402 } 403 } 404 } 405 #endif 406 407 u_int32_t 408 sili_port_intr(struct sili_port *sp, int timeout_slot) 409 { 410 u_int32_t is, pss_saved, pss_masked; 411 u_int32_t processed = 0, need_restart = 0; 412 u_int32_t err_port = 0; 413 int slot; 414 struct sili_ccb *ccb; 415 416 is = sili_pread(sp, SILI_PREG_IS); 417 pss_saved = sili_pread(sp, SILI_PREG_PSS); /* reading acks CMDCOMP */ 418 419 #ifdef SILI_DEBUG 420 if ((pss_saved & SILI_PREG_PSS_ALL_SLOTS) != sp->sp_active || 421 ((is >> 16) & ~SILI_PREG_IS_CMDCOMP)) { 422 DPRINTF(SILI_D_INTR, "%s: IS: 0x%08x (0x%b), PSS: %08x, " 423 "active: %08x\n", PORTNAME(sp), is, is >> 16, SILI_PFMT_IS, 424 pss_saved, sp->sp_active); 425 } 426 #endif 427 428 /* Only interested in slot status bits. */ 429 pss_saved &= SILI_PREG_PSS_ALL_SLOTS; 430 431 if (is & SILI_PREG_IS_CMDERR) { 432 int err_slot, err_code; 433 u_int32_t sactive = 0; 434 435 sili_pwrite(sp, SILI_PREG_IS, SILI_PREG_IS_CMDERR); 436 err_slot = SILI_PREG_PCS_ACTIVE(sili_pread(sp, SILI_PREG_PCS)); 437 err_code = sili_pread(sp, SILI_PREG_CE); 438 ccb = &sp->sp_ccbs[err_slot]; 439 440 switch (err_code) { 441 case SILI_PREG_CE_DEVICEERROR: 442 case SILI_PREG_CE_DATAFISERROR: 443 /* Extract error from command slot in LRAM. */ 444 sili_pread_fis(sp, err_slot, &ccb->ccb_xa.rfis); 445 err_port = ccb->ccb_xa.pmp_port; 446 break; 447 448 case SILI_PREG_CE_SDBERROR: 449 450 if (sp->sp_pmp_ports > 0) { 451 /* get the PMP port number for the error */ 452 err_port = (sili_pread(sp, SILI_PREG_CONTEXT) 453 >> SILI_PREG_CONTEXT_PMPORT_SHIFT) & 454 SILI_PREG_CONTEXT_PMPORT_MASK; 455 DPRINTF(SILI_D_VERBOSE, "%s: error port is " 456 "%d\n", PORTNAME(sp), err_port); 457 458 /* were there any NCQ commands active for 459 * the port? 460 */ 461 sactive = sili_pread(sp, 462 SILI_PREG_PMP_QACTIVE(err_port)); 463 DPRINTF(SILI_D_VERBOSE, "%s: error SActive " 464 "%x\n", PORTNAME(sp), sactive); 465 if (sactive == 0) 466 break; 467 } else { 468 /* No NCQ commands active? Treat as a normal 469 * error. 470 */ 471 sactive = sili_pread(sp, SILI_PREG_SACT); 472 if (sactive == 0) 473 break; 474 } 475 476 /* Extract real NCQ error slot & RFIS from 477 * log page. 478 */ 479 if (!sili_read_ncq_error(sp, &err_slot, err_port)) { 480 /* got real err_slot */ 481 DPRINTF(SILI_D_VERBOSE, "%s.%d: error slot " 482 "%d\n", PORTNAME(sp), err_port, err_slot); 483 ccb = &sp->sp_ccbs[err_slot]; 484 break; 485 } 486 DPRINTF(SILI_D_VERBOSE, "%s.%d: failed to get error " 487 "slot\n", PORTNAME(sp), err_port); 488 489 /* failed to get error or not NCQ */ 490 491 /* FALLTHROUGH */ 492 default: 493 /* All other error types are fatal. */ 494 if (err_code != SILI_PREG_CE_SDBERROR) { 495 err_port = (sili_pread(sp, SILI_PREG_CONTEXT) 496 >> SILI_PREG_CONTEXT_PMPORT_SHIFT) & 497 SILI_PREG_CONTEXT_PMPORT_MASK; 498 } 499 printf("%s.%d: fatal error (%d), aborting active slots " 500 "(%08x) and resetting device.\n", PORTNAME(sp), 501 err_port, err_code, pss_saved); 502 while (pss_saved) { 503 slot = ffs(pss_saved) - 1; 504 pss_saved &= ~(1 << slot); 505 506 ccb = &sp->sp_ccbs[slot]; 507 KASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP); 508 ccb->ccb_xa.state = ATA_S_ERROR; 509 } 510 need_restart = SILI_PREG_PCS_DEVRESET; 511 goto fatal; 512 } 513 514 DPRINTF(SILI_D_VERBOSE, "%s.%d: %serror, code %d, slot %d, " 515 "active %08x\n", PORTNAME(sp), err_port, 516 sactive ? "NCQ " : "", err_code, err_slot, sp->sp_active); 517 518 /* Clear the failed commmand in saved PSS so cmd_done runs. */ 519 pss_saved &= ~(1 << err_slot); 520 /* Track errored commands until we finish recovery */ 521 sp->sp_err_cmds |= (1 << err_slot); 522 523 KASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP); 524 ccb->ccb_xa.state = ATA_S_ERROR; 525 526 need_restart = SILI_PREG_PCS_PORTINIT; 527 } 528 fatal: 529 530 /* Process command timeout request only if command is still active. */ 531 if (timeout_slot >= 0 && (pss_saved & (1 << timeout_slot))) { 532 DPRINTF(SILI_D_VERBOSE, "%s: timing out slot %d, active %08x\n", 533 PORTNAME(sp), timeout_slot, sp->sp_active); 534 535 /* Clear the failed commmand in saved PSS so cmd_done runs. */ 536 pss_saved &= ~(1 << timeout_slot); 537 538 ccb = &sp->sp_ccbs[timeout_slot]; 539 KASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP); 540 ccb->ccb_xa.state = ATA_S_TIMEOUT; 541 542 /* Reinitialise the port and clear all active commands */ 543 need_restart = SILI_PREG_PCS_PORTINIT; 544 545 err_port = ccb->ccb_xa.pmp_port; 546 sp->sp_err_cmds |= (1 << timeout_slot); 547 548 sili_port_clear_commands(sp); 549 } 550 551 /* Command slot is complete if its bit in PSS is 0 but 1 in active. */ 552 pss_masked = ~pss_saved & sp->sp_active; 553 while (pss_masked) { 554 slot = ffs(pss_masked) - 1; 555 ccb = &sp->sp_ccbs[slot]; 556 pss_masked &= ~(1 << slot); 557 558 /* copy the rfis into the ccb if we were asked for it */ 559 if (ccb->ccb_xa.state == ATA_S_ONCHIP && 560 ccb->ccb_xa.flags & ATA_F_GET_RFIS) { 561 sili_pread_fis(sp, slot, &ccb->ccb_xa.rfis); 562 } 563 564 #ifdef SILI_ERROR_TEST 565 /* introduce random errors on reads and writes for testing */ 566 sili_simulate_error(ccb, &need_restart, &err_port); 567 #endif 568 569 DPRINTF(SILI_D_INTR, "%s: slot %d is complete%s%s\n", 570 PORTNAME(sp), slot, ccb->ccb_xa.state == ATA_S_ERROR ? 571 " (error)" : (ccb->ccb_xa.state == ATA_S_TIMEOUT ? 572 " (timeout)" : ""), 573 ccb->ccb_xa.flags & ATA_F_NCQ ? " (ncq)" : ""); 574 575 sili_ata_cmd_done(ccb, need_restart); 576 577 processed |= 1 << slot; 578 579 sili_pmp_port_do_error_recovery(sp, slot, &need_restart); 580 } 581 582 if (need_restart) { 583 584 if (sp->sp_pmp_error_recovery) { 585 if (sp->sp_err_active != 0) { 586 DPRINTF(SILI_D_VERBOSE, "%s: still waiting for " 587 "non-error commands to finish; port mask " 588 "%x, slot mask %x\n", PORTNAME(sp), 589 sp->sp_pmp_error_recovery, 590 sp->sp_err_active); 591 return (processed); 592 } 593 } else if (timeout_slot < 0 && sp->sp_pmp_ports > 0) { 594 /* wait until all other commands have finished before 595 * attempting to reinit the port. 596 */ 597 DPRINTF(SILI_D_VERBOSE, "%s: error on port with PMP " 598 "attached, error port %d\n", PORTNAME(sp), 599 err_port); 600 if (sili_pmp_port_start_error_recovery(sp, err_port)) { 601 DPRINTF(SILI_D_VERBOSE, "%s: need to wait for " 602 "other commands to finish\n", PORTNAME(sp)); 603 return (processed); 604 } 605 } else if (sp->sp_pmp_ports > 0) { 606 DPRINTF(SILI_D_VERBOSE, "%s: timeout on PMP port\n", 607 PORTNAME(sp)); 608 } else { 609 DPRINTF(SILI_D_VERBOSE, "%s: error on non-PMP port\n", 610 PORTNAME(sp)); 611 } 612 613 /* Re-enable transfers on port. */ 614 sili_pwrite(sp, SILI_PREG_PCS, need_restart); 615 if (!sili_pwait_eq(sp, SILI_PREG_PCS, need_restart, 0, 5000)) { 616 printf("%s: port reset bit didn't clear after error\n", 617 PORTNAME(sp)); 618 } 619 if (!sili_pwait_eq(sp, SILI_PREG_PCS, SILI_PREG_PCS_PORTRDY, 620 SILI_PREG_PCS_PORTRDY, 1000)) { 621 printf("%s: couldn't restart port after error\n", 622 PORTNAME(sp)); 623 } 624 sili_pwrite(sp, SILI_PREG_PCC, SILI_PREG_PCC_RESUME); 625 626 /* check that our active CCB list matches the restart mask */ 627 pss_masked = pss_saved & ~(sp->sp_err_cmds); 628 DPRINTF(SILI_D_VERBOSE, "%s: restart mask %x\n", 629 PORTNAME(sp), pss_masked); 630 TAILQ_FOREACH(ccb, &sp->sp_active_ccbs, ccb_entry) { 631 if (!(pss_masked & (1 << ccb->ccb_xa.tag))) { 632 panic("sili_intr: slot %d not active in " 633 "pss_masked: %08x, state %02x", 634 ccb->ccb_xa.tag, pss_masked, 635 ccb->ccb_xa.state); 636 } 637 pss_masked &= ~(1 << ccb->ccb_xa.tag); 638 } 639 if (pss_masked != 0) { 640 printf("%s: mask excluding active slots: %x\n", 641 PORTNAME(sp), pss_masked); 642 } 643 KASSERT(pss_masked == 0); 644 645 /* if we had a timeout on a PMP port, do a portreset. 646 * exclude the control port here as there isn't a real 647 * device there to reset. 648 */ 649 if (timeout_slot >= 0 && sp->sp_pmp_ports > 0 && 650 err_port != 15) { 651 652 DPRINTF(SILI_D_VERBOSE, 653 "%s.%d: doing portreset after timeout\n", 654 PORTNAME(sp), err_port); 655 sili_pmp_portreset(sp->sp_sc, sp->sp_port, err_port); 656 657 /* wait a bit to let the port settle down */ 658 delay(2000000); 659 } 660 661 /* if we sent a device reset to a PMP, we need to reset the 662 * devices behind it too. 663 */ 664 if (need_restart == SILI_PREG_PCS_DEVRESET && 665 sp->sp_pmp_ports > 0) { 666 int port_type; 667 int i; 668 669 port_type = sili_port_softreset(sp); 670 if (port_type != ATA_PORT_T_PM) { 671 /* device disappeared or changed type? */ 672 printf("%s: expected to find a port multiplier," 673 " got %d\n", PORTNAME(sp), port_type); 674 } 675 676 /* and now portreset all active ports */ 677 for (i = 0; i < sp->sp_pmp_ports; i++) { 678 struct sili_softc *sc = sp->sp_sc; 679 680 if ((sp->sp_active_pmp_ports & (1 << i)) == 0) 681 continue; 682 683 if (sili_pmp_portreset(sc, sp->sp_port, i)) { 684 printf("%s.%d: failed to portreset " 685 "after error\n", PORTNAME(sp), i); 686 } 687 } 688 } 689 690 /* Restart CCBs in the order they were originally queued. */ 691 TAILQ_FOREACH(ccb, &sp->sp_active_ccbs, ccb_entry) { 692 DPRINTF(SILI_D_VERBOSE, "%s: restarting slot %d " 693 "after error, state %02x\n", PORTNAME(sp), 694 ccb->ccb_xa.tag, ccb->ccb_xa.state); 695 KASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP); 696 sili_post_indirect(sp, ccb); 697 } 698 sp->sp_err_cmds = 0; 699 sp->sp_pmp_error_recovery = 0; 700 701 /* 702 * Finally, run atascsi completion for any finished CCBs. If 703 * we had run these during cmd_done above, any ccbs that their 704 * completion generated would have been activated out of order. 705 */ 706 while ((ccb = TAILQ_FIRST(&sp->sp_deferred_ccbs)) != NULL) { 707 TAILQ_REMOVE(&sp->sp_deferred_ccbs, ccb, ccb_entry); 708 709 DPRINTF(SILI_D_VERBOSE, "%s: running deferred " 710 "completion for slot %d, state %02x\n", 711 PORTNAME(sp), ccb->ccb_xa.tag, ccb->ccb_xa.state); 712 KASSERT(ccb->ccb_xa.state == ATA_S_COMPLETE || 713 ccb->ccb_xa.state == ATA_S_ERROR || 714 ccb->ccb_xa.state == ATA_S_TIMEOUT); 715 ata_complete(&ccb->ccb_xa); 716 } 717 } 718 719 return (processed); 720 } 721 722 int 723 sili_intr(void *arg) 724 { 725 struct sili_softc *sc = arg; 726 u_int32_t is; 727 int port; 728 729 /* If the card has gone away, this will return 0xffffffff. */ 730 is = sili_read(sc, SILI_REG_GIS); 731 if (is == 0 || is == 0xffffffff) 732 return (0); 733 sili_write(sc, SILI_REG_GIS, is); 734 DPRINTF(SILI_D_INTR, "sili_intr, GIS: %08x\n", is); 735 736 while (is & SILI_REG_GIS_PIS_MASK) { 737 port = ffs(is) - 1; 738 sili_port_intr(&sc->sc_ports[port], -1); 739 is &= ~(1 << port); 740 } 741 742 return (1); 743 } 744 745 int 746 sili_ports_alloc(struct sili_softc *sc) 747 { 748 struct sili_port *sp; 749 int i; 750 751 sc->sc_ports = malloc(sizeof(struct sili_port) * sc->sc_nports, 752 M_DEVBUF, M_WAITOK | M_ZERO); 753 754 for (i = 0; i < sc->sc_nports; i++) { 755 sp = &sc->sc_ports[i]; 756 757 sp->sp_sc = sc; 758 sp->sp_port = i; 759 #ifdef SILI_DEBUG 760 snprintf(sp->sp_name, sizeof(sp->sp_name), "%s.%d", 761 DEVNAME(sc), i); 762 #endif 763 if (bus_space_subregion(sc->sc_iot_port, sc->sc_ioh_port, 764 SILI_PORT_OFFSET(i), SILI_PORT_SIZE, &sp->sp_ioh) != 0) { 765 printf("%s: unable to create register window " 766 "for port %d\n", DEVNAME(sc), i); 767 goto freeports; 768 } 769 } 770 771 return (0); 772 773 freeports: 774 /* bus_space(9) says subregions dont have to be freed */ 775 free(sp, M_DEVBUF); 776 sc->sc_ports = NULL; 777 return (1); 778 } 779 780 void 781 sili_ports_free(struct sili_softc *sc) 782 { 783 struct sili_port *sp; 784 int i; 785 786 for (i = 0; i < sc->sc_nports; i++) { 787 sp = &sc->sc_ports[i]; 788 789 if (sp->sp_ccbs != NULL) 790 sili_ccb_free(sp); 791 } 792 793 /* bus_space(9) says subregions dont have to be freed */ 794 free(sc->sc_ports, M_DEVBUF); 795 sc->sc_ports = NULL; 796 } 797 798 int 799 sili_ccb_alloc(struct sili_port *sp) 800 { 801 struct sili_softc *sc = sp->sp_sc; 802 struct sili_ccb *ccb; 803 struct sili_prb *prb; 804 int i; 805 806 TAILQ_INIT(&sp->sp_free_ccbs); 807 mtx_init(&sp->sp_free_ccb_mtx, IPL_BIO); 808 TAILQ_INIT(&sp->sp_active_ccbs); 809 TAILQ_INIT(&sp->sp_deferred_ccbs); 810 811 sp->sp_ccbs = malloc(sizeof(struct sili_ccb) * SILI_MAX_CMDS, 812 M_DEVBUF, M_WAITOK); 813 sp->sp_cmds = sili_dmamem_alloc(sc, SILI_CMD_LEN * SILI_MAX_CMDS, 814 SILI_PRB_ALIGN); 815 if (sp->sp_cmds == NULL) 816 goto free_ccbs; 817 sp->sp_scratch = sili_dmamem_alloc(sc, SILI_SCRATCH_LEN, PAGE_SIZE); 818 if (sp->sp_scratch == NULL) 819 goto free_cmds; 820 821 bzero(sp->sp_ccbs, sizeof(struct sili_ccb) * SILI_MAX_CMDS); 822 823 for (i = 0; i < SILI_MAX_CMDS; i++) { 824 ccb = &sp->sp_ccbs[i]; 825 ccb->ccb_port = sp; 826 ccb->ccb_cmd = SILI_DMA_KVA(sp->sp_cmds) + i * SILI_CMD_LEN; 827 ccb->ccb_cmd_dva = SILI_DMA_DVA(sp->sp_cmds) + i * SILI_CMD_LEN; 828 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, SILI_DMA_SEGS, 829 MAXPHYS, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 830 &ccb->ccb_dmamap) != 0) 831 goto free_scratch; 832 833 prb = ccb->ccb_cmd; 834 ccb->ccb_xa.fis = (struct ata_fis_h2d *)&prb->fis; 835 ccb->ccb_xa.packetcmd = ((struct sili_prb_packet *)prb)->cdb; 836 ccb->ccb_xa.tag = i; 837 ccb->ccb_xa.state = ATA_S_COMPLETE; 838 839 sili_put_ccb(ccb); 840 } 841 842 return (0); 843 844 free_scratch: 845 sili_dmamem_free(sc, sp->sp_scratch); 846 free_cmds: 847 sili_dmamem_free(sc, sp->sp_cmds); 848 free_ccbs: 849 sili_ccb_free(sp); 850 return (1); 851 } 852 853 void 854 sili_ccb_free(struct sili_port *sp) 855 { 856 struct sili_softc *sc = sp->sp_sc; 857 struct sili_ccb *ccb; 858 859 while ((ccb = sili_get_ccb(sp)) != NULL) 860 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 861 862 free(sp->sp_ccbs, M_DEVBUF); 863 sp->sp_ccbs = NULL; 864 } 865 866 struct sili_ccb * 867 sili_get_ccb(struct sili_port *sp) 868 { 869 struct sili_ccb *ccb; 870 871 /* 872 * Don't allow new commands to start while doing PMP error 873 * recovery 874 */ 875 if (sp->sp_pmp_error_recovery != 0) { 876 return (NULL); 877 } 878 879 mtx_enter(&sp->sp_free_ccb_mtx); 880 ccb = TAILQ_FIRST(&sp->sp_free_ccbs); 881 if (ccb != NULL) { 882 KASSERT(ccb->ccb_xa.state == ATA_S_PUT); 883 TAILQ_REMOVE(&sp->sp_free_ccbs, ccb, ccb_entry); 884 ccb->ccb_xa.state = ATA_S_SETUP; 885 } 886 mtx_leave(&sp->sp_free_ccb_mtx); 887 888 return (ccb); 889 } 890 891 void 892 sili_put_ccb(struct sili_ccb *ccb) 893 { 894 struct sili_port *sp = ccb->ccb_port; 895 896 #ifdef DIAGNOSTIC 897 if (ccb->ccb_xa.state != ATA_S_COMPLETE && 898 ccb->ccb_xa.state != ATA_S_TIMEOUT && 899 ccb->ccb_xa.state != ATA_S_ERROR) { 900 printf("%s: invalid ata_xfer state %02x in sili_put_ccb, " 901 "slot %d\n", PORTNAME(sp), ccb->ccb_xa.state, 902 ccb->ccb_xa.tag); 903 } 904 #endif 905 906 ccb->ccb_xa.state = ATA_S_PUT; 907 mtx_enter(&sp->sp_free_ccb_mtx); 908 TAILQ_INSERT_TAIL(&sp->sp_free_ccbs, ccb, ccb_entry); 909 mtx_leave(&sp->sp_free_ccb_mtx); 910 } 911 912 struct sili_dmamem * 913 sili_dmamem_alloc(struct sili_softc *sc, bus_size_t size, bus_size_t align) 914 { 915 struct sili_dmamem *sdm; 916 int nsegs; 917 918 sdm = malloc(sizeof(*sdm), M_DEVBUF, M_WAITOK | M_ZERO); 919 sdm->sdm_size = size; 920 921 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 922 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &sdm->sdm_map) != 0) 923 goto sdmfree; 924 925 if (bus_dmamem_alloc(sc->sc_dmat, size, align, 0, &sdm->sdm_seg, 926 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 927 goto destroy; 928 929 if (bus_dmamem_map(sc->sc_dmat, &sdm->sdm_seg, nsegs, size, 930 &sdm->sdm_kva, BUS_DMA_NOWAIT) != 0) 931 goto free; 932 933 if (bus_dmamap_load(sc->sc_dmat, sdm->sdm_map, sdm->sdm_kva, size, 934 NULL, BUS_DMA_NOWAIT) != 0) 935 goto unmap; 936 937 return (sdm); 938 939 unmap: 940 bus_dmamem_unmap(sc->sc_dmat, sdm->sdm_kva, size); 941 free: 942 bus_dmamem_free(sc->sc_dmat, &sdm->sdm_seg, 1); 943 destroy: 944 bus_dmamap_destroy(sc->sc_dmat, sdm->sdm_map); 945 sdmfree: 946 free(sdm, M_DEVBUF); 947 948 return (NULL); 949 } 950 951 void 952 sili_dmamem_free(struct sili_softc *sc, struct sili_dmamem *sdm) 953 { 954 bus_dmamap_unload(sc->sc_dmat, sdm->sdm_map); 955 bus_dmamem_unmap(sc->sc_dmat, sdm->sdm_kva, sdm->sdm_size); 956 bus_dmamem_free(sc->sc_dmat, &sdm->sdm_seg, 1); 957 bus_dmamap_destroy(sc->sc_dmat, sdm->sdm_map); 958 free(sdm, M_DEVBUF); 959 } 960 961 u_int32_t 962 sili_read(struct sili_softc *sc, bus_size_t r) 963 { 964 u_int32_t rv; 965 966 bus_space_barrier(sc->sc_iot_global, sc->sc_ioh_global, r, 4, 967 BUS_SPACE_BARRIER_READ); 968 rv = bus_space_read_4(sc->sc_iot_global, sc->sc_ioh_global, r); 969 970 return (rv); 971 } 972 973 void 974 sili_write(struct sili_softc *sc, bus_size_t r, u_int32_t v) 975 { 976 bus_space_write_4(sc->sc_iot_global, sc->sc_ioh_global, r, v); 977 bus_space_barrier(sc->sc_iot_global, sc->sc_ioh_global, r, 4, 978 BUS_SPACE_BARRIER_WRITE); 979 } 980 981 u_int32_t 982 sili_pread(struct sili_port *sp, bus_size_t r) 983 { 984 u_int32_t rv; 985 986 bus_space_barrier(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, 4, 987 BUS_SPACE_BARRIER_READ); 988 rv = bus_space_read_4(sp->sp_sc->sc_iot_port, sp->sp_ioh, r); 989 990 return (rv); 991 } 992 993 void 994 sili_pwrite(struct sili_port *sp, bus_size_t r, u_int32_t v) 995 { 996 bus_space_write_4(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, v); 997 bus_space_barrier(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, 4, 998 BUS_SPACE_BARRIER_WRITE); 999 } 1000 1001 int 1002 sili_pwait_eq(struct sili_port *sp, bus_size_t r, u_int32_t mask, 1003 u_int32_t value, int timeout) 1004 { 1005 while ((sili_pread(sp, r) & mask) != value) { 1006 if (timeout == 0) 1007 return (0); 1008 1009 delay(1000); 1010 timeout--; 1011 } 1012 1013 return (1); 1014 } 1015 1016 int 1017 sili_pwait_ne(struct sili_port *sp, bus_size_t r, u_int32_t mask, 1018 u_int32_t value, int timeout) 1019 { 1020 while ((sili_pread(sp, r) & mask) == value) { 1021 if (timeout == 0) 1022 return (0); 1023 1024 delay(1000); 1025 timeout--; 1026 } 1027 1028 return (1); 1029 } 1030 1031 void 1032 sili_post_direct(struct sili_port *sp, u_int slot, void *buf, size_t buflen) 1033 { 1034 bus_size_t r = SILI_PREG_SLOT(slot); 1035 1036 #ifdef DIAGNOSTIC 1037 if (buflen != 64 && buflen != 128) 1038 panic("sili_pcopy: buflen of %lu is not 64 or 128", buflen); 1039 #endif 1040 1041 bus_space_write_raw_region_4(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, 1042 buf, buflen); 1043 bus_space_barrier(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, buflen, 1044 BUS_SPACE_BARRIER_WRITE); 1045 1046 sili_pwrite(sp, SILI_PREG_FIFO, slot); 1047 } 1048 1049 void 1050 sili_pread_fis(struct sili_port *sp, u_int slot, struct ata_fis_d2h *fis) 1051 { 1052 bus_size_t r = SILI_PREG_SLOT(slot) + 8; 1053 1054 bus_space_barrier(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, 1055 sizeof(struct ata_fis_d2h), BUS_SPACE_BARRIER_READ); 1056 bus_space_read_raw_region_4(sp->sp_sc->sc_iot_port, sp->sp_ioh, r, 1057 fis, sizeof(struct ata_fis_d2h)); 1058 } 1059 1060 void 1061 sili_post_indirect(struct sili_port *sp, struct sili_ccb *ccb) 1062 { 1063 sili_pwrite(sp, SILI_PREG_CAR_LO(ccb->ccb_xa.tag), 1064 (u_int32_t)ccb->ccb_cmd_dva); 1065 sili_pwrite(sp, SILI_PREG_CAR_HI(ccb->ccb_xa.tag), 1066 (u_int32_t)(ccb->ccb_cmd_dva >> 32)); 1067 } 1068 1069 u_int32_t 1070 sili_signature(struct sili_port *sp, u_int slot) 1071 { 1072 u_int32_t sig_hi, sig_lo; 1073 1074 sig_hi = sili_pread(sp, SILI_PREG_SIG_HI(slot)); 1075 sig_hi <<= SILI_PREG_SIG_HI_SHIFT; 1076 sig_lo = sili_pread(sp, SILI_PREG_SIG_LO(slot)); 1077 sig_lo &= SILI_PREG_SIG_LO_MASK; 1078 1079 return (sig_hi | sig_lo); 1080 } 1081 1082 void 1083 sili_dummy_done(struct ata_xfer *xa) 1084 { 1085 } 1086 1087 int 1088 sili_pmp_portreset(struct sili_softc *sc, int port, int pmp_port) 1089 { 1090 struct sili_port *sp; 1091 u_int32_t data; 1092 int loop; 1093 1094 sp = &sc->sc_ports[port]; 1095 DPRINTF(SILI_D_VERBOSE, "%s: resetting pmp port %d\n", PORTNAME(sp), 1096 pmp_port); 1097 1098 if (sili_pmp_write(sp, pmp_port, SATA_PMREG_SERR, -1)) 1099 goto err; 1100 if (sili_pmp_write(sp, pmp_port, SATA_PMREG_SCTL, 1101 SATA_PM_SCTL_IPM_DISABLED)) 1102 goto err; 1103 delay(10000); 1104 1105 /* enable PHY by writing 1 then 0 to Scontrol DET field, using 1106 * Write Port Multiplier commands 1107 */ 1108 data = SATA_PM_SCTL_IPM_DISABLED | SATA_PM_SCTL_DET_INIT | 1109 SATA_PM_SCTL_SPD_ANY; 1110 if (sili_pmp_write(sp, pmp_port, SATA_PMREG_SCTL, data)) 1111 goto err; 1112 delay(100000); 1113 1114 if (sili_pmp_phy_status(sp, pmp_port, &data)) { 1115 printf("%s: cannot clear phy status for PMP probe\n", 1116 PORTNAME(sp)); 1117 goto err; 1118 } 1119 1120 sili_pmp_write(sp, pmp_port, SATA_PMREG_SERR, -1); 1121 data = SATA_PM_SCTL_IPM_DISABLED | SATA_PM_SCTL_DET_NONE; 1122 if (sili_pmp_write(sp, pmp_port, SATA_PMREG_SCTL, data)) 1123 goto err; 1124 delay(100000); 1125 1126 /* wait for PHYRDY by polling SStatus */ 1127 for (loop = 3; loop; loop--) { 1128 if (sili_pmp_read(sp, pmp_port, SATA_PMREG_SSTS, &data)) 1129 goto err; 1130 if (data & SATA_PM_SSTS_DET) 1131 break; 1132 delay(100000); 1133 } 1134 if (loop == 0) { 1135 DPRINTF(SILI_D_VERBOSE, "%s.%d: port appears to be unplugged\n", 1136 PORTNAME(sp), pmp_port); 1137 goto err; 1138 } 1139 1140 /* give it a bit more time to complete negotiation */ 1141 for (loop = 30; loop; loop--) { 1142 if (sili_pmp_read(sp, pmp_port, SATA_PMREG_SSTS, &data)) 1143 goto err; 1144 if ((data & SATA_PM_SSTS_DET) == SATA_PM_SSTS_DET_DEV) 1145 break; 1146 delay(10000); 1147 } 1148 if (loop == 0) { 1149 printf("%s.%d: device may be powered down\n", PORTNAME(sp), 1150 pmp_port); 1151 goto err; 1152 } 1153 1154 DPRINTF(SILI_D_VERBOSE, "%s.%d: device detected; SStatus=%08x\n", 1155 PORTNAME(sp), pmp_port, data); 1156 1157 /* clear the X-bit and all other error bits in Serror (PCSR[1]) */ 1158 sili_pmp_write(sp, pmp_port, SATA_PMREG_SERR, -1); 1159 return (0); 1160 1161 err: 1162 DPRINTF(SILI_D_VERBOSE, "%s.%d: port reset failed\n", PORTNAME(sp), 1163 pmp_port); 1164 sili_pmp_write(sp, pmp_port, SATA_PMREG_SERR, -1); 1165 return (1); 1166 } 1167 1168 void 1169 sili_pmp_op_timeout(void *cookie) 1170 { 1171 struct sili_ccb *ccb = cookie; 1172 struct sili_port *sp = ccb->ccb_port; 1173 int s; 1174 1175 switch (ccb->ccb_xa.state) { 1176 case ATA_S_PENDING: 1177 TAILQ_REMOVE(&sp->sp_active_ccbs, ccb, ccb_entry); 1178 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1179 break; 1180 case ATA_S_ONCHIP: 1181 KASSERT(sp->sp_active == (1 << ccb->ccb_xa.tag)); 1182 s = splbio(); 1183 sili_port_intr(sp, ccb->ccb_xa.tag); 1184 splx(s); 1185 break; 1186 case ATA_S_ERROR: 1187 /* don't do anything? */ 1188 break; 1189 default: 1190 panic("%s: sili_pmp_op_timeout: ccb in bad state %d", 1191 PORTNAME(sp), ccb->ccb_xa.state); 1192 } 1193 } 1194 1195 int 1196 sili_pmp_softreset(struct sili_softc *sc, int port, int pmp_port) 1197 { 1198 struct sili_ccb *ccb; 1199 struct sili_prb *prb; 1200 struct sili_port *sp; 1201 struct ata_fis_h2d *fis; 1202 u_int32_t data; 1203 u_int32_t signature; 1204 1205 sp = &sc->sc_ports[port]; 1206 1207 ccb = sili_get_ccb(sp); 1208 if (ccb == NULL) { 1209 printf("%s: sili_pmp_softreset NULL ccb!\n", PORTNAME(sp)); 1210 return (-1); 1211 } 1212 1213 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_GET_RFIS; 1214 ccb->ccb_xa.complete = sili_dummy_done; 1215 ccb->ccb_xa.pmp_port = pmp_port; 1216 1217 prb = ccb->ccb_cmd; 1218 bzero(prb, sizeof(*prb)); 1219 fis = (struct ata_fis_h2d *)&prb->fis; 1220 fis->flags = pmp_port; 1221 prb->control = SILI_PRB_SOFT_RESET; 1222 1223 ccb->ccb_xa.state = ATA_S_PENDING; 1224 1225 if (sili_poll(ccb, 8000, sili_pmp_op_timeout) != 0) { 1226 DPRINTF(SILI_D_VERBOSE, "%s.%d: softreset FIS failed\n", 1227 PORTNAME(sp), pmp_port); 1228 1229 sili_put_ccb(ccb); 1230 /* don't return a valid device type here so the caller knows 1231 * it can retry if it wants to 1232 */ 1233 return (-1); 1234 } 1235 1236 signature = ccb->ccb_xa.rfis.sector_count | 1237 (ccb->ccb_xa.rfis.lba_low << 8) | 1238 (ccb->ccb_xa.rfis.lba_mid << 16) | 1239 (ccb->ccb_xa.rfis.lba_high << 24); 1240 DPRINTF(SILI_D_VERBOSE, "%s.%d: signature: %08x\n", PORTNAME(sp), 1241 pmp_port, signature); 1242 1243 sili_put_ccb(ccb); 1244 1245 /* clear phy status and error bits */ 1246 if (sili_pmp_phy_status(sp, pmp_port, &data)) { 1247 printf("%s.%d: cannot clear phy status after softreset\n", 1248 PORTNAME(sp), pmp_port); 1249 } 1250 sili_pmp_write(sp, pmp_port, SATA_PMREG_SERR, -1); 1251 1252 /* classify the device based on its signature */ 1253 switch (signature) { 1254 case SATA_SIGNATURE_DISK: 1255 return (ATA_PORT_T_DISK); 1256 case SATA_SIGNATURE_ATAPI: 1257 return (ATA_PORT_T_ATAPI); 1258 case SATA_SIGNATURE_PORT_MULTIPLIER: 1259 return (ATA_PORT_T_NONE); 1260 default: 1261 return (ATA_PORT_T_NONE); 1262 } 1263 } 1264 1265 u_int32_t 1266 sili_port_softreset(struct sili_port *sp) 1267 { 1268 struct sili_prb_softreset sreset; 1269 u_int32_t signature; 1270 1271 bzero(&sreset, sizeof(sreset)); 1272 sreset.control = htole16(SILI_PRB_SOFT_RESET | SILI_PRB_INTERRUPT_MASK); 1273 sreset.fis[1] = SATA_PMP_CONTROL_PORT; 1274 1275 /* we use slot 0 */ 1276 sili_post_direct(sp, 0, &sreset, sizeof(sreset)); 1277 if (!sili_pwait_eq(sp, SILI_PREG_PSS, (1 << 0), 0, 1000)) { 1278 DPRINTF(SILI_D_VERBOSE, "%s: timed out while waiting for soft " 1279 "reset\n", PORTNAME(sp)); 1280 return (ATA_PORT_T_NONE); 1281 } 1282 1283 /* Read device signature from command slot. */ 1284 signature = sili_signature(sp, 0); 1285 1286 DPRINTF(SILI_D_VERBOSE, "%s: signature 0x%08x\n", PORTNAME(sp), 1287 signature); 1288 1289 switch (signature) { 1290 case SATA_SIGNATURE_DISK: 1291 return (ATA_PORT_T_DISK); 1292 case SATA_SIGNATURE_ATAPI: 1293 return (ATA_PORT_T_ATAPI); 1294 case SATA_SIGNATURE_PORT_MULTIPLIER: 1295 return (ATA_PORT_T_PM); 1296 default: 1297 return (ATA_PORT_T_NONE); 1298 } 1299 } 1300 1301 int 1302 sili_ata_probe(void *xsc, int port, int lun) 1303 { 1304 struct sili_softc *sc = xsc; 1305 struct sili_port *sp = &sc->sc_ports[port]; 1306 int port_type; 1307 1308 /* handle pmp port probes */ 1309 if (lun != 0) { 1310 int i; 1311 int rc; 1312 int pmp_port = lun - 1; 1313 1314 if (lun > sp->sp_pmp_ports) 1315 return (ATA_PORT_T_NONE); 1316 1317 for (i = 0; i < 2; i++) { 1318 if (sili_pmp_portreset(sc, port, pmp_port)) { 1319 continue; 1320 } 1321 1322 /* small delay between attempts to allow error 1323 * conditions to settle down. this doesn't seem 1324 * to affect portreset operations, just 1325 * commands sent to the device. 1326 */ 1327 if (i != 0) { 1328 delay(5000000); 1329 } 1330 1331 rc = sili_pmp_softreset(sc, port, pmp_port); 1332 switch (rc) { 1333 case -1: 1334 /* possibly try again */ 1335 break; 1336 case ATA_PORT_T_DISK: 1337 case ATA_PORT_T_ATAPI: 1338 /* mark this port as active */ 1339 sp->sp_active_pmp_ports |= (1 << pmp_port); 1340 default: 1341 return (rc); 1342 } 1343 } 1344 DPRINTF(SILI_D_VERBOSE, "%s.%d: probe failed\n", PORTNAME(sp), 1345 pmp_port); 1346 return (ATA_PORT_T_NONE); 1347 } 1348 1349 sili_pwrite(sp, SILI_PREG_PCS, SILI_PREG_PCS_PORTRESET); 1350 delay(10000); 1351 sili_pwrite(sp, SILI_PREG_PCC, SILI_PREG_PCC_PORTRESET); 1352 1353 sili_pwrite(sp, SILI_PREG_PCS, SILI_PREG_PCS_PORTINIT); 1354 if (!sili_pwait_eq(sp, SILI_PREG_PCS, SILI_PREG_PCS_PORTRDY, 1355 SILI_PREG_PCS_PORTRDY, 1000)) { 1356 printf("%s: couldn't initialize port\n", PORTNAME(sp)); 1357 return (ATA_PORT_T_NONE); 1358 } 1359 1360 sili_pwrite(sp, SILI_PREG_PCC, SILI_PREG_PCC_A32B); 1361 1362 if (!sili_pwait_eq(sp, SILI_PREG_SSTS, SATA_SStatus_DET, 1363 SATA_SStatus_DET_DEV, 2000)) { 1364 DPRINTF(SILI_D_VERBOSE, "%s: unattached\n", PORTNAME(sp)); 1365 return (ATA_PORT_T_NONE); 1366 } 1367 1368 DPRINTF(SILI_D_VERBOSE, "%s: SSTS 0x%08x\n", PORTNAME(sp), 1369 sili_pread(sp, SILI_PREG_SSTS)); 1370 1371 port_type = sili_port_softreset(sp); 1372 if (port_type == ATA_PORT_T_NONE) 1373 return (port_type); 1374 1375 /* allocate port resources */ 1376 if (sili_ccb_alloc(sp) != 0) 1377 return (ATA_PORT_T_NONE); 1378 1379 /* do PMP probe now that we can talk to the device */ 1380 if (port_type == ATA_PORT_T_PM) { 1381 int i; 1382 1383 sili_pwrite(sp, SILI_PREG_PCS, SILI_PREG_PCS_PMEN); 1384 1385 if (sili_pmp_identify(sp, &sp->sp_pmp_ports)) { 1386 return (ATA_PORT_T_NONE); 1387 } 1388 1389 /* reset all the PMP ports to wake devices up */ 1390 for (i = 0; i < sp->sp_pmp_ports; i++) { 1391 sili_pmp_portreset(sp->sp_sc, sp->sp_port, i); 1392 } 1393 } 1394 1395 /* enable port interrupts */ 1396 sili_write(sc, SILI_REG_GC, sili_read(sc, SILI_REG_GC) | 1 << port); 1397 sili_pwrite(sp, SILI_PREG_IES, SILI_PREG_IE_CMDERR | 1398 SILI_PREG_IE_CMDCOMP); 1399 1400 return (port_type); 1401 } 1402 1403 void 1404 sili_ata_free(void *xsc, int port, int lun) 1405 { 1406 struct sili_softc *sc = xsc; 1407 struct sili_port *sp = &sc->sc_ports[port]; 1408 1409 if (lun == 0) { 1410 if (sp->sp_ccbs != NULL) 1411 sili_ccb_free(sp); 1412 1413 /* XXX we should do more here */ 1414 } 1415 } 1416 1417 void 1418 sili_ata_cmd(struct ata_xfer *xa) 1419 { 1420 struct sili_ccb *ccb = (struct sili_ccb *)xa; 1421 struct sili_port *sp = ccb->ccb_port; 1422 struct sili_softc *sc = sp->sp_sc; 1423 struct sili_prb_ata *ata; 1424 struct sili_prb_packet *atapi; 1425 struct sili_sge *sgl; 1426 int sgllen; 1427 int s; 1428 1429 KASSERT(xa->state == ATA_S_SETUP || xa->state == ATA_S_TIMEOUT); 1430 1431 if (xa->flags & ATA_F_PACKET) { 1432 atapi = ccb->ccb_cmd; 1433 1434 if (xa->flags & ATA_F_WRITE) 1435 atapi->control = htole16(SILI_PRB_PACKET_WRITE); 1436 else 1437 atapi->control = htole16(SILI_PRB_PACKET_READ); 1438 1439 sgl = atapi->sgl; 1440 sgllen = nitems(atapi->sgl); 1441 } else { 1442 ata = ccb->ccb_cmd; 1443 1444 ata->control = 0; 1445 1446 sgl = ata->sgl; 1447 sgllen = nitems(ata->sgl); 1448 } 1449 1450 if (sili_load(ccb, sgl, sgllen) != 0) 1451 goto failcmd; 1452 1453 bus_dmamap_sync(sc->sc_dmat, SILI_DMA_MAP(sp->sp_cmds), 1454 xa->tag * SILI_CMD_LEN, SILI_CMD_LEN, BUS_DMASYNC_PREWRITE); 1455 1456 timeout_set(&xa->stimeout, sili_ata_cmd_timeout, ccb); 1457 1458 xa->state = ATA_S_PENDING; 1459 1460 if (xa->flags & ATA_F_POLL) 1461 sili_poll(ccb, xa->timeout, sili_ata_cmd_timeout); 1462 else { 1463 s = splbio(); 1464 timeout_add_msec(&xa->stimeout, xa->timeout); 1465 sili_start(sp, ccb); 1466 splx(s); 1467 } 1468 1469 return; 1470 1471 failcmd: 1472 s = splbio(); 1473 xa->state = ATA_S_ERROR; 1474 ata_complete(xa); 1475 splx(s); 1476 } 1477 1478 void 1479 sili_ata_cmd_done(struct sili_ccb *ccb, int defer_completion) 1480 { 1481 struct sili_port *sp = ccb->ccb_port; 1482 struct sili_softc *sc = sp->sp_sc; 1483 struct ata_xfer *xa = &ccb->ccb_xa; 1484 1485 splassert(IPL_BIO); 1486 1487 timeout_del(&xa->stimeout); 1488 1489 bus_dmamap_sync(sc->sc_dmat, SILI_DMA_MAP(sp->sp_cmds), 1490 xa->tag * SILI_CMD_LEN, SILI_CMD_LEN, BUS_DMASYNC_POSTWRITE); 1491 1492 sili_unload(ccb); 1493 1494 TAILQ_REMOVE(&sp->sp_active_ccbs, ccb, ccb_entry); 1495 sp->sp_active &= ~(1 << xa->tag); 1496 if (sp->sp_err_active & (1 << xa->tag)) { 1497 sp->sp_err_active &= ~(1 << xa->tag); 1498 DPRINTF(SILI_D_VERBOSE, "%s: slot %d complete, error mask now " 1499 "%x\n", PORTNAME(sp), xa->tag, sp->sp_err_active); 1500 } 1501 1502 if (xa->state == ATA_S_ONCHIP) 1503 xa->state = ATA_S_COMPLETE; 1504 #ifdef DIAGNOSTIC 1505 else if (xa->state != ATA_S_ERROR && xa->state != ATA_S_TIMEOUT) 1506 printf("%s: invalid ata_xfer state %02x in sili_ata_cmd_done, " 1507 "slot %d\n", PORTNAME(sp), xa->state, xa->tag); 1508 #endif 1509 if (defer_completion) 1510 TAILQ_INSERT_TAIL(&sp->sp_deferred_ccbs, ccb, ccb_entry); 1511 else if (xa->state == ATA_S_COMPLETE) 1512 ata_complete(xa); 1513 #ifdef DIAGNOSTIC 1514 else 1515 printf("%s: completion not deferred, but xa->state is %02x?\n", 1516 PORTNAME(sp), xa->state); 1517 #endif 1518 } 1519 1520 void 1521 sili_ata_cmd_timeout(void *xccb) 1522 { 1523 struct sili_ccb *ccb = xccb; 1524 struct sili_port *sp = ccb->ccb_port; 1525 int s; 1526 1527 s = splbio(); 1528 sili_port_intr(sp, ccb->ccb_xa.tag); 1529 splx(s); 1530 } 1531 1532 int 1533 sili_load(struct sili_ccb *ccb, struct sili_sge *sgl, int sgllen) 1534 { 1535 struct sili_port *sp = ccb->ccb_port; 1536 struct sili_softc *sc = sp->sp_sc; 1537 struct ata_xfer *xa = &ccb->ccb_xa; 1538 struct sili_sge *nsge = sgl, *ce = NULL; 1539 bus_dmamap_t dmap = ccb->ccb_dmamap; 1540 u_int64_t addr; 1541 int error; 1542 int i; 1543 1544 if (xa->datalen == 0) 1545 return (0); 1546 1547 error = bus_dmamap_load(sc->sc_dmat, dmap, xa->data, xa->datalen, NULL, 1548 (xa->flags & ATA_F_NOWAIT) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 1549 if (error != 0) { 1550 printf("%s: error %d loading dmamap\n", PORTNAME(sp), error); 1551 return (1); 1552 } 1553 1554 if (dmap->dm_nsegs > sgllen) 1555 ce = &sgl[sgllen - 1]; 1556 1557 for (i = 0; i < dmap->dm_nsegs; i++) { 1558 if (nsge == ce) { 1559 nsge++; 1560 1561 addr = ccb->ccb_cmd_dva; 1562 addr += ((u_int8_t *)nsge - (u_int8_t *)ccb->ccb_cmd); 1563 1564 ce->addr_lo = htole32((u_int32_t)addr); 1565 ce->addr_hi = htole32((u_int32_t)(addr >> 32)); 1566 ce->flags = htole32(SILI_SGE_LNK); 1567 1568 if ((dmap->dm_nsegs - i) > SILI_SGT_SGLLEN) 1569 ce += SILI_SGT_SGLLEN; 1570 else 1571 ce = NULL; 1572 } 1573 1574 sgl = nsge; 1575 1576 addr = dmap->dm_segs[i].ds_addr; 1577 sgl->addr_lo = htole32((u_int32_t)addr); 1578 sgl->addr_hi = htole32((u_int32_t)(addr >> 32)); 1579 sgl->data_count = htole32(dmap->dm_segs[i].ds_len); 1580 sgl->flags = 0; 1581 1582 nsge++; 1583 } 1584 sgl->flags |= htole32(SILI_SGE_TRM); 1585 1586 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1587 (xa->flags & ATA_F_READ) ? BUS_DMASYNC_PREREAD : 1588 BUS_DMASYNC_PREWRITE); 1589 1590 return (0); 1591 } 1592 1593 void 1594 sili_unload(struct sili_ccb *ccb) 1595 { 1596 struct sili_port *sp = ccb->ccb_port; 1597 struct sili_softc *sc = sp->sp_sc; 1598 struct ata_xfer *xa = &ccb->ccb_xa; 1599 bus_dmamap_t dmap = ccb->ccb_dmamap; 1600 1601 if (xa->datalen == 0) 1602 return; 1603 1604 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1605 (xa->flags & ATA_F_READ) ? BUS_DMASYNC_POSTREAD : 1606 BUS_DMASYNC_POSTWRITE); 1607 bus_dmamap_unload(sc->sc_dmat, dmap); 1608 1609 if (xa->flags & ATA_F_READ) 1610 xa->resid = xa->datalen - sili_pread(sp, 1611 SILI_PREG_RX_COUNT(xa->tag)); 1612 else 1613 xa->resid = 0; 1614 } 1615 1616 int 1617 sili_poll(struct sili_ccb *ccb, int timeout, void (*timeout_fn)(void *)) 1618 { 1619 struct sili_port *sp = ccb->ccb_port; 1620 int s; 1621 1622 s = splbio(); 1623 sili_start(sp, ccb); 1624 do { 1625 if (sili_port_intr(sp, -1) & (1 << ccb->ccb_xa.tag)) { 1626 splx(s); 1627 return (ccb->ccb_xa.state != ATA_S_COMPLETE); 1628 } 1629 1630 delay(1000); 1631 } while (--timeout > 0); 1632 1633 /* Run timeout while at splbio, otherwise sili_intr could interfere. */ 1634 if (timeout_fn != NULL) 1635 timeout_fn(ccb); 1636 1637 splx(s); 1638 1639 return (1); 1640 } 1641 1642 void 1643 sili_start(struct sili_port *sp, struct sili_ccb *ccb) 1644 { 1645 int slot = ccb->ccb_xa.tag; 1646 1647 splassert(IPL_BIO); 1648 KASSERT(ccb->ccb_xa.state == ATA_S_PENDING); 1649 KASSERT(sp->sp_pmp_error_recovery == 0); 1650 1651 TAILQ_INSERT_TAIL(&sp->sp_active_ccbs, ccb, ccb_entry); 1652 sp->sp_active |= 1 << slot; 1653 ccb->ccb_xa.state = ATA_S_ONCHIP; 1654 1655 sili_post_indirect(sp, ccb); 1656 } 1657 1658 int 1659 sili_read_ncq_error(struct sili_port *sp, int *err_slotp, int pmp_port) 1660 { 1661 struct sili_softc *sc = sp->sp_sc; 1662 struct sili_prb_ata read_10h; 1663 u_int64_t addr; 1664 struct ata_fis_h2d *fis; 1665 struct ata_log_page_10h *log; 1666 struct sili_ccb *ccb; 1667 int rc; 1668 1669 sili_pwrite(sp, SILI_PREG_PCS, SILI_PREG_PCS_PORTINIT); 1670 if (!sili_pwait_eq(sp, SILI_PREG_PCS, SILI_PREG_PCS_PORTRDY, 1671 SILI_PREG_PCS_PORTRDY, 1000)) { 1672 printf("%s: couldn't ready port during log page read\n", 1673 PORTNAME(sp)); 1674 return (1); 1675 } 1676 1677 /* READ LOG EXT 10h into scratch space */ 1678 bzero(&read_10h, sizeof(read_10h)); 1679 read_10h.control = htole16(SILI_PRB_INTERRUPT_MASK); 1680 1681 addr = SILI_DMA_DVA(sp->sp_scratch); 1682 read_10h.sgl[0].addr_lo = htole32((u_int32_t)addr); 1683 read_10h.sgl[0].addr_hi = htole32((u_int32_t)(addr >> 32)); 1684 read_10h.sgl[0].data_count = htole32(512); 1685 read_10h.sgl[0].flags = htole32(SILI_SGE_TRM); 1686 1687 fis = (struct ata_fis_h2d *)read_10h.fis; 1688 fis->type = ATA_FIS_TYPE_H2D; 1689 fis->flags = ATA_H2D_FLAGS_CMD | pmp_port; 1690 fis->command = ATA_C_READ_LOG_EXT; 1691 fis->lba_low = 0x10; /* queued error log page (10h) */ 1692 fis->sector_count = 1; /* number of sectors (1) */ 1693 fis->sector_count_exp = 0; 1694 fis->lba_mid = 0; /* starting offset */ 1695 fis->lba_mid_exp = 0; 1696 fis->device = 0; 1697 1698 bus_dmamap_sync(sc->sc_dmat, SILI_DMA_MAP(sp->sp_scratch), 0, 1699 512, BUS_DMASYNC_PREREAD); 1700 1701 /* issue read and poll for completion */ 1702 sili_post_direct(sp, 0, &read_10h, sizeof(read_10h)); 1703 rc = sili_pwait_eq(sp, SILI_PREG_PSS, (1 << 0), 0, 1000); 1704 1705 bus_dmamap_sync(sc->sc_dmat, SILI_DMA_MAP(sp->sp_scratch), 0, 1706 512, BUS_DMASYNC_POSTREAD); 1707 1708 if (!rc) { 1709 DPRINTF(SILI_D_VERBOSE, "%s: timed out while waiting for log " 1710 "page read\n", PORTNAME(sp)); 1711 return (1); 1712 } 1713 1714 /* Extract failed register set and tags from the scratch space. */ 1715 log = (struct ata_log_page_10h *)SILI_DMA_KVA(sp->sp_scratch); 1716 if (ISSET(log->err_regs.type, ATA_LOG_10H_TYPE_NOTQUEUED)) { 1717 /* Not queued bit was set - wasn't an NCQ error? */ 1718 printf("%s: read NCQ error page, but not an NCQ error?\n", 1719 PORTNAME(sp)); 1720 return (1); 1721 } 1722 1723 /* Copy back the log record as a D2H register FIS. */ 1724 *err_slotp = log->err_regs.type & ATA_LOG_10H_TYPE_TAG_MASK; 1725 1726 ccb = &sp->sp_ccbs[*err_slotp]; 1727 memcpy(&ccb->ccb_xa.rfis, &log->err_regs, sizeof(struct ata_fis_d2h)); 1728 ccb->ccb_xa.rfis.type = ATA_FIS_TYPE_D2H; 1729 ccb->ccb_xa.rfis.flags = 0; 1730 1731 return (0); 1732 } 1733 1734 struct ata_xfer * 1735 sili_ata_get_xfer(void *xsc, int port) 1736 { 1737 struct sili_softc *sc = xsc; 1738 struct sili_port *sp = &sc->sc_ports[port]; 1739 struct sili_ccb *ccb; 1740 1741 ccb = sili_get_ccb(sp); 1742 if (ccb == NULL) { 1743 printf("%s: sili_ata_get_xfer NULL ccb!\n", PORTNAME(sp)); 1744 return (NULL); 1745 } 1746 1747 bzero(ccb->ccb_cmd, SILI_CMD_LEN); 1748 1749 return ((struct ata_xfer *)ccb); 1750 } 1751 1752 void 1753 sili_ata_put_xfer(struct ata_xfer *xa) 1754 { 1755 struct sili_ccb *ccb = (struct sili_ccb *)xa; 1756 1757 sili_put_ccb(ccb); 1758 } 1759 1760 /* PMP register ops */ 1761 int 1762 sili_pmp_read(struct sili_port *sp, int target, int which, u_int32_t *datap) 1763 { 1764 struct sili_ccb *ccb; 1765 struct sili_prb *prb; 1766 struct ata_fis_h2d *fis; 1767 int error; 1768 1769 ccb = sili_get_ccb(sp); 1770 if (ccb == NULL) { 1771 printf("%s: sili_pmp_read NULL ccb!\n", PORTNAME(sp)); 1772 return (1); 1773 } 1774 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_GET_RFIS; 1775 ccb->ccb_xa.complete = sili_dummy_done; 1776 ccb->ccb_xa.pmp_port = SATA_PMP_CONTROL_PORT; 1777 ccb->ccb_xa.state = ATA_S_PENDING; 1778 1779 prb = ccb->ccb_cmd; 1780 bzero(prb, sizeof(*prb)); 1781 fis = (struct ata_fis_h2d *)&prb->fis; 1782 fis->type = ATA_FIS_TYPE_H2D; 1783 fis->flags = ATA_H2D_FLAGS_CMD | SATA_PMP_CONTROL_PORT; 1784 fis->command = ATA_C_READ_PM; 1785 fis->features = which; 1786 fis->device = target | ATA_H2D_DEVICE_LBA; 1787 fis->control = ATA_FIS_CONTROL_4BIT; 1788 1789 if (sili_poll(ccb, 1000, sili_pmp_op_timeout) != 0) { 1790 printf("sili_pmp_read(%d, %d) failed\n", target, which); 1791 error = 1; 1792 } else { 1793 *datap = ccb->ccb_xa.rfis.sector_count | 1794 (ccb->ccb_xa.rfis.lba_low << 8) | 1795 (ccb->ccb_xa.rfis.lba_mid << 16) | 1796 (ccb->ccb_xa.rfis.lba_high << 24); 1797 error = 0; 1798 } 1799 sili_put_ccb(ccb); 1800 return (error); 1801 } 1802 1803 int 1804 sili_pmp_write(struct sili_port *sp, int target, int which, u_int32_t data) 1805 { 1806 struct sili_ccb *ccb; 1807 struct sili_prb *prb; 1808 struct ata_fis_h2d *fis; 1809 int error; 1810 1811 ccb = sili_get_ccb(sp); 1812 if (ccb == NULL) { 1813 printf("%s: sili_pmp_write NULL ccb!\n", PORTNAME(sp)); 1814 return (1); 1815 } 1816 ccb->ccb_xa.complete = sili_dummy_done; 1817 ccb->ccb_xa.flags = ATA_F_POLL; 1818 ccb->ccb_xa.pmp_port = SATA_PMP_CONTROL_PORT; 1819 ccb->ccb_xa.state = ATA_S_PENDING; 1820 1821 prb = ccb->ccb_cmd; 1822 bzero(prb, sizeof(*prb)); 1823 fis = (struct ata_fis_h2d *)&prb->fis; 1824 fis->type = ATA_FIS_TYPE_H2D; 1825 fis->flags = ATA_H2D_FLAGS_CMD | SATA_PMP_CONTROL_PORT; 1826 fis->command = ATA_C_WRITE_PM; 1827 fis->features = which; 1828 fis->device = target | ATA_H2D_DEVICE_LBA; 1829 fis->sector_count = (u_int8_t)data; 1830 fis->lba_low = (u_int8_t)(data >> 8); 1831 fis->lba_mid = (u_int8_t)(data >> 16); 1832 fis->lba_high = (u_int8_t)(data >> 24); 1833 fis->control = ATA_FIS_CONTROL_4BIT; 1834 1835 error = sili_poll(ccb, 1000, sili_pmp_op_timeout); 1836 sili_put_ccb(ccb); 1837 return (error); 1838 } 1839 1840 int 1841 sili_pmp_phy_status(struct sili_port *sp, int target, u_int32_t *datap) 1842 { 1843 int error; 1844 1845 error = sili_pmp_read(sp, target, SATA_PMREG_SSTS, datap); 1846 if (error == 0) 1847 error = sili_pmp_write(sp, target, SATA_PMREG_SERR, -1); 1848 if (error) 1849 *datap = 0; 1850 1851 return (error); 1852 } 1853 1854 int 1855 sili_pmp_identify(struct sili_port *sp, int *ret_nports) 1856 { 1857 u_int32_t chipid; 1858 u_int32_t rev; 1859 u_int32_t nports; 1860 u_int32_t features; 1861 u_int32_t enabled; 1862 1863 if (sili_pmp_read(sp, 15, 0, &chipid) || 1864 sili_pmp_read(sp, 15, 1, &rev) || 1865 sili_pmp_read(sp, 15, 2, &nports) || 1866 sili_pmp_read(sp, 15, SATA_PMREG_FEA, &features) || 1867 sili_pmp_read(sp, 15, SATA_PMREG_FEAEN, &enabled)) { 1868 printf("%s: port multiplier identification failed\n", 1869 PORTNAME(sp)); 1870 return (1); 1871 } 1872 1873 nports &= 0x0F; 1874 1875 /* ignore SEMB port on SiI3726 port multiplier chips */ 1876 if (chipid == 0x37261095) { 1877 nports--; 1878 } 1879 1880 printf("%s: port multiplier found: chip=%08x rev=0x%b nports=%d, " 1881 "features: 0x%b, enabled: 0x%b\n", PORTNAME(sp), chipid, rev, 1882 SATA_PFMT_PM_REV, nports, features, SATA_PFMT_PM_FEA, enabled, 1883 SATA_PFMT_PM_FEA); 1884 1885 *ret_nports = nports; 1886 return (0); 1887 } 1888