1 /* $OpenBSD: rtwn.c,v 1.57 2023/04/28 01:24:14 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek 802.11b/g/n chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/task.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_radiotap.h> 54 55 #include <dev/ic/r92creg.h> 56 #include <dev/ic/rtwnvar.h> 57 58 #define RTWN_RIDX_CCK1 0 59 #define RTWN_RIDX_CCK2 1 60 #define RTWN_RIDX_CCK11 3 61 #define RTWN_RIDX_OFDM6 4 62 #define RTWN_RIDX_OFDM54 11 63 #define RTWN_RIDX_MCS0 12 64 #define RTWN_RIDX_MCS8 (RTWN_RIDX_MCS0 + 8) 65 #define RTWN_RIDX_MCS15 27 66 #define RTWN_RIDX_MAX 27 67 68 #define RTWN_POWER_CCK1 0 69 #define RTWN_POWER_CCK2 1 70 #define RTWN_POWER_CCK55 2 71 #define RTWN_POWER_CCK11 3 72 #define RTWN_POWER_OFDM6 4 73 #define RTWN_POWER_OFDM9 5 74 #define RTWN_POWER_OFDM12 6 75 #define RTWN_POWER_OFDM18 7 76 #define RTWN_POWER_OFDM24 8 77 #define RTWN_POWER_OFDM36 9 78 #define RTWN_POWER_OFDM48 10 79 #define RTWN_POWER_OFDM54 11 80 #define RTWN_POWER_MCS(mcs) (12 + (mcs)) 81 #define RTWN_POWER_COUNT 28 82 83 84 #ifdef RTWN_DEBUG 85 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 86 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 87 int rtwn_debug = 0; 88 #else 89 #define DPRINTF(x) 90 #define DPRINTFN(n, x) 91 #endif 92 93 /* Registers to save and restore during IQ calibration. */ 94 struct rtwn_iq_cal_regs { 95 uint32_t adda[16]; 96 uint8_t txpause; 97 uint8_t bcn_ctrl; 98 uint8_t bcn_ctrl1; 99 uint32_t gpio_muxcfg; 100 uint32_t ofdm0_trxpathena; 101 uint32_t ofdm0_trmuxpar; 102 uint32_t fpga0_rfifacesw0; 103 uint32_t fpga0_rfifacesw1; 104 uint32_t fpga0_rfifaceoe0; 105 uint32_t fpga0_rfifaceoe1; 106 uint32_t config_ant_a; 107 uint32_t config_ant_b; 108 uint32_t cck0_afesetting; 109 }; 110 111 void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 void rtwn_rf_write(struct rtwn_softc *, int, uint16_t, uint32_t); 119 uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 void rtwn_cam_write(struct rtwn_softc *, uint32_t, uint32_t); 121 uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 void rtwn_efuse_read(struct rtwn_softc *, uint8_t *, size_t); 123 void rtwn_efuse_switch_power(struct rtwn_softc *); 124 int rtwn_read_chipid(struct rtwn_softc *); 125 void rtwn_read_rom(struct rtwn_softc *); 126 void rtwn_r92c_read_rom(struct rtwn_softc *); 127 void rtwn_r92e_read_rom(struct rtwn_softc *); 128 void rtwn_r88e_read_rom(struct rtwn_softc *); 129 void rtwn_r88f_read_rom(struct rtwn_softc *); 130 void rtwn_r23a_read_rom(struct rtwn_softc *); 131 int rtwn_media_change(struct ifnet *); 132 int rtwn_ra_init(struct rtwn_softc *); 133 int rtwn_r92c_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 134 int, uint32_t, int); 135 int rtwn_r88e_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 136 int, uint32_t, int); 137 void rtwn_tsf_sync_enable(struct rtwn_softc *); 138 void rtwn_set_led(struct rtwn_softc *, int, int); 139 void rtwn_set_nettype(struct rtwn_softc *, enum ieee80211_opmode); 140 void rtwn_update_short_preamble(struct ieee80211com *); 141 void rtwn_r92c_update_short_preamble(struct rtwn_softc *); 142 void rtwn_r88e_update_short_preamble(struct rtwn_softc *); 143 int8_t rtwn_r88e_get_rssi(struct rtwn_softc *, int, void *); 144 int8_t rtwn_r88f_get_rssi(struct rtwn_softc *, int, void *); 145 void rtwn_watchdog(struct ifnet *); 146 void rtwn_fw_reset(struct rtwn_softc *); 147 void rtwn_r92c_fw_reset(struct rtwn_softc *); 148 void rtwn_r88e_fw_reset(struct rtwn_softc *); 149 int rtwn_load_firmware(struct rtwn_softc *); 150 void rtwn_rf_init(struct rtwn_softc *); 151 void rtwn_cam_init(struct rtwn_softc *); 152 void rtwn_pa_bias_init(struct rtwn_softc *); 153 void rtwn_rxfilter_init(struct rtwn_softc *); 154 void rtwn_edca_init(struct rtwn_softc *); 155 void rtwn_rate_fallback_init(struct rtwn_softc *); 156 void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t *); 157 void rtwn_get_txpower(struct rtwn_softc *sc, int, 158 struct ieee80211_channel *, struct ieee80211_channel *, 159 uint16_t *); 160 void rtwn_r92c_get_txpower(struct rtwn_softc *, int, 161 struct ieee80211_channel *, struct ieee80211_channel *, 162 uint16_t *); 163 void rtwn_r92e_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, 165 struct ieee80211_channel *, uint16_t *); 166 void rtwn_r88e_get_txpower(struct rtwn_softc *, int, 167 struct ieee80211_channel *, 168 struct ieee80211_channel *, uint16_t *); 169 void rtwn_set_txpower(struct rtwn_softc *, 170 struct ieee80211_channel *, struct ieee80211_channel *); 171 void rtwn_set_chan(struct rtwn_softc *, 172 struct ieee80211_channel *, struct ieee80211_channel *); 173 int rtwn_chan2group(int); 174 int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 175 uint16_t[2]); 176 void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 177 uint16_t rx[2][2], struct rtwn_iq_cal_regs *); 178 int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 179 uint16_t[2][2], uint16_t[2][2], int); 180 void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 181 uint16_t[2], int); 182 void rtwn_iq_calib(struct rtwn_softc *); 183 void rtwn_lc_calib(struct rtwn_softc *); 184 void rtwn_temp_calib(struct rtwn_softc *); 185 void rtwn_enable_intr(struct rtwn_softc *); 186 void rtwn_disable_intr(struct rtwn_softc *); 187 int rtwn_init(struct ifnet *); 188 void rtwn_init_task(void *); 189 void rtwn_stop(struct ifnet *); 190 191 /* Aliases. */ 192 #define rtwn_bb_write rtwn_write_4 193 #define rtwn_bb_read rtwn_read_4 194 195 /* 196 * Macro to convert 4-bit signed integer to 8-bit signed integer. 197 */ 198 #define RTWN_SIGN4TO8(val) (((val) & 0x08) ? (val) | 0xf0 : (val)) 199 200 int 201 rtwn_attach(struct device *pdev, struct rtwn_softc *sc) 202 { 203 struct ieee80211com *ic = &sc->sc_ic; 204 struct ifnet *ifp = &ic->ic_if; 205 int i, error; 206 207 sc->sc_pdev = pdev; 208 209 task_set(&sc->init_task, rtwn_init_task, sc); 210 211 error = rtwn_read_chipid(sc); 212 if (error != 0) { 213 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 214 return (ENXIO); 215 } 216 217 /* Determine number of Tx/Rx chains. */ 218 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_92E)) { 219 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 220 sc->nrxchains = 2; 221 } else { 222 sc->ntxchains = 1; 223 sc->nrxchains = 1; 224 } 225 226 rtwn_read_rom(sc); 227 228 if (sc->chip & RTWN_CHIP_PCI) { 229 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 230 sc->sc_pdev->dv_xname, 231 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : 232 (sc->chip & RTWN_CHIP_88E) ? "8188EE" : 233 (sc->chip & RTWN_CHIP_92E) ? "8192EE" : 234 (sc->chip & RTWN_CHIP_23A) ? "8723AE" : 235 (sc->chip & RTWN_CHIP_23B) ? "8723BE" : "8188CE", 236 sc->ntxchains, sc->nrxchains, 237 ether_sprintf(ic->ic_myaddr)); 238 } else if (sc->chip & RTWN_CHIP_USB) { 239 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 240 sc->sc_pdev->dv_xname, 241 (sc->chip & RTWN_CHIP_92C) ? "8192CU" : 242 (sc->chip & RTWN_CHIP_92E) ? "8192EU" : 243 (sc->chip & RTWN_CHIP_88E) ? "8188EU" : 244 (sc->chip & RTWN_CHIP_88F) ? "8188FTV" : 245 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 246 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? 247 "8188CE-VAU" : "8188CUS", 248 sc->ntxchains, sc->nrxchains, 249 ether_sprintf(ic->ic_myaddr)); 250 } else { 251 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 252 return (ENXIO); 253 } 254 255 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 256 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* Set device capabilities. */ 260 ic->ic_caps = 261 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 262 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 263 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 264 IEEE80211_C_WEP | /* WEP. */ 265 IEEE80211_C_RSN; /* WPA/RSN. */ 266 267 /* Set HT capabilities. */ 268 ic->ic_htcaps = 269 IEEE80211_HTCAP_CBW20_40 | 270 IEEE80211_HTCAP_DSSSCCK40; 271 /* Set supported HT rates. */ 272 for (i = 0; i < sc->nrxchains; i++) 273 ic->ic_sup_mcs[i] = 0xff; 274 275 /* Set supported .11b and .11g rates. */ 276 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 277 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 278 279 /* Set supported .11b and .11g channels (1 through 14). */ 280 for (i = 1; i <= 14; i++) { 281 ic->ic_channels[i].ic_freq = 282 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 283 ic->ic_channels[i].ic_flags = 284 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 285 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 286 } 287 288 #ifdef notyet 289 /* 290 * The number of STAs that we can support is limited by the number 291 * of CAM entries used for hardware crypto. 292 */ 293 ic->ic_max_nnodes = R92C_CAM_ENTRY_COUNT - 4; 294 if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE) 295 ic->ic_max_nnodes = IEEE80211_CACHE_SIZE; 296 #endif 297 298 ifp->if_softc = sc; 299 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 300 ifp->if_ioctl = rtwn_ioctl; 301 ifp->if_start = rtwn_start; 302 ifp->if_watchdog = rtwn_watchdog; 303 memcpy(ifp->if_xname, sc->sc_pdev->dv_xname, IFNAMSIZ); 304 305 if_attach(ifp); 306 ieee80211_ifattach(ifp); 307 ic->ic_updateslot = rtwn_updateslot; 308 ic->ic_updateedca = rtwn_updateedca; 309 #ifdef notyet 310 ic->ic_set_key = rtwn_set_key; 311 ic->ic_delete_key = rtwn_delete_key; 312 #endif 313 /* Override state transition machine. */ 314 sc->sc_newstate = ic->ic_newstate; 315 ic->ic_newstate = rtwn_newstate; 316 ieee80211_media_init(ifp, rtwn_media_change, ieee80211_media_status); 317 318 return (0); 319 } 320 321 int 322 rtwn_detach(struct rtwn_softc *sc, int flags) 323 { 324 struct ifnet *ifp = &sc->sc_ic.ic_if; 325 int s; 326 327 s = splnet(); 328 329 task_del(systq, &sc->init_task); 330 331 if (ifp->if_softc != NULL) { 332 ieee80211_ifdetach(ifp); 333 if_detach(ifp); 334 } 335 336 splx(s); 337 338 return (0); 339 } 340 341 int 342 rtwn_activate(struct rtwn_softc *sc, int act) 343 { 344 struct ifnet *ifp = &sc->sc_ic.ic_if; 345 346 switch (act) { 347 case DVACT_QUIESCE: /* rtwn_stop() may sleep */ 348 if (ifp->if_flags & IFF_RUNNING) 349 rtwn_stop(ifp); 350 break; 351 case DVACT_WAKEUP: 352 rtwn_init_task(sc); 353 break; 354 } 355 return (0); 356 } 357 358 void 359 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 360 { 361 sc->sc_ops.write_1(sc->sc_ops.cookie, addr, val); 362 } 363 364 void 365 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 366 { 367 sc->sc_ops.write_2(sc->sc_ops.cookie, addr, val); 368 } 369 370 void 371 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 372 { 373 sc->sc_ops.write_4(sc->sc_ops.cookie, addr, val); 374 } 375 376 uint8_t 377 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 378 { 379 return sc->sc_ops.read_1(sc->sc_ops.cookie, addr); 380 } 381 382 uint16_t 383 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 384 { 385 return sc->sc_ops.read_2(sc->sc_ops.cookie, addr); 386 } 387 388 uint32_t 389 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 390 { 391 return sc->sc_ops.read_4(sc->sc_ops.cookie, addr); 392 } 393 394 int 395 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 396 { 397 struct r92c_fw_cmd cmd; 398 int ntries; 399 400 /* Wait for current FW box to be empty. */ 401 for (ntries = 0; ntries < 100; ntries++) { 402 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 403 break; 404 DELAY(10); 405 } 406 if (ntries == 100) { 407 printf("%s: could not send firmware command %d\n", 408 sc->sc_pdev->dv_xname, id); 409 return (ETIMEDOUT); 410 } 411 memset(&cmd, 0, sizeof(cmd)); 412 cmd.id = id; 413 if (len > 3) 414 cmd.id |= R92C_CMD_FLAG_EXT; 415 KASSERT(len <= sizeof(cmd.msg)); 416 memcpy(cmd.msg, buf, len); 417 418 /* Write the first word last since that will trigger the FW. */ 419 if (sc->chip & RTWN_CHIP_92E) 420 rtwn_write_2(sc, R88E_HMEBOX_EXT(sc->fwcur), 421 *((uint8_t *)&cmd + 4)); 422 else 423 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), 424 *((uint8_t *)&cmd + 4)); 425 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 426 427 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 428 429 if (sc->chip & RTWN_CHIP_PCI) { 430 /* Give firmware some time for processing. */ 431 DELAY(2000); 432 } 433 434 return (0); 435 } 436 437 void 438 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint16_t addr, uint32_t val) 439 { 440 uint32_t param_addr; 441 442 if (sc->chip & RTWN_CHIP_92E) { 443 rtwn_write_4(sc, R92C_FPGA0_POWER_SAVE, 444 rtwn_read_4(sc, R92C_FPGA0_POWER_SAVE) & ~0x20000); 445 } 446 447 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) 448 param_addr = SM(R88E_LSSI_PARAM_ADDR, addr); 449 else 450 param_addr = SM(R92C_LSSI_PARAM_ADDR, addr); 451 452 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 453 param_addr | SM(R92C_LSSI_PARAM_DATA, val)); 454 455 DELAY(1); 456 457 if (sc->chip & RTWN_CHIP_92E) { 458 rtwn_write_4(sc, R92C_FPGA0_POWER_SAVE, 459 rtwn_read_4(sc, R92C_FPGA0_POWER_SAVE) | 0x20000); 460 } 461 } 462 463 uint32_t 464 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 465 { 466 uint32_t reg[R92C_MAX_CHAINS], val; 467 468 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 469 if (chain != 0) 470 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 471 472 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 473 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 474 DELAY(1000); 475 476 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 477 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 478 R92C_HSSI_PARAM2_READ_EDGE); 479 DELAY(1000); 480 481 if (!(sc->chip & RTWN_CHIP_88E)) { 482 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 483 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 484 DELAY(1000); 485 } 486 487 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 488 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 489 else 490 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 491 return (MS(val, R92C_LSSI_READBACK_DATA)); 492 } 493 494 void 495 rtwn_cam_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 496 { 497 rtwn_write_4(sc, R92C_CAMWRITE, data); 498 rtwn_write_4(sc, R92C_CAMCMD, 499 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 500 SM(R92C_CAMCMD_ADDR, addr)); 501 } 502 503 uint8_t 504 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 505 { 506 uint32_t reg; 507 int ntries; 508 509 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 510 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 511 reg &= ~R92C_EFUSE_CTRL_VALID; 512 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 513 /* Wait for read operation to complete. */ 514 for (ntries = 0; ntries < 100; ntries++) { 515 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 516 if (reg & R92C_EFUSE_CTRL_VALID) 517 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 518 DELAY(5); 519 } 520 printf("%s: could not read efuse byte at address 0x%x\n", 521 sc->sc_pdev->dv_xname, addr); 522 return (0xff); 523 } 524 525 void 526 rtwn_efuse_read(struct rtwn_softc *sc, uint8_t *rom, size_t size) 527 { 528 uint8_t off, msk, tmp; 529 uint16_t addr = 0; 530 uint32_t reg; 531 int i, len; 532 533 if (!(sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))) 534 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 535 536 rtwn_efuse_switch_power(sc); 537 538 /* Switch bank to 0 for wifi/bt later use. */ 539 if (sc->chip & RTWN_CHIP_88F) { 540 reg = rtwn_read_4(sc, R92C_EFUSE_TEST); 541 reg = RW(reg, R92C_EFUSE_TEST_SEL, 0); 542 rtwn_write_4(sc, R92C_EFUSE_TEST, reg); 543 } 544 545 memset(rom, 0xff, size); 546 len = (sc->chip & RTWN_CHIP_88E) ? 256 : 512; 547 while (addr < len) { 548 reg = rtwn_efuse_read_1(sc, addr); 549 if (reg == 0xff) 550 break; 551 addr++; 552 553 /* Check for extended header. */ 554 if ((sc->sc_flags & RTWN_FLAG_EXT_HDR) && 555 (reg & 0x1f) == 0x0f) { 556 tmp = (reg & 0xe0) >> 5; 557 reg = rtwn_efuse_read_1(sc, addr); 558 addr++; 559 if ((reg & 0x0f) != 0x0f) 560 off = ((reg & 0xf0) >> 1) | tmp; 561 else 562 continue; 563 } else 564 off = reg >> 4; 565 msk = reg & 0xf; 566 for (i = 0; i < 4; i++) { 567 if (msk & (1 << i)) 568 continue; 569 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 570 addr++; 571 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 572 addr++; 573 } 574 } 575 #ifdef RTWN_DEBUG 576 if (rtwn_debug >= 2) { 577 /* Dump ROM content. */ 578 printf("\n"); 579 for (i = 0; i < size; i++) 580 printf("%02x:", rom[i]); 581 printf("\n"); 582 } 583 #endif 584 if (!(sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))) 585 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 586 } 587 588 void 589 rtwn_efuse_switch_power(struct rtwn_softc *sc) 590 { 591 uint16_t reg; 592 593 if (!(sc->chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))) { 594 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 595 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 596 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 597 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 598 } 599 } 600 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 601 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 602 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 603 reg | R92C_SYS_FUNC_EN_ELDR); 604 } 605 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 606 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 607 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 608 rtwn_write_2(sc, R92C_SYS_CLKR, 609 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 610 } 611 } 612 613 int 614 rtwn_read_chipid(struct rtwn_softc *sc) 615 { 616 uint32_t reg; 617 618 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) { 619 sc->sc_flags |= RTWN_FLAG_EXT_HDR; 620 return (0); 621 } 622 623 reg = rtwn_read_4(sc, R92C_SYS_CFG); 624 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 625 /* Unsupported test chip. */ 626 return (EIO); 627 628 if ((sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) != 0) { 629 if (reg & R92C_SYS_CFG_TYPE_92C) { 630 sc->chip &= ~RTWN_CHIP_88C; 631 /* Check if it is a castrated 8192C. */ 632 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 633 R92C_HPON_FSM_CHIP_BONDING_ID) == 634 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 635 sc->chip |= RTWN_CHIP_92C_1T2R; 636 } else 637 sc->chip &= ~RTWN_CHIP_92C; 638 639 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 640 sc->chip |= RTWN_CHIP_UMC; 641 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 642 sc->chip |= RTWN_CHIP_UMC_A_CUT; 643 } 644 645 return (0); 646 } else if (sc->chip & RTWN_CHIP_23A) { 647 sc->sc_flags |= RTWN_FLAG_EXT_HDR; 648 649 if ((reg & 0xf000) == 0) 650 sc->chip |= RTWN_CHIP_UMC_A_CUT; 651 return (0); 652 } 653 654 return (ENXIO); /* unsupported chip */ 655 } 656 657 void 658 rtwn_read_rom(struct rtwn_softc *sc) 659 { 660 if (sc->chip & RTWN_CHIP_88E) 661 rtwn_r88e_read_rom(sc); 662 else if (sc->chip & RTWN_CHIP_88F) 663 rtwn_r88f_read_rom(sc); 664 else if (sc->chip & RTWN_CHIP_92E) 665 rtwn_r92e_read_rom(sc); 666 else if (sc->chip & RTWN_CHIP_23A) 667 rtwn_r23a_read_rom(sc); 668 else 669 rtwn_r92c_read_rom(sc); 670 } 671 672 void 673 rtwn_r92c_read_rom(struct rtwn_softc *sc) 674 { 675 struct ieee80211com *ic = &sc->sc_ic; 676 struct r92c_rom *rom = &sc->sc_r92c_rom; 677 678 /* Read full ROM image. */ 679 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r92c_rom, 680 sizeof(sc->sc_r92c_rom)); 681 682 /* XXX Weird but this is what the vendor driver does. */ 683 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 684 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 685 686 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 687 DPRINTF(("board type=%d\n", sc->board_type)); 688 689 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 690 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 691 692 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 693 } 694 695 void 696 rtwn_r92e_read_rom(struct rtwn_softc *sc) 697 { 698 struct ieee80211com *ic = &sc->sc_ic; 699 struct r92e_rom *rom = &sc->sc_r92e_rom; 700 701 /* Read full ROM image. */ 702 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r92e_rom, 703 sizeof(sc->sc_r92e_rom)); 704 705 sc->crystal_cap = rom->xtal_k; 706 DPRINTF(("crystal cap=0x%x\n", sc->crystal_cap)); 707 708 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 709 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 710 711 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 712 } 713 714 void 715 rtwn_r88e_read_rom(struct rtwn_softc *sc) 716 { 717 struct ieee80211com *ic = &sc->sc_ic; 718 struct r88e_rom *rom = &sc->sc_r88e_rom; 719 720 /* Read full ROM image. */ 721 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r88e_rom, 722 sizeof(sc->sc_r88e_rom)); 723 724 sc->crystal_cap = (sc->chip & RTWN_CHIP_PCI) ? 0x20 : rom->xtal; 725 DPRINTF(("Crystal cap=0x%x\n", sc->crystal_cap)); 726 727 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 728 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 729 730 if (sc->chip & RTWN_CHIP_PCI) 731 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88ee_rom.macaddr); 732 else 733 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88eu_rom.macaddr); 734 } 735 736 void 737 rtwn_r88f_read_rom(struct rtwn_softc *sc) 738 { 739 struct ieee80211com *ic = &sc->sc_ic; 740 struct r88f_rom *rom = &sc->sc_r88f_rom; 741 742 /* Read full ROM image. */ 743 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r88f_rom, 744 sizeof(sc->sc_r88f_rom)); 745 746 sc->crystal_cap = rom->xtal; 747 748 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 749 } 750 751 void 752 rtwn_r23a_read_rom(struct rtwn_softc *sc) 753 { 754 struct ieee80211com *ic = &sc->sc_ic; 755 struct r23a_rom *rom = &sc->sc_r23a_rom; 756 757 /* Read full ROM image. */ 758 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r23a_rom, 759 sizeof(sc->sc_r23a_rom)); 760 761 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 762 } 763 764 int 765 rtwn_media_change(struct ifnet *ifp) 766 { 767 int error; 768 769 error = ieee80211_media_change(ifp); 770 if (error != ENETRESET) 771 return (error); 772 773 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 774 (IFF_UP | IFF_RUNNING)) { 775 rtwn_stop(ifp); 776 error = rtwn_init(ifp); 777 } 778 return (error); 779 } 780 781 /* 782 * Initialize rate adaptation. 783 */ 784 int 785 rtwn_ra_init(struct rtwn_softc *sc) 786 { 787 static const uint8_t map[] = 788 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 789 struct ieee80211com *ic = &sc->sc_ic; 790 struct ieee80211_node *ni = ic->ic_bss; 791 struct ieee80211_rateset *rs = &ni->ni_rates; 792 uint32_t rates, basicrates; 793 uint8_t mode; 794 int maxrate, maxbasicrate, i, j; 795 int error = 0; 796 797 /* Get normal and basic rates mask. */ 798 rates = basicrates = 0; 799 maxrate = maxbasicrate = 0; 800 for (i = 0; i < rs->rs_nrates; i++) { 801 /* Convert 802.11 rate to HW rate index. */ 802 for (j = 0; j < nitems(map); j++) 803 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 804 break; 805 if (j == nitems(map)) /* Unknown rate, skip. */ 806 continue; 807 rates |= 1 << j; 808 if (j > maxrate) 809 maxrate = j; 810 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 811 basicrates |= 1 << j; 812 if (j > maxbasicrate) 813 maxbasicrate = j; 814 } 815 } 816 if (ic->ic_curmode == IEEE80211_MODE_11B) 817 mode = R92C_RAID_11B; 818 else 819 mode = R92C_RAID_11BG; 820 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 821 mode, rates, basicrates)); 822 823 if (sc->chip & RTWN_CHIP_PCI) { 824 /* Configure Automatic Rate Fallback Register. */ 825 if (ic->ic_curmode == IEEE80211_MODE_11B) { 826 if (rates & 0x0c) 827 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x05); 828 else 829 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x07); 830 } else 831 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x07f5); 832 } 833 834 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) { 835 error = rtwn_r88e_ra_init(sc, mode, rates, maxrate, 836 basicrates, maxbasicrate); 837 /* We use AMRR with this chip. Start with the lowest rate. */ 838 ni->ni_txrate = 0; 839 } else { 840 if (sc->chip & RTWN_CHIP_PCI) { 841 ni->ni_txrate = 0; /* AMRR will raise. */ 842 /* Set initial MRR rates. */ 843 rtwn_write_1(sc, 844 R92C_INIDATA_RATE_SEL(R92C_MACID_BC), maxbasicrate); 845 rtwn_write_1(sc, 846 R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 0); 847 } else { 848 error = rtwn_r92c_ra_init(sc, mode, rates, maxrate, 849 basicrates, maxbasicrate); 850 /* No AMRR support. Indicate highest supported rate. */ 851 ni->ni_txrate = rs->rs_nrates - 1; 852 } 853 } 854 return (error); 855 } 856 857 /* 858 * Initialize rate adaptation in firmware. 859 */ 860 int rtwn_r92c_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 861 int maxrate, uint32_t basicrates, int maxbasicrate) 862 { 863 struct r92c_fw_cmd_macid_cfg cmd; 864 int error; 865 866 /* Set rates mask for group addressed frames. */ 867 cmd.macid = R92C_MACID_BC | R92C_MACID_VALID; 868 cmd.mask = htole32(mode << 28 | basicrates); 869 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 870 if (error != 0) { 871 printf("%s: could not add broadcast station\n", 872 sc->sc_pdev->dv_xname); 873 return (error); 874 } 875 /* Set initial MRR rate. */ 876 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 877 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BC), 878 maxbasicrate); 879 880 /* Set rates mask for unicast frames. */ 881 cmd.macid = R92C_MACID_BSS | R92C_MACID_VALID; 882 cmd.mask = htole32(mode << 28 | rates); 883 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 884 if (error != 0) { 885 printf("%s: could not add BSS station\n", 886 sc->sc_pdev->dv_xname); 887 return (error); 888 } 889 /* Set initial MRR rate. */ 890 DPRINTF(("maxrate=%d\n", maxrate)); 891 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 892 maxrate); 893 894 return (0); 895 } 896 897 int 898 rtwn_r88e_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 899 int maxrate, uint32_t basicrates, int maxbasicrate) 900 { 901 u_int32_t reg; 902 903 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, maxbasicrate); 904 905 reg = rtwn_read_4(sc, R92C_RRSR); 906 reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates); 907 rtwn_write_4(sc, R92C_RRSR, reg); 908 909 /* 910 * Workaround for performance problems with firmware rate adaptation: 911 * If the AP only supports 11b rates, disable mixed B/G mode. 912 */ 913 if (mode != R92C_RAID_11B && maxrate <= 3 /* 11M */) 914 sc->sc_flags |= RTWN_FLAG_FORCE_RAID_11B; 915 916 return (0); 917 } 918 919 void 920 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 921 { 922 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 923 uint64_t tsf; 924 925 /* Enable TSF synchronization. */ 926 rtwn_write_1(sc, R92C_BCN_CTRL, 927 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 928 929 rtwn_write_1(sc, R92C_BCN_CTRL, 930 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 931 932 /* Set initial TSF. */ 933 memcpy(&tsf, ni->ni_tstamp, sizeof(tsf)); 934 tsf = letoh64(tsf); 935 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 936 tsf -= IEEE80211_DUR_TU; 937 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 938 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 939 940 rtwn_write_1(sc, R92C_BCN_CTRL, 941 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 942 } 943 944 void 945 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 946 { 947 uint8_t reg; 948 949 if (led != RTWN_LED_LINK) 950 return; /* not supported */ 951 952 if (sc->chip & RTWN_CHIP_PCI) { 953 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 954 if (!on) 955 reg |= R92C_LEDCFG2_DIS; 956 else 957 reg |= R92C_LEDCFG2_EN; 958 rtwn_write_1(sc, R92C_LEDCFG2, reg); 959 } else if (sc->chip & RTWN_CHIP_USB) { 960 if (sc->chip & RTWN_CHIP_92E) { 961 rtwn_write_1(sc, 0x64, rtwn_read_1(sc, 0x64) & 0xfe); 962 reg = rtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 963 rtwn_write_1(sc, R92C_LEDCFG1, reg | 964 (R92C_LEDCFG0_DIS << 1)); 965 if (on) { 966 reg = rtwn_read_1(sc, R92C_LEDCFG1) & 967 R92E_LEDSON; 968 rtwn_write_1(sc, R92C_LEDCFG1, reg); 969 } 970 } else if (sc->chip & RTWN_CHIP_88E) { 971 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 972 rtwn_write_1(sc, R92C_LEDCFG2, reg | R92C_LEDCFG2_EN); 973 if (!on) { 974 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 975 rtwn_write_1(sc, R92C_LEDCFG2, 976 reg | R92C_LEDCFG0_DIS); 977 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 978 rtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 979 0xfe); 980 } 981 } else { 982 reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 983 if (!on) 984 reg |= R92C_LEDCFG0_DIS; 985 rtwn_write_1(sc, R92C_LEDCFG0, reg); 986 } 987 } 988 sc->ledlink = on; /* Save LED state. */ 989 } 990 991 void 992 rtwn_set_nettype(struct rtwn_softc *sc, enum ieee80211_opmode opmode) 993 { 994 uint8_t msr; 995 996 msr = rtwn_read_1(sc, R92C_MSR) & ~R92C_MSR_NETTYPE_MASK; 997 998 switch (opmode) { 999 case IEEE80211_M_MONITOR: 1000 msr |= R92C_MSR_NETTYPE_NOLINK; 1001 break; 1002 case IEEE80211_M_STA: 1003 msr |= R92C_MSR_NETTYPE_INFRA; 1004 break; 1005 default: 1006 break; 1007 } 1008 1009 rtwn_write_1(sc, R92C_MSR, msr); 1010 } 1011 1012 void 1013 rtwn_calib(struct rtwn_softc *sc) 1014 { 1015 1016 if (sc->avg_pwdb != -1) { 1017 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1018 1019 /* Indicate Rx signal strength to FW for rate adaptation. */ 1020 if (sc->chip & RTWN_CHIP_92E) { 1021 struct r92e_fw_cmd_rssi cmd; 1022 1023 memset(&cmd, 0, sizeof(cmd)); 1024 cmd.macid = 0; /* BSS. */ 1025 cmd.pwdb = sc->avg_pwdb; 1026 rtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmd, 1027 sizeof(cmd)); 1028 } else { 1029 struct r92c_fw_cmd_rssi cmd; 1030 1031 memset(&cmd, 0, sizeof(cmd)); 1032 cmd.macid = 0; /* BSS. */ 1033 cmd.pwdb = sc->avg_pwdb; 1034 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1035 sizeof(cmd)); 1036 } 1037 } 1038 1039 /* Do temperature compensation. */ 1040 rtwn_temp_calib(sc); 1041 1042 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1043 } 1044 1045 void 1046 rtwn_next_scan(struct rtwn_softc *sc) 1047 { 1048 struct ieee80211com *ic = &sc->sc_ic; 1049 int s; 1050 1051 s = splnet(); 1052 if (ic->ic_state == IEEE80211_S_SCAN) 1053 ieee80211_next_scan(&ic->ic_if); 1054 splx(s); 1055 } 1056 1057 int 1058 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1059 { 1060 struct rtwn_softc *sc = ic->ic_softc; 1061 struct ieee80211_node *ni; 1062 enum ieee80211_state ostate; 1063 uint32_t reg; 1064 int s, error; 1065 1066 s = splnet(); 1067 ostate = ic->ic_state; 1068 1069 if (nstate != ostate) 1070 DPRINTF(("newstate %s -> %s\n", 1071 ieee80211_state_name[ostate], 1072 ieee80211_state_name[nstate])); 1073 1074 if (ostate == IEEE80211_S_RUN) { 1075 /* Stop calibration. */ 1076 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 1077 1078 /* Turn link LED off. */ 1079 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1080 1081 /* Set media status to 'No Link'. */ 1082 rtwn_set_nettype(sc, IEEE80211_M_MONITOR); 1083 1084 /* Stop Rx of data frames. */ 1085 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1086 1087 /* Rest TSF. */ 1088 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1089 1090 /* Disable TSF synchronization. */ 1091 rtwn_write_1(sc, R92C_BCN_CTRL, 1092 rtwn_read_1(sc, R92C_BCN_CTRL) | 1093 R92C_BCN_CTRL_DIS_TSF_UDT0); 1094 1095 /* Reset EDCA parameters. */ 1096 rtwn_edca_init(sc); 1097 1098 rtwn_updateslot(ic); 1099 rtwn_update_short_preamble(ic); 1100 1101 /* Disable 11b-only AP workaround (see rtwn_r88e_ra_init). */ 1102 sc->sc_flags &= ~RTWN_FLAG_FORCE_RAID_11B; 1103 } 1104 switch (nstate) { 1105 case IEEE80211_S_INIT: 1106 /* Turn link LED off. */ 1107 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1108 break; 1109 case IEEE80211_S_SCAN: 1110 if (ostate != IEEE80211_S_SCAN) { 1111 /* Allow Rx from any BSSID. */ 1112 rtwn_write_4(sc, R92C_RCR, 1113 rtwn_read_4(sc, R92C_RCR) & 1114 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1115 1116 /* Set gain for scanning. */ 1117 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1118 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1119 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1120 1121 if (!(sc->chip & RTWN_CHIP_88E)) { 1122 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1123 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1124 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1125 } 1126 } 1127 1128 /* Make link LED blink during scan. */ 1129 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1130 1131 /* Pause AC Tx queues. */ 1132 rtwn_write_1(sc, R92C_TXPAUSE, 1133 rtwn_read_1(sc, R92C_TXPAUSE) | R92C_TXPAUSE_AC_VO | 1134 R92C_TXPAUSE_AC_VI | R92C_TXPAUSE_AC_BE | 1135 R92C_TXPAUSE_AC_BK); 1136 1137 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 1138 sc->sc_ops.next_scan(sc->sc_ops.cookie); 1139 break; 1140 1141 case IEEE80211_S_AUTH: 1142 /* Set initial gain under link. */ 1143 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1144 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1145 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1146 1147 if (!(sc->chip & RTWN_CHIP_88E)) { 1148 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1149 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1150 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1151 } 1152 1153 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 1154 break; 1155 case IEEE80211_S_ASSOC: 1156 break; 1157 case IEEE80211_S_RUN: 1158 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1159 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1160 1161 /* Enable Rx of data frames. */ 1162 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1163 1164 /* Enable Rx of control frames. */ 1165 rtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1166 1167 rtwn_write_4(sc, R92C_RCR, 1168 rtwn_read_4(sc, R92C_RCR) | 1169 R92C_RCR_AAP | R92C_RCR_ADF | R92C_RCR_ACF | 1170 R92C_RCR_AMF); 1171 1172 /* Turn link LED on. */ 1173 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1174 break; 1175 } 1176 ni = ic->ic_bss; 1177 1178 /* Set media status to 'Associated'. */ 1179 rtwn_set_nettype(sc, IEEE80211_M_STA); 1180 1181 /* Set BSSID. */ 1182 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1183 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1184 1185 if (ic->ic_curmode == IEEE80211_MODE_11B) 1186 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1187 else /* 802.11b/g */ 1188 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1189 1190 rtwn_updateslot(ic); 1191 rtwn_update_short_preamble(ic); 1192 1193 /* Enable Rx of data frames. */ 1194 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1195 1196 /* Flush all AC queues. */ 1197 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 1198 1199 /* Set beacon interval. */ 1200 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1201 1202 /* Allow Rx from our BSSID only. */ 1203 rtwn_write_4(sc, R92C_RCR, 1204 rtwn_read_4(sc, R92C_RCR) | 1205 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1206 1207 /* Enable TSF synchronization. */ 1208 rtwn_tsf_sync_enable(sc); 1209 1210 /* Initialize rate adaptation. */ 1211 rtwn_ra_init(sc); 1212 1213 /* Turn link LED on. */ 1214 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1215 1216 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1217 /* Reset temperature calibration state machine. */ 1218 sc->thcal_state = 0; 1219 sc->thcal_lctemp = 0; 1220 /* Start periodic calibration. */ 1221 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1222 break; 1223 } 1224 1225 error = sc->sc_newstate(ic, nstate, arg); 1226 splx(s); 1227 1228 return (error); 1229 } 1230 1231 void 1232 rtwn_update_short_preamble(struct ieee80211com *ic) 1233 { 1234 struct rtwn_softc *sc = ic->ic_softc; 1235 1236 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1237 rtwn_r88e_update_short_preamble(sc); 1238 else 1239 rtwn_r92c_update_short_preamble(sc); 1240 } 1241 1242 void 1243 rtwn_r92c_update_short_preamble(struct rtwn_softc *sc) 1244 { 1245 uint32_t reg; 1246 1247 reg = rtwn_read_4(sc, R92C_RRSR); 1248 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1249 reg |= R92C_RRSR_SHORT; 1250 else 1251 reg &= ~R92C_RRSR_SHORT; 1252 rtwn_write_4(sc, R92C_RRSR, reg); 1253 } 1254 1255 void 1256 rtwn_r88e_update_short_preamble(struct rtwn_softc *sc) 1257 { 1258 uint32_t reg; 1259 1260 reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL); 1261 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1262 reg |= R92C_WMAC_TRXPTCL_CTL_SHORT; 1263 else 1264 reg &= ~R92C_WMAC_TRXPTCL_CTL_SHORT; 1265 rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg); 1266 } 1267 1268 void 1269 rtwn_updateslot(struct ieee80211com *ic) 1270 { 1271 struct rtwn_softc *sc = ic->ic_softc; 1272 int s; 1273 1274 s = splnet(); 1275 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1276 rtwn_write_1(sc, R92C_SLOT, IEEE80211_DUR_DS_SHSLOT); 1277 else 1278 rtwn_write_1(sc, R92C_SLOT, IEEE80211_DUR_DS_SLOT); 1279 splx(s); 1280 } 1281 1282 void 1283 rtwn_updateedca(struct ieee80211com *ic) 1284 { 1285 struct rtwn_softc *sc = ic->ic_softc; 1286 const uint16_t aci2reg[EDCA_NUM_AC] = { 1287 R92C_EDCA_BE_PARAM, 1288 R92C_EDCA_BK_PARAM, 1289 R92C_EDCA_VI_PARAM, 1290 R92C_EDCA_VO_PARAM 1291 }; 1292 struct ieee80211_edca_ac_params *ac; 1293 int s, aci, aifs, slottime; 1294 uint8_t acm = 0; 1295 1296 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1297 slottime = IEEE80211_DUR_DS_SHSLOT; 1298 else 1299 slottime = IEEE80211_DUR_DS_SLOT; 1300 s = splnet(); 1301 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1302 ac = &ic->ic_edca_ac[aci]; 1303 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1304 aifs = ac->ac_aifsn * slottime + IEEE80211_DUR_DS_SIFS; 1305 rtwn_write_4(sc, aci2reg[aci], 1306 SM(R92C_EDCA_PARAM_TXOP, ac->ac_txoplimit) | 1307 SM(R92C_EDCA_PARAM_ECWMIN, ac->ac_ecwmin) | 1308 SM(R92C_EDCA_PARAM_ECWMAX, ac->ac_ecwmax) | 1309 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1310 1311 /* Is admission control mandatory for this queue? */ 1312 if (ac->ac_acm) { 1313 switch (aci) { 1314 case EDCA_AC_BE: 1315 acm |= R92C_ACMHW_BEQEN; 1316 break; 1317 case EDCA_AC_VI: 1318 acm |= R92C_ACMHW_VIQEN; 1319 break; 1320 case EDCA_AC_VO: 1321 acm |= R92C_ACMHW_VOQEN; 1322 break; 1323 default: 1324 break; 1325 } 1326 } 1327 } 1328 splx(s); 1329 1330 /* Enable hardware admission control. */ 1331 rtwn_write_1(sc, R92C_ACMHWCTRL, R92C_ACMHW_HWEN | acm); 1332 } 1333 1334 int 1335 rtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1336 struct ieee80211_key *k) 1337 { 1338 struct rtwn_softc *sc = ic->ic_softc; 1339 static const uint8_t etherzeroaddr[6] = { 0 }; 1340 const uint8_t *macaddr; 1341 uint8_t keybuf[16], algo; 1342 int i, entry; 1343 1344 /* Defer setting of WEP keys until interface is brought up. */ 1345 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1346 (IFF_UP | IFF_RUNNING)) 1347 return (0); 1348 1349 /* Map net80211 cipher to HW crypto algorithm. */ 1350 switch (k->k_cipher) { 1351 case IEEE80211_CIPHER_WEP40: 1352 algo = R92C_CAM_ALGO_WEP40; 1353 break; 1354 case IEEE80211_CIPHER_WEP104: 1355 algo = R92C_CAM_ALGO_WEP104; 1356 break; 1357 case IEEE80211_CIPHER_TKIP: 1358 algo = R92C_CAM_ALGO_TKIP; 1359 break; 1360 case IEEE80211_CIPHER_CCMP: 1361 algo = R92C_CAM_ALGO_AES; 1362 break; 1363 default: 1364 /* Fallback to software crypto for other ciphers. */ 1365 return (ieee80211_set_key(ic, ni, k)); 1366 } 1367 if (k->k_flags & IEEE80211_KEY_GROUP) { 1368 macaddr = etherzeroaddr; 1369 entry = k->k_id; 1370 } else { 1371 macaddr = ic->ic_bss->ni_macaddr; 1372 entry = 4; 1373 } 1374 /* Write key. */ 1375 memset(keybuf, 0, sizeof(keybuf)); 1376 memcpy(keybuf, k->k_key, MIN(k->k_len, sizeof(keybuf))); 1377 for (i = 0; i < 4; i++) { 1378 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 1379 LE_READ_4(&keybuf[i * 4])); 1380 } 1381 /* Write CTL0 last since that will validate the CAM entry. */ 1382 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 1383 LE_READ_4(&macaddr[2])); 1384 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 1385 SM(R92C_CAM_ALGO, algo) | 1386 SM(R92C_CAM_KEYID, k->k_id) | 1387 SM(R92C_CAM_MACLO, LE_READ_2(&macaddr[0])) | 1388 R92C_CAM_VALID); 1389 1390 return (0); 1391 } 1392 1393 void 1394 rtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1395 struct ieee80211_key *k) 1396 { 1397 struct rtwn_softc *sc = ic->ic_softc; 1398 int i, entry; 1399 1400 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1401 ic->ic_state != IEEE80211_S_RUN) 1402 return; /* Nothing to do. */ 1403 1404 if (k->k_flags & IEEE80211_KEY_GROUP) 1405 entry = k->k_id; 1406 else 1407 entry = 4; 1408 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 0); 1409 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 0); 1410 /* Clear key. */ 1411 for (i = 0; i < 4; i++) 1412 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 0); 1413 } 1414 1415 void 1416 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1417 { 1418 int pwdb; 1419 1420 /* Convert antenna signal to percentage. */ 1421 if (rssi <= -100 || rssi >= 20) 1422 pwdb = 0; 1423 else if (rssi >= 0) 1424 pwdb = 100; 1425 else 1426 pwdb = 100 + rssi; 1427 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) { 1428 if (rate <= 3) { 1429 /* CCK gain is smaller than OFDM/MCS gain. */ 1430 pwdb += 6; 1431 if (pwdb > 100) 1432 pwdb = 100; 1433 if (pwdb <= 14) 1434 pwdb -= 4; 1435 else if (pwdb <= 26) 1436 pwdb -= 8; 1437 else if (pwdb <= 34) 1438 pwdb -= 6; 1439 else if (pwdb <= 42) 1440 pwdb -= 2; 1441 } 1442 } 1443 if (sc->avg_pwdb == -1) /* Init. */ 1444 sc->avg_pwdb = pwdb; 1445 else if (sc->avg_pwdb < pwdb) 1446 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1447 else 1448 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1449 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1450 } 1451 1452 int8_t 1453 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1454 { 1455 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1456 struct r92c_rx_phystat *phy; 1457 struct r92c_rx_cck *cck; 1458 uint8_t rpt; 1459 int8_t rssi; 1460 1461 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1462 return rtwn_r88e_get_rssi(sc, rate, physt); 1463 else if (sc->chip & RTWN_CHIP_88E) 1464 return rtwn_r88f_get_rssi(sc, rate, physt); 1465 1466 if (rate <= 3) { 1467 cck = (struct r92c_rx_cck *)physt; 1468 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1469 rpt = (cck->agc_rpt >> 5) & 0x3; 1470 rssi = (cck->agc_rpt & 0x1f) << 1; 1471 } else { 1472 rpt = (cck->agc_rpt >> 6) & 0x3; 1473 rssi = cck->agc_rpt & 0x3e; 1474 } 1475 rssi = cckoff[rpt] - rssi; 1476 } else { /* OFDM/HT. */ 1477 phy = (struct r92c_rx_phystat *)physt; 1478 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 110; 1479 } 1480 return (rssi); 1481 } 1482 1483 int8_t 1484 rtwn_r88e_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1485 { 1486 static const int8_t cckoff[] = { 20, 14, 10, -4, -16, -22, -38, -40 }; 1487 struct r88e_rx_phystat *phy; 1488 uint8_t rpt; 1489 int8_t rssi; 1490 1491 phy = (struct r88e_rx_phystat *)physt; 1492 1493 if (rate <= 3) { 1494 rpt = (phy->agc_rpt >> 5) & 0x7; 1495 rssi = (phy->agc_rpt & 0x1f) << 1; 1496 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1497 if (rpt == 2) 1498 rssi -= 6; 1499 } 1500 rssi = (phy->agc_rpt & 0x1f) > 27 ? -94 : cckoff[rpt] - rssi; 1501 } else { /* OFDM/HT. */ 1502 rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110; 1503 } 1504 return (rssi); 1505 } 1506 1507 int8_t 1508 rtwn_r88f_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1509 { 1510 struct r88e_rx_phystat *phy; 1511 uint8_t lna_idx, vga_idx; 1512 int8_t rssi; 1513 1514 phy = (struct r88e_rx_phystat *)physt; 1515 lna_idx = (phy->agc_rpt & 0xe0) >> 5; 1516 vga_idx = (phy->agc_rpt & 0x1f); 1517 rssi = -(2 * vga_idx); 1518 1519 if (rate <= 3) { 1520 switch (lna_idx) { 1521 case 7: 1522 if (vga_idx > 27) 1523 rssi = -100; 1524 else 1525 rssi += -46; 1526 break; 1527 case 5: 1528 rssi += -32; 1529 break; 1530 case 3: 1531 rssi += -20; 1532 break; 1533 case 1: 1534 rssi += -6; 1535 break; 1536 default: 1537 rssi = 0; 1538 break; 1539 } 1540 } else { /* OFDM/HT. */ 1541 rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110; 1542 } 1543 return (rssi); 1544 } 1545 1546 void 1547 rtwn_start(struct ifnet *ifp) 1548 { 1549 struct rtwn_softc *sc = ifp->if_softc; 1550 struct ieee80211com *ic = &sc->sc_ic; 1551 struct ieee80211_node *ni; 1552 struct mbuf *m; 1553 1554 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1555 return; 1556 1557 for (;;) { 1558 if (sc->sc_ops.is_oactive(sc->sc_ops.cookie)) { 1559 ifq_set_oactive(&ifp->if_snd); 1560 break; 1561 } 1562 /* Send pending management frames first. */ 1563 m = mq_dequeue(&ic->ic_mgtq); 1564 if (m != NULL) { 1565 ni = m->m_pkthdr.ph_cookie; 1566 goto sendit; 1567 } 1568 if (ic->ic_state != IEEE80211_S_RUN) 1569 break; 1570 1571 /* Encapsulate and send data frames. */ 1572 m = ifq_dequeue(&ifp->if_snd); 1573 if (m == NULL) 1574 break; 1575 #if NBPFILTER > 0 1576 if (ifp->if_bpf != NULL) 1577 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1578 #endif 1579 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1580 continue; 1581 sendit: 1582 #if NBPFILTER > 0 1583 if (ic->ic_rawbpf != NULL) 1584 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1585 #endif 1586 if (sc->sc_ops.tx(sc->sc_ops.cookie, m, ni) != 0) { 1587 ieee80211_release_node(ic, ni); 1588 ifp->if_oerrors++; 1589 continue; 1590 } 1591 1592 sc->sc_tx_timer = 5; 1593 ifp->if_timer = 1; 1594 } 1595 } 1596 1597 void 1598 rtwn_watchdog(struct ifnet *ifp) 1599 { 1600 struct rtwn_softc *sc = ifp->if_softc; 1601 1602 ifp->if_timer = 0; 1603 1604 if (sc->sc_tx_timer > 0) { 1605 if (--sc->sc_tx_timer == 0) { 1606 printf("%s: device timeout\n", sc->sc_pdev->dv_xname); 1607 task_add(systq, &sc->init_task); 1608 ifp->if_oerrors++; 1609 return; 1610 } 1611 ifp->if_timer = 1; 1612 } 1613 ieee80211_watchdog(ifp); 1614 } 1615 1616 int 1617 rtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1618 { 1619 struct rtwn_softc *sc = ifp->if_softc; 1620 struct ieee80211com *ic = &sc->sc_ic; 1621 int s, error = 0; 1622 1623 s = splnet(); 1624 /* 1625 * Prevent processes from entering this function while another 1626 * process is tsleep'ing in it. 1627 */ 1628 while ((sc->sc_flags & RTWN_FLAG_BUSY) && error == 0) 1629 error = tsleep_nsec(&sc->sc_flags, PCATCH, "rtwnioc", INFSLP); 1630 if (error != 0) { 1631 splx(s); 1632 return error; 1633 } 1634 sc->sc_flags |= RTWN_FLAG_BUSY; 1635 1636 switch (cmd) { 1637 case SIOCSIFADDR: 1638 ifp->if_flags |= IFF_UP; 1639 /* FALLTHROUGH */ 1640 case SIOCSIFFLAGS: 1641 if (ifp->if_flags & IFF_UP) { 1642 if (!(ifp->if_flags & IFF_RUNNING)) 1643 rtwn_init(ifp); 1644 } else { 1645 if (ifp->if_flags & IFF_RUNNING) 1646 rtwn_stop(ifp); 1647 } 1648 break; 1649 case SIOCS80211CHANNEL: 1650 error = ieee80211_ioctl(ifp, cmd, data); 1651 if (error == ENETRESET && 1652 ic->ic_opmode == IEEE80211_M_MONITOR) { 1653 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1654 (IFF_UP | IFF_RUNNING)) 1655 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1656 error = 0; 1657 } 1658 break; 1659 default: 1660 error = ieee80211_ioctl(ifp, cmd, data); 1661 } 1662 1663 if (error == ENETRESET) { 1664 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1665 (IFF_UP | IFF_RUNNING)) { 1666 rtwn_stop(ifp); 1667 rtwn_init(ifp); 1668 } 1669 error = 0; 1670 } 1671 sc->sc_flags &= ~RTWN_FLAG_BUSY; 1672 wakeup(&sc->sc_flags); 1673 splx(s); 1674 1675 return (error); 1676 } 1677 1678 void 1679 rtwn_fw_reset(struct rtwn_softc *sc) 1680 { 1681 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) 1682 rtwn_r88e_fw_reset(sc); 1683 else 1684 rtwn_r92c_fw_reset(sc); 1685 } 1686 1687 void 1688 rtwn_r92c_fw_reset(struct rtwn_softc *sc) 1689 { 1690 uint16_t reg; 1691 int ntries; 1692 1693 /* Tell 8051 to reset itself. */ 1694 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 1695 1696 /* Wait until 8051 resets by itself. */ 1697 for (ntries = 0; ntries < 100; ntries++) { 1698 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1699 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 1700 goto sleep; 1701 DELAY(50); 1702 } 1703 /* Force 8051 reset. */ 1704 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1705 sleep: 1706 if (sc->chip & RTWN_CHIP_PCI) { 1707 /* 1708 * We must sleep for one second to let the firmware settle. 1709 * Accessing registers too early will hang the whole system. 1710 */ 1711 tsleep_nsec(®, 0, "rtwnrst", SEC_TO_NSEC(1)); 1712 } 1713 } 1714 1715 void 1716 rtwn_r88e_fw_reset(struct rtwn_softc *sc) 1717 { 1718 /* Reset MCU IO wrapper. */ 1719 if (!(sc->chip & RTWN_CHIP_88F)) { 1720 rtwn_write_1(sc, R92C_RSV_CTRL, 1721 rtwn_read_1(sc, R92C_RSV_CTRL) & ~R92C_RSV_CTRL_WLOCK_00); 1722 } 1723 if (sc->chip & RTWN_CHIP_88E) { 1724 rtwn_write_2(sc, R92C_RSV_CTRL, 1725 rtwn_read_2(sc, R92C_RSV_CTRL) & ~R88E_RSV_CTRL_MCU_RST); 1726 } else { 1727 rtwn_write_2(sc, R92C_RSV_CTRL, 1728 rtwn_read_2(sc, R92C_RSV_CTRL) & ~R88E_RSV_CTRL_MIO_EN); 1729 } 1730 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1731 rtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 1732 1733 /* Enable MCU IO wrapper. */ 1734 if (!(sc->chip & RTWN_CHIP_88F)) { 1735 rtwn_write_1(sc, R92C_RSV_CTRL, 1736 rtwn_read_1(sc, R92C_RSV_CTRL) & ~R92C_RSV_CTRL_WLOCK_00); 1737 } 1738 if (sc->chip & RTWN_CHIP_88E) { 1739 rtwn_write_2(sc, R92C_RSV_CTRL, 1740 rtwn_read_2(sc, R92C_RSV_CTRL) | R88E_RSV_CTRL_MCU_RST); 1741 } else { 1742 rtwn_write_2(sc, R92C_RSV_CTRL, 1743 rtwn_read_2(sc, R92C_RSV_CTRL) | R88E_RSV_CTRL_MIO_EN); 1744 } 1745 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1746 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | R92C_SYS_FUNC_EN_CPUEN); 1747 } 1748 1749 int 1750 rtwn_load_firmware(struct rtwn_softc *sc) 1751 { 1752 const struct r92c_fw_hdr *hdr; 1753 u_char *fw, *ptr; 1754 size_t len0, len; 1755 uint32_t reg; 1756 int mlen, ntries, page, error; 1757 1758 /* Read firmware image from the filesystem. */ 1759 error = sc->sc_ops.load_firmware(sc->sc_ops.cookie, &fw, &len0); 1760 if (error) 1761 return (error); 1762 len = len0; 1763 if (len < sizeof(*hdr)) { 1764 printf("%s: firmware too short\n", sc->sc_pdev->dv_xname); 1765 error = EINVAL; 1766 goto fail; 1767 } 1768 ptr = fw; 1769 hdr = (const struct r92c_fw_hdr *)ptr; 1770 /* Check if there is a valid FW header and skip it. */ 1771 if ((letoh16(hdr->signature) >> 4) == 0x230 || 1772 (letoh16(hdr->signature) >> 4) == 0x88c || 1773 (letoh16(hdr->signature) >> 4) == 0x88e || 1774 (letoh16(hdr->signature) >> 4) == 0x88f || 1775 (letoh16(hdr->signature) >> 4) == 0x92c || 1776 (letoh16(hdr->signature) >> 4) == 0x92e) { 1777 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 1778 letoh16(hdr->version), letoh16(hdr->subversion), 1779 hdr->month, hdr->date, hdr->hour, hdr->minute)); 1780 ptr += sizeof(*hdr); 1781 len -= sizeof(*hdr); 1782 } 1783 1784 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 1785 rtwn_write_1(sc, R92C_MCUFWDL, 0); 1786 rtwn_fw_reset(sc); 1787 } 1788 1789 if ((sc->chip & RTWN_CHIP_PCI) || (sc->chip & RTWN_CHIP_88F)) { 1790 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1791 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | R92C_SYS_FUNC_EN_CPUEN); 1792 } 1793 1794 /* Enable FW download. */ 1795 rtwn_write_1(sc, R92C_MCUFWDL, 1796 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 1797 rtwn_write_4(sc, R92C_MCUFWDL, 1798 rtwn_read_4(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_ROM_DLEN); 1799 1800 /* Reset the FWDL checksum. */ 1801 rtwn_write_1(sc, R92C_MCUFWDL, 1802 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 1803 1804 DELAY(50); 1805 for (page = 0; len > 0; page++) { 1806 mlen = MIN(len, R92C_FW_PAGE_SIZE); 1807 error = sc->sc_ops.fw_loadpage(sc->sc_ops.cookie, page, ptr, 1808 mlen); 1809 if (error != 0) { 1810 printf("%s: could not load firmware page %d\n", 1811 sc->sc_pdev->dv_xname, page); 1812 goto fail; 1813 } 1814 ptr += mlen; 1815 len -= mlen; 1816 } 1817 1818 /* Wait for checksum report. */ 1819 for (ntries = 0; ntries < 1000; ntries++) { 1820 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 1821 break; 1822 DELAY(5); 1823 } 1824 if (ntries == 1000) { 1825 printf("%s: timeout waiting for checksum report\n", 1826 sc->sc_pdev->dv_xname); 1827 error = ETIMEDOUT; 1828 goto fail; 1829 } 1830 1831 /* Disable FW download. */ 1832 rtwn_write_1(sc, R92C_MCUFWDL, 1833 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 1834 1835 /* Reserved for fw extension. */ 1836 if (!(sc->chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))) 1837 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 1838 1839 reg = rtwn_read_4(sc, R92C_MCUFWDL); 1840 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 1841 rtwn_write_4(sc, R92C_MCUFWDL, reg); 1842 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C | RTWN_CHIP_23A)) { 1843 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1844 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1845 reg & ~R92C_SYS_FUNC_EN_CPUEN); 1846 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1847 reg | R92C_SYS_FUNC_EN_CPUEN); 1848 } else 1849 rtwn_fw_reset(sc); 1850 /* Wait for firmware readiness. */ 1851 for (ntries = 0; ntries < 1000; ntries++) { 1852 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 1853 break; 1854 DELAY(10); 1855 } 1856 if (ntries == 1000) { 1857 printf("%s: timeout waiting for firmware readiness\n", 1858 sc->sc_pdev->dv_xname); 1859 error = ETIMEDOUT; 1860 goto fail; 1861 } 1862 fail: 1863 free(fw, M_DEVBUF, len0); 1864 /* Init H2C command. */ 1865 if (sc->chip & RTWN_CHIP_88F) 1866 rtwn_write_1(sc, R92C_HMETFR, 0xf); 1867 return (error); 1868 } 1869 1870 void 1871 rtwn_rf_init(struct rtwn_softc *sc) 1872 { 1873 const struct r92c_rf_prog *prog; 1874 uint32_t reg, type; 1875 int i, j, idx, off; 1876 1877 /* Select RF programming based on board type. */ 1878 if (sc->chip & RTWN_CHIP_88E) 1879 prog = rtl8188eu_rf_prog; 1880 else if (sc->chip & RTWN_CHIP_88F) 1881 prog = rtl8188ftv_rf_prog; 1882 else if (sc->chip & RTWN_CHIP_92E) 1883 prog = rtl8192e_rf_prog; 1884 else if (!(sc->chip & RTWN_CHIP_92C)) { 1885 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 1886 prog = rtl8188ce_rf_prog; 1887 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 1888 prog = rtl8188ru_rf_prog; 1889 else 1890 prog = rtl8188cu_rf_prog; 1891 } else 1892 prog = rtl8192ce_rf_prog; 1893 1894 for (i = 0; i < sc->nrxchains; i++) { 1895 /* Save RF_ENV control type. */ 1896 idx = i / 2; 1897 off = (i % 2) * 16; 1898 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1899 type = (reg >> off) & 0x10; 1900 1901 /* Set RF_ENV enable. */ 1902 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1903 reg |= 0x100000; 1904 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1905 DELAY(50); 1906 /* Set RF_ENV output high. */ 1907 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1908 reg |= 0x10; 1909 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1910 DELAY(50); 1911 /* Set address and data lengths of RF registers. */ 1912 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1913 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 1914 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1915 DELAY(50); 1916 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1917 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 1918 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1919 DELAY(50); 1920 1921 /* Write RF initialization values for this chain. */ 1922 for (j = 0; j < prog[i].count; j++) { 1923 switch (prog[i].regs[j]) { 1924 case 0xfe: 1925 case 0xffe: 1926 DELAY(50000); 1927 continue; 1928 case 0xfd: 1929 DELAY(5000); 1930 continue; 1931 case 0xfc: 1932 DELAY(1000); 1933 continue; 1934 case 0xfb: 1935 DELAY(50); 1936 continue; 1937 case 0xfa: 1938 DELAY(5); 1939 continue; 1940 case 0xf9: 1941 DELAY(1); 1942 continue; 1943 } 1944 rtwn_rf_write(sc, i, prog[i].regs[j], 1945 prog[i].vals[j]); 1946 DELAY(5); 1947 } 1948 1949 /* Restore RF_ENV control type. */ 1950 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1951 reg &= ~(0x10 << off) | (type << off); 1952 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 1953 1954 /* Cache RF register CHNLBW. */ 1955 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 1956 } 1957 1958 /* magic value for HP 8188EEs */ 1959 if (sc->chip == (RTWN_CHIP_88E | RTWN_CHIP_PCI)) { 1960 struct r88e_rom *rom = &sc->sc_r88e_rom; 1961 if (rom->r88ee_rom.svid == 0x103c && 1962 rom->r88ee_rom.smid == 0x197d) 1963 rtwn_rf_write(sc, 0, 0x52, 0x7e4bd); 1964 } 1965 1966 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1967 RTWN_CHIP_UMC_A_CUT) { 1968 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 1969 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 1970 } else if (sc->chip & RTWN_CHIP_23A) { 1971 rtwn_rf_write(sc, 0, 0x0C, 0x894ae); 1972 rtwn_rf_write(sc, 0, 0x0A, 0x1af31); 1973 rtwn_rf_write(sc, 0, R92C_RF_IPA, 0x8f425); 1974 rtwn_rf_write(sc, 0, R92C_RF_SYN_G(1), 0x4f200); 1975 rtwn_rf_write(sc, 0, R92C_RF_RCK1, 0x44053); 1976 rtwn_rf_write(sc, 0, R92C_RF_RCK2, 0x80201); 1977 } 1978 } 1979 1980 void 1981 rtwn_cam_init(struct rtwn_softc *sc) 1982 { 1983 /* Invalidate all CAM entries. */ 1984 rtwn_write_4(sc, R92C_CAMCMD, 1985 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 1986 } 1987 1988 void 1989 rtwn_pa_bias_init(struct rtwn_softc *sc) 1990 { 1991 uint8_t reg; 1992 int i; 1993 1994 for (i = 0; i < sc->nrxchains; i++) { 1995 if (sc->pa_setting & (1 << i)) 1996 continue; 1997 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 1998 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 1999 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2000 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2001 } 2002 if (!(sc->pa_setting & 0x10)) { 2003 reg = rtwn_read_1(sc, 0x16); 2004 reg = (reg & ~0xf0) | 0x90; 2005 rtwn_write_1(sc, 0x16, reg); 2006 } 2007 } 2008 2009 void 2010 rtwn_rxfilter_init(struct rtwn_softc *sc) 2011 { 2012 /* Initialize Rx filter. */ 2013 rtwn_write_4(sc, R92C_RCR, 2014 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2015 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2016 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2017 /* Accept all multicast frames. */ 2018 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2019 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2020 /* Accept all management frames. */ 2021 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2022 /* Reject all control frames. */ 2023 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2024 /* Accept all data frames. */ 2025 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2026 } 2027 2028 void 2029 rtwn_edca_init(struct rtwn_softc *sc) 2030 { 2031 struct ieee80211com *ic = &sc->sc_ic; 2032 int mode, aci; 2033 2034 /* Set SIFS; 0x10 = 16 usec (SIFS 11g), 0x0a = 10 usec (SIFS 11b) */ 2035 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2036 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2037 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2038 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2039 if (!(sc->chip & RTWN_CHIP_88F)) { 2040 rtwn_write_2(sc, R92C_RESP_SIFS_CCK, 0x100a); 2041 rtwn_write_2(sc, R92C_RESP_SIFS_OFDM, 0x100a); 2042 } else { 2043 rtwn_write_2(sc, R92C_RESP_SIFS_CCK, 0x0808); 2044 rtwn_write_2(sc, R92C_RESP_SIFS_OFDM, 0x0a0a); 2045 } 2046 2047 if (ic->ic_curmode == IEEE80211_MODE_AUTO) 2048 mode = IEEE80211_MODE_11G; /* XXX */ 2049 else 2050 mode = ic->ic_curmode; 2051 for (aci = 0; aci < EDCA_NUM_AC; aci++) 2052 memcpy(&ic->ic_edca_ac[aci], &ieee80211_edca_table[mode][aci], 2053 sizeof(struct ieee80211_edca_ac_params)); 2054 rtwn_updateedca(ic); 2055 2056 if (sc->chip & RTWN_CHIP_PCI) { 2057 /* linux magic */ 2058 rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x086666); 2059 } 2060 2061 rtwn_write_4(sc, R92C_EDCA_RANDOM_GEN, arc4random()); 2062 } 2063 2064 void 2065 rtwn_rate_fallback_init(struct rtwn_softc *sc) 2066 { 2067 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2068 if (sc->chip & RTWN_CHIP_PCI) { 2069 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 2070 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 2071 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 2072 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 2073 } else if (sc->chip & RTWN_CHIP_USB) { 2074 rtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 2075 rtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 2076 rtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 2077 rtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 2078 } 2079 } 2080 } 2081 2082 void 2083 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2084 uint16_t power[RTWN_POWER_COUNT]) 2085 { 2086 uint32_t reg; 2087 2088 /* Write per-CCK rate Tx power. */ 2089 if (chain == 0) { 2090 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2091 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_POWER_CCK1]); 2092 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2093 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2094 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_POWER_CCK2]); 2095 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_POWER_CCK55]); 2096 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_POWER_CCK11]); 2097 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2098 } else { 2099 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2100 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_POWER_CCK1]); 2101 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_POWER_CCK2]); 2102 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_POWER_CCK55]); 2103 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2104 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2105 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_POWER_CCK11]); 2106 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2107 } 2108 /* Write per-OFDM rate Tx power. */ 2109 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2110 SM(R92C_TXAGC_RATE06, power[RTWN_POWER_OFDM6]) | 2111 SM(R92C_TXAGC_RATE09, power[RTWN_POWER_OFDM9]) | 2112 SM(R92C_TXAGC_RATE12, power[RTWN_POWER_OFDM12]) | 2113 SM(R92C_TXAGC_RATE18, power[RTWN_POWER_OFDM18])); 2114 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2115 SM(R92C_TXAGC_RATE24, power[RTWN_POWER_OFDM24]) | 2116 SM(R92C_TXAGC_RATE36, power[RTWN_POWER_OFDM36]) | 2117 SM(R92C_TXAGC_RATE48, power[RTWN_POWER_OFDM48]) | 2118 SM(R92C_TXAGC_RATE54, power[RTWN_POWER_OFDM54])); 2119 /* Write per-MCS Tx power. */ 2120 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2121 SM(R92C_TXAGC_MCS00, power[RTWN_POWER_MCS( 0)]) | 2122 SM(R92C_TXAGC_MCS01, power[RTWN_POWER_MCS( 1)]) | 2123 SM(R92C_TXAGC_MCS02, power[RTWN_POWER_MCS( 2)]) | 2124 SM(R92C_TXAGC_MCS03, power[RTWN_POWER_MCS( 3)])); 2125 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2126 SM(R92C_TXAGC_MCS04, power[RTWN_POWER_MCS( 4)]) | 2127 SM(R92C_TXAGC_MCS05, power[RTWN_POWER_MCS( 5)]) | 2128 SM(R92C_TXAGC_MCS06, power[RTWN_POWER_MCS( 6)]) | 2129 SM(R92C_TXAGC_MCS07, power[RTWN_POWER_MCS( 7)])); 2130 if (sc->ntxchains > 1) { 2131 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2132 SM(R92C_TXAGC_MCS08, power[RTWN_POWER_MCS( 8)]) | 2133 SM(R92C_TXAGC_MCS09, power[RTWN_POWER_MCS( 9)]) | 2134 SM(R92C_TXAGC_MCS10, power[RTWN_POWER_MCS(10)]) | 2135 SM(R92C_TXAGC_MCS11, power[RTWN_POWER_MCS(11)])); 2136 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2137 SM(R92C_TXAGC_MCS12, power[RTWN_POWER_MCS(12)]) | 2138 SM(R92C_TXAGC_MCS13, power[RTWN_POWER_MCS(13)]) | 2139 SM(R92C_TXAGC_MCS14, power[RTWN_POWER_MCS(14)]) | 2140 SM(R92C_TXAGC_MCS15, power[RTWN_POWER_MCS(15)])); 2141 } 2142 } 2143 2144 void 2145 rtwn_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c, 2146 struct ieee80211_channel *extc, uint16_t power[RTWN_POWER_COUNT]) 2147 { 2148 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F)) 2149 rtwn_r88e_get_txpower(sc, chain, c, extc, power); 2150 else if (sc->chip & RTWN_CHIP_92E) 2151 rtwn_r92e_get_txpower(sc, chain, c, extc, power); 2152 else 2153 rtwn_r92c_get_txpower(sc, chain, c, extc, power); 2154 } 2155 2156 void 2157 rtwn_r92c_get_txpower(struct rtwn_softc *sc, int chain, 2158 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2159 uint16_t power[RTWN_POWER_COUNT]) 2160 { 2161 struct ieee80211com *ic = &sc->sc_ic; 2162 struct r92c_rom *rom = &sc->sc_r92c_rom; 2163 uint16_t cckpow, ofdmpow, htpow, diff, max; 2164 const struct r92c_txpwr *base; 2165 int ridx, chan, group; 2166 2167 /* Determine channel group. */ 2168 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2169 if (chan <= 3) 2170 group = 0; 2171 else if (chan <= 9) 2172 group = 1; 2173 else 2174 group = 2; 2175 2176 /* Get original Tx power based on board type and RF chain. */ 2177 if (!(sc->chip & RTWN_CHIP_92C)) { 2178 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2179 base = &rtl8188ru_txagc[chain]; 2180 else 2181 base = &rtl8192cu_txagc[chain]; 2182 } else 2183 base = &rtl8192cu_txagc[chain]; 2184 2185 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2186 if (sc->regulatory == 0) { 2187 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 2188 power[ridx] = base->pwr[0][ridx]; 2189 } 2190 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_MAX; ridx++) { 2191 if (sc->regulatory == 3) { 2192 power[ridx] = base->pwr[0][ridx]; 2193 /* Apply vendor limits. */ 2194 if (extc != NULL) 2195 max = rom->ht40_max_pwr[group]; 2196 else 2197 max = rom->ht20_max_pwr[group]; 2198 max = (max >> (chain * 4)) & 0xf; 2199 if (power[ridx] > max) 2200 power[ridx] = max; 2201 } else if (sc->regulatory == 1) { 2202 if (extc == NULL) 2203 power[ridx] = base->pwr[group][ridx]; 2204 } else if (sc->regulatory != 2) 2205 power[ridx] = base->pwr[0][ridx]; 2206 } 2207 2208 /* Compute per-CCK rate Tx power. */ 2209 cckpow = rom->cck_tx_pwr[chain][group]; 2210 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2211 power[ridx] += cckpow; 2212 if (power[ridx] > R92C_MAX_TX_PWR) 2213 power[ridx] = R92C_MAX_TX_PWR; 2214 } 2215 2216 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2217 if (sc->ntxchains > 1) { 2218 /* Apply reduction for 2 spatial streams. */ 2219 diff = rom->ht40_2s_tx_pwr_diff[group]; 2220 diff = (diff >> (chain * 4)) & 0xf; 2221 htpow = (htpow > diff) ? htpow - diff : 0; 2222 } 2223 2224 /* Compute per-OFDM rate Tx power. */ 2225 diff = rom->ofdm_tx_pwr_diff[group]; 2226 diff = (diff >> (chain * 4)) & 0xf; 2227 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2228 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2229 power[ridx] += ofdmpow; 2230 if (power[ridx] > R92C_MAX_TX_PWR) 2231 power[ridx] = R92C_MAX_TX_PWR; 2232 } 2233 2234 /* Compute per-MCS Tx power. */ 2235 if (extc == NULL) { 2236 diff = rom->ht20_tx_pwr_diff[group]; 2237 diff = (diff >> (chain * 4)) & 0xf; 2238 htpow += diff; /* HT40->HT20 correction. */ 2239 } 2240 for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2241 power[ridx] += htpow; 2242 if (power[ridx] > R92C_MAX_TX_PWR) 2243 power[ridx] = R92C_MAX_TX_PWR; 2244 } 2245 #ifdef RTWN_DEBUG 2246 if (rtwn_debug >= 4) { 2247 /* Dump per-rate Tx power values. */ 2248 printf("Tx power for chain %d:\n", chain); 2249 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_MAX; ridx++) 2250 printf("Rate %d = %u\n", ridx, power[ridx]); 2251 } 2252 #endif 2253 } 2254 2255 void 2256 rtwn_r92e_get_txpower(struct rtwn_softc *sc, int chain, 2257 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2258 uint16_t power[RTWN_POWER_COUNT]) 2259 { 2260 struct ieee80211com *ic = &sc->sc_ic; 2261 struct r92e_rom *rom = &sc->sc_r92e_rom; 2262 struct r92e_tx_pwr *txpwr; 2263 uint8_t cckpow, htpow, htpow2s = 0, ofdmpow; 2264 int8_t diff; 2265 int ridx, chan, group; 2266 2267 /* Determine channel group. */ 2268 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2269 group = rtwn_chan2group(chan); 2270 2271 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2272 2273 if (chain == 0) 2274 txpwr = &rom->txpwr_a; 2275 else 2276 txpwr = &rom->txpwr_b; 2277 2278 /* Compute per-CCK rate Tx power. */ 2279 cckpow = txpwr->cck_tx_pwr[group]; 2280 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2281 power[ridx] = cckpow; 2282 if (power[ridx] > R92C_MAX_TX_PWR) 2283 power[ridx] = R92C_MAX_TX_PWR; 2284 } 2285 2286 htpow = txpwr->ht40_tx_pwr[group]; 2287 2288 /* Compute per-OFDM rate Tx power. */ 2289 diff = RTWN_SIGN4TO8(MS(txpwr->ht20_ofdm_tx_pwr_diff, 2290 R92E_ROM_TXPWR_OFDM_DIFF)); 2291 ofdmpow = htpow + diff; 2292 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2293 power[ridx] = ofdmpow; 2294 if (power[ridx] > R92C_MAX_TX_PWR) 2295 power[ridx] = R92C_MAX_TX_PWR; 2296 } 2297 2298 /* Compute per-MCS Tx power. */ 2299 if (extc == NULL) { 2300 diff = RTWN_SIGN4TO8(MS(txpwr->ht20_ofdm_tx_pwr_diff, 2301 R92E_ROM_TXPWR_HT20_DIFF)); 2302 htpow += diff; 2303 if (sc->ntxchains > 1) { 2304 diff = RTWN_SIGN4TO8(MS( 2305 txpwr->pwr_diff[0].ht40_ht20_tx_pwr_diff, 2306 R92E_ROM_TXPWR_HT20_2S_DIFF)); 2307 htpow2s = htpow + diff; 2308 } 2309 } 2310 2311 for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2312 power[ridx] = (ridx < RTWN_RIDX_MCS8) ? htpow : htpow2s; 2313 if (power[ridx] > R92C_MAX_TX_PWR) 2314 power[ridx] = R92C_MAX_TX_PWR; 2315 } 2316 } 2317 2318 void 2319 rtwn_r88e_get_txpower(struct rtwn_softc *sc, int chain, 2320 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2321 uint16_t power[RTWN_POWER_COUNT]) 2322 { 2323 struct ieee80211com *ic = &sc->sc_ic; 2324 struct r88e_rom *rom = &sc->sc_r88e_rom; 2325 uint8_t cckpow, htpow, ofdmpow; 2326 int8_t diff; 2327 int ridx, chan, group; 2328 2329 /* Determine channel group. */ 2330 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2331 if (sc->chip & RTWN_CHIP_88F) 2332 group = rtwn_chan2group(chan); 2333 else { 2334 if (chan <= 2) 2335 group = 0; 2336 else if (chan <= 5) 2337 group = 1; 2338 else if (chan <= 8) 2339 group = 2; 2340 else if (chan <= 11) 2341 group = 3; 2342 else if (chan <= 13) 2343 group = 4; 2344 else 2345 group = 5; 2346 } 2347 2348 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2349 2350 /* Compute per-CCK rate Tx power. */ 2351 cckpow = rom->txpwr.cck_tx_pwr[group]; 2352 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2353 if (sc->chip & RTWN_CHIP_88F) 2354 power[ridx] = cckpow; 2355 else 2356 power[ridx] = (ridx == RTWN_RIDX_CCK2) ? 2357 cckpow - 9 : cckpow; 2358 if (power[ridx] > R92C_MAX_TX_PWR) 2359 power[ridx] = R92C_MAX_TX_PWR; 2360 } 2361 2362 if (sc->chip & RTWN_CHIP_88F) 2363 htpow = rom->txpwr.ht40_tx_pwr[group]; 2364 else 2365 htpow = (group == 5) ? rom->txpwr.ht40_tx_pwr[group - 1] : 2366 rom->txpwr.ht40_tx_pwr[group]; 2367 2368 /* Compute per-OFDM rate Tx power. */ 2369 diff = RTWN_SIGN4TO8(MS(rom->txpwr.ht20_ofdm_tx_pwr_diff, 2370 R88E_ROM_TXPWR_OFDM_DIFF)); 2371 ofdmpow = htpow + diff; 2372 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2373 power[ridx] = ofdmpow; 2374 if (power[ridx] > R92C_MAX_TX_PWR) 2375 power[ridx] = R92C_MAX_TX_PWR; 2376 } 2377 2378 /* Compute per-MCS Tx power. */ 2379 if (extc == NULL) { 2380 diff = RTWN_SIGN4TO8(MS(rom->txpwr.ht20_ofdm_tx_pwr_diff, 2381 R88E_ROM_TXPWR_HT20_DIFF)); 2382 htpow += diff; 2383 } 2384 for (ridx = RTWN_RIDX_MCS0; ridx < RTWN_RIDX_MCS8; ridx++) { 2385 power[ridx] = htpow; 2386 if (power[ridx] > R92C_MAX_TX_PWR) 2387 power[ridx] = R92C_MAX_TX_PWR; 2388 } 2389 } 2390 2391 void 2392 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2393 struct ieee80211_channel *extc) 2394 { 2395 uint16_t power[RTWN_POWER_COUNT]; 2396 int i; 2397 2398 for (i = 0; i < sc->ntxchains; i++) { 2399 /* Compute per-rate Tx power values. */ 2400 rtwn_get_txpower(sc, i, c, extc, power); 2401 /* Write per-rate Tx power values to hardware. */ 2402 rtwn_write_txpower(sc, i, power); 2403 } 2404 } 2405 2406 void 2407 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2408 struct ieee80211_channel *extc) 2409 { 2410 struct ieee80211com *ic = &sc->sc_ic; 2411 u_int chan; 2412 uint32_t reg; 2413 int i; 2414 2415 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2416 2417 /* Set Tx power for this new channel. */ 2418 rtwn_set_txpower(sc, c, extc); 2419 2420 if (extc != NULL) { 2421 /* Is secondary channel below or above primary? */ 2422 int prichlo = c->ic_freq < extc->ic_freq; 2423 2424 if (sc->chip & RTWN_CHIP_92E) { 2425 reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL); 2426 reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK; 2427 reg |= R92C_WMAC_TRXPTCL_CTL_BW_40; 2428 rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg); 2429 rtwn_write_1(sc, R92E_DATA_SC, 0); 2430 } else { 2431 rtwn_write_1(sc, R92C_BWOPMODE, 2432 rtwn_read_1(sc, R92C_BWOPMODE) & 2433 ~R92C_BWOPMODE_20MHZ); 2434 } 2435 2436 reg = rtwn_read_1(sc, R92C_RRSR + 2); 2437 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2438 rtwn_write_1(sc, R92C_RRSR + 2, reg); 2439 2440 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2441 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2442 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2443 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2444 2445 /* Set CCK side band. */ 2446 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2447 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2448 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2449 2450 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2451 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2452 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2453 2454 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2455 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2456 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2457 ~R92C_FPGA0_ANAPARAM2_CBW20); 2458 } 2459 2460 reg = rtwn_bb_read(sc, 0x818); 2461 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2462 rtwn_bb_write(sc, 0x818, reg); 2463 2464 /* Select 40MHz bandwidth. */ 2465 for (i = 0; i < sc->nrxchains; i++) { 2466 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2467 (sc->rf_chnlbw[i] & ~0xfff) | chan); 2468 } 2469 } else { 2470 if (sc->chip & RTWN_CHIP_92E) { 2471 reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL); 2472 reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK; 2473 rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg); 2474 rtwn_write_1(sc, R92E_DATA_SC, 0); 2475 } else if (!(sc->chip & RTWN_CHIP_88F)) { 2476 rtwn_write_1(sc, R92C_BWOPMODE, 2477 rtwn_read_1(sc, R92C_BWOPMODE) | 2478 R92C_BWOPMODE_20MHZ); 2479 } 2480 2481 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2482 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2483 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2484 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2485 2486 if (!(sc->chip & 2487 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 2488 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2489 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2490 R92C_FPGA0_ANAPARAM2_CBW20); 2491 } else if (sc->chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) { 2492 if (sc->chip & RTWN_CHIP_88F) { 2493 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2494 reg = (reg & ~0x00000700) | 0x7 << 8; 2495 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2496 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2497 reg = (reg & ~0x00007000) | 0x5 << 12; 2498 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2499 } 2500 2501 reg = rtwn_bb_read(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT); 2502 reg &= ~0xc0000000; 2503 rtwn_bb_write(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg); 2504 2505 if (sc->chip & RTWN_CHIP_88F) { 2506 /* Small bandwidth */ 2507 reg = rtwn_bb_read(sc, 2508 R92C_OFDM0_TX_PSDO_NOISE_WEIGHT); 2509 reg |= 0x30000000; 2510 rtwn_bb_write(sc, 2511 R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg); 2512 /* ADC buffer clk */ 2513 rtwn_bb_write(sc, R92C_OFDM0_RXAFE, 2514 rtwn_bb_read(sc, R92C_OFDM0_RXAFE) | 2515 0x30000000); 2516 /* OFDM Rx DFIR */ 2517 rtwn_bb_write(sc, R88F_RX_DFIR, 2518 rtwn_bb_read(sc, R88F_RX_DFIR) & 2519 ~0x00080000); 2520 reg = rtwn_bb_read(sc, R88F_RX_DFIR); 2521 reg = (reg & ~0x00f00000) | 0x3 << 15; 2522 rtwn_bb_write(sc, R88F_RX_DFIR, reg); 2523 } 2524 } 2525 2526 /* Select 20MHz bandwidth. */ 2527 for (i = 0; i < sc->nrxchains; i++) { 2528 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2529 (sc->rf_chnlbw[i] & ~0xfff) | chan | 2530 ((sc->chip & 2531 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) ? 2532 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 2533 2534 if (sc->chip & RTWN_CHIP_88F) { 2535 rtwn_rf_write(sc, i, 0x87, 0x65); 2536 rtwn_rf_write(sc, i, 0x1c, 0); 2537 rtwn_rf_write(sc, i, 0xdf, 0x0140); 2538 rtwn_rf_write(sc, i, 0x1b, 0x1c6c);; 2539 } 2540 } 2541 } 2542 2543 if (sc->chip == (RTWN_CHIP_88E | RTWN_CHIP_PCI)) 2544 DELAY(25000); 2545 } 2546 2547 int 2548 rtwn_chan2group(int chan) 2549 { 2550 int group; 2551 2552 if (chan <= 2) 2553 group = 0; 2554 else if (chan <= 5) 2555 group = 1; 2556 else if (chan <= 8) 2557 group = 2; 2558 else if (chan <= 11) 2559 group = 3; 2560 else 2561 group = 4; 2562 2563 return (group); 2564 } 2565 2566 int 2567 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2568 uint16_t rx[2]) 2569 { 2570 uint32_t status; 2571 int offset = chain * 0x20; 2572 uint32_t iqk_tone_92c[] = { 2573 0x10008c1f, 0x10008c1f, 0x82140102, 0x28160202, 0x10008c22 2574 }; 2575 uint32_t iqk_tone_92e[] = { 2576 0x18008c1c, 0x38008c1c, 0x82140303, 0x68160000, 0x38008c1c 2577 }; 2578 uint32_t *iqk_tone; 2579 2580 if (sc->chip & RTWN_CHIP_92E) 2581 iqk_tone = iqk_tone_92e; 2582 else 2583 iqk_tone = iqk_tone_92c; 2584 2585 if (chain == 0) { /* IQ calibration for chain 0. */ 2586 /* IQ calibration settings for chain 0. */ 2587 rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, iqk_tone[0]); 2588 rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[1]); 2589 rtwn_bb_write(sc, R92C_TX_IQK_PI_A, iqk_tone[2]); 2590 2591 if (sc->ntxchains > 1) { 2592 rtwn_bb_write(sc, R92C_RX_IQK_PI_A, iqk_tone[3]); 2593 /* IQ calibration settings for chain 1. */ 2594 rtwn_bb_write(sc, R92C_TX_IQK_TONE_B, iqk_tone[4]); 2595 rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[4]); 2596 rtwn_bb_write(sc, R92C_TX_IQK_PI_B, 0x82140102); 2597 rtwn_bb_write(sc, R92C_RX_IQK_PI_B, 0x28160202); 2598 } else 2599 rtwn_bb_write(sc, R92C_RX_IQK_PI_A, 0x28160502); 2600 2601 /* LO calibration settings. */ 2602 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 2603 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x00462911); 2604 else 2605 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); 2606 /* We're doing LO and IQ calibration in one shot. */ 2607 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); 2608 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); 2609 2610 } else { /* IQ calibration for chain 1. */ 2611 /* We're doing LO and IQ calibration in one shot. */ 2612 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000002); 2613 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000000); 2614 } 2615 2616 /* Give LO and IQ calibrations the time to complete. */ 2617 DELAY(1000); 2618 2619 /* Read IQ calibration status. */ 2620 status = rtwn_bb_read(sc, 0xeac); 2621 2622 if (status & (1 << (28 + chain * 3))) 2623 return (0); /* Tx failed. */ 2624 /* Read Tx IQ calibration results. */ 2625 tx[0] = (rtwn_bb_read(sc, R92C_TX_POWER_BEFORE_IQK_A + offset) >> 16) 2626 & 0x3ff; 2627 tx[1] = (rtwn_bb_read(sc, R92C_TX_POWER_AFTER_IQK_A + offset) >> 16) 2628 & 0x3ff; 2629 if (tx[0] == 0x142 || tx[1] == 0x042) 2630 return (0); /* Tx failed. */ 2631 2632 if (status & (1 << (27 + chain * 3))) 2633 return (1); /* Rx failed. */ 2634 /* Read Rx IQ calibration results. */ 2635 rx[0] = (rtwn_bb_read(sc, R92C_RX_POWER_BEFORE_IQK_A_2 + offset) >> 16) 2636 & 0x3ff; 2637 rx[1] = (rtwn_bb_read(sc, R92C_RX_POWER_AFTER_IQK_A_2 + offset) >> 16) 2638 & 0x3ff; 2639 if (rx[0] == 0x132 || rx[1] == 0x036) 2640 return (1); /* Rx failed. */ 2641 2642 return (3); /* Both Tx and Rx succeeded. */ 2643 } 2644 2645 void 2646 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2647 uint16_t rx[2][2], struct rtwn_iq_cal_regs *iq_cal_regs) 2648 { 2649 static const uint16_t reg_adda[16] = { 2650 0x85c, 0xe6c, 0xe70, 0xe74, 2651 0xe78, 0xe7c, 0xe80, 0xe84, 2652 0xe88, 0xe8c, 0xed0, 0xed4, 2653 0xed8, 0xedc, 0xee0, 0xeec 2654 }; 2655 static const uint32_t adda_92c[] = { 2656 0x0b1b25a0, 0x0bdb25a0, 0x04db25a4, 0x0b1b25a4 2657 }; 2658 static const uint32_t adda_92e[] = { 2659 0x0fc01616, 0x0fc01616, 0x0fc01616, 0x0fc01616 2660 }; 2661 const uint32_t *adda_vals; 2662 2663 int i, chain; 2664 uint32_t hssi_param1, reg; 2665 uint8_t xa_agc, xb_agc; 2666 2667 xa_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)) & 0xff; 2668 xb_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)) & 0xff; 2669 2670 if (sc->chip & RTWN_CHIP_92E) 2671 adda_vals = adda_92e; 2672 else 2673 adda_vals = adda_92c; 2674 2675 if (n == 0) { 2676 for (i = 0; i < nitems(reg_adda); i++) 2677 iq_cal_regs->adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2678 2679 iq_cal_regs->txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2680 iq_cal_regs->bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2681 iq_cal_regs->bcn_ctrl1 = rtwn_read_1(sc, R92C_BCN_CTRL1); 2682 iq_cal_regs->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2683 } 2684 2685 if (sc->ntxchains == 1) { 2686 rtwn_bb_write(sc, reg_adda[0], adda_vals[0]); 2687 for (i = 1; i < nitems(reg_adda); i++) 2688 rtwn_bb_write(sc, reg_adda[i], adda_vals[1]); 2689 } else { 2690 for (i = 0; i < nitems(reg_adda); i++) 2691 rtwn_bb_write(sc, reg_adda[i], adda_vals[2]); 2692 } 2693 2694 if (n == 0) { 2695 iq_cal_regs->ofdm0_trxpathena = 2696 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2697 iq_cal_regs->ofdm0_trmuxpar = 2698 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2699 iq_cal_regs->fpga0_rfifacesw0 = 2700 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)); 2701 iq_cal_regs->fpga0_rfifacesw1 = 2702 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2703 iq_cal_regs->fpga0_rfifaceoe0 = 2704 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 2705 iq_cal_regs->fpga0_rfifaceoe1 = 2706 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1)); 2707 iq_cal_regs->config_ant_a = 2708 rtwn_bb_read(sc, R92C_CONFIG_ANT_A); 2709 iq_cal_regs->config_ant_b = 2710 rtwn_bb_read(sc, R92C_CONFIG_ANT_B); 2711 iq_cal_regs->cck0_afesetting = 2712 rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2713 } 2714 2715 if (sc->chip & RTWN_CHIP_92E) { 2716 rtwn_write_4(sc, R92C_CCK0_AFESETTING, rtwn_read_4(sc, 2717 R92C_CCK0_AFESETTING) | 0x0f000000); 2718 } else { 2719 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2720 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2721 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2722 hssi_param1 | R92C_HSSI_PARAM1_PI); 2723 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2724 hssi_param1 | R92C_HSSI_PARAM1_PI); 2725 } 2726 } 2727 2728 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2729 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2730 2731 if (sc->chip & RTWN_CHIP_92E) { 2732 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22208200); 2733 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), 2734 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)) | (1 << 10) | 2735 (1 << 26)); 2736 2737 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), rtwn_bb_read(sc, 2738 R92C_FPGA0_RFIFACEOE(0)) | (1 << 10)); 2739 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), rtwn_bb_read(sc, 2740 R92C_FPGA0_RFIFACEOE(1)) | (1 << 10)); 2741 } else { 2742 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2743 2744 if (sc->ntxchains > 1) { 2745 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2746 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2747 } 2748 2749 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TXPAUSE_AC_VO | 2750 R92C_TXPAUSE_AC_VI | R92C_TXPAUSE_AC_BE | 2751 R92C_TXPAUSE_AC_BK | R92C_TXPAUSE_MGNT | 2752 R92C_TXPAUSE_HIGH); 2753 } 2754 rtwn_write_1(sc, R92C_BCN_CTRL, 2755 iq_cal_regs->bcn_ctrl & ~(R92C_BCN_CTRL_EN_BCN)); 2756 rtwn_write_1(sc, R92C_BCN_CTRL1, 2757 iq_cal_regs->bcn_ctrl1 & ~(R92C_BCN_CTRL_EN_BCN)); 2758 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2759 iq_cal_regs->gpio_muxcfg & ~(R92C_GPIO_MUXCFG_ENBT)); 2760 2761 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000); 2762 if (sc->ntxchains > 1) 2763 rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 0x00080000); 2764 2765 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 2766 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); 2767 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); 2768 2769 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000); 2770 2771 for (chain = 0; chain < sc->ntxchains; chain++) { 2772 if (chain > 0) { 2773 /* Put chain 0 on standby. */ 2774 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00); 2775 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2776 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 2777 2778 /* Enable chain 1. */ 2779 for (i = 0; i < nitems(reg_adda); i++) 2780 rtwn_bb_write(sc, reg_adda[i], adda_vals[3]); 2781 } 2782 2783 /* Run IQ calibration twice. */ 2784 for (i = 0; i < 2; i++) { 2785 int ret; 2786 2787 ret = rtwn_iq_calib_chain(sc, chain, 2788 tx[chain], rx[chain]); 2789 if (ret == 0) { 2790 DPRINTF(("%s: chain %d: Tx failed.\n", 2791 __func__, chain)); 2792 tx[chain][0] = 0xff; 2793 tx[chain][1] = 0xff; 2794 rx[chain][0] = 0xff; 2795 rx[chain][1] = 0xff; 2796 } else if (ret == 1) { 2797 DPRINTF(("%s: chain %d: Rx failed.\n", 2798 __func__, chain)); 2799 rx[chain][0] = 0xff; 2800 rx[chain][1] = 0xff; 2801 } else if (ret == 3) { 2802 DPRINTF(("%s: chain %d: Both Tx and Rx " 2803 "succeeded.\n", __func__, chain)); 2804 } 2805 } 2806 2807 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 2808 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 2809 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 2810 } 2811 2812 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00); 2813 2814 if (!(sc->chip & RTWN_CHIP_92E)) { 2815 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 2816 if (sc->ntxchains > 1) 2817 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 2818 } 2819 2820 if (n != 0) { 2821 if (!(sc->chip & RTWN_CHIP_92E)) { 2822 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2823 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2824 hssi_param1); 2825 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2826 hssi_param1); 2827 } 2828 } 2829 2830 for (i = 0; i < nitems(reg_adda); i++) 2831 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs->adda[i]); 2832 2833 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs->txpause); 2834 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs->bcn_ctrl); 2835 rtwn_write_1(sc, R92C_BCN_CTRL1, iq_cal_regs->bcn_ctrl1); 2836 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs->gpio_muxcfg); 2837 2838 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 2839 iq_cal_regs->ofdm0_trxpathena); 2840 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), 2841 iq_cal_regs->fpga0_rfifacesw0); 2842 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 2843 iq_cal_regs->fpga0_rfifacesw1); 2844 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), 2845 iq_cal_regs->fpga0_rfifaceoe0); 2846 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), 2847 iq_cal_regs->fpga0_rfifaceoe1); 2848 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 2849 iq_cal_regs->ofdm0_trmuxpar); 2850 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 2851 iq_cal_regs->config_ant_a); 2852 rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 2853 iq_cal_regs->config_ant_b); 2854 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, 2855 iq_cal_regs->cck0_afesetting); 2856 2857 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2858 reg &= ~0xff; 2859 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | 0x50); 2860 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | xa_agc); 2861 2862 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2863 reg &= ~0xff; 2864 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | 0x50); 2865 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | xb_agc); 2866 2867 rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, 0x01008c00); 2868 rtwn_bb_write(sc, R92C_RX_IQK_TONE_A, 0x01008c00); 2869 } 2870 } 2871 2872 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 2873 int 2874 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 2875 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 2876 { 2877 int chain, i, tx_ok[2], rx_ok[2]; 2878 2879 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 2880 for (chain = 0; chain < ntxchains; chain++) { 2881 for (i = 0; i < 2; i++) { 2882 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 2883 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 2884 continue; 2885 2886 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 2887 RTWN_IQ_CAL_MAX_TOLERANCE); 2888 2889 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 2890 RTWN_IQ_CAL_MAX_TOLERANCE); 2891 } 2892 } 2893 2894 if (ntxchains > 1) 2895 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 2896 else 2897 return (tx_ok[0] && rx_ok[0]); 2898 } 2899 #undef RTWN_IQ_CAL_MAX_TOLERANCE 2900 2901 void 2902 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 2903 uint16_t rx[2], int chain) 2904 { 2905 uint32_t reg, val, x; 2906 long y, tx_c; 2907 2908 if (tx[0] == 0xff || tx[1] == 0xff) 2909 return; 2910 2911 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2912 val = ((reg >> 22) & 0x3ff); 2913 x = tx[0]; 2914 if (x & 0x00000200) 2915 x |= 0xfffffc00; 2916 reg &= ~0x3ff; 2917 reg |= (((x * val) >> 8) & 0x3ff); 2918 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2919 2920 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2921 if (((x * val) >> 7) & 0x01) 2922 reg |= 0x80000000; 2923 else 2924 reg &= ~0x80000000; 2925 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2926 2927 y = tx[1]; 2928 if (y & 0x00000200) 2929 y |= 0xfffffc00; 2930 tx_c = (y * val) >> 8; 2931 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 2932 reg &= ~0xf0000000; 2933 reg |= ((tx_c & 0x3c0) << 22); 2934 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 2935 2936 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2937 reg &= ~0x003f0000; 2938 reg |= ((tx_c & 0x3f) << 16); 2939 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2940 2941 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2942 if (((y * val) >> 7) & 0x01) 2943 reg |= 0x20000000; 2944 else 2945 reg &= ~0x20000000; 2946 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2947 2948 if (rx[0] == 0xff || rx[1] == 0xff) 2949 return; 2950 2951 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 2952 reg &= ~0x3ff; 2953 reg |= (rx[0] & 0x3ff); 2954 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2955 2956 reg &= ~0xfc00; 2957 reg |= ((rx[1] & 0x03f) << 10); 2958 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2959 2960 if (chain == 0) { 2961 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 2962 reg &= ~0xf0000000; 2963 reg |= ((rx[1] & 0x3c0) << 22); 2964 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 2965 } else { 2966 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 2967 reg &= ~0xf000; 2968 reg |= ((rx[1] & 0x3c0) << 6); 2969 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 2970 } 2971 } 2972 2973 #define RTWN_IQ_CAL_NRUN 3 2974 void 2975 rtwn_iq_calib(struct rtwn_softc *sc) 2976 { 2977 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 2978 int n, valid; 2979 struct rtwn_iq_cal_regs regs; 2980 2981 valid = 0; 2982 memset(®s, 0, sizeof(regs)); 2983 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 2984 rtwn_iq_calib_run(sc, n, tx[n], rx[n], ®s); 2985 2986 if (n == 0) 2987 continue; 2988 2989 /* Valid results remain stable after consecutive runs. */ 2990 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 2991 tx[n], rx[n], sc->ntxchains); 2992 if (valid) 2993 break; 2994 } 2995 2996 if (valid) { 2997 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 2998 if (sc->ntxchains > 1) 2999 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 3000 } 3001 } 3002 #undef RTWN_IQ_CAL_NRUN 3003 3004 void 3005 rtwn_lc_calib(struct rtwn_softc *sc) 3006 { 3007 uint32_t rf_ac[2]; 3008 uint8_t txmode; 3009 int i; 3010 3011 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3012 if ((txmode & 0x70) != 0) { 3013 /* Disable all continuous Tx. */ 3014 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3015 3016 /* Set RF mode to standby mode. */ 3017 for (i = 0; i < sc->nrxchains; i++) { 3018 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3019 rtwn_rf_write(sc, i, R92C_RF_AC, 3020 RW(rf_ac[i], R92C_RF_AC_MODE, 3021 R92C_RF_AC_MODE_STANDBY)); 3022 } 3023 } else { 3024 /* Block all Tx queues. */ 3025 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TXPAUSE_ALL); 3026 } 3027 /* Start calibration. */ 3028 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3029 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3030 3031 /* Give calibration the time to complete. */ 3032 DELAY(100); 3033 3034 /* Restore configuration. */ 3035 if ((txmode & 0x70) != 0) { 3036 /* Restore Tx mode. */ 3037 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3038 /* Restore RF mode. */ 3039 for (i = 0; i < sc->nrxchains; i++) 3040 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3041 } else { 3042 /* Unblock all Tx queues. */ 3043 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3044 } 3045 } 3046 3047 void 3048 rtwn_temp_calib(struct rtwn_softc *sc) 3049 { 3050 int temp, t_meter_reg, t_meter_val; 3051 3052 if (sc->chip & RTWN_CHIP_92E) { 3053 t_meter_reg = R92E_RF_T_METER; 3054 t_meter_val = 0x37cf8; 3055 } else { 3056 t_meter_reg = R92C_RF_T_METER; 3057 t_meter_val = 0x60; 3058 } 3059 3060 if (sc->thcal_state == 0) { 3061 /* Start measuring temperature. */ 3062 rtwn_rf_write(sc, 0, t_meter_reg, t_meter_val); 3063 sc->thcal_state = 1; 3064 return; 3065 } 3066 sc->thcal_state = 0; 3067 3068 /* Read measured temperature. */ 3069 temp = rtwn_rf_read(sc, 0, t_meter_reg) & 0x1f; 3070 if (temp == 0) /* Read failed, skip. */ 3071 return; 3072 DPRINTFN(2, ("temperature=%d\n", temp)); 3073 3074 /* 3075 * Redo IQ and LC calibration if temperature changed significantly 3076 * since last calibration. 3077 */ 3078 if (sc->thcal_lctemp == 0) { 3079 /* First calibration is performed in rtwn_init(). */ 3080 sc->thcal_lctemp = temp; 3081 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3082 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3083 sc->thcal_lctemp, temp)); 3084 rtwn_iq_calib(sc); 3085 rtwn_lc_calib(sc); 3086 /* Record temperature of last calibration. */ 3087 sc->thcal_lctemp = temp; 3088 } 3089 } 3090 3091 void 3092 rtwn_enable_intr(struct rtwn_softc *sc) 3093 { 3094 if (sc->chip & RTWN_CHIP_92E) { 3095 rtwn_write_4(sc, R88E_HISR, 0xffffffff); 3096 rtwn_write_4(sc, R88E_HISRE, 0xffffffff); 3097 rtwn_write_4(sc, R88E_HIMR, 0); 3098 rtwn_write_4(sc, R88E_HIMRE, 0); 3099 } else if (sc->chip & RTWN_CHIP_88E) { 3100 rtwn_write_4(sc, R88E_HISR, 0xffffffff); 3101 if (sc->chip & RTWN_CHIP_USB) { 3102 rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | 3103 R88E_HIMR_CPWM2 | R88E_HIMR_TBDER | 3104 R88E_HIMR_PSTIMEOUT); 3105 rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3106 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | 3107 R88E_HIMRE_TXERR); 3108 } else { 3109 rtwn_write_4(sc, R88E_HIMR, 3110 RTWN_88E_INT_ENABLE); 3111 rtwn_write_4(sc, R88E_HIMRE, 3112 R88E_HIMRE_RXFOVW); 3113 rtwn_write_1(sc, R92C_C2HEVT_CLEAR, 0); 3114 rtwn_write_4(sc, R92C_HSIMR, 3115 R88E_HSIMR_PDN_INT_EN | R88E_HSIMR_RON_INT_EN); 3116 } 3117 3118 if (sc->chip & RTWN_CHIP_USB) { 3119 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3120 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3121 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3122 } 3123 } else { 3124 uint32_t imask = 0; 3125 3126 if (sc->chip & RTWN_CHIP_USB) 3127 imask = 0xffffffff; 3128 else if (sc->chip & RTWN_CHIP_PCI) 3129 imask = RTWN_92C_INT_ENABLE; 3130 else 3131 panic("unknown chip type 0x%x", sc->chip); 3132 3133 /* CLear pending interrupts. */ 3134 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3135 3136 /* Enable interrupts. */ 3137 rtwn_write_4(sc, R92C_HIMR, imask); 3138 } 3139 } 3140 3141 void 3142 rtwn_disable_intr(struct rtwn_softc *sc) 3143 { 3144 if (sc->chip & RTWN_CHIP_88E) { 3145 rtwn_write_4(sc, R88E_HISR, 0x00000000); 3146 rtwn_write_4(sc, R88E_HIMR, 0x00000000); 3147 rtwn_write_4(sc, R88E_HIMRE, 0x00000000); 3148 if (sc->chip & RTWN_CHIP_USB) { 3149 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3150 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3151 ~R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3152 } 3153 } else { 3154 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3155 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3156 } 3157 } 3158 3159 int 3160 rtwn_init(struct ifnet *ifp) 3161 { 3162 struct rtwn_softc *sc = ifp->if_softc; 3163 struct ieee80211com *ic = &sc->sc_ic; 3164 uint32_t reg; 3165 int i, error; 3166 3167 /* Init firmware commands ring. */ 3168 sc->fwcur = 0; 3169 3170 error = sc->sc_ops.alloc_buffers(sc->sc_ops.cookie); 3171 if (error) 3172 goto fail; 3173 3174 /* Power on adapter. */ 3175 error = sc->sc_ops.power_on(sc->sc_ops.cookie); 3176 if (error != 0) { 3177 printf("%s: could not power on adapter\n", 3178 sc->sc_pdev->dv_xname); 3179 goto fail; 3180 } 3181 3182 /* Initialize DMA. */ 3183 error = sc->sc_ops.dma_init(sc->sc_ops.cookie); 3184 if (error != 0) { 3185 printf("%s: could not initialize DMA\n", 3186 sc->sc_pdev->dv_xname); 3187 goto fail; 3188 } 3189 3190 /* Set info size in Rx descriptors (in 64-bit words). */ 3191 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3192 3193 if ((sc->chip & RTWN_CHIP_USB) && !(sc->chip & RTWN_CHIP_88F)) { 3194 /* Init interrupts. */ 3195 rtwn_enable_intr(sc); 3196 } else if (sc->chip & RTWN_CHIP_PCI) { 3197 rtwn_disable_intr(sc); 3198 } 3199 3200 /* Set MAC address. */ 3201 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3202 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3203 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3204 3205 /* Set initial network type. */ 3206 rtwn_set_nettype(sc, IEEE80211_M_MONITOR); 3207 3208 rtwn_rxfilter_init(sc); 3209 3210 reg = rtwn_read_4(sc, R92C_RRSR); 3211 if (sc->chip & RTWN_CHIP_USB) { 3212 reg = RW(reg, R92C_RRSR_RATE_BITMAP, 3213 R92C_RRSR_RATE_CCK_ONLY_1M); 3214 } else { 3215 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3216 } 3217 rtwn_write_4(sc, R92C_RRSR, reg); 3218 3219 /* Set short/long retry limits. */ 3220 if (sc->chip & RTWN_CHIP_USB) { 3221 rtwn_write_2(sc, R92C_RL, 3222 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3223 } else { 3224 rtwn_write_2(sc, R92C_RL, 3225 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3226 } 3227 3228 /* Initialize EDCA parameters. */ 3229 rtwn_edca_init(sc); 3230 3231 /* Set data and response automatic rate fallback retry counts. */ 3232 rtwn_rate_fallback_init(sc); 3233 3234 if (sc->chip & RTWN_CHIP_USB) { 3235 rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3236 rtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3237 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3238 } else { 3239 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3240 } 3241 3242 /* Set ACK timeout. */ 3243 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3244 3245 /* Setup USB aggregation. */ 3246 if (sc->chip & RTWN_CHIP_USB) 3247 sc->sc_ops.aggr_init(sc->sc_ops.cookie); 3248 3249 /* Initialize beacon parameters. */ 3250 rtwn_write_2(sc, R92C_BCN_CTRL, 3251 (R92C_BCN_CTRL_DIS_TSF_UDT0 << 8) | R92C_BCN_CTRL_DIS_TSF_UDT0); 3252 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3253 if (!(sc->chip & RTWN_CHIP_88F)) 3254 rtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 3255 rtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 3256 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3257 3258 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 3259 /* Setup AMPDU aggregation. */ 3260 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3261 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3262 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3263 3264 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3265 } 3266 3267 if (sc->chip & RTWN_CHIP_PCI) { 3268 /* Reset H2C protection register. */ 3269 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3270 } 3271 3272 /* Load 8051 microcode. */ 3273 error = rtwn_load_firmware(sc); 3274 if (error != 0) 3275 goto fail; 3276 3277 /* Initialize MAC/BB/RF blocks. */ 3278 sc->sc_ops.mac_init(sc->sc_ops.cookie); 3279 sc->sc_ops.bb_init(sc->sc_ops.cookie); 3280 rtwn_rf_init(sc); 3281 3282 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) { 3283 rtwn_write_2(sc, R92C_CR, 3284 rtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3285 R92C_CR_MACRXEN); 3286 } 3287 3288 /* Turn CCK and OFDM blocks on. */ 3289 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3290 reg |= R92C_RFMOD_CCK_EN; 3291 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3292 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3293 reg |= R92C_RFMOD_OFDM_EN; 3294 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3295 3296 /* Clear per-station keys table. */ 3297 rtwn_cam_init(sc); 3298 3299 /* Enable decryption / encryption. */ 3300 if (sc->chip & RTWN_CHIP_USB) { 3301 rtwn_write_2(sc, R92C_SECCFG, 3302 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 3303 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXENC_ENA | 3304 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 3305 } 3306 3307 /* Enable hardware sequence numbering. */ 3308 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3309 3310 if (sc->chip & RTWN_CHIP_92E) { 3311 rtwn_write_1(sc, R92C_QUEUE_CTRL, 3312 rtwn_read_1(sc, R92C_QUEUE_CTRL) & ~0x08); 3313 } 3314 3315 /* Perform LO and IQ calibrations. */ 3316 rtwn_iq_calib(sc); 3317 /* Perform LC calibration. */ 3318 rtwn_lc_calib(sc); 3319 3320 /* Fix USB interference issue. */ 3321 if (sc->chip & RTWN_CHIP_USB) { 3322 if (!(sc->chip & 3323 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 3324 rtwn_write_1(sc, 0xfe40, 0xe0); 3325 rtwn_write_1(sc, 0xfe41, 0x8d); 3326 rtwn_write_1(sc, 0xfe42, 0x80); 3327 3328 rtwn_pa_bias_init(sc); 3329 } 3330 } 3331 3332 /* Initialize GPIO setting. */ 3333 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3334 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3335 3336 /* Fix for lower temperature. */ 3337 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) 3338 rtwn_write_1(sc, 0x15, 0xe9); 3339 3340 /* Set default channel. */ 3341 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3342 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 3343 3344 if (sc->chip & RTWN_CHIP_PCI) 3345 rtwn_enable_intr(sc); 3346 3347 error = sc->sc_ops.init(sc->sc_ops.cookie); 3348 if (error) 3349 goto fail; 3350 3351 /* We're ready to go. */ 3352 ifq_clr_oactive(&ifp->if_snd); 3353 ifp->if_flags |= IFF_RUNNING; 3354 3355 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3356 (sc->chip & RTWN_CHIP_USB)) { 3357 /* Install WEP keys. */ 3358 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3359 ic->ic_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3360 sc->sc_ops.wait_async(sc->sc_ops.cookie); 3361 } 3362 3363 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3364 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3365 else 3366 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3367 return (0); 3368 fail: 3369 rtwn_stop(ifp); 3370 return (error); 3371 } 3372 3373 void 3374 rtwn_init_task(void *arg1) 3375 { 3376 struct rtwn_softc *sc = arg1; 3377 struct ifnet *ifp = &sc->sc_ic.ic_if; 3378 int s; 3379 3380 s = splnet(); 3381 while (sc->sc_flags & RTWN_FLAG_BUSY) 3382 tsleep_nsec(&sc->sc_flags, 0, "rtwnpwr", INFSLP); 3383 sc->sc_flags |= RTWN_FLAG_BUSY; 3384 3385 rtwn_stop(ifp); 3386 3387 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3388 rtwn_init(ifp); 3389 3390 sc->sc_flags &= ~RTWN_FLAG_BUSY; 3391 wakeup(&sc->sc_flags); 3392 splx(s); 3393 } 3394 3395 void 3396 rtwn_stop(struct ifnet *ifp) 3397 { 3398 struct rtwn_softc *sc = ifp->if_softc; 3399 struct ieee80211com *ic = &sc->sc_ic; 3400 int s; 3401 3402 sc->sc_tx_timer = 0; 3403 ifp->if_timer = 0; 3404 ifp->if_flags &= ~IFF_RUNNING; 3405 ifq_clr_oactive(&ifp->if_snd); 3406 3407 s = splnet(); 3408 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3409 splx(s); 3410 3411 sc->sc_ops.wait_async(sc->sc_ops.cookie); 3412 3413 s = splnet(); 3414 3415 sc->sc_ops.cancel_scan(sc->sc_ops.cookie); 3416 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 3417 3418 task_del(systq, &sc->init_task); 3419 3420 splx(s); 3421 3422 sc->sc_ops.stop(sc->sc_ops.cookie); 3423 } 3424