1 /* $OpenBSD: rtwn.c,v 1.10 2016/07/26 13:00:28 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Realtek RTL8188CE 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/task.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #if NBPFILTER > 0 42 #include <net/bpf.h> 43 #endif 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #include <netinet/in.h> 49 #include <netinet/if_ether.h> 50 51 #include <net80211/ieee80211_var.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/ic/r92creg.h> 55 #include <dev/ic/rtwnvar.h> 56 57 #define RTWN_RIDX_COUNT 28 58 59 #ifdef RTWN_DEBUG 60 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 61 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 62 int rtwn_debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n, x) 66 #endif 67 68 void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 69 void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 70 void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 71 uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 72 uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 73 uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 74 int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 75 void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 76 uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 77 void rtwn_cam_write(struct rtwn_softc *, uint32_t, uint32_t); 78 uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 79 void rtwn_efuse_read(struct rtwn_softc *); 80 void rtwn_efuse_switch_power(struct rtwn_softc *); 81 int rtwn_read_chipid(struct rtwn_softc *, uint32_t); 82 void rtwn_read_rom(struct rtwn_softc *); 83 void rtwn_r88e_read_rom(struct rtwn_softc *); 84 int rtwn_media_change(struct ifnet *); 85 int rtwn_ra_init(struct rtwn_softc *); 86 int rtwn_r92c_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 87 int, uint32_t, int); 88 int rtwn_r88e_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 89 int, uint32_t, int); 90 void rtwn_tsf_sync_enable(struct rtwn_softc *); 91 void rtwn_set_led(struct rtwn_softc *, int, int); 92 void rtwn_updateedca(struct ieee80211com *); 93 void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 94 int8_t rtwn_r88e_get_rssi(struct rtwn_softc *, int, void *); 95 void rtwn_watchdog(struct ifnet *); 96 void rtwn_r88e_fw_reset(struct rtwn_softc *); 97 int rtwn_load_firmware(struct rtwn_softc *); 98 void rtwn_rf_init(struct rtwn_softc *); 99 void rtwn_cam_init(struct rtwn_softc *); 100 void rtwn_pa_bias_init(struct rtwn_softc *); 101 void rtwn_rxfilter_init(struct rtwn_softc *); 102 void rtwn_edca_init(struct rtwn_softc *); 103 void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 104 void rtwn_get_txpower(struct rtwn_softc *, int, 105 struct ieee80211_channel *, struct ieee80211_channel *, 106 uint16_t[]); 107 void rtwn_r88e_get_txpower(struct rtwn_softc *, int, 108 struct ieee80211_channel *, 109 struct ieee80211_channel *, uint16_t[]); 110 void rtwn_set_txpower(struct rtwn_softc *, 111 struct ieee80211_channel *, struct ieee80211_channel *); 112 void rtwn_set_chan(struct rtwn_softc *, 113 struct ieee80211_channel *, struct ieee80211_channel *); 114 int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 115 uint16_t[2]); 116 void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 117 uint16_t[2][2]); 118 int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 119 uint16_t[2][2], uint16_t[2][2], int); 120 void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 121 uint16_t[2], int); 122 void rtwn_iq_calib(struct rtwn_softc *); 123 void rtwn_lc_calib(struct rtwn_softc *); 124 void rtwn_temp_calib(struct rtwn_softc *); 125 void rtwn_enable_intr(struct rtwn_softc *); 126 void rtwn_disable_intr(struct rtwn_softc *); 127 int rtwn_init(struct ifnet *); 128 void rtwn_init_task(void *); 129 void rtwn_stop(struct ifnet *); 130 131 /* Aliases. */ 132 #define rtwn_bb_write rtwn_write_4 133 #define rtwn_bb_read rtwn_read_4 134 135 int 136 rtwn_attach(struct device *pdev, struct rtwn_softc *sc, uint32_t chip_type) 137 { 138 struct ieee80211com *ic = &sc->sc_ic; 139 struct ifnet *ifp = &ic->ic_if; 140 int i, error; 141 142 sc->sc_pdev = pdev; 143 144 task_set(&sc->init_task, rtwn_init_task, sc); 145 146 sc->chip = 0; 147 error = rtwn_read_chipid(sc, chip_type); 148 if (error != 0) { 149 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 150 return (ENXIO); 151 } 152 153 /* Determine number of Tx/Rx chains. */ 154 if (sc->chip & RTWN_CHIP_92C) { 155 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 156 sc->nrxchains = 2; 157 } else if (sc->chip & RTWN_CHIP_88C) { 158 sc->ntxchains = 1; 159 sc->nrxchains = 1; 160 } 161 162 if (sc->chip & RTWN_CHIP_88E) 163 rtwn_r88e_read_rom(sc); 164 else 165 rtwn_read_rom(sc); 166 167 if (sc->chip & RTWN_CHIP_PCI) { 168 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 169 sc->sc_pdev->dv_xname, 170 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : 171 (sc->chip & RTWN_CHIP_88E) ? "8188EE" : "8188CE", 172 sc->ntxchains, sc->nrxchains, 173 ether_sprintf(ic->ic_myaddr)); 174 } else if (sc->chip & RTWN_CHIP_USB) { 175 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 176 sc->sc_pdev->dv_xname, 177 (sc->chip & RTWN_CHIP_92C) ? "8192CU" : 178 (sc->chip & RTWN_CHIP_88E) ? "8188EU" : 179 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 180 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? 181 "8188CE-VAU" : "8188CUS", 182 sc->ntxchains, sc->nrxchains, 183 ether_sprintf(ic->ic_myaddr)); 184 } else { 185 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 186 return (ENXIO); 187 } 188 189 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 190 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 191 ic->ic_state = IEEE80211_S_INIT; 192 193 /* Set device capabilities. */ 194 ic->ic_caps = 195 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 196 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 197 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 198 IEEE80211_C_WEP | /* WEP. */ 199 IEEE80211_C_RSN; /* WPA/RSN. */ 200 201 /* Set HT capabilities. */ 202 ic->ic_htcaps = 203 IEEE80211_HTCAP_CBW20_40 | 204 IEEE80211_HTCAP_DSSSCCK40; 205 /* Set supported HT rates. */ 206 for (i = 0; i < sc->nrxchains; i++) 207 ic->ic_sup_mcs[i] = 0xff; 208 209 /* Set supported .11b and .11g rates. */ 210 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 211 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 212 213 /* Set supported .11b and .11g channels (1 through 14). */ 214 for (i = 1; i <= 14; i++) { 215 ic->ic_channels[i].ic_freq = 216 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 217 ic->ic_channels[i].ic_flags = 218 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 219 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 220 } 221 222 #ifdef notyet 223 /* 224 * The number of STAs that we can support is limited by the number 225 * of CAM entries used for hardware crypto. 226 */ 227 ic->ic_max_nnodes = R92C_CAM_ENTRY_COUNT - 4; 228 if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE) 229 ic->ic_max_nnodes = IEEE80211_CACHE_SIZE; 230 #endif 231 232 ifp->if_softc = sc; 233 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 234 ifp->if_ioctl = rtwn_ioctl; 235 ifp->if_start = rtwn_start; 236 ifp->if_watchdog = rtwn_watchdog; 237 memcpy(ifp->if_xname, sc->sc_pdev->dv_xname, IFNAMSIZ); 238 239 if_attach(ifp); 240 ieee80211_ifattach(ifp); 241 ic->ic_updateedca = rtwn_updateedca; 242 #ifdef notyet 243 ic->ic_set_key = rtwn_set_key; 244 ic->ic_delete_key = rtwn_delete_key; 245 #endif 246 /* Override state transition machine. */ 247 sc->sc_newstate = ic->ic_newstate; 248 ic->ic_newstate = rtwn_newstate; 249 ieee80211_media_init(ifp, rtwn_media_change, ieee80211_media_status); 250 251 return (0); 252 } 253 254 int 255 rtwn_detach(struct rtwn_softc *sc, int flags) 256 { 257 struct ifnet *ifp = &sc->sc_ic.ic_if; 258 int s; 259 260 s = splnet(); 261 262 task_del(systq, &sc->init_task); 263 264 if (ifp->if_softc != NULL) { 265 ieee80211_ifdetach(ifp); 266 if_detach(ifp); 267 } 268 269 splx(s); 270 271 return (0); 272 } 273 274 int 275 rtwn_activate(struct rtwn_softc *sc, int act) 276 { 277 struct ifnet *ifp = &sc->sc_ic.ic_if; 278 279 switch (act) { 280 case DVACT_QUIESCE: /* rtwn_stop() may sleep */ 281 if (ifp->if_flags & IFF_RUNNING) 282 rtwn_stop(ifp); 283 break; 284 case DVACT_WAKEUP: 285 rtwn_init_task(sc); 286 break; 287 } 288 return (0); 289 } 290 291 void 292 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 293 { 294 sc->sc_ops.write_1(sc->sc_ops.cookie, addr, val); 295 } 296 297 void 298 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 299 { 300 sc->sc_ops.write_2(sc->sc_ops.cookie, addr, val); 301 } 302 303 void 304 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 305 { 306 sc->sc_ops.write_4(sc->sc_ops.cookie, addr, val); 307 } 308 309 uint8_t 310 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 311 { 312 return sc->sc_ops.read_1(sc->sc_ops.cookie, addr); 313 } 314 315 uint16_t 316 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 317 { 318 return sc->sc_ops.read_2(sc->sc_ops.cookie, addr); 319 } 320 321 uint32_t 322 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 323 { 324 return sc->sc_ops.read_4(sc->sc_ops.cookie, addr); 325 } 326 327 int 328 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 329 { 330 struct r92c_fw_cmd cmd; 331 int ntries; 332 333 /* Wait for current FW box to be empty. */ 334 for (ntries = 0; ntries < 100; ntries++) { 335 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 336 break; 337 DELAY(1); 338 } 339 if (ntries == 100) { 340 printf("%s: could not send firmware command %d\n", 341 sc->sc_pdev->dv_xname, id); 342 return (ETIMEDOUT); 343 } 344 memset(&cmd, 0, sizeof(cmd)); 345 cmd.id = id; 346 if (len > 3) 347 cmd.id |= R92C_CMD_FLAG_EXT; 348 KASSERT(len <= sizeof(cmd.msg)); 349 memcpy(cmd.msg, buf, len); 350 351 /* Write the first word last since that will trigger the FW. */ 352 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), *((uint8_t *)&cmd + 4)); 353 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 354 355 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 356 357 if (sc->chip & RTWN_CHIP_PCI) { 358 /* Give firmware some time for processing. */ 359 DELAY(2000); 360 } 361 362 return (0); 363 } 364 365 void 366 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 367 { 368 uint32_t param_addr; 369 370 if (sc->chip & RTWN_CHIP_88E) 371 param_addr = SM(R88E_LSSI_PARAM_ADDR, addr); 372 else 373 param_addr = SM(R92C_LSSI_PARAM_ADDR, addr); 374 375 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 376 param_addr | SM(R92C_LSSI_PARAM_DATA, val)); 377 } 378 379 uint32_t 380 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 381 { 382 uint32_t reg[R92C_MAX_CHAINS], val; 383 384 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 385 if (chain != 0) 386 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 387 388 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 389 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 390 DELAY(1000); 391 392 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 393 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 394 R92C_HSSI_PARAM2_READ_EDGE); 395 DELAY(1000); 396 397 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 398 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 399 DELAY(1000); 400 401 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 402 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 403 else 404 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 405 return (MS(val, R92C_LSSI_READBACK_DATA)); 406 } 407 408 void 409 rtwn_cam_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 410 { 411 rtwn_write_4(sc, R92C_CAMWRITE, data); 412 rtwn_write_4(sc, R92C_CAMCMD, 413 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 414 SM(R92C_CAMCMD_ADDR, addr)); 415 } 416 417 uint8_t 418 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 419 { 420 uint32_t reg; 421 int ntries; 422 423 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 424 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 425 reg &= ~R92C_EFUSE_CTRL_VALID; 426 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 427 /* Wait for read operation to complete. */ 428 for (ntries = 0; ntries < 100; ntries++) { 429 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 430 if (reg & R92C_EFUSE_CTRL_VALID) 431 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 432 DELAY(5); 433 } 434 printf("%s: could not read efuse byte at address 0x%x\n", 435 sc->sc_pdev->dv_xname, addr); 436 return (0xff); 437 } 438 439 void 440 rtwn_efuse_read(struct rtwn_softc *sc) 441 { 442 uint8_t *rom = (uint8_t *)&sc->rom; 443 uint16_t addr = 0; 444 uint32_t reg; 445 uint8_t off, msk; 446 int i; 447 448 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 449 rtwn_efuse_switch_power(sc); 450 451 memset(&sc->rom, 0xff, sizeof(sc->rom)); 452 while (addr < 512) { 453 reg = rtwn_efuse_read_1(sc, addr); 454 if (reg == 0xff) 455 break; 456 addr++; 457 off = reg >> 4; 458 msk = reg & 0xf; 459 for (i = 0; i < 4; i++) { 460 if (msk & (1 << i)) 461 continue; 462 rom[off * 8 + i * 2 + 0] = 463 rtwn_efuse_read_1(sc, addr); 464 addr++; 465 rom[off * 8 + i * 2 + 1] = 466 rtwn_efuse_read_1(sc, addr); 467 addr++; 468 } 469 } 470 #ifdef RTWN_DEBUG 471 if (rtwn_debug >= 2) { 472 /* Dump ROM content. */ 473 printf("\n"); 474 for (i = 0; i < sizeof(sc->rom); i++) 475 printf("%02x:", rom[i]); 476 printf("\n"); 477 } 478 #endif 479 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 480 } 481 482 void 483 rtwn_efuse_switch_power(struct rtwn_softc *sc) 484 { 485 uint16_t reg; 486 487 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 488 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 489 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 490 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 491 } 492 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 493 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 494 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 495 reg | R92C_SYS_FUNC_EN_ELDR); 496 } 497 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 498 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 499 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 500 rtwn_write_2(sc, R92C_SYS_CLKR, 501 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 502 } 503 } 504 505 int 506 rtwn_read_chipid(struct rtwn_softc *sc, uint32_t chip_type) 507 { 508 uint32_t reg; 509 510 if (chip_type & RTWN_CHIP_88E) { 511 sc->chip = chip_type; 512 return (0); 513 } 514 515 reg = rtwn_read_4(sc, R92C_SYS_CFG); 516 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 517 /* Unsupported test chip. */ 518 return (EIO); 519 520 if ((chip_type & (RTWN_CHIP_92C | RTWN_CHIP_88C)) != 0) { 521 if (reg & R92C_SYS_CFG_TYPE_92C) { 522 sc->chip = RTWN_CHIP_92C; 523 /* Check if it is a castrated 8192C. */ 524 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 525 R92C_HPON_FSM_CHIP_BONDING_ID) == 526 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 527 sc->chip |= RTWN_CHIP_92C_1T2R; 528 } else 529 sc->chip = RTWN_CHIP_88C; 530 531 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 532 sc->chip |= RTWN_CHIP_UMC; 533 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 534 sc->chip |= RTWN_CHIP_UMC_A_CUT; 535 } 536 537 sc->chip |= (chip_type & (RTWN_CHIP_USB | RTWN_CHIP_PCI)); 538 return (0); 539 } 540 541 return (ENXIO); /* unsupported chip */ 542 } 543 544 void 545 rtwn_read_rom(struct rtwn_softc *sc) 546 { 547 struct ieee80211com *ic = &sc->sc_ic; 548 struct r92c_rom *rom = &sc->rom; 549 550 /* Read full ROM image. */ 551 rtwn_efuse_read(sc); 552 553 /* XXX Weird but this is what the vendor driver does. */ 554 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 555 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 556 557 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 558 DPRINTF(("board type=%d\n", sc->board_type)); 559 560 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 561 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 562 563 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 564 } 565 566 void 567 rtwn_r88e_read_rom(struct rtwn_softc *sc) 568 { 569 struct ieee80211com *ic = &sc->sc_ic; 570 uint8_t *rom = sc->r88e_rom; 571 uint16_t addr = 0; 572 uint32_t reg; 573 uint8_t off, msk, tmp; 574 int i; 575 576 off = 0; 577 578 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 579 rtwn_efuse_switch_power(sc); 580 581 /* Read full ROM image. */ 582 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 583 while (addr < 512) { 584 reg = rtwn_efuse_read_1(sc, addr); 585 if (reg == 0xff) 586 break; 587 addr++; 588 if ((reg & 0x1f) == 0x0f) { 589 tmp = (reg & 0xe0) >> 5; 590 reg = rtwn_efuse_read_1(sc, addr); 591 if ((reg & 0x0f) != 0x0f) 592 off = ((reg & 0xf0) >> 1) | tmp; 593 addr++; 594 } else 595 off = reg >> 4; 596 msk = reg & 0xf; 597 for (i = 0; i < 4; i++) { 598 if (msk & (1 << i)) 599 continue; 600 rom[off * 8 + i * 2 + 0] = 601 rtwn_efuse_read_1(sc, addr); 602 addr++; 603 rom[off * 8 + i * 2 + 1] = 604 rtwn_efuse_read_1(sc, addr); 605 addr++; 606 } 607 } 608 609 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 610 611 addr = 0x10; 612 for (i = 0; i < 6; i++) 613 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 614 for (i = 0; i < 5; i++) 615 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 616 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 617 if (sc->bw20_tx_pwr_diff & 0x08) 618 sc->bw20_tx_pwr_diff |= 0xf0; 619 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 620 if (sc->ofdm_tx_pwr_diff & 0x08) 621 sc->ofdm_tx_pwr_diff |= 0xf0; 622 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 623 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 624 } 625 626 int 627 rtwn_media_change(struct ifnet *ifp) 628 { 629 int error; 630 631 error = ieee80211_media_change(ifp); 632 if (error != ENETRESET) 633 return (error); 634 635 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 636 (IFF_UP | IFF_RUNNING)) { 637 rtwn_stop(ifp); 638 rtwn_init(ifp); 639 } 640 return (0); 641 } 642 643 /* 644 * Initialize rate adaptation in firmware. 645 */ 646 int 647 rtwn_ra_init(struct rtwn_softc *sc) 648 { 649 static const uint8_t map[] = 650 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 651 struct ieee80211com *ic = &sc->sc_ic; 652 struct ieee80211_node *ni = ic->ic_bss; 653 struct ieee80211_rateset *rs = &ni->ni_rates; 654 uint32_t rates, basicrates; 655 uint8_t mode; 656 int maxrate, maxbasicrate, error, i, j; 657 658 /* Get normal and basic rates mask. */ 659 rates = basicrates = 0; 660 maxrate = maxbasicrate = 0; 661 for (i = 0; i < rs->rs_nrates; i++) { 662 /* Convert 802.11 rate to HW rate index. */ 663 for (j = 0; j < nitems(map); j++) 664 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 665 break; 666 if (j == nitems(map)) /* Unknown rate, skip. */ 667 continue; 668 rates |= 1 << j; 669 if (j > maxrate) 670 maxrate = j; 671 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 672 basicrates |= 1 << j; 673 if (j > maxbasicrate) 674 maxbasicrate = j; 675 } 676 } 677 if (ic->ic_curmode == IEEE80211_MODE_11B) 678 mode = R92C_RAID_11B; 679 else 680 mode = R92C_RAID_11BG; 681 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 682 mode, rates, basicrates)); 683 684 if (sc->chip & RTWN_CHIP_PCI) { 685 /* Configure Automatic Rate Fallback Register. */ 686 if (ic->ic_curmode == IEEE80211_MODE_11B) { 687 if (rates & 0x0c) 688 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x0d); 689 else 690 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x0f); 691 } else 692 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x0ff5); 693 } 694 695 if (sc->chip & RTWN_CHIP_88E) 696 error = rtwn_r88e_ra_init(sc, mode, rates, maxrate, 697 basicrates, maxbasicrate); 698 else 699 error = rtwn_r92c_ra_init(sc, mode, rates, maxrate, 700 basicrates, maxbasicrate); 701 702 /* Indicate highest supported rate. */ 703 ni->ni_txrate = rs->rs_nrates - 1; 704 return (error); 705 } 706 707 int rtwn_r92c_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 708 int maxrate, uint32_t basicrates, int maxbasicrate) 709 { 710 struct r92c_fw_cmd_macid_cfg cmd; 711 int error; 712 713 /* Set rates mask for group addressed frames. */ 714 cmd.macid = R92C_MACID_BC | R92C_MACID_VALID; 715 cmd.mask = htole32(mode << 28 | basicrates); 716 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 717 if (error != 0) { 718 printf("%s: could not add broadcast station\n", 719 sc->sc_pdev->dv_xname); 720 return (error); 721 } 722 /* Set initial MRR rate. */ 723 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 724 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BC), 725 maxbasicrate); 726 727 /* Set rates mask for unicast frames. */ 728 cmd.macid = R92C_MACID_BSS | R92C_MACID_VALID; 729 cmd.mask = htole32(mode << 28 | rates); 730 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 731 if (error != 0) { 732 printf("%s: could not add BSS station\n", 733 sc->sc_pdev->dv_xname); 734 return (error); 735 } 736 /* Set initial MRR rate. */ 737 DPRINTF(("maxrate=%d\n", maxrate)); 738 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 739 maxrate); 740 741 return (0); 742 } 743 744 int 745 rtwn_r88e_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 746 int maxrate, uint32_t basicrates, int maxbasicrate) 747 { 748 u_int32_t reg; 749 750 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, maxbasicrate); 751 752 reg = rtwn_read_4(sc, R92C_RRSR); 753 reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates); 754 rtwn_write_4(sc, R92C_RRSR, reg); 755 756 /* 757 * Workaround for performance problems with firmware rate adaptation: 758 * If the AP only supports 11b rates, disable mixed B/G mode. 759 */ 760 if (mode != R92C_RAID_11B && maxrate <= 3 /* 11M */) 761 sc->sc_flags |= RTWN_FLAG_FORCE_RAID_11B; 762 763 return (0); 764 } 765 766 void 767 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 768 { 769 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 770 uint64_t tsf; 771 772 /* Enable TSF synchronization. */ 773 rtwn_write_1(sc, R92C_BCN_CTRL, 774 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 775 776 rtwn_write_1(sc, R92C_BCN_CTRL, 777 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 778 779 /* Set initial TSF. */ 780 memcpy(&tsf, ni->ni_tstamp, 8); 781 tsf = letoh64(tsf); 782 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 783 tsf -= IEEE80211_DUR_TU; 784 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 785 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 786 787 rtwn_write_1(sc, R92C_BCN_CTRL, 788 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 789 } 790 791 void 792 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 793 { 794 uint8_t reg; 795 796 if (led != RTWN_LED_LINK) 797 return; /* not supported */ 798 799 if (sc->chip & RTWN_CHIP_PCI) { 800 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 801 if (!on) 802 reg |= R92C_LEDCFG2_DIS; 803 else 804 reg |= R92C_LEDCFG2_EN; 805 rtwn_write_1(sc, R92C_LEDCFG2, reg); 806 } else if (sc->chip & RTWN_CHIP_USB) { 807 if (sc->chip & RTWN_CHIP_88E) { 808 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 809 rtwn_write_1(sc, R92C_LEDCFG2, reg | R92C_LEDCFG2_EN); 810 if (!on) { 811 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 812 rtwn_write_1(sc, R92C_LEDCFG2, 813 reg | R92C_LEDCFG0_DIS); 814 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 815 rtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 816 0xfe); 817 } 818 } else { 819 reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 820 if (!on) 821 reg |= R92C_LEDCFG0_DIS; 822 rtwn_write_1(sc, R92C_LEDCFG0, reg); 823 } 824 } 825 sc->ledlink = on; /* Save LED state. */ 826 } 827 828 void 829 rtwn_calib(struct rtwn_softc *sc) 830 { 831 struct r92c_fw_cmd_rssi cmd; 832 833 if (sc->avg_pwdb != -1) { 834 /* Indicate Rx signal strength to FW for rate adaptation. */ 835 memset(&cmd, 0, sizeof(cmd)); 836 cmd.macid = 0; /* BSS. */ 837 cmd.pwdb = sc->avg_pwdb; 838 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 839 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 840 } 841 842 /* Do temperature compensation. */ 843 rtwn_temp_calib(sc); 844 845 sc->sc_ops.next_calib(sc->sc_ops.cookie); 846 } 847 848 void 849 rtwn_next_scan(struct rtwn_softc *sc) 850 { 851 struct ieee80211com *ic = &sc->sc_ic; 852 int s; 853 854 s = splnet(); 855 if (ic->ic_state == IEEE80211_S_SCAN) 856 ieee80211_next_scan(&ic->ic_if); 857 splx(s); 858 } 859 860 int 861 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 862 { 863 struct rtwn_softc *sc = ic->ic_softc; 864 struct ieee80211_node *ni; 865 enum ieee80211_state ostate; 866 uint32_t reg; 867 int s, error; 868 869 s = splnet(); 870 ostate = ic->ic_state; 871 872 if (nstate != ostate) 873 DPRINTF(("newstate %s -> %s\n", 874 ieee80211_state_name[ostate], 875 ieee80211_state_name[nstate])); 876 877 if (ostate == IEEE80211_S_RUN) { 878 /* Stop calibration. */ 879 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 880 881 /* Turn link LED off. */ 882 rtwn_set_led(sc, RTWN_LED_LINK, 0); 883 884 /* Set media status to 'No Link'. */ 885 reg = rtwn_read_4(sc, R92C_CR); 886 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 887 rtwn_write_4(sc, R92C_CR, reg); 888 889 /* Stop Rx of data frames. */ 890 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 891 892 /* Rest TSF. */ 893 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 894 895 /* Disable TSF synchronization. */ 896 rtwn_write_1(sc, R92C_BCN_CTRL, 897 rtwn_read_1(sc, R92C_BCN_CTRL) | 898 R92C_BCN_CTRL_DIS_TSF_UDT0); 899 900 /* Reset EDCA parameters. */ 901 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 902 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 903 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 904 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 905 906 /* Disable 11b-only AP workaround (see rtwn_r88e_ra_init). */ 907 sc->sc_flags &= ~RTWN_FLAG_FORCE_RAID_11B; 908 } 909 switch (nstate) { 910 case IEEE80211_S_INIT: 911 /* Turn link LED off. */ 912 rtwn_set_led(sc, RTWN_LED_LINK, 0); 913 break; 914 case IEEE80211_S_SCAN: 915 if (ostate != IEEE80211_S_SCAN) { 916 /* Allow Rx from any BSSID. */ 917 rtwn_write_4(sc, R92C_RCR, 918 rtwn_read_4(sc, R92C_RCR) & 919 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 920 921 /* Set gain for scanning. */ 922 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 923 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 924 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 925 926 if (!(sc->chip & RTWN_CHIP_88E)) { 927 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 928 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 929 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 930 } 931 } 932 933 /* Make link LED blink during scan. */ 934 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 935 936 /* Pause AC Tx queues. */ 937 rtwn_write_1(sc, R92C_TXPAUSE, 938 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 939 940 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 941 sc->sc_ops.next_scan(sc->sc_ops.cookie); 942 break; 943 944 case IEEE80211_S_AUTH: 945 /* Set initial gain under link. */ 946 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 947 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 948 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 949 950 if (!(sc->chip & RTWN_CHIP_88E)) { 951 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 952 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 953 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 954 } 955 956 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 957 break; 958 case IEEE80211_S_ASSOC: 959 break; 960 case IEEE80211_S_RUN: 961 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 962 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 963 964 /* Enable Rx of data frames. */ 965 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 966 967 /* Turn link LED on. */ 968 rtwn_set_led(sc, RTWN_LED_LINK, 1); 969 break; 970 } 971 ni = ic->ic_bss; 972 973 /* Set media status to 'Associated'. */ 974 reg = rtwn_read_4(sc, R92C_CR); 975 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 976 rtwn_write_4(sc, R92C_CR, reg); 977 978 /* Set BSSID. */ 979 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 980 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 981 982 if (ic->ic_curmode == IEEE80211_MODE_11B) 983 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 984 else /* 802.11b/g */ 985 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 986 987 /* Enable Rx of data frames. */ 988 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 989 990 /* Flush all AC queues. */ 991 rtwn_write_1(sc, R92C_TXPAUSE, 0); 992 993 /* Set beacon interval. */ 994 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 995 996 /* Allow Rx from our BSSID only. */ 997 rtwn_write_4(sc, R92C_RCR, 998 rtwn_read_4(sc, R92C_RCR) | 999 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1000 1001 /* Enable TSF synchronization. */ 1002 rtwn_tsf_sync_enable(sc); 1003 1004 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1005 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1006 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1007 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1008 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1009 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1010 1011 /* Intialize rate adaptation. */ 1012 rtwn_ra_init(sc); 1013 /* Turn link LED on. */ 1014 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1015 1016 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1017 /* Reset temperature calibration state machine. */ 1018 sc->thcal_state = 0; 1019 sc->thcal_lctemp = 0; 1020 /* Start periodic calibration. */ 1021 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1022 break; 1023 } 1024 1025 error = sc->sc_newstate(ic, nstate, arg); 1026 splx(s); 1027 1028 return (error); 1029 } 1030 1031 void 1032 rtwn_updateedca(struct ieee80211com *ic) 1033 { 1034 struct rtwn_softc *sc = ic->ic_softc; 1035 const uint16_t aci2reg[EDCA_NUM_AC] = { 1036 R92C_EDCA_BE_PARAM, 1037 R92C_EDCA_BK_PARAM, 1038 R92C_EDCA_VI_PARAM, 1039 R92C_EDCA_VO_PARAM 1040 }; 1041 struct ieee80211_edca_ac_params *ac; 1042 int s, aci, aifs, slottime; 1043 1044 s = splnet(); 1045 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1046 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1047 ac = &ic->ic_edca_ac[aci]; 1048 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1049 aifs = ac->ac_aifsn * slottime + 10; 1050 rtwn_write_4(sc, aci2reg[aci], 1051 SM(R92C_EDCA_PARAM_TXOP, ac->ac_txoplimit) | 1052 SM(R92C_EDCA_PARAM_ECWMIN, ac->ac_ecwmin) | 1053 SM(R92C_EDCA_PARAM_ECWMAX, ac->ac_ecwmax) | 1054 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1055 } 1056 splx(s); 1057 } 1058 1059 int 1060 rtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1061 struct ieee80211_key *k) 1062 { 1063 struct rtwn_softc *sc = ic->ic_softc; 1064 static const uint8_t etherzeroaddr[6] = { 0 }; 1065 const uint8_t *macaddr; 1066 uint8_t keybuf[16], algo; 1067 int i, entry; 1068 1069 /* Defer setting of WEP keys until interface is brought up. */ 1070 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1071 (IFF_UP | IFF_RUNNING)) 1072 return (0); 1073 1074 /* Map net80211 cipher to HW crypto algorithm. */ 1075 switch (k->k_cipher) { 1076 case IEEE80211_CIPHER_WEP40: 1077 algo = R92C_CAM_ALGO_WEP40; 1078 break; 1079 case IEEE80211_CIPHER_WEP104: 1080 algo = R92C_CAM_ALGO_WEP104; 1081 break; 1082 case IEEE80211_CIPHER_TKIP: 1083 algo = R92C_CAM_ALGO_TKIP; 1084 break; 1085 case IEEE80211_CIPHER_CCMP: 1086 algo = R92C_CAM_ALGO_AES; 1087 break; 1088 default: 1089 /* Fallback to software crypto for other ciphers. */ 1090 return (ieee80211_set_key(ic, ni, k)); 1091 } 1092 if (k->k_flags & IEEE80211_KEY_GROUP) { 1093 macaddr = etherzeroaddr; 1094 entry = k->k_id; 1095 } else { 1096 macaddr = ic->ic_bss->ni_macaddr; 1097 entry = 4; 1098 } 1099 /* Write key. */ 1100 memset(keybuf, 0, sizeof(keybuf)); 1101 memcpy(keybuf, k->k_key, MIN(k->k_len, sizeof(keybuf))); 1102 for (i = 0; i < 4; i++) { 1103 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 1104 LE_READ_4(&keybuf[i * 4])); 1105 } 1106 /* Write CTL0 last since that will validate the CAM entry. */ 1107 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 1108 LE_READ_4(&macaddr[2])); 1109 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 1110 SM(R92C_CAM_ALGO, algo) | 1111 SM(R92C_CAM_KEYID, k->k_id) | 1112 SM(R92C_CAM_MACLO, LE_READ_2(&macaddr[0])) | 1113 R92C_CAM_VALID); 1114 1115 return (0); 1116 } 1117 1118 void 1119 rtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1120 struct ieee80211_key *k) 1121 { 1122 struct rtwn_softc *sc = ic->ic_softc; 1123 int i, entry; 1124 1125 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1126 ic->ic_state != IEEE80211_S_RUN) 1127 return; /* Nothing to do. */ 1128 1129 if (k->k_flags & IEEE80211_KEY_GROUP) 1130 entry = k->k_id; 1131 else 1132 entry = 4; 1133 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 0); 1134 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 0); 1135 /* Clear key. */ 1136 for (i = 0; i < 4; i++) 1137 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 0); 1138 } 1139 1140 void 1141 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1142 { 1143 int pwdb; 1144 1145 /* Convert antenna signal to percentage. */ 1146 if (rssi <= -100 || rssi >= 20) 1147 pwdb = 0; 1148 else if (rssi >= 0) 1149 pwdb = 100; 1150 else 1151 pwdb = 100 + rssi; 1152 if (rate <= 3) { 1153 /* CCK gain is smaller than OFDM/MCS gain. */ 1154 pwdb += 6; 1155 if (pwdb > 100) 1156 pwdb = 100; 1157 if (pwdb <= 14) 1158 pwdb -= 4; 1159 else if (pwdb <= 26) 1160 pwdb -= 8; 1161 else if (pwdb <= 34) 1162 pwdb -= 6; 1163 else if (pwdb <= 42) 1164 pwdb -= 2; 1165 } 1166 if (sc->avg_pwdb == -1) /* Init. */ 1167 sc->avg_pwdb = pwdb; 1168 else if (sc->avg_pwdb < pwdb) 1169 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1170 else 1171 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1172 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1173 } 1174 1175 int8_t 1176 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1177 { 1178 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1179 struct r92c_rx_phystat *phy; 1180 struct r92c_rx_cck *cck; 1181 uint8_t rpt; 1182 int8_t rssi; 1183 1184 if (sc->chip & RTWN_CHIP_88E) 1185 return rtwn_r88e_get_rssi(sc, rate, physt); 1186 1187 if (rate <= 3) { 1188 cck = (struct r92c_rx_cck *)physt; 1189 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1190 rpt = (cck->agc_rpt >> 5) & 0x3; 1191 rssi = (cck->agc_rpt & 0x1f) << 1; 1192 } else { 1193 rpt = (cck->agc_rpt >> 6) & 0x3; 1194 rssi = cck->agc_rpt & 0x3e; 1195 } 1196 rssi = cckoff[rpt] - rssi; 1197 } else { /* OFDM/HT. */ 1198 phy = (struct r92c_rx_phystat *)physt; 1199 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 110; 1200 } 1201 return (rssi); 1202 } 1203 1204 int8_t 1205 rtwn_r88e_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1206 { 1207 struct r92c_rx_phystat *phy; 1208 struct r88e_rx_cck *cck; 1209 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1210 int8_t rssi; 1211 1212 rssi = 0; 1213 if (rate <= 3) { 1214 cck = (struct r88e_rx_cck *)physt; 1215 cck_agc_rpt = cck->agc_rpt; 1216 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1217 vga_idx = cck_agc_rpt & 0x1f; 1218 switch (lna_idx) { 1219 case 7: 1220 if (vga_idx <= 27) 1221 rssi = -100 + 2* (27 - vga_idx); 1222 else 1223 rssi = -100; 1224 break; 1225 case 6: 1226 rssi = -48 + 2 * (2 - vga_idx); 1227 break; 1228 case 5: 1229 rssi = -42 + 2 * (7 - vga_idx); 1230 break; 1231 case 4: 1232 rssi = -36 + 2 * (7 - vga_idx); 1233 break; 1234 case 3: 1235 rssi = -24 + 2 * (7 - vga_idx); 1236 break; 1237 case 2: 1238 rssi = -12 + 2 * (5 - vga_idx); 1239 break; 1240 case 1: 1241 rssi = 8 - (2 * vga_idx); 1242 break; 1243 case 0: 1244 rssi = 14 - (2 * vga_idx); 1245 break; 1246 } 1247 rssi += 6; 1248 } else { /* OFDM/HT. */ 1249 phy = (struct r92c_rx_phystat *)physt; 1250 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1251 } 1252 return (rssi); 1253 } 1254 1255 void 1256 rtwn_start(struct ifnet *ifp) 1257 { 1258 struct rtwn_softc *sc = ifp->if_softc; 1259 struct ieee80211com *ic = &sc->sc_ic; 1260 struct ieee80211_node *ni; 1261 struct mbuf *m; 1262 1263 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1264 return; 1265 1266 for (;;) { 1267 if (sc->sc_ops.is_oactive(sc->sc_ops.cookie)) { 1268 ifq_set_oactive(&ifp->if_snd); 1269 break; 1270 } 1271 /* Send pending management frames first. */ 1272 m = mq_dequeue(&ic->ic_mgtq); 1273 if (m != NULL) { 1274 ni = m->m_pkthdr.ph_cookie; 1275 goto sendit; 1276 } 1277 if (ic->ic_state != IEEE80211_S_RUN) 1278 break; 1279 1280 /* Encapsulate and send data frames. */ 1281 IFQ_DEQUEUE(&ifp->if_snd, m); 1282 if (m == NULL) 1283 break; 1284 #if NBPFILTER > 0 1285 if (ifp->if_bpf != NULL) 1286 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1287 #endif 1288 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1289 continue; 1290 sendit: 1291 #if NBPFILTER > 0 1292 if (ic->ic_rawbpf != NULL) 1293 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1294 #endif 1295 if (sc->sc_ops.tx(sc->sc_ops.cookie, m, ni) != 0) { 1296 ieee80211_release_node(ic, ni); 1297 ifp->if_oerrors++; 1298 continue; 1299 } 1300 1301 sc->sc_tx_timer = 5; 1302 ifp->if_timer = 1; 1303 } 1304 } 1305 1306 void 1307 rtwn_watchdog(struct ifnet *ifp) 1308 { 1309 struct rtwn_softc *sc = ifp->if_softc; 1310 1311 ifp->if_timer = 0; 1312 1313 if (sc->sc_tx_timer > 0) { 1314 if (--sc->sc_tx_timer == 0) { 1315 printf("%s: device timeout\n", sc->sc_pdev->dv_xname); 1316 task_add(systq, &sc->init_task); 1317 ifp->if_oerrors++; 1318 return; 1319 } 1320 ifp->if_timer = 1; 1321 } 1322 ieee80211_watchdog(ifp); 1323 } 1324 1325 int 1326 rtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1327 { 1328 struct rtwn_softc *sc = ifp->if_softc; 1329 struct ieee80211com *ic = &sc->sc_ic; 1330 struct ifreq *ifr; 1331 int s, error = 0; 1332 1333 s = splnet(); 1334 /* 1335 * Prevent processes from entering this function while another 1336 * process is tsleep'ing in it. 1337 */ 1338 while ((sc->sc_flags & RTWN_FLAG_BUSY) && error == 0) 1339 error = tsleep(&sc->sc_flags, PCATCH, "rtwnioc", 0); 1340 if (error != 0) { 1341 splx(s); 1342 return error; 1343 } 1344 sc->sc_flags |= RTWN_FLAG_BUSY; 1345 1346 switch (cmd) { 1347 case SIOCSIFADDR: 1348 ifp->if_flags |= IFF_UP; 1349 /* FALLTHROUGH */ 1350 case SIOCSIFFLAGS: 1351 if (ifp->if_flags & IFF_UP) { 1352 if (!(ifp->if_flags & IFF_RUNNING)) 1353 rtwn_init(ifp); 1354 } else { 1355 if (ifp->if_flags & IFF_RUNNING) 1356 rtwn_stop(ifp); 1357 } 1358 break; 1359 case SIOCADDMULTI: 1360 case SIOCDELMULTI: 1361 ifr = (struct ifreq *)data; 1362 error = (cmd == SIOCADDMULTI) ? 1363 ether_addmulti(ifr, &ic->ic_ac) : 1364 ether_delmulti(ifr, &ic->ic_ac); 1365 if (error == ENETRESET) 1366 error = 0; 1367 break; 1368 case SIOCS80211CHANNEL: 1369 error = ieee80211_ioctl(ifp, cmd, data); 1370 if (error == ENETRESET && 1371 ic->ic_opmode == IEEE80211_M_MONITOR) { 1372 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1373 (IFF_UP | IFF_RUNNING)) 1374 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1375 error = 0; 1376 } 1377 break; 1378 default: 1379 error = ieee80211_ioctl(ifp, cmd, data); 1380 } 1381 1382 if (error == ENETRESET) { 1383 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1384 (IFF_UP | IFF_RUNNING)) { 1385 rtwn_stop(ifp); 1386 rtwn_init(ifp); 1387 } 1388 error = 0; 1389 } 1390 sc->sc_flags &= ~RTWN_FLAG_BUSY; 1391 wakeup(&sc->sc_flags); 1392 splx(s); 1393 1394 return (error); 1395 } 1396 1397 void 1398 rtwn_fw_reset(struct rtwn_softc *sc) 1399 { 1400 uint16_t reg; 1401 int ntries; 1402 1403 /* Tell 8051 to reset itself. */ 1404 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 1405 1406 /* Wait until 8051 resets by itself. */ 1407 for (ntries = 0; ntries < 100; ntries++) { 1408 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1409 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 1410 goto sleep; 1411 DELAY(50); 1412 } 1413 /* Force 8051 reset. */ 1414 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1415 sleep: 1416 if (sc->chip & RTWN_CHIP_PCI) { 1417 /* 1418 * We must sleep for one second to let the firmware settle. 1419 * Accessing registers too early will hang the whole system. 1420 */ 1421 tsleep(®, 0, "rtwnrst", hz); 1422 } 1423 } 1424 1425 void 1426 rtwn_r88e_fw_reset(struct rtwn_softc *sc) 1427 { 1428 uint16_t reg; 1429 1430 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1431 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1432 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 1433 } 1434 1435 int 1436 rtwn_load_firmware(struct rtwn_softc *sc) 1437 { 1438 const struct r92c_fw_hdr *hdr; 1439 u_char *fw, *ptr; 1440 size_t len; 1441 uint32_t reg; 1442 int mlen, ntries, page, error; 1443 1444 /* Read firmware image from the filesystem. */ 1445 error = sc->sc_ops.load_firmware(sc->sc_ops.cookie, &fw, &len); 1446 if (error) 1447 return (error); 1448 if (len < sizeof(*hdr)) { 1449 printf("%s: firmware too short\n", sc->sc_pdev->dv_xname); 1450 error = EINVAL; 1451 goto fail; 1452 } 1453 ptr = fw; 1454 hdr = (const struct r92c_fw_hdr *)ptr; 1455 /* Check if there is a valid FW header and skip it. */ 1456 if ((letoh16(hdr->signature) >> 4) == 0x88c || 1457 (letoh16(hdr->signature) >> 4) == 0x88e || 1458 (letoh16(hdr->signature) >> 4) == 0x92c) { 1459 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 1460 letoh16(hdr->version), letoh16(hdr->subversion), 1461 hdr->month, hdr->date, hdr->hour, hdr->minute)); 1462 ptr += sizeof(*hdr); 1463 len -= sizeof(*hdr); 1464 } 1465 1466 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 1467 if (sc->chip & RTWN_CHIP_88E) 1468 rtwn_r88e_fw_reset(sc); 1469 else 1470 rtwn_fw_reset(sc); 1471 rtwn_write_1(sc, R92C_MCUFWDL, 0); 1472 } 1473 1474 /* Enable FW download. */ 1475 if (!(sc->chip & RTWN_CHIP_88E)) 1476 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1477 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 1478 R92C_SYS_FUNC_EN_CPUEN); 1479 1480 rtwn_write_1(sc, R92C_MCUFWDL, 1481 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 1482 rtwn_write_1(sc, R92C_MCUFWDL + 2, 1483 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 1484 1485 /* Reset the FWDL checksum. */ 1486 rtwn_write_1(sc, R92C_MCUFWDL, 1487 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 1488 1489 for (page = 0; len > 0; page++) { 1490 mlen = MIN(len, R92C_FW_PAGE_SIZE); 1491 error = sc->sc_ops.fw_loadpage(sc->sc_ops.cookie, page, ptr, 1492 mlen); 1493 if (error != 0) { 1494 printf("%s: could not load firmware page %d\n", 1495 sc->sc_pdev->dv_xname, page); 1496 goto fail; 1497 } 1498 ptr += mlen; 1499 len -= mlen; 1500 } 1501 1502 /* Disable FW download. */ 1503 rtwn_write_1(sc, R92C_MCUFWDL, 1504 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 1505 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 1506 1507 /* Wait for checksum report. */ 1508 for (ntries = 0; ntries < 1000; ntries++) { 1509 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 1510 break; 1511 DELAY(5); 1512 } 1513 if (ntries == 1000) { 1514 printf("%s: timeout waiting for checksum report\n", 1515 sc->sc_pdev->dv_xname); 1516 error = ETIMEDOUT; 1517 goto fail; 1518 } 1519 1520 reg = rtwn_read_4(sc, R92C_MCUFWDL); 1521 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 1522 rtwn_write_4(sc, R92C_MCUFWDL, reg); 1523 if (sc->chip & RTWN_CHIP_88E) 1524 rtwn_r88e_fw_reset(sc); 1525 /* Wait for firmware readiness. */ 1526 for (ntries = 0; ntries < 1000; ntries++) { 1527 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 1528 break; 1529 DELAY(10); 1530 } 1531 if (ntries == 1000) { 1532 printf("%s: timeout waiting for firmware readiness\n", 1533 sc->sc_pdev->dv_xname); 1534 error = ETIMEDOUT; 1535 goto fail; 1536 } 1537 fail: 1538 free(fw, M_DEVBUF, len); 1539 return (error); 1540 } 1541 1542 void 1543 rtwn_rf_init(struct rtwn_softc *sc) 1544 { 1545 const struct r92c_rf_prog *prog; 1546 uint32_t reg, type; 1547 int i, j, idx, off; 1548 1549 /* Select RF programming based on board type. */ 1550 if (sc->chip & RTWN_CHIP_88E) 1551 prog = rtl8188eu_rf_prog; 1552 else if (!(sc->chip & RTWN_CHIP_92C)) { 1553 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 1554 prog = rtl8188ce_rf_prog; 1555 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 1556 prog = rtl8188ru_rf_prog; 1557 else 1558 prog = rtl8188cu_rf_prog; 1559 } else 1560 prog = rtl8192ce_rf_prog; 1561 1562 for (i = 0; i < sc->nrxchains; i++) { 1563 /* Save RF_ENV control type. */ 1564 idx = i / 2; 1565 off = (i % 2) * 16; 1566 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1567 type = (reg >> off) & 0x10; 1568 1569 /* Set RF_ENV enable. */ 1570 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1571 reg |= 0x100000; 1572 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1573 DELAY(1); 1574 /* Set RF_ENV output high. */ 1575 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1576 reg |= 0x10; 1577 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1578 DELAY(1); 1579 /* Set address and data lengths of RF registers. */ 1580 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1581 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 1582 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1583 DELAY(1); 1584 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1585 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 1586 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1587 DELAY(1); 1588 1589 /* Write RF initialization values for this chain. */ 1590 for (j = 0; j < prog[i].count; j++) { 1591 if (prog[i].regs[j] >= 0xf9 && 1592 prog[i].regs[j] <= 0xfe) { 1593 /* 1594 * These are fake RF registers offsets that 1595 * indicate a delay is required. 1596 */ 1597 DELAY(50); 1598 continue; 1599 } 1600 rtwn_rf_write(sc, i, prog[i].regs[j], 1601 prog[i].vals[j]); 1602 DELAY(1); 1603 } 1604 1605 /* Restore RF_ENV control type. */ 1606 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1607 reg &= ~(0x10 << off) | (type << off); 1608 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 1609 1610 /* Cache RF register CHNLBW. */ 1611 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 1612 } 1613 1614 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1615 RTWN_CHIP_UMC_A_CUT) { 1616 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 1617 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 1618 } 1619 } 1620 1621 void 1622 rtwn_cam_init(struct rtwn_softc *sc) 1623 { 1624 /* Invalidate all CAM entries. */ 1625 rtwn_write_4(sc, R92C_CAMCMD, 1626 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 1627 } 1628 1629 void 1630 rtwn_pa_bias_init(struct rtwn_softc *sc) 1631 { 1632 uint8_t reg; 1633 int i; 1634 1635 for (i = 0; i < sc->nrxchains; i++) { 1636 if (sc->pa_setting & (1 << i)) 1637 continue; 1638 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 1639 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 1640 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 1641 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 1642 } 1643 if (!(sc->pa_setting & 0x10)) { 1644 reg = rtwn_read_1(sc, 0x16); 1645 reg = (reg & ~0xf0) | 0x90; 1646 rtwn_write_1(sc, 0x16, reg); 1647 } 1648 } 1649 1650 void 1651 rtwn_rxfilter_init(struct rtwn_softc *sc) 1652 { 1653 /* Initialize Rx filter. */ 1654 /* TODO: use better filter for monitor mode. */ 1655 rtwn_write_4(sc, R92C_RCR, 1656 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 1657 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 1658 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 1659 /* Accept all multicast frames. */ 1660 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 1661 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 1662 /* Accept all management frames. */ 1663 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 1664 /* Reject all control frames. */ 1665 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 1666 /* Accept all data frames. */ 1667 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1668 } 1669 1670 void 1671 rtwn_edca_init(struct rtwn_softc *sc) 1672 { 1673 /* XXX Use the same values for PCI and USB? */ 1674 if (sc->chip & RTWN_CHIP_PCI) { 1675 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 1676 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 1677 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 1678 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 1679 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 1680 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 1681 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 1682 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 1683 } else if (sc->chip & RTWN_CHIP_USB) { 1684 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 1685 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 1686 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 1687 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 1688 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 1689 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 1690 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 1691 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 1692 } 1693 } 1694 1695 void 1696 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 1697 uint16_t power[RTWN_RIDX_COUNT]) 1698 { 1699 uint32_t reg; 1700 1701 /* Write per-CCK rate Tx power. */ 1702 if (chain == 0) { 1703 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 1704 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 1705 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 1706 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 1707 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 1708 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 1709 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 1710 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 1711 } else { 1712 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 1713 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 1714 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 1715 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 1716 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 1717 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 1718 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 1719 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 1720 } 1721 /* Write per-OFDM rate Tx power. */ 1722 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 1723 SM(R92C_TXAGC_RATE06, power[ 4]) | 1724 SM(R92C_TXAGC_RATE09, power[ 5]) | 1725 SM(R92C_TXAGC_RATE12, power[ 6]) | 1726 SM(R92C_TXAGC_RATE18, power[ 7])); 1727 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 1728 SM(R92C_TXAGC_RATE24, power[ 8]) | 1729 SM(R92C_TXAGC_RATE36, power[ 9]) | 1730 SM(R92C_TXAGC_RATE48, power[10]) | 1731 SM(R92C_TXAGC_RATE54, power[11])); 1732 /* Write per-MCS Tx power. */ 1733 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 1734 SM(R92C_TXAGC_MCS00, power[12]) | 1735 SM(R92C_TXAGC_MCS01, power[13]) | 1736 SM(R92C_TXAGC_MCS02, power[14]) | 1737 SM(R92C_TXAGC_MCS03, power[15])); 1738 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 1739 SM(R92C_TXAGC_MCS04, power[16]) | 1740 SM(R92C_TXAGC_MCS05, power[17]) | 1741 SM(R92C_TXAGC_MCS06, power[18]) | 1742 SM(R92C_TXAGC_MCS07, power[19])); 1743 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 1744 SM(R92C_TXAGC_MCS08, power[20]) | 1745 SM(R92C_TXAGC_MCS09, power[21]) | 1746 SM(R92C_TXAGC_MCS10, power[22]) | 1747 SM(R92C_TXAGC_MCS11, power[23])); 1748 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 1749 SM(R92C_TXAGC_MCS12, power[24]) | 1750 SM(R92C_TXAGC_MCS13, power[25]) | 1751 SM(R92C_TXAGC_MCS14, power[26]) | 1752 SM(R92C_TXAGC_MCS15, power[27])); 1753 } 1754 1755 void 1756 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 1757 struct ieee80211_channel *c, struct ieee80211_channel *extc, 1758 uint16_t power[RTWN_RIDX_COUNT]) 1759 { 1760 struct ieee80211com *ic = &sc->sc_ic; 1761 struct r92c_rom *rom = &sc->rom; 1762 uint16_t cckpow, ofdmpow, htpow, diff, max; 1763 const struct r92c_txpwr *base; 1764 int ridx, chan, group; 1765 1766 /* Determine channel group. */ 1767 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 1768 if (chan <= 3) 1769 group = 0; 1770 else if (chan <= 9) 1771 group = 1; 1772 else 1773 group = 2; 1774 1775 /* Get original Tx power based on board type and RF chain. */ 1776 if (!(sc->chip & RTWN_CHIP_92C)) { 1777 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 1778 base = &rtl8188ru_txagc[chain]; 1779 else 1780 base = &rtl8192cu_txagc[chain]; 1781 } else 1782 base = &rtl8192cu_txagc[chain]; 1783 1784 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 1785 if (sc->regulatory == 0) { 1786 for (ridx = 0; ridx <= 3; ridx++) 1787 power[ridx] = base->pwr[0][ridx]; 1788 } 1789 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 1790 if (sc->regulatory == 3) { 1791 power[ridx] = base->pwr[0][ridx]; 1792 /* Apply vendor limits. */ 1793 if (extc != NULL) 1794 max = rom->ht40_max_pwr[group]; 1795 else 1796 max = rom->ht20_max_pwr[group]; 1797 max = (max >> (chain * 4)) & 0xf; 1798 if (power[ridx] > max) 1799 power[ridx] = max; 1800 } else if (sc->regulatory == 1) { 1801 if (extc == NULL) 1802 power[ridx] = base->pwr[group][ridx]; 1803 } else if (sc->regulatory != 2) 1804 power[ridx] = base->pwr[0][ridx]; 1805 } 1806 1807 /* Compute per-CCK rate Tx power. */ 1808 cckpow = rom->cck_tx_pwr[chain][group]; 1809 for (ridx = 0; ridx <= 3; ridx++) { 1810 power[ridx] += cckpow; 1811 if (power[ridx] > R92C_MAX_TX_PWR) 1812 power[ridx] = R92C_MAX_TX_PWR; 1813 } 1814 1815 htpow = rom->ht40_1s_tx_pwr[chain][group]; 1816 if (sc->ntxchains > 1) { 1817 /* Apply reduction for 2 spatial streams. */ 1818 diff = rom->ht40_2s_tx_pwr_diff[group]; 1819 diff = (diff >> (chain * 4)) & 0xf; 1820 htpow = (htpow > diff) ? htpow - diff : 0; 1821 } 1822 1823 /* Compute per-OFDM rate Tx power. */ 1824 diff = rom->ofdm_tx_pwr_diff[group]; 1825 diff = (diff >> (chain * 4)) & 0xf; 1826 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 1827 for (ridx = 4; ridx <= 11; ridx++) { 1828 power[ridx] += ofdmpow; 1829 if (power[ridx] > R92C_MAX_TX_PWR) 1830 power[ridx] = R92C_MAX_TX_PWR; 1831 } 1832 1833 /* Compute per-MCS Tx power. */ 1834 if (extc == NULL) { 1835 diff = rom->ht20_tx_pwr_diff[group]; 1836 diff = (diff >> (chain * 4)) & 0xf; 1837 htpow += diff; /* HT40->HT20 correction. */ 1838 } 1839 for (ridx = 12; ridx <= 27; ridx++) { 1840 power[ridx] += htpow; 1841 if (power[ridx] > R92C_MAX_TX_PWR) 1842 power[ridx] = R92C_MAX_TX_PWR; 1843 } 1844 #ifdef RTWN_DEBUG 1845 if (rtwn_debug >= 4) { 1846 /* Dump per-rate Tx power values. */ 1847 printf("Tx power for chain %d:\n", chain); 1848 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 1849 printf("Rate %d = %u\n", ridx, power[ridx]); 1850 } 1851 #endif 1852 } 1853 1854 void 1855 rtwn_r88e_get_txpower(struct rtwn_softc *sc, int chain, 1856 struct ieee80211_channel *c, struct ieee80211_channel *extc, 1857 uint16_t power[RTWN_RIDX_COUNT]) 1858 { 1859 struct ieee80211com *ic = &sc->sc_ic; 1860 uint16_t cckpow, ofdmpow, bw20pow, htpow; 1861 const struct r88e_txpwr *base; 1862 int ridx, chan, group; 1863 1864 /* Determine channel group. */ 1865 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 1866 if (chan <= 2) 1867 group = 0; 1868 else if (chan <= 5) 1869 group = 1; 1870 else if (chan <= 8) 1871 group = 2; 1872 else if (chan <= 11) 1873 group = 3; 1874 else if (chan <= 13) 1875 group = 4; 1876 else 1877 group = 5; 1878 1879 /* Get original Tx power based on board type and RF chain. */ 1880 base = &rtl8188eu_txagc[chain]; 1881 1882 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 1883 if (sc->regulatory == 0) { 1884 for (ridx = 0; ridx <= 3; ridx++) 1885 power[ridx] = base->pwr[0][ridx]; 1886 } 1887 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 1888 if (sc->regulatory == 3) 1889 power[ridx] = base->pwr[0][ridx]; 1890 else if (sc->regulatory == 1) { 1891 if (extc == NULL) 1892 power[ridx] = base->pwr[group][ridx]; 1893 } else if (sc->regulatory != 2) 1894 power[ridx] = base->pwr[0][ridx]; 1895 } 1896 1897 /* Compute per-CCK rate Tx power. */ 1898 cckpow = sc->cck_tx_pwr[group]; 1899 for (ridx = 0; ridx <= 3; ridx++) { 1900 power[ridx] += cckpow; 1901 if (power[ridx] > R92C_MAX_TX_PWR) 1902 power[ridx] = R92C_MAX_TX_PWR; 1903 } 1904 1905 htpow = sc->ht40_tx_pwr[group]; 1906 1907 /* Compute per-OFDM rate Tx power. */ 1908 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 1909 for (ridx = 4; ridx <= 11; ridx++) { 1910 power[ridx] += ofdmpow; 1911 if (power[ridx] > R92C_MAX_TX_PWR) 1912 power[ridx] = R92C_MAX_TX_PWR; 1913 } 1914 1915 bw20pow = htpow + sc->bw20_tx_pwr_diff; 1916 for (ridx = 12; ridx <= 27; ridx++) { 1917 power[ridx] += bw20pow; 1918 if (power[ridx] > R92C_MAX_TX_PWR) 1919 power[ridx] = R92C_MAX_TX_PWR; 1920 } 1921 } 1922 1923 void 1924 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 1925 struct ieee80211_channel *extc) 1926 { 1927 uint16_t power[RTWN_RIDX_COUNT]; 1928 int i; 1929 1930 for (i = 0; i < sc->ntxchains; i++) { 1931 /* Compute per-rate Tx power values. */ 1932 if (sc->chip & RTWN_CHIP_88E) 1933 rtwn_r88e_get_txpower(sc, i, c, extc, power); 1934 else 1935 rtwn_get_txpower(sc, i, c, extc, power); 1936 /* Write per-rate Tx power values to hardware. */ 1937 rtwn_write_txpower(sc, i, power); 1938 } 1939 } 1940 1941 void 1942 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 1943 struct ieee80211_channel *extc) 1944 { 1945 struct ieee80211com *ic = &sc->sc_ic; 1946 u_int chan; 1947 int i; 1948 1949 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 1950 1951 /* Set Tx power for this new channel. */ 1952 rtwn_set_txpower(sc, c, extc); 1953 1954 for (i = 0; i < sc->nrxchains; i++) { 1955 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 1956 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 1957 } 1958 if (extc != NULL) { 1959 uint32_t reg; 1960 1961 /* Is secondary channel below or above primary? */ 1962 int prichlo = c->ic_freq < extc->ic_freq; 1963 1964 rtwn_write_1(sc, R92C_BWOPMODE, 1965 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 1966 1967 reg = rtwn_read_1(sc, R92C_RRSR + 2); 1968 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 1969 rtwn_write_1(sc, R92C_RRSR + 2, reg); 1970 1971 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 1972 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 1973 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 1974 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 1975 1976 /* Set CCK side band. */ 1977 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 1978 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 1979 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 1980 1981 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 1982 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 1983 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 1984 1985 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 1986 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 1987 ~R92C_FPGA0_ANAPARAM2_CBW20); 1988 1989 reg = rtwn_bb_read(sc, 0x818); 1990 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 1991 rtwn_bb_write(sc, 0x818, reg); 1992 1993 /* Select 40MHz bandwidth. */ 1994 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 1995 (sc->rf_chnlbw[0] & ~0xfff) | chan); 1996 } else { 1997 rtwn_write_1(sc, R92C_BWOPMODE, 1998 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 1999 2000 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2001 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2002 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2003 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2004 2005 if (!(sc->chip & RTWN_CHIP_88E)) { 2006 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2007 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2008 R92C_FPGA0_ANAPARAM2_CBW20); 2009 } 2010 2011 /* Select 20MHz bandwidth. */ 2012 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2013 (sc->rf_chnlbw[0] & ~0xfff) | chan | 2014 ((sc->chip & RTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 2015 R92C_RF_CHNLBW_BW20)); 2016 } 2017 } 2018 2019 int 2020 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2021 uint16_t rx[2]) 2022 { 2023 uint32_t status; 2024 int offset = chain * 0x20; 2025 2026 if (chain == 0) { /* IQ calibration for chain 0. */ 2027 /* IQ calibration settings for chain 0. */ 2028 rtwn_bb_write(sc, 0xe30, 0x10008c1f); 2029 rtwn_bb_write(sc, 0xe34, 0x10008c1f); 2030 rtwn_bb_write(sc, 0xe38, 0x82140102); 2031 2032 if (sc->ntxchains > 1) { 2033 rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */ 2034 /* IQ calibration settings for chain 1. */ 2035 rtwn_bb_write(sc, 0xe50, 0x10008c22); 2036 rtwn_bb_write(sc, 0xe54, 0x10008c22); 2037 rtwn_bb_write(sc, 0xe58, 0x82140102); 2038 rtwn_bb_write(sc, 0xe5c, 0x28160202); 2039 } else 2040 rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */ 2041 2042 /* LO calibration settings. */ 2043 rtwn_bb_write(sc, 0xe4c, 0x001028d1); 2044 /* We're doing LO and IQ calibration in one shot. */ 2045 rtwn_bb_write(sc, 0xe48, 0xf9000000); 2046 rtwn_bb_write(sc, 0xe48, 0xf8000000); 2047 2048 } else { /* IQ calibration for chain 1. */ 2049 /* We're doing LO and IQ calibration in one shot. */ 2050 rtwn_bb_write(sc, 0xe60, 0x00000002); 2051 rtwn_bb_write(sc, 0xe60, 0x00000000); 2052 } 2053 2054 /* Give LO and IQ calibrations the time to complete. */ 2055 DELAY(1000); 2056 2057 /* Read IQ calibration status. */ 2058 status = rtwn_bb_read(sc, 0xeac); 2059 2060 if (status & (1 << (28 + chain * 3))) 2061 return (0); /* Tx failed. */ 2062 /* Read Tx IQ calibration results. */ 2063 tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff; 2064 tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff; 2065 if (tx[0] == 0x142 || tx[1] == 0x042) 2066 return (0); /* Tx failed. */ 2067 2068 if (status & (1 << (27 + chain * 3))) 2069 return (1); /* Rx failed. */ 2070 /* Read Rx IQ calibration results. */ 2071 rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff; 2072 rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff; 2073 if (rx[0] == 0x132 || rx[1] == 0x036) 2074 return (1); /* Rx failed. */ 2075 2076 return (3); /* Both Tx and Rx succeeded. */ 2077 } 2078 2079 void 2080 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2081 uint16_t rx[2][2]) 2082 { 2083 /* Registers to save and restore during IQ calibration. */ 2084 struct iq_cal_regs { 2085 uint32_t adda[16]; 2086 uint8_t txpause; 2087 uint8_t bcn_ctrl; 2088 uint8_t ustime_tsf; 2089 uint32_t gpio_muxcfg; 2090 uint32_t ofdm0_trxpathena; 2091 uint32_t ofdm0_trmuxpar; 2092 uint32_t fpga0_rfifacesw1; 2093 } iq_cal_regs; 2094 static const uint16_t reg_adda[16] = { 2095 0x85c, 0xe6c, 0xe70, 0xe74, 2096 0xe78, 0xe7c, 0xe80, 0xe84, 2097 0xe88, 0xe8c, 0xed0, 0xed4, 2098 0xed8, 0xedc, 0xee0, 0xeec 2099 }; 2100 int i, chain; 2101 uint32_t hssi_param1; 2102 2103 if (n == 0) { 2104 for (i = 0; i < nitems(reg_adda); i++) 2105 iq_cal_regs.adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2106 2107 iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2108 iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2109 iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF); 2110 iq_cal_regs.gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2111 } 2112 2113 if (sc->ntxchains == 1) { 2114 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 2115 for (i = 1; i < nitems(reg_adda); i++) 2116 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 2117 } else { 2118 for (i = 0; i < nitems(reg_adda); i++) 2119 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 2120 } 2121 2122 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2123 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2124 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2125 hssi_param1 | R92C_HSSI_PARAM1_PI); 2126 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2127 hssi_param1 | R92C_HSSI_PARAM1_PI); 2128 } 2129 2130 if (n == 0) { 2131 iq_cal_regs.ofdm0_trxpathena = 2132 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2133 iq_cal_regs.ofdm0_trmuxpar = 2134 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2135 iq_cal_regs.fpga0_rfifacesw1 = 2136 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2137 } 2138 2139 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2140 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2141 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2142 if (sc->ntxchains > 1) { 2143 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2144 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2145 } 2146 2147 rtwn_write_1(sc, R92C_TXPAUSE, 0x3f); 2148 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl & ~(0x08)); 2149 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf & ~(0x08)); 2150 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2151 iq_cal_regs.gpio_muxcfg & ~(0x20)); 2152 2153 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2154 if (sc->ntxchains > 1) 2155 rtwn_bb_write(sc, 0x0b6c, 0x00080000); 2156 2157 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2158 rtwn_bb_write(sc, 0x0e40, 0x01007c00); 2159 rtwn_bb_write(sc, 0x0e44, 0x01004800); 2160 2161 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2162 2163 for (chain = 0; chain < sc->ntxchains; chain++) { 2164 if (chain > 0) { 2165 /* Put chain 0 on standby. */ 2166 rtwn_bb_write(sc, 0x0e28, 0x00); 2167 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2168 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2169 2170 /* Enable chain 1. */ 2171 for (i = 0; i < nitems(reg_adda); i++) 2172 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 2173 } 2174 2175 /* Run IQ calibration twice. */ 2176 for (i = 0; i < 2; i++) { 2177 int ret; 2178 2179 ret = rtwn_iq_calib_chain(sc, chain, 2180 tx[chain], rx[chain]); 2181 if (ret == 0) { 2182 DPRINTF(("%s: chain %d: Tx failed.\n", 2183 __func__, chain)); 2184 tx[chain][0] = 0xff; 2185 tx[chain][1] = 0xff; 2186 rx[chain][0] = 0xff; 2187 rx[chain][1] = 0xff; 2188 } else if (ret == 1) { 2189 DPRINTF(("%s: chain %d: Rx failed.\n", 2190 __func__, chain)); 2191 rx[chain][0] = 0xff; 2192 rx[chain][1] = 0xff; 2193 } else if (ret == 3) { 2194 DPRINTF(("%s: chain %d: Both Tx and Rx " 2195 "succeeded.\n", __func__, chain)); 2196 } 2197 } 2198 2199 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 2200 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 2201 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 2202 } 2203 2204 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 2205 iq_cal_regs.ofdm0_trxpathena); 2206 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 2207 iq_cal_regs.fpga0_rfifacesw1); 2208 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, iq_cal_regs.ofdm0_trmuxpar); 2209 2210 rtwn_bb_write(sc, 0x0e28, 0x00); 2211 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 2212 if (sc->ntxchains > 1) 2213 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 2214 2215 if (n != 0) { 2216 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2217 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 2218 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 2219 } 2220 2221 for (i = 0; i < nitems(reg_adda); i++) 2222 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs.adda[i]); 2223 2224 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs.txpause); 2225 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl); 2226 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf); 2227 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs.gpio_muxcfg); 2228 } 2229 } 2230 2231 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 2232 int 2233 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 2234 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 2235 { 2236 int chain, i, tx_ok[2], rx_ok[2]; 2237 2238 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 2239 for (chain = 0; chain < ntxchains; chain++) { 2240 for (i = 0; i < 2; i++) { 2241 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 2242 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 2243 continue; 2244 2245 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 2246 RTWN_IQ_CAL_MAX_TOLERANCE); 2247 2248 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 2249 RTWN_IQ_CAL_MAX_TOLERANCE); 2250 } 2251 } 2252 2253 if (ntxchains > 1) 2254 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 2255 else 2256 return (tx_ok[0] && rx_ok[0]); 2257 } 2258 #undef RTWN_IQ_CAL_MAX_TOLERANCE 2259 2260 void 2261 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 2262 uint16_t rx[2], int chain) 2263 { 2264 uint32_t reg, val, x; 2265 long y, tx_c; 2266 2267 if (tx[0] == 0xff || tx[1] == 0xff) 2268 return; 2269 2270 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2271 val = ((reg >> 22) & 0x3ff); 2272 x = tx[0]; 2273 if (x & 0x0200) 2274 x |= 0xfc00; 2275 reg = (((x * val) >> 8) & 0x3ff); 2276 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2277 2278 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2279 if (((x * val) >> 7) & 0x01) 2280 reg |= 0x80000000; 2281 else 2282 reg &= ~0x80000000; 2283 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2284 2285 y = tx[1]; 2286 if (y & 0x00000200) 2287 y |= 0xfffffc00; 2288 tx_c = (y * val) >> 8; 2289 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 2290 reg |= ((((tx_c & 0x3c0) >> 6) << 24) & 0xf0000000); 2291 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 2292 2293 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2294 reg |= (((tx_c & 0x3f) << 16) & 0x003F0000); 2295 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2296 2297 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2298 if (((y * val) >> 7) & 0x01) 2299 reg |= 0x20000000; 2300 else 2301 reg &= ~0x20000000; 2302 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2303 2304 if (rx[0] == 0xff || rx[1] == 0xff) 2305 return; 2306 2307 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 2308 reg |= (rx[0] & 0x3ff); 2309 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2310 reg |= (((rx[1] & 0x03f) << 8) & 0xFC00); 2311 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2312 2313 if (chain == 0) { 2314 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 2315 reg |= (((rx[1] & 0xf) >> 6) & 0x000f); 2316 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 2317 } else { 2318 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 2319 reg |= ((((rx[1] & 0xf) >> 6) << 12) & 0xf000); 2320 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 2321 } 2322 } 2323 2324 #define RTWN_IQ_CAL_NRUN 3 2325 void 2326 rtwn_iq_calib(struct rtwn_softc *sc) 2327 { 2328 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 2329 int n, valid; 2330 2331 /* FIXME IQ calib breaks Rx on USB devices. */ 2332 if (sc->chip & RTWN_CHIP_USB) 2333 return; 2334 2335 valid = 0; 2336 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 2337 rtwn_iq_calib_run(sc, n, tx[n], rx[n]); 2338 2339 if (n == 0) 2340 continue; 2341 2342 /* Valid results remain stable after consecutive runs. */ 2343 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 2344 tx[n], rx[n], sc->ntxchains); 2345 if (valid) 2346 break; 2347 } 2348 2349 if (valid) { 2350 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 2351 if (sc->ntxchains > 1) 2352 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 2353 } 2354 } 2355 #undef RTWN_IQ_CAL_NRUN 2356 2357 void 2358 rtwn_lc_calib(struct rtwn_softc *sc) 2359 { 2360 uint32_t rf_ac[2]; 2361 uint8_t txmode; 2362 int i; 2363 2364 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 2365 if ((txmode & 0x70) != 0) { 2366 /* Disable all continuous Tx. */ 2367 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 2368 2369 /* Set RF mode to standby mode. */ 2370 for (i = 0; i < sc->nrxchains; i++) { 2371 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 2372 rtwn_rf_write(sc, i, R92C_RF_AC, 2373 RW(rf_ac[i], R92C_RF_AC_MODE, 2374 R92C_RF_AC_MODE_STANDBY)); 2375 } 2376 } else { 2377 /* Block all Tx queues. */ 2378 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 2379 } 2380 /* Start calibration. */ 2381 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2382 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 2383 2384 /* Give calibration the time to complete. */ 2385 DELAY(100); 2386 2387 /* Restore configuration. */ 2388 if ((txmode & 0x70) != 0) { 2389 /* Restore Tx mode. */ 2390 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 2391 /* Restore RF mode. */ 2392 for (i = 0; i < sc->nrxchains; i++) 2393 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 2394 } else { 2395 /* Unblock all Tx queues. */ 2396 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 2397 } 2398 } 2399 2400 void 2401 rtwn_temp_calib(struct rtwn_softc *sc) 2402 { 2403 int temp; 2404 2405 if (sc->thcal_state == 0) { 2406 /* Start measuring temperature. */ 2407 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 2408 sc->thcal_state = 1; 2409 return; 2410 } 2411 sc->thcal_state = 0; 2412 2413 /* Read measured temperature. */ 2414 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 2415 if (temp == 0) /* Read failed, skip. */ 2416 return; 2417 DPRINTFN(2, ("temperature=%d\n", temp)); 2418 2419 /* 2420 * Redo IQ and LC calibration if temperature changed significantly 2421 * since last calibration. 2422 */ 2423 if (sc->thcal_lctemp == 0) { 2424 /* First calibration is performed in rtwn_init(). */ 2425 sc->thcal_lctemp = temp; 2426 } else if (abs(temp - sc->thcal_lctemp) > 1) { 2427 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 2428 sc->thcal_lctemp, temp)); 2429 rtwn_iq_calib(sc); 2430 rtwn_lc_calib(sc); 2431 /* Record temperature of last calibration. */ 2432 sc->thcal_lctemp = temp; 2433 } 2434 } 2435 2436 void 2437 rtwn_enable_intr(struct rtwn_softc *sc) 2438 { 2439 if (sc->chip & RTWN_CHIP_88E) { 2440 rtwn_write_4(sc, R88E_HISR, 0xffffffff); 2441 rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | 2442 R88E_HIMR_CPWM2 | R88E_HIMR_TBDER | 2443 R88E_HIMR_PSTIMEOUT); 2444 rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 2445 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | 2446 R88E_HIMRE_TXERR); 2447 if (sc->chip & RTWN_CHIP_USB) { 2448 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2449 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 2450 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 2451 } 2452 } else { 2453 uint32_t imask = 0; 2454 2455 if (sc->chip & RTWN_CHIP_USB) 2456 imask = 0xffffffff; 2457 else if (sc->chip & RTWN_CHIP_PCI) 2458 imask = RTWN_INT_ENABLE; 2459 else 2460 panic("unknown chip type 0x%x", sc->chip); 2461 2462 /* CLear pending interrupts. */ 2463 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 2464 2465 /* Enable interrupts. */ 2466 rtwn_write_4(sc, R92C_HIMR, imask); 2467 } 2468 } 2469 2470 void 2471 rtwn_disable_intr(struct rtwn_softc *sc) 2472 { 2473 if (sc->chip & RTWN_CHIP_88E) { 2474 rtwn_write_4(sc, R88E_HISR, 0x00000000); 2475 rtwn_write_4(sc, R88E_HIMR, 0x00000000); 2476 rtwn_write_4(sc, R88E_HIMRE, 0x00000000); 2477 if (sc->chip & RTWN_CHIP_USB) { 2478 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2479 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 2480 ~R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 2481 } 2482 } else { 2483 rtwn_write_4(sc, R92C_HISR, 0x00000000); 2484 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 2485 } 2486 } 2487 2488 int 2489 rtwn_init(struct ifnet *ifp) 2490 { 2491 struct rtwn_softc *sc = ifp->if_softc; 2492 struct ieee80211com *ic = &sc->sc_ic; 2493 uint32_t reg; 2494 int i, error; 2495 2496 /* Init firmware commands ring. */ 2497 sc->fwcur = 0; 2498 2499 error = sc->sc_ops.alloc_buffers(sc->sc_ops.cookie); 2500 if (error) 2501 goto fail; 2502 2503 /* Power on adapter. */ 2504 error = sc->sc_ops.power_on(sc->sc_ops.cookie); 2505 if (error != 0) { 2506 printf("%s: could not power on adapter\n", 2507 sc->sc_pdev->dv_xname); 2508 goto fail; 2509 } 2510 2511 /* Initialize DMA. */ 2512 error = sc->sc_ops.dma_init(sc->sc_ops.cookie); 2513 if (error != 0) { 2514 printf("%s: could not initialize DMA\n", 2515 sc->sc_pdev->dv_xname); 2516 goto fail; 2517 } 2518 2519 /* Set info size in Rx descriptors (in 64-bit words). */ 2520 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 2521 2522 if (sc->chip & RTWN_CHIP_USB) { 2523 /* Init interrupts. */ 2524 rtwn_enable_intr(sc); 2525 } else if (sc->chip & RTWN_CHIP_PCI) { 2526 rtwn_disable_intr(sc); 2527 } 2528 2529 /* Set MAC address. */ 2530 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2531 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 2532 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 2533 2534 /* Set initial network type. */ 2535 reg = rtwn_read_4(sc, R92C_CR); 2536 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 2537 rtwn_write_4(sc, R92C_CR, reg); 2538 2539 rtwn_rxfilter_init(sc); 2540 2541 reg = rtwn_read_4(sc, R92C_RRSR); 2542 if (sc->chip & RTWN_CHIP_USB) { 2543 reg = RW(reg, R92C_RRSR_RATE_BITMAP, 2544 R92C_RRSR_RATE_CCK_ONLY_1M); 2545 } else { 2546 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 2547 } 2548 rtwn_write_4(sc, R92C_RRSR, reg); 2549 2550 /* Set short/long retry limits. */ 2551 if (sc->chip & RTWN_CHIP_USB) { 2552 rtwn_write_2(sc, R92C_RL, 2553 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 2554 } else { 2555 rtwn_write_2(sc, R92C_RL, 2556 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 2557 } 2558 2559 /* Initialize EDCA parameters. */ 2560 rtwn_edca_init(sc); 2561 2562 /* Set data and response automatic rate fallback retry counts. */ 2563 if (!(sc->chip & RTWN_CHIP_88E)) { 2564 /* XXX Use the same values for PCI and USB? */ 2565 if (sc->chip & RTWN_CHIP_PCI) { 2566 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 2567 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 2568 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 2569 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 2570 } else if (sc->chip & RTWN_CHIP_USB) { 2571 rtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 2572 rtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 2573 rtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 2574 rtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 2575 } 2576 } 2577 2578 if (sc->chip & RTWN_CHIP_USB) { 2579 rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 2580 rtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 2581 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 2582 } else { 2583 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 2584 } 2585 2586 /* Set ACK timeout. */ 2587 rtwn_write_1(sc, R92C_ACKTO, 0x40); 2588 2589 if (sc->chip & RTWN_CHIP_USB) { 2590 /* Setup USB aggregation. */ 2591 reg = rtwn_read_4(sc, R92C_TDECTRL); 2592 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 2593 rtwn_write_4(sc, R92C_TDECTRL, reg); 2594 rtwn_write_1(sc, R92C_TRXDMA_CTRL, 2595 rtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2596 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2597 rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 2598 if (sc->chip & RTWN_CHIP_88E) { 2599 rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 2600 } else { 2601 rtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 2602 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2603 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 2604 R92C_USB_SPECIAL_OPTION_AGG_EN); 2605 rtwn_write_1(sc, R92C_USB_AGG_TH, 8); 2606 rtwn_write_1(sc, R92C_USB_AGG_TO, 6); 2607 } 2608 } 2609 2610 /* Initialize beacon parameters. */ 2611 rtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 2612 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 2613 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 2614 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 2615 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 2616 2617 if (!(sc->chip & RTWN_CHIP_88E)) { 2618 /* Setup AMPDU aggregation. */ 2619 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 2620 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 2621 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 2622 2623 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 2624 } 2625 2626 if (sc->chip & RTWN_CHIP_PCI) { /* also for USB? */ 2627 rtwn_write_4(sc, R92C_PIFS, 0x1c); 2628 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 2629 } 2630 2631 /* Load 8051 microcode. */ 2632 error = rtwn_load_firmware(sc); 2633 if (error != 0) 2634 goto fail; 2635 2636 /* Initialize MAC/BB/RF blocks. */ 2637 sc->sc_ops.mac_init(sc->sc_ops.cookie); 2638 sc->sc_ops.bb_init(sc->sc_ops.cookie); 2639 rtwn_rf_init(sc); 2640 2641 if (sc->chip & RTWN_CHIP_88E) { 2642 rtwn_write_2(sc, R92C_CR, 2643 rtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 2644 R92C_CR_MACRXEN); 2645 } 2646 2647 /* Turn CCK and OFDM blocks on. */ 2648 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2649 reg |= R92C_RFMOD_CCK_EN; 2650 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2651 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2652 reg |= R92C_RFMOD_OFDM_EN; 2653 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2654 2655 /* Clear per-station keys table. */ 2656 rtwn_cam_init(sc); 2657 2658 /* Enable hardware sequence numbering. */ 2659 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 2660 2661 /* Perform LO and IQ calibrations. */ 2662 rtwn_iq_calib(sc); 2663 /* Perform LC calibration. */ 2664 rtwn_lc_calib(sc); 2665 2666 /* Fix USB interference issue. */ 2667 if ((sc->chip & RTWN_CHIP_USB) && !(sc->chip & RTWN_CHIP_88E)) { 2668 rtwn_write_1(sc, 0xfe40, 0xe0); 2669 rtwn_write_1(sc, 0xfe41, 0x8d); 2670 rtwn_write_1(sc, 0xfe42, 0x80); 2671 2672 rtwn_pa_bias_init(sc); 2673 } 2674 2675 /* Initialize GPIO setting. */ 2676 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2677 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 2678 2679 /* Fix for lower temperature. */ 2680 if (!(sc->chip & RTWN_CHIP_88E)) 2681 rtwn_write_1(sc, 0x15, 0xe9); 2682 2683 /* Set default channel. */ 2684 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2685 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 2686 2687 if (sc->chip & RTWN_CHIP_PCI) 2688 rtwn_enable_intr(sc); 2689 2690 error = sc->sc_ops.init(sc->sc_ops.cookie); 2691 if (error) 2692 goto fail; 2693 2694 /* We're ready to go. */ 2695 ifq_clr_oactive(&ifp->if_snd); 2696 ifp->if_flags |= IFF_RUNNING; 2697 2698 #ifdef notyet 2699 if (ic->ic_flags & IEEE80211_F_WEPON) { 2700 /* Install WEP keys. */ 2701 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2702 ic->ic_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2703 sc->sc_ops.wait_async(sc->sc_ops.cookie); 2704 } 2705 #endif 2706 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2707 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2708 else 2709 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2710 return (0); 2711 fail: 2712 rtwn_stop(ifp); 2713 return (error); 2714 } 2715 2716 void 2717 rtwn_init_task(void *arg1) 2718 { 2719 struct rtwn_softc *sc = arg1; 2720 struct ifnet *ifp = &sc->sc_ic.ic_if; 2721 int s; 2722 2723 s = splnet(); 2724 while (sc->sc_flags & RTWN_FLAG_BUSY) 2725 tsleep(&sc->sc_flags, 0, "rtwnpwr", 0); 2726 sc->sc_flags |= RTWN_FLAG_BUSY; 2727 2728 rtwn_stop(ifp); 2729 2730 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 2731 rtwn_init(ifp); 2732 2733 sc->sc_flags &= ~RTWN_FLAG_BUSY; 2734 wakeup(&sc->sc_flags); 2735 splx(s); 2736 } 2737 2738 void 2739 rtwn_stop(struct ifnet *ifp) 2740 { 2741 struct rtwn_softc *sc = ifp->if_softc; 2742 struct ieee80211com *ic = &sc->sc_ic; 2743 int s; 2744 2745 sc->sc_tx_timer = 0; 2746 ifp->if_timer = 0; 2747 ifp->if_flags &= ~IFF_RUNNING; 2748 ifq_clr_oactive(&ifp->if_snd); 2749 2750 s = splnet(); 2751 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2752 splx(s); 2753 2754 sc->sc_ops.wait_async(sc->sc_ops.cookie); 2755 2756 s = splnet(); 2757 2758 sc->sc_ops.cancel_scan(sc->sc_ops.cookie); 2759 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 2760 2761 task_del(systq, &sc->init_task); 2762 2763 splx(s); 2764 2765 sc->sc_ops.stop(sc->sc_ops.cookie); 2766 } 2767