1 /* $OpenBSD: rtsx.c,v 1.19 2017/09/07 17:00:28 jcs Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Realtek RTS52xx/RTL84xx Card Reader driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/systm.h> 28 29 #include <dev/ic/rtsxreg.h> 30 #include <dev/ic/rtsxvar.h> 31 #include <dev/sdmmc/sdmmcvar.h> 32 #include <dev/sdmmc/sdmmc_ioreg.h> 33 34 /* 35 * We use two DMA buffers, a command buffer and a data buffer. 36 * 37 * The command buffer contains a command queue for the host controller, 38 * which describes SD/MMC commands to run, and other parameters. The chip 39 * runs the command queue when a special bit in the RTSX_HCBAR register is set 40 * and signals completion with the TRANS_OK interrupt. 41 * Each command is encoded as a 4 byte sequence containing command number 42 * (read, write, or check a host controller register), a register address, 43 * and a data bit-mask and value. 44 * 45 * The data buffer is used to transfer data sectors to or from the SD card. 46 * Data transfer is controlled via the RTSX_HDBAR register. Completion is 47 * also signalled by the TRANS_OK interrupt. 48 * 49 * The chip is unable to perform DMA above 4GB. 50 * 51 * SD/MMC commands which do not transfer any data from/to the card only use 52 * the command buffer. 53 */ 54 55 #define RTSX_DMA_MAX_SEGSIZE 0x80000 56 #define RTSX_HOSTCMD_MAX 256 57 #define RTSX_HOSTCMD_BUFSIZE (sizeof(u_int32_t) * RTSX_HOSTCMD_MAX) 58 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 59 60 #define READ4(sc, reg) \ 61 (bus_space_read_4((sc)->iot, (sc)->ioh, (reg))) 62 #define WRITE4(sc, reg, val) \ 63 bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val)) 64 65 #define RTSX_READ(sc, reg, val) \ 66 do { \ 67 int err = rtsx_read((sc), (reg), (val)); \ 68 if (err) \ 69 return (err); \ 70 } while (0) 71 72 #define RTSX_WRITE(sc, reg, val) \ 73 do { \ 74 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 75 if (err) \ 76 return (err); \ 77 } while (0) 78 79 #define RTSX_CLR(sc, reg, bits) \ 80 do { \ 81 int err = rtsx_write((sc), (reg), (bits), 0); \ 82 if (err) \ 83 return (err); \ 84 } while (0) 85 86 #define RTSX_SET(sc, reg, bits) \ 87 do { \ 88 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 89 if (err) \ 90 return (err); \ 91 } while (0) 92 93 int rtsx_host_reset(sdmmc_chipset_handle_t); 94 u_int32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 95 int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 96 int rtsx_card_detect(sdmmc_chipset_handle_t); 97 int rtsx_bus_power(sdmmc_chipset_handle_t, u_int32_t); 98 int rtsx_bus_clock(sdmmc_chipset_handle_t, int, int); 99 int rtsx_bus_width(sdmmc_chipset_handle_t, int); 100 void rtsx_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 101 int rtsx_init(struct rtsx_softc *, int); 102 void rtsx_soft_reset(struct rtsx_softc *); 103 int rtsx_bus_power_off(struct rtsx_softc *); 104 int rtsx_bus_power_on(struct rtsx_softc *); 105 int rtsx_set_bus_width(struct rtsx_softc *, int); 106 int rtsx_stop_sd_clock(struct rtsx_softc *); 107 int rtsx_switch_sd_clock(struct rtsx_softc *, u_int8_t, int, int); 108 int rtsx_wait_intr(struct rtsx_softc *, int, int); 109 int rtsx_read(struct rtsx_softc *, u_int16_t, u_int8_t *); 110 int rtsx_write(struct rtsx_softc *, u_int16_t, u_int8_t, u_int8_t); 111 #ifdef notyet 112 int rtsx_read_phy(struct rtsx_softc *, u_int8_t, u_int16_t *); 113 #endif 114 int rtsx_write_phy(struct rtsx_softc *, u_int8_t, u_int16_t); 115 int rtsx_read_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t *); 116 #ifdef notyet 117 int rtsx_write_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t, 118 u_int32_t); 119 #endif 120 void rtsx_hostcmd(u_int32_t *, int *, u_int8_t, u_int16_t, u_int8_t, 121 u_int8_t); 122 int rtsx_hostcmd_send(struct rtsx_softc *, int); 123 u_int8_t rtsx_response_type(u_int16_t); 124 int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, u_int32_t *); 125 void rtsx_card_insert(struct rtsx_softc *); 126 void rtsx_card_eject(struct rtsx_softc *); 127 int rtsx_led_enable(struct rtsx_softc *); 128 int rtsx_led_disable(struct rtsx_softc *); 129 void rtsx_save_regs(struct rtsx_softc *); 130 void rtsx_restore_regs(struct rtsx_softc *); 131 132 #ifdef RTSX_DEBUG 133 int rtsxdebug = 0; 134 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 135 #else 136 #define DPRINTF(n,s) do {} while(0) 137 #endif 138 139 struct sdmmc_chip_functions rtsx_functions = { 140 /* host controller reset */ 141 rtsx_host_reset, 142 /* host controller capabilities */ 143 rtsx_host_ocr, 144 rtsx_host_maxblklen, 145 /* card detection */ 146 rtsx_card_detect, 147 /* bus power and clock frequency */ 148 rtsx_bus_power, 149 rtsx_bus_clock, 150 rtsx_bus_width, 151 /* command execution */ 152 rtsx_exec_command, 153 /* card interrupt */ 154 NULL, NULL 155 }; 156 157 struct cfdriver rtsx_cd = { 158 NULL, "rtsx", DV_DULL 159 }; 160 161 /* 162 * Called by attachment driver. 163 */ 164 int 165 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, 166 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) 167 { 168 struct sdmmcbus_attach_args saa; 169 u_int32_t sdio_cfg; 170 171 sc->iot = iot; 172 sc->ioh = ioh; 173 sc->dmat = dmat; 174 sc->flags = flags; 175 176 if (rtsx_init(sc, 1)) 177 return 1; 178 179 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 180 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 181 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 182 sc->flags |= RTSX_F_SDIO_SUPPORT; 183 } 184 185 if (bus_dmamap_create(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 1, 186 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 187 &sc->dmap_cmd) != 0) 188 return 1; 189 if (bus_dmamap_create(sc->dmat, RTSX_DMA_DATA_BUFSIZE, 1, 190 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 191 &sc->dmap_data) != 0) 192 return 1; 193 194 /* 195 * Attach the generic SD/MMC bus driver. (The bus driver must 196 * not invoke any chipset functions before it is attached.) 197 */ 198 bzero(&saa, sizeof(saa)); 199 saa.saa_busname = "sdmmc"; 200 saa.sct = &rtsx_functions; 201 saa.sch = sc; 202 saa.flags = SMF_STOP_AFTER_MULTIPLE; 203 saa.caps = SMC_CAPS_4BIT_MODE; 204 205 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 206 if (sc->sdmmc == NULL) 207 return 1; 208 209 /* Now handle cards discovered during attachment. */ 210 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 211 rtsx_card_insert(sc); 212 213 return 0; 214 } 215 216 int 217 rtsx_init(struct rtsx_softc *sc, int attaching) 218 { 219 u_int32_t status; 220 u_int8_t version; 221 int error; 222 223 /* Read IC version from dummy register. */ 224 if (sc->flags & RTSX_F_5229) { 225 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 226 switch (version & 0x0F) { 227 case RTSX_IC_VERSION_A: 228 case RTSX_IC_VERSION_B: 229 case RTSX_IC_VERSION_D: 230 break; 231 case RTSX_IC_VERSION_C: 232 sc->flags |= RTSX_F_5229_TYPE_C; 233 break; 234 default: 235 printf("rtsx_init: unknown ic %02x\n", version); 236 return (1); 237 } 238 } 239 240 /* Enable interrupt write-clear (default is read-clear). */ 241 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 242 243 /* Clear any pending interrupts. */ 244 status = READ4(sc, RTSX_BIPR); 245 WRITE4(sc, RTSX_BIPR, status); 246 247 /* Check for cards already inserted at attach time. */ 248 if (attaching && (status & RTSX_SD_EXIST)) 249 sc->flags |= RTSX_F_CARD_PRESENT; 250 251 /* Enable interrupts. */ 252 WRITE4(sc, RTSX_BIER, 253 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); 254 255 /* Power on SSC clock. */ 256 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 257 delay(200); 258 259 /* XXX magic numbers from linux driver */ 260 if (sc->flags & RTSX_F_5209) 261 error = rtsx_write_phy(sc, 0x00, 0xB966); 262 else 263 error = rtsx_write_phy(sc, 0x00, 0xBA42); 264 if (error) { 265 printf("%s: cannot write phy register\n", DEVNAME(sc)); 266 return (1); 267 } 268 269 RTSX_SET(sc, RTSX_CLK_DIV, 0x07); 270 271 /* Disable sleep mode. */ 272 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 273 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 274 275 /* Disable card clock. */ 276 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 277 278 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 279 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); 280 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); 281 282 /* Enable SSC clock. */ 283 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 284 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 285 286 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); 287 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); 288 289 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 290 291 /* Set RC oscillator to 400K. */ 292 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 293 294 /* Request clock by driving CLKREQ pin to zero. */ 295 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); 296 297 /* Set up LED GPIO. */ 298 if (sc->flags & RTSX_F_5209) { 299 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 300 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 301 } else { 302 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 303 /* Switch LDO3318 source from DV33 to 3V3. */ 304 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 305 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); 306 /* Set default OLT blink period. */ 307 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); 308 } 309 310 return (0); 311 } 312 313 int 314 rtsx_activate(struct device *self, int act) 315 { 316 struct rtsx_softc *sc = (struct rtsx_softc *)self; 317 int rv = 0; 318 319 switch (act) { 320 case DVACT_SUSPEND: 321 rv = config_activate_children(self, act); 322 rtsx_save_regs(sc); 323 break; 324 case DVACT_RESUME: 325 rtsx_restore_regs(sc); 326 327 /* Handle cards ejected/inserted during suspend. */ 328 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) 329 rtsx_card_insert(sc); 330 else 331 rtsx_card_eject(sc); 332 333 rv = config_activate_children(self, act); 334 break; 335 default: 336 rv = config_activate_children(self, act); 337 break; 338 } 339 return (rv); 340 } 341 342 int 343 rtsx_led_enable(struct rtsx_softc *sc) 344 { 345 if (sc->flags & RTSX_F_5209) { 346 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 347 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 348 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 349 } else { 350 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 351 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 352 } 353 354 return 0; 355 } 356 357 int 358 rtsx_led_disable(struct rtsx_softc *sc) 359 { 360 if (sc->flags & RTSX_F_5209) { 361 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 362 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 363 } else { 364 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 365 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 366 } 367 368 return 0; 369 } 370 371 /* 372 * Reset the host controller. Called during initialization, when 373 * cards are removed, upon resume, and during error recovery. 374 */ 375 int 376 rtsx_host_reset(sdmmc_chipset_handle_t sch) 377 { 378 struct rtsx_softc *sc = sch; 379 int s; 380 381 DPRINTF(1,("%s: host reset\n", DEVNAME(sc))); 382 383 s = splsdmmc(); 384 385 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 386 rtsx_soft_reset(sc); 387 388 if (rtsx_init(sc, 0)) { 389 splx(s); 390 return 1; 391 } 392 393 splx(s); 394 return 0; 395 } 396 397 u_int32_t 398 rtsx_host_ocr(sdmmc_chipset_handle_t sch) 399 { 400 return RTSX_SUPPORT_VOLTAGE; 401 } 402 403 int 404 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) 405 { 406 return 512; 407 } 408 409 /* 410 * Return non-zero if the card is currently inserted. 411 */ 412 int 413 rtsx_card_detect(sdmmc_chipset_handle_t sch) 414 { 415 struct rtsx_softc *sc = sch; 416 417 return ISSET(sc->flags, RTSX_F_CARD_PRESENT); 418 } 419 420 /* 421 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 422 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 423 * it is a mask of *enabled* gates. 424 */ 425 426 int 427 rtsx_bus_power_off(struct rtsx_softc *sc) 428 { 429 int error; 430 u_int8_t disable3; 431 432 error = rtsx_stop_sd_clock(sc); 433 if (error) 434 return error; 435 436 /* Disable SD output. */ 437 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); 438 439 /* Turn off power. */ 440 disable3 = RTSX_PULL_CTL_DISABLE3; 441 if (sc->flags & RTSX_F_5209) 442 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 443 else { 444 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | 445 RTSX_LDO3318_VCC2); 446 if (sc->flags & RTSX_F_5229_TYPE_C) 447 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; 448 } 449 450 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 451 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 452 453 /* Disable pull control. */ 454 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 455 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 456 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); 457 458 return 0; 459 } 460 461 int 462 rtsx_bus_power_on(struct rtsx_softc *sc) 463 { 464 u_int8_t enable3; 465 int err; 466 467 if (sc->flags & RTSX_F_525A) { 468 err = rtsx_write(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, 469 RTSX_LDO_VCC_3V3); 470 if (err) 471 return (err); 472 } 473 474 /* Select SD card. */ 475 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); 476 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); 477 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 478 479 /* Enable pull control. */ 480 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 481 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 482 if (sc->flags & RTSX_F_5229_TYPE_C) 483 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; 484 else 485 enable3 = RTSX_PULL_CTL_ENABLE3; 486 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); 487 488 /* 489 * To avoid a current peak, enable card power in two phases with a 490 * delay in between. 491 */ 492 493 /* Partial power. */ 494 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); 495 if (sc->flags & RTSX_F_5209) 496 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); 497 else 498 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); 499 500 delay(200); 501 502 /* Full power. */ 503 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 504 if (sc->flags & RTSX_F_5209) 505 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 506 else 507 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); 508 509 /* Enable SD card output. */ 510 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 511 512 return 0; 513 } 514 515 int 516 rtsx_set_bus_width(struct rtsx_softc *sc, int w) 517 { 518 u_int32_t bus_width; 519 int error; 520 521 switch (w) { 522 case 8: 523 bus_width = RTSX_BUS_WIDTH_8; 524 break; 525 case 4: 526 bus_width = RTSX_BUS_WIDTH_4; 527 break; 528 case 1: 529 default: 530 bus_width = RTSX_BUS_WIDTH_1; 531 break; 532 } 533 534 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 535 return error; 536 } 537 538 int 539 rtsx_stop_sd_clock(struct rtsx_softc *sc) 540 { 541 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 542 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 543 544 return 0; 545 } 546 547 int 548 rtsx_switch_sd_clock(struct rtsx_softc *sc, u_int8_t n, int div, int mcu) 549 { 550 /* Enable SD 2.0 mode. */ 551 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); 552 553 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 554 555 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 556 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 557 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); 558 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 559 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 560 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 561 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); 562 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 563 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); 564 delay(100); 565 566 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 567 568 return 0; 569 } 570 571 /* 572 * Set or change SD bus voltage and enable or disable SD bus power. 573 * Return zero on success. 574 */ 575 int 576 rtsx_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 577 { 578 struct rtsx_softc *sc = sch; 579 int s, error = 0; 580 581 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr)); 582 583 s = splsdmmc(); 584 585 /* 586 * Disable bus power before voltage change. 587 */ 588 error = rtsx_bus_power_off(sc); 589 if (error) 590 goto ret; 591 592 delay(200); 593 594 /* If power is disabled, reset the host and return now. */ 595 if (ocr == 0) { 596 splx(s); 597 (void)rtsx_host_reset(sc); 598 return 0; 599 } 600 601 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { 602 /* Unsupported voltage level requested. */ 603 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n", 604 DEVNAME(sc), ocr)); 605 error = EINVAL; 606 goto ret; 607 } 608 609 error = rtsx_bus_power_on(sc); 610 if (error) 611 goto ret; 612 613 error = rtsx_set_bus_width(sc, 1); 614 ret: 615 splx(s); 616 return error; 617 } 618 619 /* 620 * Set or change SDCLK frequency or disable the SD clock. 621 * Return zero on success. 622 */ 623 int 624 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 625 { 626 struct rtsx_softc *sc = sch; 627 int s; 628 u_int8_t n; 629 int div; 630 int mcu; 631 int error = 0; 632 633 s = splsdmmc(); 634 635 if (freq == SDMMC_SDCLK_OFF) { 636 error = rtsx_stop_sd_clock(sc); 637 goto ret; 638 } 639 640 /* Round down to a supported frequency. */ 641 if (freq >= SDMMC_SDCLK_50MHZ) 642 freq = SDMMC_SDCLK_50MHZ; 643 else if (freq >= SDMMC_SDCLK_25MHZ) 644 freq = SDMMC_SDCLK_25MHZ; 645 else 646 freq = SDMMC_SDCLK_400KHZ; 647 648 /* 649 * Configure the clock frequency. 650 */ 651 switch (freq) { 652 case SDMMC_SDCLK_400KHZ: 653 n = 80; /* minimum */ 654 div = RTSX_CLK_DIV_8; 655 mcu = 7; 656 RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128); 657 break; 658 case SDMMC_SDCLK_25MHZ: 659 n = 100; 660 div = RTSX_CLK_DIV_4; 661 mcu = 7; 662 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 663 break; 664 case SDMMC_SDCLK_50MHZ: 665 n = 100; 666 div = RTSX_CLK_DIV_2; 667 mcu = 7; 668 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 669 break; 670 default: 671 error = EINVAL; 672 goto ret; 673 } 674 675 /* 676 * Enable SD clock. 677 */ 678 error = rtsx_switch_sd_clock(sc, n, div, mcu); 679 ret: 680 splx(s); 681 return error; 682 } 683 684 int 685 rtsx_bus_width(sdmmc_chipset_handle_t sch, int width) 686 { 687 struct rtsx_softc *sc = sch; 688 689 return rtsx_set_bus_width(sc, width); 690 } 691 692 int 693 rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val) 694 { 695 int tries = 1024; 696 u_int32_t reg; 697 698 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 699 (u_int32_t)((addr & 0x3FFF) << 16)); 700 701 while (tries--) { 702 reg = READ4(sc, RTSX_HAIMR); 703 if (!(reg & RTSX_HAIMR_BUSY)) 704 break; 705 } 706 707 *val = (reg & 0xff); 708 return (tries == 0) ? ETIMEDOUT : 0; 709 } 710 711 int 712 rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val) 713 { 714 int tries = 1024; 715 u_int32_t reg; 716 717 WRITE4(sc, RTSX_HAIMR, 718 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 719 (u_int32_t)(((addr & 0x3FFF) << 16) | 720 (mask << 8) | val)); 721 722 while (tries--) { 723 reg = READ4(sc, RTSX_HAIMR); 724 if (!(reg & RTSX_HAIMR_BUSY)) { 725 if (val != (reg & 0xff)) 726 return EIO; 727 return 0; 728 } 729 } 730 731 return ETIMEDOUT; 732 } 733 734 #ifdef notyet 735 int 736 rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val) 737 { 738 int timeout = 100000; 739 u_int8_t data0; 740 u_int8_t data1; 741 u_int8_t rwctl; 742 743 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 744 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); 745 746 while (timeout--) { 747 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 748 if (!(rwctl & RTSX_PHY_BUSY)) 749 break; 750 } 751 752 if (timeout == 0) 753 return ETIMEDOUT; 754 755 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 756 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 757 *val = data0 | (data1 << 8); 758 759 return 0; 760 } 761 #endif 762 763 int 764 rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val) 765 { 766 int timeout = 100000; 767 u_int8_t rwctl; 768 769 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 770 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 771 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 772 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); 773 774 while (timeout--) { 775 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 776 if (!(rwctl & RTSX_PHY_BUSY)) 777 break; 778 } 779 780 if (timeout == 0) 781 return ETIMEDOUT; 782 783 return 0; 784 } 785 786 int 787 rtsx_read_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 788 u_int32_t *val) 789 { 790 int tries = 1024; 791 u_int8_t data0, data1, data2, data3, rwctl; 792 793 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 794 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 795 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 796 797 while (tries--) { 798 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 799 if (!(rwctl & RTSX_CFG_BUSY)) 800 break; 801 } 802 803 if (tries == 0) 804 return EIO; 805 806 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 807 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 808 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 809 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 810 811 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 812 813 return 0; 814 } 815 816 #ifdef notyet 817 int 818 rtsx_write_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 819 u_int32_t mask, u_int32_t val) 820 { 821 int i, writemask = 0, tries = 1024; 822 u_int8_t rwctl; 823 824 for (i = 0; i < 4; i++) { 825 if (mask & 0xff) { 826 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); 827 writemask |= (1 << i); 828 } 829 mask >>= 8; 830 val >>= 8; 831 } 832 833 if (writemask) { 834 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 835 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 836 RTSX_WRITE(sc, RTSX_CFGRWCTL, 837 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); 838 } 839 840 while (tries--) { 841 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 842 if (!(rwctl & RTSX_CFG_BUSY)) 843 break; 844 } 845 846 if (tries == 0) 847 return EIO; 848 849 return 0; 850 } 851 #endif 852 853 /* Append a properly encoded host command to the host command buffer. */ 854 void 855 rtsx_hostcmd(u_int32_t *cmdbuf, int *n, u_int8_t cmd, u_int16_t reg, 856 u_int8_t mask, u_int8_t data) 857 { 858 KASSERT(*n < RTSX_HOSTCMD_MAX); 859 860 cmdbuf[(*n)++] = htole32((u_int32_t)(cmd & 0x3) << 30) | 861 ((u_int32_t)(reg & 0x3fff) << 16) | 862 ((u_int32_t)(mask) << 8) | 863 ((u_int32_t)data); 864 } 865 866 void 867 rtsx_save_regs(struct rtsx_softc *sc) 868 { 869 int s, i; 870 u_int16_t reg; 871 872 s = splsdmmc(); 873 874 i = 0; 875 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 876 (void)rtsx_read(sc, reg, &sc->regs[i++]); 877 for (reg = 0xFD52; reg < 0xFD69; reg++) 878 (void)rtsx_read(sc, reg, &sc->regs[i++]); 879 for (reg = 0xFE20; reg < 0xFE34; reg++) 880 (void)rtsx_read(sc, reg, &sc->regs[i++]); 881 882 sc->regs4[0] = READ4(sc, RTSX_HCBAR); 883 sc->regs4[1] = READ4(sc, RTSX_HCBCTLR); 884 sc->regs4[2] = READ4(sc, RTSX_HDBAR); 885 sc->regs4[3] = READ4(sc, RTSX_HDBCTLR); 886 sc->regs4[4] = READ4(sc, RTSX_HAIMR); 887 sc->regs4[5] = READ4(sc, RTSX_BIER); 888 /* Not saving RTSX_BIPR. */ 889 890 splx(s); 891 } 892 893 void 894 rtsx_restore_regs(struct rtsx_softc *sc) 895 { 896 int s, i; 897 u_int16_t reg; 898 899 s = splsdmmc(); 900 901 WRITE4(sc, RTSX_HCBAR, sc->regs4[0]); 902 WRITE4(sc, RTSX_HCBCTLR, sc->regs4[1]); 903 WRITE4(sc, RTSX_HDBAR, sc->regs4[2]); 904 WRITE4(sc, RTSX_HDBCTLR, sc->regs4[3]); 905 WRITE4(sc, RTSX_HAIMR, sc->regs4[4]); 906 WRITE4(sc, RTSX_BIER, sc->regs4[5]); 907 /* Not writing RTSX_BIPR since doing so would clear it. */ 908 909 i = 0; 910 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 911 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 912 for (reg = 0xFD52; reg < 0xFD69; reg++) 913 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 914 for (reg = 0xFE20; reg < 0xFE34; reg++) 915 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 916 917 splx(s); 918 } 919 920 u_int8_t 921 rtsx_response_type(u_int16_t sdmmc_rsp) 922 { 923 int i; 924 struct rsp_type { 925 u_int16_t sdmmc_rsp; 926 u_int8_t rtsx_rsp; 927 } rsp_types[] = { 928 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, 929 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 930 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 931 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 932 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 933 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 934 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 935 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 936 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 937 }; 938 939 for (i = 0; i < nitems(rsp_types); i++) { 940 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) 941 return rsp_types[i].rtsx_rsp; 942 } 943 944 return 0; 945 } 946 947 int 948 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) 949 { 950 int s; 951 952 s = splsdmmc(); 953 954 /* Tell the chip where the command buffer is and run the commands. */ 955 WRITE4(sc, RTSX_HCBAR, sc->dmap_cmd->dm_segs[0].ds_addr); 956 WRITE4(sc, RTSX_HCBCTLR, 957 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 958 959 splx(s); 960 961 return 0; 962 } 963 964 int 965 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, u_int32_t *cmdbuf) 966 { 967 caddr_t datakvap; 968 bus_dma_segment_t segs; 969 int ncmd, s, dma_dir, error, rsegs, tmode; 970 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 971 u_int8_t cfg2; 972 973 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc), 974 read ? "read" : "write", 975 cmd->c_datalen, cmd->c_blklen)); 976 977 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { 978 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 979 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); 980 return ENOMEM; 981 } 982 983 /* Configure DMA transfer mode parameters. */ 984 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | 985 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 986 if (read) { 987 dma_dir = RTSX_DMA_DIR_FROM_CARD; 988 /* Use transfer mode AUTO_READ3, which assumes we've already 989 * sent the read command and gotten the response, and will 990 * send CMD 12 manually after reading multiple blocks. */ 991 tmode = RTSX_TM_AUTO_READ3; 992 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 993 } else { 994 dma_dir = RTSX_DMA_DIR_TO_CARD; 995 /* Use transfer mode AUTO_WRITE3, which assumes we've already 996 * sent the write command and gotten the response, and will 997 * send CMD 12 manually after writing multiple blocks. */ 998 tmode = RTSX_TM_AUTO_WRITE3; 999 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 1000 } 1001 1002 ncmd = 0; 1003 1004 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 1005 0xff, cfg2); 1006 1007 /* Queue commands to configure data transfer size. */ 1008 rtsx_hostcmd(cmdbuf, &ncmd, 1009 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 0xff, 1010 (cmd->c_blklen & 0xff)); 1011 rtsx_hostcmd(cmdbuf, &ncmd, 1012 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 0xff, 1013 (cmd->c_blklen >> 8)); 1014 rtsx_hostcmd(cmdbuf, &ncmd, 1015 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 0xff, 1016 ((cmd->c_datalen / cmd->c_blklen) & 0xff)); 1017 rtsx_hostcmd(cmdbuf, &ncmd, 1018 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 0xff, 1019 ((cmd->c_datalen / cmd->c_blklen) >> 8)); 1020 1021 /* Use the DMA ring buffer for commands which transfer data. */ 1022 rtsx_hostcmd(cmdbuf, &ncmd, 1023 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 0x01, RTSX_RING_BUFFER); 1024 1025 /* Configure DMA controller. */ 1026 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 1027 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 1028 rtsx_hostcmd(cmdbuf, &ncmd, 1029 RTSX_WRITE_REG_CMD, RTSX_DMATC3, 0xff, cmd->c_datalen >> 24); 1030 rtsx_hostcmd(cmdbuf, &ncmd, 1031 RTSX_WRITE_REG_CMD, RTSX_DMATC2, 0xff, cmd->c_datalen >> 16); 1032 rtsx_hostcmd(cmdbuf, &ncmd, 1033 RTSX_WRITE_REG_CMD, RTSX_DMATC1, 0xff, cmd->c_datalen >> 8); 1034 rtsx_hostcmd(cmdbuf, &ncmd, 1035 RTSX_WRITE_REG_CMD, RTSX_DMATC0, 0xff, cmd->c_datalen); 1036 rtsx_hostcmd(cmdbuf, &ncmd, 1037 RTSX_WRITE_REG_CMD, RTSX_DMACTL, 1038 0x03 | RTSX_DMA_PACK_SIZE_MASK, 1039 dma_dir | RTSX_DMA_EN | RTSX_DMA_512); 1040 1041 /* Queue commands to perform SD transfer. */ 1042 rtsx_hostcmd(cmdbuf, &ncmd, 1043 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1044 0xff, tmode | RTSX_SD_TRANSFER_START); 1045 rtsx_hostcmd(cmdbuf, &ncmd, 1046 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1047 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1048 1049 error = rtsx_hostcmd_send(sc, ncmd); 1050 if (error) 1051 goto ret; 1052 1053 /* Allocate and map DMA memory for data transfer. */ 1054 error = bus_dmamem_alloc(sc->dmat, cmd->c_datalen, 0, 0, &segs, 1, 1055 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1056 if (error) { 1057 DPRINTF(3, ("%s: could not allocate %d bytes\n", 1058 DEVNAME(sc), cmd->c_datalen)); 1059 goto ret; 1060 } 1061 error = bus_dmamem_map(sc->dmat, &segs, rsegs, cmd->c_datalen, 1062 &datakvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1063 if (error) { 1064 DPRINTF(3, ("%s: could not map data buffer\n", DEVNAME(sc))); 1065 goto free_databuf; 1066 } 1067 1068 /* If this is a write, copy data from sdmmc-provided buffer. */ 1069 if (!read) 1070 memcpy(datakvap, cmd->c_data, cmd->c_datalen); 1071 1072 /* Load the data buffer and sync it. */ 1073 error = bus_dmamap_load(sc->dmat, sc->dmap_data, datakvap, 1074 cmd->c_datalen, NULL, BUS_DMA_WAITOK); 1075 if (error) { 1076 DPRINTF(3, ("%s: could not load DMA map\n", DEVNAME(sc))); 1077 goto unmap_databuf; 1078 } 1079 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1080 BUS_DMASYNC_PREREAD); 1081 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1082 BUS_DMASYNC_PREWRITE); 1083 1084 s = splsdmmc(); 1085 1086 /* Tell the chip where the data buffer is and run the transfer. */ 1087 WRITE4(sc, RTSX_HDBAR, sc->dmap_data->dm_segs[0].ds_addr); 1088 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 1089 (sc->dmap_data->dm_segs[0].ds_len & 0x00ffffff)); 1090 1091 splx(s); 1092 1093 /* Wait for completion. */ 1094 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz); 1095 if (error) 1096 goto unload_databuf; 1097 1098 /* Sync and unload data DMA buffer. */ 1099 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1100 BUS_DMASYNC_POSTREAD); 1101 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1102 BUS_DMASYNC_POSTWRITE); 1103 1104 unload_databuf: 1105 bus_dmamap_unload(sc->dmat, sc->dmap_data); 1106 1107 /* If this is a read, copy data into sdmmc-provided buffer. */ 1108 if (error == 0 && read) 1109 memcpy(cmd->c_data, datakvap, cmd->c_datalen); 1110 1111 /* Free DMA data buffer. */ 1112 unmap_databuf: 1113 bus_dmamem_unmap(sc->dmat, datakvap, cmd->c_datalen); 1114 free_databuf: 1115 bus_dmamem_free(sc->dmat, &segs, rsegs); 1116 ret: 1117 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error)); 1118 return error; 1119 } 1120 1121 void 1122 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1123 { 1124 struct rtsx_softc *sc = sch; 1125 bus_dma_segment_t segs; 1126 int rsegs; 1127 caddr_t cmdkvap; 1128 u_int32_t *cmdbuf; 1129 u_int8_t rsp_type; 1130 u_int16_t r; 1131 int ncmd; 1132 int error = 0; 1133 1134 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode)); 1135 1136 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 1137 if (cmd->c_opcode == SD_IO_SEND_OP_COND && 1138 !ISSET(sc->flags, RTSX_F_SDIO_SUPPORT)) { 1139 error = ENOTSUP; 1140 goto ret; 1141 } 1142 1143 rsp_type = rtsx_response_type(cmd->c_flags & 0xff00); 1144 if (rsp_type == 0) { 1145 printf("%s: unknown response type 0x%x\n", DEVNAME(sc), 1146 (cmd->c_flags & 0xff00)); 1147 error = EINVAL; 1148 goto ret; 1149 } 1150 1151 /* Allocate and map the host command buffer. */ 1152 error = bus_dmamem_alloc(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, &segs, 1, 1153 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1154 if (error) 1155 goto ret; 1156 error = bus_dmamem_map(sc->dmat, &segs, rsegs, RTSX_HOSTCMD_BUFSIZE, 1157 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1158 if (error) 1159 goto free_cmdbuf; 1160 1161 /* The command buffer queues commands the host controller will 1162 * run asynchronously. */ 1163 cmdbuf = (u_int32_t *)cmdkvap; 1164 ncmd = 0; 1165 1166 /* Queue commands to set SD command index and argument. */ 1167 rtsx_hostcmd(cmdbuf, &ncmd, 1168 RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode); 1169 rtsx_hostcmd(cmdbuf, &ncmd, 1170 RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 0xff, cmd->c_arg >> 24); 1171 rtsx_hostcmd(cmdbuf, &ncmd, 1172 RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 0xff, cmd->c_arg >> 16); 1173 rtsx_hostcmd(cmdbuf, &ncmd, 1174 RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 0xff, cmd->c_arg >> 8); 1175 rtsx_hostcmd(cmdbuf, &ncmd, 1176 RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 0xff, cmd->c_arg); 1177 1178 /* Queue command to set response type. */ 1179 rtsx_hostcmd(cmdbuf, &ncmd, 1180 RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 1181 1182 /* Use the ping-pong buffer for commands which do not transfer data. */ 1183 rtsx_hostcmd(cmdbuf, &ncmd, 1184 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1185 0x01, RTSX_PINGPONG_BUFFER); 1186 1187 /* Queue commands to perform SD transfer. */ 1188 rtsx_hostcmd(cmdbuf, &ncmd, 1189 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1190 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 1191 rtsx_hostcmd(cmdbuf, &ncmd, 1192 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1193 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 1194 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 1195 1196 /* Queue commands to read back card status response.*/ 1197 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 1198 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) 1199 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1200 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, 1201 0, 0); 1202 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 1203 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) 1204 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1205 } 1206 1207 /* Load and sync command DMA buffer. */ 1208 error = bus_dmamap_load(sc->dmat, sc->dmap_cmd, cmdkvap, 1209 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); 1210 if (error) 1211 goto unmap_cmdbuf; 1212 1213 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1214 BUS_DMASYNC_PREREAD); 1215 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1216 BUS_DMASYNC_PREWRITE); 1217 1218 /* Run the command queue and wait for completion. */ 1219 error = rtsx_hostcmd_send(sc, ncmd); 1220 if (error == 0) 1221 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz); 1222 if (error) 1223 goto unload_cmdbuf; 1224 1225 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1226 BUS_DMASYNC_POSTREAD); 1227 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1228 BUS_DMASYNC_POSTWRITE); 1229 1230 /* Copy card response into sdmmc response buffer. */ 1231 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1232 /* Copy bytes like sdhc(4), which on little-endian uses 1233 * different byte order for short and long responses... */ 1234 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1235 memcpy(cmd->c_resp, cmdkvap + 1, sizeof(cmd->c_resp)); 1236 } else { 1237 /* First byte is CHECK_REG_CMD return value, second 1238 * one is the command op code -- we skip those. */ 1239 cmd->c_resp[0] = 1240 ((betoh32(cmdbuf[0]) & 0x0000ffff) << 16) | 1241 ((betoh32(cmdbuf[1]) & 0xffff0000) >> 16); 1242 } 1243 } 1244 1245 if (cmd->c_data) { 1246 error = rtsx_xfer(sc, cmd, cmdbuf); 1247 if (error) { 1248 u_int8_t stat1; 1249 1250 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 1251 (stat1 & RTSX_SD_CRC_ERR)) 1252 printf("%s: CRC error\n", DEVNAME(sc)); 1253 } 1254 } 1255 1256 unload_cmdbuf: 1257 bus_dmamap_unload(sc->dmat, sc->dmap_cmd); 1258 unmap_cmdbuf: 1259 bus_dmamem_unmap(sc->dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); 1260 free_cmdbuf: 1261 bus_dmamem_free(sc->dmat, &segs, rsegs); 1262 ret: 1263 SET(cmd->c_flags, SCF_ITSDONE); 1264 cmd->c_error = error; 1265 } 1266 1267 /* Prepare for another command. */ 1268 void 1269 rtsx_soft_reset(struct rtsx_softc *sc) 1270 { 1271 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc))); 1272 1273 /* Stop command transfer. */ 1274 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 1275 1276 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, 1277 RTSX_SD_STOP|RTSX_SD_CLR_ERR); 1278 1279 /* Stop DMA transfer. */ 1280 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 1281 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 1282 1283 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 1284 } 1285 1286 int 1287 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo) 1288 { 1289 int status; 1290 int error = 0; 1291 int s; 1292 1293 mask |= RTSX_TRANS_FAIL_INT; 1294 1295 s = splsdmmc(); 1296 status = sc->intr_status & mask; 1297 while (status == 0) { 1298 if (tsleep(&sc->intr_status, PRIBIO, "rtsxintr", timo) 1299 == EWOULDBLOCK) { 1300 rtsx_soft_reset(sc); 1301 error = ETIMEDOUT; 1302 break; 1303 } 1304 status = sc->intr_status & mask; 1305 } 1306 sc->intr_status &= ~status; 1307 1308 /* Has the card disappeared? */ 1309 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1310 error = ENODEV; 1311 1312 splx(s); 1313 1314 if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) 1315 error = EIO; 1316 1317 return error; 1318 } 1319 1320 void 1321 rtsx_card_insert(struct rtsx_softc *sc) 1322 { 1323 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc))); 1324 1325 sc->flags |= RTSX_F_CARD_PRESENT; 1326 (void)rtsx_led_enable(sc); 1327 1328 /* Schedule card discovery task. */ 1329 sdmmc_needs_discover(sc->sdmmc); 1330 } 1331 1332 void 1333 rtsx_card_eject(struct rtsx_softc *sc) 1334 { 1335 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc))); 1336 1337 sc->flags &= ~RTSX_F_CARD_PRESENT; 1338 (void)rtsx_led_disable(sc); 1339 1340 /* Schedule card discovery task. */ 1341 sdmmc_needs_discover(sc->sdmmc); 1342 } 1343 1344 /* 1345 * Established by attachment driver at interrupt priority IPL_SDMMC. 1346 */ 1347 int 1348 rtsx_intr(void *arg) 1349 { 1350 struct rtsx_softc *sc = arg; 1351 u_int32_t enabled, status; 1352 1353 enabled = READ4(sc, RTSX_BIER); 1354 status = READ4(sc, RTSX_BIPR); 1355 1356 /* Ack interrupts. */ 1357 WRITE4(sc, RTSX_BIPR, status); 1358 1359 if (((enabled & status) == 0) || status == 0xffffffff) 1360 return 0; 1361 1362 if (status & RTSX_SD_INT) { 1363 if (status & RTSX_SD_EXIST) { 1364 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1365 rtsx_card_insert(sc); 1366 } else { 1367 rtsx_card_eject(sc); 1368 } 1369 } 1370 1371 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { 1372 sc->intr_status |= status; 1373 wakeup(&sc->intr_status); 1374 } 1375 1376 return 1; 1377 } 1378