1 /* $OpenBSD: rtsx.c,v 1.22 2020/02/18 00:06:56 cheloha Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Realtek RTS52xx/RTL84xx Card Reader driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/systm.h> 28 29 #include <dev/ic/rtsxreg.h> 30 #include <dev/ic/rtsxvar.h> 31 #include <dev/sdmmc/sdmmcvar.h> 32 #include <dev/sdmmc/sdmmc_ioreg.h> 33 34 /* 35 * We use three DMA buffers: a command buffer, a data buffer, and a buffer for 36 * ADMA transfer descriptors which describe scatter-gather (SG) I/O operations. 37 * 38 * The command buffer contains a command queue for the host controller, 39 * which describes SD/MMC commands to run, and other parameters. The chip 40 * runs the command queue when a special bit in the RTSX_HCBAR register is 41 * set and signals completion with the TRANS_OK interrupt. 42 * Each command is encoded as a 4 byte sequence containing command number 43 * (read, write, or check a host controller register), a register address, 44 * and a data bit-mask and value. 45 * SD/MMC commands which do not transfer any data from/to the card only use 46 * the command buffer. 47 * 48 * The smmmc stack provides DMA-safe buffers with data transfer commands. 49 * In this case we write a list of descriptors to the ADMA descriptor buffer, 50 * instructing the chip to transfer data directly from/to sdmmc DMA buffers. 51 * 52 * However, some sdmmc commands used during card initialization also carry 53 * data, and these don't come with DMA-safe buffers. In this case, we transfer 54 * data from/to the SD card via a DMA data bounce buffer. 55 * 56 * In both cases, data transfer is controlled via the RTSX_HDBAR register 57 * and completion is signalled by the TRANS_OK interrupt. 58 * 59 * The chip is unable to perform DMA above 4GB. 60 */ 61 62 #define RTSX_DMA_MAX_SEGSIZE 0x80000 63 #define RTSX_HOSTCMD_MAX 256 64 #define RTSX_HOSTCMD_BUFSIZE (sizeof(u_int32_t) * RTSX_HOSTCMD_MAX) 65 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 66 #define RTSX_ADMA_DESC_SIZE (sizeof(uint64_t) * SDMMC_MAXNSEGS) 67 68 #define READ4(sc, reg) \ 69 (bus_space_read_4((sc)->iot, (sc)->ioh, (reg))) 70 #define WRITE4(sc, reg, val) \ 71 bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val)) 72 73 #define RTSX_READ(sc, reg, val) \ 74 do { \ 75 int err = rtsx_read((sc), (reg), (val)); \ 76 if (err) \ 77 return (err); \ 78 } while (0) 79 80 #define RTSX_WRITE(sc, reg, val) \ 81 do { \ 82 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 83 if (err) \ 84 return (err); \ 85 } while (0) 86 87 #define RTSX_CLR(sc, reg, bits) \ 88 do { \ 89 int err = rtsx_write((sc), (reg), (bits), 0); \ 90 if (err) \ 91 return (err); \ 92 } while (0) 93 94 #define RTSX_SET(sc, reg, bits) \ 95 do { \ 96 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 97 if (err) \ 98 return (err); \ 99 } while (0) 100 101 int rtsx_host_reset(sdmmc_chipset_handle_t); 102 u_int32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 103 int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 104 int rtsx_card_detect(sdmmc_chipset_handle_t); 105 int rtsx_bus_power(sdmmc_chipset_handle_t, u_int32_t); 106 int rtsx_bus_clock(sdmmc_chipset_handle_t, int, int); 107 int rtsx_bus_width(sdmmc_chipset_handle_t, int); 108 void rtsx_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 109 int rtsx_init(struct rtsx_softc *, int); 110 void rtsx_soft_reset(struct rtsx_softc *); 111 int rtsx_bus_power_off(struct rtsx_softc *); 112 int rtsx_bus_power_on(struct rtsx_softc *); 113 int rtsx_set_bus_width(struct rtsx_softc *, int); 114 int rtsx_stop_sd_clock(struct rtsx_softc *); 115 int rtsx_switch_sd_clock(struct rtsx_softc *, u_int8_t, int, int); 116 int rtsx_wait_intr(struct rtsx_softc *, int, int); 117 int rtsx_read(struct rtsx_softc *, u_int16_t, u_int8_t *); 118 int rtsx_write(struct rtsx_softc *, u_int16_t, u_int8_t, u_int8_t); 119 #ifdef notyet 120 int rtsx_read_phy(struct rtsx_softc *, u_int8_t, u_int16_t *); 121 #endif 122 int rtsx_write_phy(struct rtsx_softc *, u_int8_t, u_int16_t); 123 int rtsx_read_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t *); 124 #ifdef notyet 125 int rtsx_write_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t, 126 u_int32_t); 127 #endif 128 void rtsx_hostcmd(u_int32_t *, int *, u_int8_t, u_int16_t, u_int8_t, 129 u_int8_t); 130 int rtsx_hostcmd_send(struct rtsx_softc *, int); 131 u_int8_t rtsx_response_type(u_int16_t); 132 int rtsx_xfer_exec(struct rtsx_softc *, bus_dmamap_t, int); 133 int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, u_int32_t *); 134 int rtsx_xfer_bounce(struct rtsx_softc *, struct sdmmc_command *); 135 int rtsx_xfer_adma(struct rtsx_softc *, struct sdmmc_command *); 136 void rtsx_card_insert(struct rtsx_softc *); 137 void rtsx_card_eject(struct rtsx_softc *); 138 int rtsx_led_enable(struct rtsx_softc *); 139 int rtsx_led_disable(struct rtsx_softc *); 140 void rtsx_save_regs(struct rtsx_softc *); 141 void rtsx_restore_regs(struct rtsx_softc *); 142 143 #ifdef RTSX_DEBUG 144 int rtsxdebug = 0; 145 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 146 #else 147 #define DPRINTF(n,s) do {} while(0) 148 #endif 149 150 struct sdmmc_chip_functions rtsx_functions = { 151 /* host controller reset */ 152 rtsx_host_reset, 153 /* host controller capabilities */ 154 rtsx_host_ocr, 155 rtsx_host_maxblklen, 156 /* card detection */ 157 rtsx_card_detect, 158 /* bus power and clock frequency */ 159 rtsx_bus_power, 160 rtsx_bus_clock, 161 rtsx_bus_width, 162 /* command execution */ 163 rtsx_exec_command, 164 /* card interrupt */ 165 NULL, NULL 166 }; 167 168 struct cfdriver rtsx_cd = { 169 NULL, "rtsx", DV_DULL 170 }; 171 172 /* 173 * Called by attachment driver. 174 */ 175 int 176 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, 177 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) 178 { 179 struct sdmmcbus_attach_args saa; 180 u_int32_t sdio_cfg; 181 int rsegs; 182 183 sc->iot = iot; 184 sc->ioh = ioh; 185 sc->dmat = dmat; 186 sc->flags = flags; 187 188 if (rtsx_init(sc, 1)) 189 return 1; 190 191 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 192 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 193 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 194 sc->flags |= RTSX_F_SDIO_SUPPORT; 195 } 196 197 if (bus_dmamap_create(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 1, 198 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 199 &sc->dmap_cmd) != 0) 200 return 1; 201 if (bus_dmamap_create(sc->dmat, RTSX_DMA_DATA_BUFSIZE, 1, 202 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 203 &sc->dmap_data) != 0) 204 goto destroy_cmd; 205 if (bus_dmamap_create(sc->dmat, RTSX_ADMA_DESC_SIZE, 1, 206 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 207 &sc->dmap_adma) != 0) 208 goto destroy_data; 209 if (bus_dmamem_alloc(sc->dmat, RTSX_ADMA_DESC_SIZE, 0, 0, 210 sc->adma_segs, 1, &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO)) 211 goto destroy_adma; 212 if (bus_dmamem_map(sc->dmat, sc->adma_segs, rsegs, RTSX_ADMA_DESC_SIZE, 213 &sc->admabuf, BUS_DMA_WAITOK|BUS_DMA_COHERENT)) 214 goto free_adma; 215 216 /* 217 * Attach the generic SD/MMC bus driver. (The bus driver must 218 * not invoke any chipset functions before it is attached.) 219 */ 220 bzero(&saa, sizeof(saa)); 221 saa.saa_busname = "sdmmc"; 222 saa.sct = &rtsx_functions; 223 saa.sch = sc; 224 saa.flags = SMF_STOP_AFTER_MULTIPLE; 225 saa.caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_DMA; 226 saa.dmat = sc->dmat; 227 228 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 229 if (sc->sdmmc == NULL) 230 goto unmap_adma; 231 232 /* Now handle cards discovered during attachment. */ 233 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 234 rtsx_card_insert(sc); 235 236 return 0; 237 238 unmap_adma: 239 bus_dmamem_unmap(sc->dmat, sc->admabuf, RTSX_ADMA_DESC_SIZE); 240 free_adma: 241 bus_dmamem_free(sc->dmat, sc->adma_segs, rsegs); 242 destroy_adma: 243 bus_dmamap_destroy(sc->dmat, sc->dmap_adma); 244 destroy_data: 245 bus_dmamap_destroy(sc->dmat, sc->dmap_data); 246 destroy_cmd: 247 bus_dmamap_destroy(sc->dmat, sc->dmap_cmd); 248 return 1; 249 } 250 251 int 252 rtsx_init(struct rtsx_softc *sc, int attaching) 253 { 254 u_int32_t status; 255 u_int8_t version; 256 int error; 257 258 /* Read IC version from dummy register. */ 259 if (sc->flags & RTSX_F_5229) { 260 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 261 switch (version & 0x0F) { 262 case RTSX_IC_VERSION_A: 263 case RTSX_IC_VERSION_B: 264 case RTSX_IC_VERSION_D: 265 break; 266 case RTSX_IC_VERSION_C: 267 sc->flags |= RTSX_F_5229_TYPE_C; 268 break; 269 default: 270 printf("rtsx_init: unknown ic %02x\n", version); 271 return (1); 272 } 273 } 274 275 /* Enable interrupt write-clear (default is read-clear). */ 276 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 277 278 /* Clear any pending interrupts. */ 279 status = READ4(sc, RTSX_BIPR); 280 WRITE4(sc, RTSX_BIPR, status); 281 282 /* Check for cards already inserted at attach time. */ 283 if (attaching && (status & RTSX_SD_EXIST)) 284 sc->flags |= RTSX_F_CARD_PRESENT; 285 286 /* Enable interrupts. */ 287 WRITE4(sc, RTSX_BIER, 288 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); 289 290 /* Power on SSC clock. */ 291 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 292 delay(200); 293 294 /* XXX magic numbers from linux driver */ 295 if (sc->flags & RTSX_F_5209) 296 error = rtsx_write_phy(sc, 0x00, 0xB966); 297 else 298 error = rtsx_write_phy(sc, 0x00, 0xBA42); 299 if (error) { 300 printf("%s: cannot write phy register\n", DEVNAME(sc)); 301 return (1); 302 } 303 304 RTSX_SET(sc, RTSX_CLK_DIV, 0x07); 305 306 /* Disable sleep mode. */ 307 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 308 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 309 310 /* Disable card clock. */ 311 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 312 313 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 314 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); 315 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); 316 317 /* Enable SSC clock. */ 318 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 319 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 320 321 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); 322 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); 323 324 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 325 326 /* Set RC oscillator to 400K. */ 327 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 328 329 /* Request clock by driving CLKREQ pin to zero. */ 330 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); 331 332 /* Set up LED GPIO. */ 333 if (sc->flags & RTSX_F_5209) { 334 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 335 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 336 } else { 337 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 338 /* Switch LDO3318 source from DV33 to 3V3. */ 339 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 340 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); 341 /* Set default OLT blink period. */ 342 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); 343 } 344 345 return (0); 346 } 347 348 int 349 rtsx_activate(struct device *self, int act) 350 { 351 struct rtsx_softc *sc = (struct rtsx_softc *)self; 352 int rv = 0; 353 354 switch (act) { 355 case DVACT_SUSPEND: 356 rv = config_activate_children(self, act); 357 rtsx_save_regs(sc); 358 break; 359 case DVACT_RESUME: 360 rtsx_restore_regs(sc); 361 362 /* Handle cards ejected/inserted during suspend. */ 363 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) 364 rtsx_card_insert(sc); 365 else 366 rtsx_card_eject(sc); 367 368 rv = config_activate_children(self, act); 369 break; 370 default: 371 rv = config_activate_children(self, act); 372 break; 373 } 374 return (rv); 375 } 376 377 int 378 rtsx_led_enable(struct rtsx_softc *sc) 379 { 380 if (sc->flags & RTSX_F_5209) { 381 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 382 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 383 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 384 } else { 385 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 386 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 387 } 388 389 return 0; 390 } 391 392 int 393 rtsx_led_disable(struct rtsx_softc *sc) 394 { 395 if (sc->flags & RTSX_F_5209) { 396 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 397 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 398 } else { 399 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 400 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 401 } 402 403 return 0; 404 } 405 406 /* 407 * Reset the host controller. Called during initialization, when 408 * cards are removed, upon resume, and during error recovery. 409 */ 410 int 411 rtsx_host_reset(sdmmc_chipset_handle_t sch) 412 { 413 struct rtsx_softc *sc = sch; 414 int s; 415 416 DPRINTF(1,("%s: host reset\n", DEVNAME(sc))); 417 418 s = splsdmmc(); 419 420 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 421 rtsx_soft_reset(sc); 422 423 if (rtsx_init(sc, 0)) { 424 splx(s); 425 return 1; 426 } 427 428 splx(s); 429 return 0; 430 } 431 432 u_int32_t 433 rtsx_host_ocr(sdmmc_chipset_handle_t sch) 434 { 435 return RTSX_SUPPORT_VOLTAGE; 436 } 437 438 int 439 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) 440 { 441 return 512; 442 } 443 444 /* 445 * Return non-zero if the card is currently inserted. 446 */ 447 int 448 rtsx_card_detect(sdmmc_chipset_handle_t sch) 449 { 450 struct rtsx_softc *sc = sch; 451 452 return ISSET(sc->flags, RTSX_F_CARD_PRESENT); 453 } 454 455 /* 456 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 457 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 458 * it is a mask of *enabled* gates. 459 */ 460 461 int 462 rtsx_bus_power_off(struct rtsx_softc *sc) 463 { 464 int error; 465 u_int8_t disable3; 466 467 error = rtsx_stop_sd_clock(sc); 468 if (error) 469 return error; 470 471 /* Disable SD output. */ 472 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); 473 474 /* Turn off power. */ 475 disable3 = RTSX_PULL_CTL_DISABLE3; 476 if (sc->flags & RTSX_F_5209) 477 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 478 else { 479 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | 480 RTSX_LDO3318_VCC2); 481 if (sc->flags & RTSX_F_5229_TYPE_C) 482 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; 483 } 484 485 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 486 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 487 488 /* Disable pull control. */ 489 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 490 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 491 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); 492 493 return 0; 494 } 495 496 int 497 rtsx_bus_power_on(struct rtsx_softc *sc) 498 { 499 u_int8_t enable3; 500 int err; 501 502 if (sc->flags & RTSX_F_525A) { 503 err = rtsx_write(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, 504 RTSX_LDO_VCC_3V3); 505 if (err) 506 return (err); 507 } 508 509 /* Select SD card. */ 510 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); 511 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); 512 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 513 514 /* Enable pull control. */ 515 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 516 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 517 if (sc->flags & RTSX_F_5229_TYPE_C) 518 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; 519 else 520 enable3 = RTSX_PULL_CTL_ENABLE3; 521 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); 522 523 /* 524 * To avoid a current peak, enable card power in two phases with a 525 * delay in between. 526 */ 527 528 /* Partial power. */ 529 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); 530 if (sc->flags & RTSX_F_5209) 531 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); 532 else 533 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); 534 535 delay(200); 536 537 /* Full power. */ 538 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 539 if (sc->flags & RTSX_F_5209) 540 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 541 else 542 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); 543 544 /* Enable SD card output. */ 545 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 546 547 return 0; 548 } 549 550 int 551 rtsx_set_bus_width(struct rtsx_softc *sc, int w) 552 { 553 u_int32_t bus_width; 554 int error; 555 556 switch (w) { 557 case 8: 558 bus_width = RTSX_BUS_WIDTH_8; 559 break; 560 case 4: 561 bus_width = RTSX_BUS_WIDTH_4; 562 break; 563 case 1: 564 default: 565 bus_width = RTSX_BUS_WIDTH_1; 566 break; 567 } 568 569 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 570 return error; 571 } 572 573 int 574 rtsx_stop_sd_clock(struct rtsx_softc *sc) 575 { 576 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 577 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 578 579 return 0; 580 } 581 582 int 583 rtsx_switch_sd_clock(struct rtsx_softc *sc, u_int8_t n, int div, int mcu) 584 { 585 /* Enable SD 2.0 mode. */ 586 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); 587 588 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 589 590 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 591 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 592 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); 593 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 594 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 595 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 596 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); 597 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 598 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); 599 delay(100); 600 601 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 602 603 return 0; 604 } 605 606 /* 607 * Set or change SD bus voltage and enable or disable SD bus power. 608 * Return zero on success. 609 */ 610 int 611 rtsx_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 612 { 613 struct rtsx_softc *sc = sch; 614 int s, error = 0; 615 616 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr)); 617 618 s = splsdmmc(); 619 620 /* 621 * Disable bus power before voltage change. 622 */ 623 error = rtsx_bus_power_off(sc); 624 if (error) 625 goto ret; 626 627 delay(200); 628 629 /* If power is disabled, reset the host and return now. */ 630 if (ocr == 0) { 631 splx(s); 632 (void)rtsx_host_reset(sc); 633 return 0; 634 } 635 636 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { 637 /* Unsupported voltage level requested. */ 638 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n", 639 DEVNAME(sc), ocr)); 640 error = EINVAL; 641 goto ret; 642 } 643 644 error = rtsx_bus_power_on(sc); 645 if (error) 646 goto ret; 647 648 error = rtsx_set_bus_width(sc, 1); 649 ret: 650 splx(s); 651 return error; 652 } 653 654 /* 655 * Set or change SDCLK frequency or disable the SD clock. 656 * Return zero on success. 657 */ 658 int 659 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 660 { 661 struct rtsx_softc *sc = sch; 662 int s; 663 u_int8_t n; 664 int div; 665 int mcu; 666 int error = 0; 667 668 s = splsdmmc(); 669 670 if (freq == SDMMC_SDCLK_OFF) { 671 error = rtsx_stop_sd_clock(sc); 672 goto ret; 673 } 674 675 /* Round down to a supported frequency. */ 676 if (freq >= SDMMC_SDCLK_50MHZ) 677 freq = SDMMC_SDCLK_50MHZ; 678 else if (freq >= SDMMC_SDCLK_25MHZ) 679 freq = SDMMC_SDCLK_25MHZ; 680 else 681 freq = SDMMC_SDCLK_400KHZ; 682 683 /* 684 * Configure the clock frequency. 685 */ 686 switch (freq) { 687 case SDMMC_SDCLK_400KHZ: 688 n = 80; /* minimum */ 689 div = RTSX_CLK_DIV_8; 690 mcu = 7; 691 RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128); 692 break; 693 case SDMMC_SDCLK_25MHZ: 694 n = 100; 695 div = RTSX_CLK_DIV_4; 696 mcu = 7; 697 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 698 break; 699 case SDMMC_SDCLK_50MHZ: 700 n = 100; 701 div = RTSX_CLK_DIV_2; 702 mcu = 7; 703 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 704 break; 705 default: 706 error = EINVAL; 707 goto ret; 708 } 709 710 /* 711 * Enable SD clock. 712 */ 713 error = rtsx_switch_sd_clock(sc, n, div, mcu); 714 ret: 715 splx(s); 716 return error; 717 } 718 719 int 720 rtsx_bus_width(sdmmc_chipset_handle_t sch, int width) 721 { 722 struct rtsx_softc *sc = sch; 723 724 return rtsx_set_bus_width(sc, width); 725 } 726 727 int 728 rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val) 729 { 730 int tries = 1024; 731 u_int32_t reg; 732 733 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 734 (u_int32_t)((addr & 0x3FFF) << 16)); 735 736 while (tries--) { 737 reg = READ4(sc, RTSX_HAIMR); 738 if (!(reg & RTSX_HAIMR_BUSY)) 739 break; 740 } 741 742 *val = (reg & 0xff); 743 return (tries == 0) ? ETIMEDOUT : 0; 744 } 745 746 int 747 rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val) 748 { 749 int tries = 1024; 750 u_int32_t reg; 751 752 WRITE4(sc, RTSX_HAIMR, 753 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 754 (u_int32_t)(((addr & 0x3FFF) << 16) | 755 (mask << 8) | val)); 756 757 while (tries--) { 758 reg = READ4(sc, RTSX_HAIMR); 759 if (!(reg & RTSX_HAIMR_BUSY)) { 760 if (val != (reg & 0xff)) 761 return EIO; 762 return 0; 763 } 764 } 765 766 return ETIMEDOUT; 767 } 768 769 #ifdef notyet 770 int 771 rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val) 772 { 773 int timeout = 100000; 774 u_int8_t data0; 775 u_int8_t data1; 776 u_int8_t rwctl; 777 778 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 779 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); 780 781 while (timeout--) { 782 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 783 if (!(rwctl & RTSX_PHY_BUSY)) 784 break; 785 } 786 787 if (timeout == 0) 788 return ETIMEDOUT; 789 790 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 791 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 792 *val = data0 | (data1 << 8); 793 794 return 0; 795 } 796 #endif 797 798 int 799 rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val) 800 { 801 int timeout = 100000; 802 u_int8_t rwctl; 803 804 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 805 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 806 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 807 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); 808 809 while (timeout--) { 810 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 811 if (!(rwctl & RTSX_PHY_BUSY)) 812 break; 813 } 814 815 if (timeout == 0) 816 return ETIMEDOUT; 817 818 return 0; 819 } 820 821 int 822 rtsx_read_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 823 u_int32_t *val) 824 { 825 int tries = 1024; 826 u_int8_t data0, data1, data2, data3, rwctl; 827 828 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 829 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 830 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 831 832 while (tries--) { 833 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 834 if (!(rwctl & RTSX_CFG_BUSY)) 835 break; 836 } 837 838 if (tries == 0) 839 return EIO; 840 841 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 842 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 843 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 844 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 845 846 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 847 848 return 0; 849 } 850 851 #ifdef notyet 852 int 853 rtsx_write_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 854 u_int32_t mask, u_int32_t val) 855 { 856 int i, writemask = 0, tries = 1024; 857 u_int8_t rwctl; 858 859 for (i = 0; i < 4; i++) { 860 if (mask & 0xff) { 861 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); 862 writemask |= (1 << i); 863 } 864 mask >>= 8; 865 val >>= 8; 866 } 867 868 if (writemask) { 869 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 870 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 871 RTSX_WRITE(sc, RTSX_CFGRWCTL, 872 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); 873 } 874 875 while (tries--) { 876 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 877 if (!(rwctl & RTSX_CFG_BUSY)) 878 break; 879 } 880 881 if (tries == 0) 882 return EIO; 883 884 return 0; 885 } 886 #endif 887 888 /* Append a properly encoded host command to the host command buffer. */ 889 void 890 rtsx_hostcmd(u_int32_t *cmdbuf, int *n, u_int8_t cmd, u_int16_t reg, 891 u_int8_t mask, u_int8_t data) 892 { 893 KASSERT(*n < RTSX_HOSTCMD_MAX); 894 895 cmdbuf[(*n)++] = htole32((u_int32_t)(cmd & 0x3) << 30) | 896 ((u_int32_t)(reg & 0x3fff) << 16) | 897 ((u_int32_t)(mask) << 8) | 898 ((u_int32_t)data); 899 } 900 901 void 902 rtsx_save_regs(struct rtsx_softc *sc) 903 { 904 int s, i; 905 u_int16_t reg; 906 907 s = splsdmmc(); 908 909 i = 0; 910 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 911 (void)rtsx_read(sc, reg, &sc->regs[i++]); 912 for (reg = 0xFD52; reg < 0xFD69; reg++) 913 (void)rtsx_read(sc, reg, &sc->regs[i++]); 914 for (reg = 0xFE20; reg < 0xFE34; reg++) 915 (void)rtsx_read(sc, reg, &sc->regs[i++]); 916 917 sc->regs4[0] = READ4(sc, RTSX_HCBAR); 918 sc->regs4[1] = READ4(sc, RTSX_HCBCTLR); 919 sc->regs4[2] = READ4(sc, RTSX_HDBAR); 920 sc->regs4[3] = READ4(sc, RTSX_HDBCTLR); 921 sc->regs4[4] = READ4(sc, RTSX_HAIMR); 922 sc->regs4[5] = READ4(sc, RTSX_BIER); 923 /* Not saving RTSX_BIPR. */ 924 925 splx(s); 926 } 927 928 void 929 rtsx_restore_regs(struct rtsx_softc *sc) 930 { 931 int s, i; 932 u_int16_t reg; 933 934 s = splsdmmc(); 935 936 WRITE4(sc, RTSX_HCBAR, sc->regs4[0]); 937 WRITE4(sc, RTSX_HCBCTLR, sc->regs4[1]); 938 WRITE4(sc, RTSX_HDBAR, sc->regs4[2]); 939 WRITE4(sc, RTSX_HDBCTLR, sc->regs4[3]); 940 WRITE4(sc, RTSX_HAIMR, sc->regs4[4]); 941 WRITE4(sc, RTSX_BIER, sc->regs4[5]); 942 /* Not writing RTSX_BIPR since doing so would clear it. */ 943 944 i = 0; 945 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 946 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 947 for (reg = 0xFD52; reg < 0xFD69; reg++) 948 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 949 for (reg = 0xFE20; reg < 0xFE34; reg++) 950 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 951 952 splx(s); 953 } 954 955 u_int8_t 956 rtsx_response_type(u_int16_t sdmmc_rsp) 957 { 958 int i; 959 struct rsp_type { 960 u_int16_t sdmmc_rsp; 961 u_int8_t rtsx_rsp; 962 } rsp_types[] = { 963 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, 964 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 965 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 966 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 967 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 968 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 969 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 970 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 971 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 972 }; 973 974 for (i = 0; i < nitems(rsp_types); i++) { 975 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) 976 return rsp_types[i].rtsx_rsp; 977 } 978 979 return 0; 980 } 981 982 int 983 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) 984 { 985 int s; 986 987 s = splsdmmc(); 988 989 /* Tell the chip where the command buffer is and run the commands. */ 990 WRITE4(sc, RTSX_HCBAR, sc->dmap_cmd->dm_segs[0].ds_addr); 991 WRITE4(sc, RTSX_HCBCTLR, 992 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 993 994 splx(s); 995 996 return 0; 997 } 998 999 int 1000 rtsx_xfer_exec(struct rtsx_softc *sc, bus_dmamap_t dmap, int dmaflags) 1001 { 1002 int s = splsdmmc(); 1003 1004 /* Tell the chip where the data buffer is and run the transfer. */ 1005 WRITE4(sc, RTSX_HDBAR, dmap->dm_segs[0].ds_addr); 1006 WRITE4(sc, RTSX_HDBCTLR, dmaflags); 1007 1008 splx(s); 1009 1010 /* Wait for completion. */ 1011 return rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10); 1012 } 1013 1014 int 1015 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, u_int32_t *cmdbuf) 1016 { 1017 int ncmd, dma_dir, error, tmode; 1018 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 1019 u_int8_t cfg2; 1020 1021 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc), 1022 read ? "read" : "write", 1023 cmd->c_datalen, cmd->c_blklen)); 1024 1025 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { 1026 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 1027 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); 1028 return ENOMEM; 1029 } 1030 1031 /* Configure DMA transfer mode parameters. */ 1032 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | 1033 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 1034 if (read) { 1035 dma_dir = RTSX_DMA_DIR_FROM_CARD; 1036 /* Use transfer mode AUTO_READ3, which assumes we've already 1037 * sent the read command and gotten the response, and will 1038 * send CMD 12 manually after reading multiple blocks. */ 1039 tmode = RTSX_TM_AUTO_READ3; 1040 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 1041 } else { 1042 dma_dir = RTSX_DMA_DIR_TO_CARD; 1043 /* Use transfer mode AUTO_WRITE3, which assumes we've already 1044 * sent the write command and gotten the response, and will 1045 * send CMD 12 manually after writing multiple blocks. */ 1046 tmode = RTSX_TM_AUTO_WRITE3; 1047 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 1048 } 1049 1050 ncmd = 0; 1051 1052 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 1053 0xff, cfg2); 1054 1055 /* Queue commands to configure data transfer size. */ 1056 rtsx_hostcmd(cmdbuf, &ncmd, 1057 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 0xff, 1058 (cmd->c_blklen & 0xff)); 1059 rtsx_hostcmd(cmdbuf, &ncmd, 1060 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 0xff, 1061 (cmd->c_blklen >> 8)); 1062 rtsx_hostcmd(cmdbuf, &ncmd, 1063 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 0xff, 1064 ((cmd->c_datalen / cmd->c_blklen) & 0xff)); 1065 rtsx_hostcmd(cmdbuf, &ncmd, 1066 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 0xff, 1067 ((cmd->c_datalen / cmd->c_blklen) >> 8)); 1068 1069 /* Use the DMA ring buffer for commands which transfer data. */ 1070 rtsx_hostcmd(cmdbuf, &ncmd, 1071 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 0x01, RTSX_RING_BUFFER); 1072 1073 /* Configure DMA controller. */ 1074 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 1075 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 1076 rtsx_hostcmd(cmdbuf, &ncmd, 1077 RTSX_WRITE_REG_CMD, RTSX_DMATC3, 0xff, cmd->c_datalen >> 24); 1078 rtsx_hostcmd(cmdbuf, &ncmd, 1079 RTSX_WRITE_REG_CMD, RTSX_DMATC2, 0xff, cmd->c_datalen >> 16); 1080 rtsx_hostcmd(cmdbuf, &ncmd, 1081 RTSX_WRITE_REG_CMD, RTSX_DMATC1, 0xff, cmd->c_datalen >> 8); 1082 rtsx_hostcmd(cmdbuf, &ncmd, 1083 RTSX_WRITE_REG_CMD, RTSX_DMATC0, 0xff, cmd->c_datalen); 1084 rtsx_hostcmd(cmdbuf, &ncmd, 1085 RTSX_WRITE_REG_CMD, RTSX_DMACTL, 1086 0x03 | RTSX_DMA_PACK_SIZE_MASK, 1087 dma_dir | RTSX_DMA_EN | RTSX_DMA_512); 1088 1089 /* Queue commands to perform SD transfer. */ 1090 rtsx_hostcmd(cmdbuf, &ncmd, 1091 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1092 0xff, tmode | RTSX_SD_TRANSFER_START); 1093 rtsx_hostcmd(cmdbuf, &ncmd, 1094 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1095 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1096 1097 error = rtsx_hostcmd_send(sc, ncmd); 1098 if (error) 1099 goto ret; 1100 1101 if (cmd->c_dmamap) 1102 error = rtsx_xfer_adma(sc, cmd); 1103 else 1104 error = rtsx_xfer_bounce(sc, cmd); 1105 ret: 1106 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error)); 1107 return error; 1108 } 1109 1110 int 1111 rtsx_xfer_bounce(struct rtsx_softc *sc, struct sdmmc_command *cmd) 1112 { 1113 caddr_t datakvap; 1114 bus_dma_segment_t segs; 1115 int rsegs, error; 1116 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 1117 1118 /* Allocate and map DMA bounce buffer for data transfer. */ 1119 error = bus_dmamem_alloc(sc->dmat, cmd->c_datalen, 0, 0, &segs, 1, 1120 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1121 if (error) { 1122 DPRINTF(3, ("%s: could not allocate %d bytes\n", 1123 DEVNAME(sc), cmd->c_datalen)); 1124 return error; 1125 } 1126 error = bus_dmamem_map(sc->dmat, &segs, rsegs, cmd->c_datalen, 1127 &datakvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1128 if (error) { 1129 DPRINTF(3, ("%s: could not map data buffer\n", DEVNAME(sc))); 1130 goto free_databuf; 1131 } 1132 1133 /* If this is a write, copy data from sdmmc-provided buffer. */ 1134 if (!read) 1135 memcpy(datakvap, cmd->c_data, cmd->c_datalen); 1136 1137 /* Load the data buffer and sync it. */ 1138 error = bus_dmamap_load(sc->dmat, sc->dmap_data, datakvap, 1139 cmd->c_datalen, NULL, BUS_DMA_WAITOK); 1140 if (error) { 1141 DPRINTF(3, ("%s: could not load DMA map\n", DEVNAME(sc))); 1142 goto unmap_databuf; 1143 } 1144 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1145 BUS_DMASYNC_PREREAD); 1146 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1147 BUS_DMASYNC_PREWRITE); 1148 1149 error = rtsx_xfer_exec(sc, sc->dmap_data, 1150 RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 1151 (cmd->c_datalen & 0x00ffffff)); 1152 if (error) 1153 goto unload_databuf; 1154 1155 /* Sync and unload data DMA buffer. */ 1156 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1157 BUS_DMASYNC_POSTREAD); 1158 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1159 BUS_DMASYNC_POSTWRITE); 1160 1161 unload_databuf: 1162 bus_dmamap_unload(sc->dmat, sc->dmap_data); 1163 1164 /* If this is a read, copy data into sdmmc-provided buffer. */ 1165 if (error == 0 && read) 1166 memcpy(cmd->c_data, datakvap, cmd->c_datalen); 1167 1168 /* Free DMA data buffer. */ 1169 unmap_databuf: 1170 bus_dmamem_unmap(sc->dmat, datakvap, cmd->c_datalen); 1171 free_databuf: 1172 bus_dmamem_free(sc->dmat, &segs, rsegs); 1173 return error; 1174 } 1175 1176 int 1177 rtsx_xfer_adma(struct rtsx_softc *sc, struct sdmmc_command *cmd) 1178 { 1179 int i, error; 1180 uint64_t *descp; 1181 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 1182 1183 /* Initialize scatter-gather transfer descriptors. */ 1184 descp = (uint64_t *)sc->admabuf; 1185 for (i = 0; i < cmd->c_dmamap->dm_nsegs; i++) { 1186 uint64_t paddr = cmd->c_dmamap->dm_segs[i].ds_addr; 1187 uint64_t len = cmd->c_dmamap->dm_segs[i].ds_len; 1188 uint8_t sgflags = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; 1189 uint64_t desc; 1190 1191 if (i == cmd->c_dmamap->dm_nsegs - 1) 1192 sgflags |= RTSX_SG_END; 1193 len &= 0x00ffffff; 1194 desc = htole64((paddr << 32) | (len << 12) | sgflags); 1195 memcpy(descp, &desc, sizeof(*descp)); 1196 descp++; 1197 } 1198 1199 error = bus_dmamap_load(sc->dmat, sc->dmap_adma, sc->admabuf, 1200 RTSX_ADMA_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1201 if (error) { 1202 DPRINTF(3, ("%s: could not load DMA map\n", DEVNAME(sc))); 1203 return error; 1204 } 1205 bus_dmamap_sync(sc->dmat, sc->dmap_adma, 0, RTSX_ADMA_DESC_SIZE, 1206 BUS_DMASYNC_PREWRITE); 1207 1208 error = rtsx_xfer_exec(sc, sc->dmap_adma, 1209 RTSX_ADMA_MODE | RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0)); 1210 1211 bus_dmamap_sync(sc->dmat, sc->dmap_adma, 0, RTSX_ADMA_DESC_SIZE, 1212 BUS_DMASYNC_POSTWRITE); 1213 1214 bus_dmamap_unload(sc->dmat, sc->dmap_adma); 1215 return error; 1216 } 1217 1218 void 1219 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1220 { 1221 struct rtsx_softc *sc = sch; 1222 bus_dma_segment_t segs; 1223 int rsegs; 1224 caddr_t cmdkvap; 1225 u_int32_t *cmdbuf; 1226 u_int8_t rsp_type; 1227 u_int16_t r; 1228 int ncmd; 1229 int error = 0; 1230 1231 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode)); 1232 1233 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 1234 if (cmd->c_opcode == SD_IO_SEND_OP_COND && 1235 !ISSET(sc->flags, RTSX_F_SDIO_SUPPORT)) { 1236 error = ENOTSUP; 1237 goto ret; 1238 } 1239 1240 rsp_type = rtsx_response_type(cmd->c_flags & 0xff00); 1241 if (rsp_type == 0) { 1242 printf("%s: unknown response type 0x%x\n", DEVNAME(sc), 1243 (cmd->c_flags & 0xff00)); 1244 error = EINVAL; 1245 goto ret; 1246 } 1247 1248 /* Allocate and map the host command buffer. */ 1249 error = bus_dmamem_alloc(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, &segs, 1, 1250 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1251 if (error) 1252 goto ret; 1253 error = bus_dmamem_map(sc->dmat, &segs, rsegs, RTSX_HOSTCMD_BUFSIZE, 1254 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1255 if (error) 1256 goto free_cmdbuf; 1257 1258 /* The command buffer queues commands the host controller will 1259 * run asynchronously. */ 1260 cmdbuf = (u_int32_t *)cmdkvap; 1261 ncmd = 0; 1262 1263 /* Queue commands to set SD command index and argument. */ 1264 rtsx_hostcmd(cmdbuf, &ncmd, 1265 RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode); 1266 rtsx_hostcmd(cmdbuf, &ncmd, 1267 RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 0xff, cmd->c_arg >> 24); 1268 rtsx_hostcmd(cmdbuf, &ncmd, 1269 RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 0xff, cmd->c_arg >> 16); 1270 rtsx_hostcmd(cmdbuf, &ncmd, 1271 RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 0xff, cmd->c_arg >> 8); 1272 rtsx_hostcmd(cmdbuf, &ncmd, 1273 RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 0xff, cmd->c_arg); 1274 1275 /* Queue command to set response type. */ 1276 rtsx_hostcmd(cmdbuf, &ncmd, 1277 RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 1278 1279 /* Use the ping-pong buffer for commands which do not transfer data. */ 1280 rtsx_hostcmd(cmdbuf, &ncmd, 1281 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1282 0x01, RTSX_PINGPONG_BUFFER); 1283 1284 /* Queue commands to perform SD transfer. */ 1285 rtsx_hostcmd(cmdbuf, &ncmd, 1286 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1287 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 1288 rtsx_hostcmd(cmdbuf, &ncmd, 1289 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1290 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 1291 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 1292 1293 /* Queue commands to read back card status response.*/ 1294 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 1295 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) 1296 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1297 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, 1298 0, 0); 1299 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 1300 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) 1301 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1302 } 1303 1304 /* Load and sync command DMA buffer. */ 1305 error = bus_dmamap_load(sc->dmat, sc->dmap_cmd, cmdkvap, 1306 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); 1307 if (error) 1308 goto unmap_cmdbuf; 1309 1310 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1311 BUS_DMASYNC_PREREAD); 1312 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1313 BUS_DMASYNC_PREWRITE); 1314 1315 /* Run the command queue and wait for completion. */ 1316 error = rtsx_hostcmd_send(sc, ncmd); 1317 if (error == 0) 1318 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 1); 1319 if (error) 1320 goto unload_cmdbuf; 1321 1322 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1323 BUS_DMASYNC_POSTREAD); 1324 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1325 BUS_DMASYNC_POSTWRITE); 1326 1327 /* Copy card response into sdmmc response buffer. */ 1328 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1329 /* Copy bytes like sdhc(4), which on little-endian uses 1330 * different byte order for short and long responses... */ 1331 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1332 memcpy(cmd->c_resp, cmdkvap + 1, sizeof(cmd->c_resp)); 1333 } else { 1334 /* First byte is CHECK_REG_CMD return value, second 1335 * one is the command op code -- we skip those. */ 1336 cmd->c_resp[0] = 1337 ((betoh32(cmdbuf[0]) & 0x0000ffff) << 16) | 1338 ((betoh32(cmdbuf[1]) & 0xffff0000) >> 16); 1339 } 1340 } 1341 1342 if (cmd->c_data) { 1343 error = rtsx_xfer(sc, cmd, cmdbuf); 1344 if (error) { 1345 u_int8_t stat1; 1346 1347 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 1348 (stat1 & RTSX_SD_CRC_ERR)) 1349 printf("%s: CRC error\n", DEVNAME(sc)); 1350 } 1351 } 1352 1353 unload_cmdbuf: 1354 bus_dmamap_unload(sc->dmat, sc->dmap_cmd); 1355 unmap_cmdbuf: 1356 bus_dmamem_unmap(sc->dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); 1357 free_cmdbuf: 1358 bus_dmamem_free(sc->dmat, &segs, rsegs); 1359 ret: 1360 SET(cmd->c_flags, SCF_ITSDONE); 1361 cmd->c_error = error; 1362 } 1363 1364 /* Prepare for another command. */ 1365 void 1366 rtsx_soft_reset(struct rtsx_softc *sc) 1367 { 1368 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc))); 1369 1370 /* Stop command transfer. */ 1371 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 1372 1373 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, 1374 RTSX_SD_STOP|RTSX_SD_CLR_ERR); 1375 1376 /* Stop DMA transfer. */ 1377 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 1378 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 1379 1380 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 1381 } 1382 1383 int 1384 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int secs) 1385 { 1386 int status; 1387 int error = 0; 1388 int s; 1389 1390 mask |= RTSX_TRANS_FAIL_INT; 1391 1392 s = splsdmmc(); 1393 status = sc->intr_status & mask; 1394 while (status == 0) { 1395 if (tsleep_nsec(&sc->intr_status, PRIBIO, "rtsxintr", 1396 SEC_TO_NSEC(secs)) == EWOULDBLOCK) { 1397 rtsx_soft_reset(sc); 1398 error = ETIMEDOUT; 1399 break; 1400 } 1401 status = sc->intr_status & mask; 1402 } 1403 sc->intr_status &= ~status; 1404 1405 /* Has the card disappeared? */ 1406 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1407 error = ENODEV; 1408 1409 splx(s); 1410 1411 if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) 1412 error = EIO; 1413 1414 return error; 1415 } 1416 1417 void 1418 rtsx_card_insert(struct rtsx_softc *sc) 1419 { 1420 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc))); 1421 1422 sc->flags |= RTSX_F_CARD_PRESENT; 1423 (void)rtsx_led_enable(sc); 1424 1425 /* Schedule card discovery task. */ 1426 sdmmc_needs_discover(sc->sdmmc); 1427 } 1428 1429 void 1430 rtsx_card_eject(struct rtsx_softc *sc) 1431 { 1432 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc))); 1433 1434 sc->flags &= ~RTSX_F_CARD_PRESENT; 1435 (void)rtsx_led_disable(sc); 1436 1437 /* Schedule card discovery task. */ 1438 sdmmc_needs_discover(sc->sdmmc); 1439 } 1440 1441 /* 1442 * Established by attachment driver at interrupt priority IPL_SDMMC. 1443 */ 1444 int 1445 rtsx_intr(void *arg) 1446 { 1447 struct rtsx_softc *sc = arg; 1448 u_int32_t enabled, status; 1449 1450 enabled = READ4(sc, RTSX_BIER); 1451 status = READ4(sc, RTSX_BIPR); 1452 1453 /* Ack interrupts. */ 1454 WRITE4(sc, RTSX_BIPR, status); 1455 1456 if (((enabled & status) == 0) || status == 0xffffffff) 1457 return 0; 1458 1459 if (status & RTSX_SD_INT) { 1460 if (status & RTSX_SD_EXIST) { 1461 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1462 rtsx_card_insert(sc); 1463 } else { 1464 rtsx_card_eject(sc); 1465 } 1466 } 1467 1468 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { 1469 sc->intr_status |= status; 1470 wakeup(&sc->intr_status); 1471 } 1472 1473 return 1; 1474 } 1475