1 /* $OpenBSD: rtsx.c,v 1.9 2014/05/18 10:52:16 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Realtek RTS5209/RTS5227/RTS5229/RTL8402 Card Reader driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/kthread.h> 28 #include <sys/systm.h> 29 30 #include <dev/ic/rtsxreg.h> 31 #include <dev/ic/rtsxvar.h> 32 #include <dev/sdmmc/sdmmcvar.h> 33 #include <dev/sdmmc/sdmmc_ioreg.h> 34 35 /* 36 * We use two DMA buffers, a command buffer and a data buffer. 37 * 38 * The command buffer contains a command queue for the host controller, 39 * which describes SD/MMC commands to run, and other parameters. The chip 40 * runs the command queue when a special bit in the RTSX_HCBAR register is set 41 * and signals completion with the TRANS_OK interrupt. 42 * Each command is encoded as a 4 byte sequence containing command number 43 * (read, write, or check a host controller register), a register address, 44 * and a data bit-mask and value. 45 * 46 * The data buffer is used to transfer data sectors to or from the SD card. 47 * Data transfer is controlled via the RTSX_HDBAR register. Completion is 48 * also signalled by the TRANS_OK interrupt. 49 * 50 * The chip is unable to perform DMA above 4GB. 51 * 52 * SD/MMC commands which do not transfer any data from/to the card only use 53 * the command buffer. 54 */ 55 56 #define RTSX_DMA_MAX_SEGSIZE 0x80000 57 #define RTSX_HOSTCMD_MAX 256 58 #define RTSX_HOSTCMD_BUFSIZE (sizeof(u_int32_t) * RTSX_HOSTCMD_MAX) 59 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 60 61 #define READ4(sc, reg) \ 62 (bus_space_read_4((sc)->iot, (sc)->ioh, (reg))) 63 #define WRITE4(sc, reg, val) \ 64 bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val)) 65 66 #define RTSX_READ(sc, reg, val) \ 67 do { \ 68 int err = rtsx_read((sc), (reg), (val)); \ 69 if (err) \ 70 return (err); \ 71 } while (0) 72 73 #define RTSX_WRITE(sc, reg, val) \ 74 do { \ 75 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 76 if (err) \ 77 return (err); \ 78 } while (0) 79 80 #define RTSX_CLR(sc, reg, bits) \ 81 do { \ 82 int err = rtsx_write((sc), (reg), (bits), 0); \ 83 if (err) \ 84 return (err); \ 85 } while (0) 86 87 #define RTSX_SET(sc, reg, bits) \ 88 do { \ 89 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 90 if (err) \ 91 return (err); \ 92 } while (0) 93 94 int rtsx_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 96 int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 97 int rtsx_card_detect(sdmmc_chipset_handle_t); 98 int rtsx_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int rtsx_bus_clock(sdmmc_chipset_handle_t, int); 100 void rtsx_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 101 int rtsx_init(struct rtsx_softc *, int); 102 void rtsx_soft_reset(struct rtsx_softc *); 103 int rtsx_bus_power_off(struct rtsx_softc *); 104 int rtsx_bus_power_on(struct rtsx_softc *); 105 int rtsx_set_bus_width(struct rtsx_softc *, int); 106 int rtsx_stop_sd_clock(struct rtsx_softc *); 107 int rtsx_switch_sd_clock(struct rtsx_softc *, u_int8_t, int, int); 108 int rtsx_wait_intr(struct rtsx_softc *, int, int); 109 int rtsx_read(struct rtsx_softc *, u_int16_t, u_int8_t *); 110 int rtsx_write(struct rtsx_softc *, u_int16_t, u_int8_t, u_int8_t); 111 #ifdef notyet 112 int rtsx_read_phy(struct rtsx_softc *, u_int8_t, u_int16_t *); 113 #endif 114 int rtsx_write_phy(struct rtsx_softc *, u_int8_t, u_int16_t); 115 int rtsx_read_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t *); 116 #ifdef notyet 117 int rtsx_write_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t, 118 u_int32_t); 119 #endif 120 void rtsx_hostcmd(u_int32_t *, int *, u_int8_t, u_int16_t, u_int8_t, 121 u_int8_t); 122 int rtsx_hostcmd_send(struct rtsx_softc *, int); 123 u_int8_t rtsx_response_type(u_int16_t); 124 int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, u_int32_t *); 125 void rtsx_card_insert(struct rtsx_softc *); 126 void rtsx_card_eject(struct rtsx_softc *); 127 int rtsx_led_enable(struct rtsx_softc *); 128 int rtsx_led_disable(struct rtsx_softc *); 129 void rtsx_save_regs(struct rtsx_softc *); 130 void rtsx_restore_regs(struct rtsx_softc *); 131 132 #ifdef RTSX_DEBUG 133 int rtsxdebug = 0; 134 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 135 #else 136 #define DPRINTF(n,s) do {} while(0) 137 #endif 138 139 struct sdmmc_chip_functions rtsx_functions = { 140 /* host controller reset */ 141 rtsx_host_reset, 142 /* host controller capabilities */ 143 rtsx_host_ocr, 144 rtsx_host_maxblklen, 145 /* card detection */ 146 rtsx_card_detect, 147 /* bus power and clock frequency */ 148 rtsx_bus_power, 149 rtsx_bus_clock, 150 /* command execution */ 151 rtsx_exec_command, 152 /* card interrupt */ 153 NULL, NULL 154 }; 155 156 struct cfdriver rtsx_cd = { 157 NULL, "rtsx", DV_DULL 158 }; 159 160 /* 161 * Called by attachment driver. 162 */ 163 int 164 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, 165 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) 166 { 167 struct sdmmcbus_attach_args saa; 168 u_int32_t sdio_cfg; 169 170 sc->iot = iot; 171 sc->ioh = ioh; 172 sc->dmat = dmat; 173 sc->flags = flags; 174 175 if (rtsx_init(sc, 1)) 176 return 1; 177 178 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 179 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 180 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 181 sc->flags |= RTSX_F_SDIO_SUPPORT; 182 } 183 184 if (bus_dmamap_create(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 1, 185 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 186 &sc->dmap_cmd) != 0) 187 return 1; 188 if (bus_dmamap_create(sc->dmat, RTSX_DMA_DATA_BUFSIZE, 1, 189 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 190 &sc->dmap_data) != 0) 191 return 1; 192 193 /* 194 * Attach the generic SD/MMC bus driver. (The bus driver must 195 * not invoke any chipset functions before it is attached.) 196 */ 197 bzero(&saa, sizeof(saa)); 198 saa.saa_busname = "sdmmc"; 199 saa.sct = &rtsx_functions; 200 saa.sch = sc; 201 saa.flags = SMF_STOP_AFTER_MULTIPLE; 202 203 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 204 if (sc->sdmmc == NULL) 205 return 1; 206 207 /* Now handle cards discovered during attachment. */ 208 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 209 rtsx_card_insert(sc); 210 211 return 0; 212 } 213 214 int 215 rtsx_init(struct rtsx_softc *sc, int attaching) 216 { 217 u_int32_t status; 218 u_int8_t version; 219 int error; 220 221 /* Read IC version from dummy register. */ 222 if (sc->flags & RTSX_F_5229) { 223 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 224 switch (version & 0x0F) { 225 case RTSX_IC_VERSION_A: 226 case RTSX_IC_VERSION_B: 227 case RTSX_IC_VERSION_D: 228 break; 229 case RTSX_IC_VERSION_C: 230 sc->flags |= RTSX_F_5229_TYPE_C; 231 break; 232 default: 233 printf("rtsx_init: unknown ic %02x\n", version); 234 return (1); 235 } 236 } 237 238 /* Enable interrupt write-clear (default is read-clear). */ 239 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 240 241 /* Clear any pending interrupts. */ 242 status = READ4(sc, RTSX_BIPR); 243 WRITE4(sc, RTSX_BIPR, status); 244 245 /* Check for cards already inserted at attach time. */ 246 if (attaching && (status & RTSX_SD_EXIST)) 247 sc->flags |= RTSX_F_CARD_PRESENT; 248 249 /* Enable interrupts. */ 250 WRITE4(sc, RTSX_BIER, 251 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); 252 253 /* Power on SSC clock. */ 254 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 255 delay(200); 256 257 /* XXX magic numbers from linux driver */ 258 if (sc->flags & RTSX_F_5209) 259 error = rtsx_write_phy(sc, 0x00, 0xB966); 260 else 261 error = rtsx_write_phy(sc, 0x00, 0xBA42); 262 if (error) { 263 printf("%s: cannot write phy register\n", DEVNAME(sc)); 264 return (1); 265 } 266 267 RTSX_SET(sc, RTSX_CLK_DIV, 0x07); 268 269 /* Disable sleep mode. */ 270 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 271 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 272 273 /* Disable card clock. */ 274 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 275 276 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 277 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); 278 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); 279 280 /* Enable SSC clock. */ 281 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 282 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 283 284 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); 285 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); 286 287 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 288 289 /* Set RC oscillator to 400K. */ 290 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 291 292 /* Request clock by driving CLKREQ pin to zero. */ 293 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); 294 295 /* Set up LED GPIO. */ 296 if (sc->flags & RTSX_F_5209) { 297 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 298 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 299 } else { 300 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 301 /* Switch LDO3318 source from DV33 to 3V3. */ 302 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 303 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); 304 /* Set default OLT blink period. */ 305 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); 306 } 307 308 return (0); 309 } 310 311 int 312 rtsx_activate(struct device *self, int act) 313 { 314 struct rtsx_softc *sc = (struct rtsx_softc *)self; 315 int rv = 0; 316 317 switch (act) { 318 case DVACT_SUSPEND: 319 rv = config_activate_children(self, act); 320 rtsx_save_regs(sc); 321 break; 322 case DVACT_RESUME: 323 rtsx_restore_regs(sc); 324 325 /* Handle cards ejected/inserted during suspend. */ 326 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) 327 rtsx_card_insert(sc); 328 else 329 rtsx_card_eject(sc); 330 331 rv = config_activate_children(self, act); 332 break; 333 default: 334 rv = config_activate_children(self, act); 335 break; 336 } 337 return (rv); 338 } 339 340 int 341 rtsx_led_enable(struct rtsx_softc *sc) 342 { 343 if (sc->flags & RTSX_F_5209) { 344 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 345 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 346 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 347 } else { 348 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 349 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 350 } 351 352 return 0; 353 } 354 355 int 356 rtsx_led_disable(struct rtsx_softc *sc) 357 { 358 if (sc->flags & RTSX_F_5209) { 359 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 360 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 361 } else { 362 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 363 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 364 } 365 366 return 0; 367 } 368 369 /* 370 * Reset the host controller. Called during initialization, when 371 * cards are removed, upon resume, and during error recovery. 372 */ 373 int 374 rtsx_host_reset(sdmmc_chipset_handle_t sch) 375 { 376 struct rtsx_softc *sc = sch; 377 int s; 378 379 DPRINTF(1,("%s: host reset\n", DEVNAME(sc))); 380 381 s = splsdmmc(); 382 383 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 384 rtsx_soft_reset(sc); 385 386 if (rtsx_init(sc, 0)) { 387 splx(s); 388 return 1; 389 } 390 391 splx(s); 392 return 0; 393 } 394 395 u_int32_t 396 rtsx_host_ocr(sdmmc_chipset_handle_t sch) 397 { 398 return RTSX_SUPPORT_VOLTAGE; 399 } 400 401 int 402 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) 403 { 404 return 512; 405 } 406 407 /* 408 * Return non-zero if the card is currently inserted. 409 */ 410 int 411 rtsx_card_detect(sdmmc_chipset_handle_t sch) 412 { 413 struct rtsx_softc *sc = sch; 414 415 return ISSET(sc->flags, RTSX_F_CARD_PRESENT); 416 } 417 418 /* 419 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 420 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 421 * it is a mask of *enabled* gates. 422 */ 423 424 int 425 rtsx_bus_power_off(struct rtsx_softc *sc) 426 { 427 int error; 428 u_int8_t disable3; 429 430 error = rtsx_stop_sd_clock(sc); 431 if (error) 432 return error; 433 434 /* Disable SD output. */ 435 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); 436 437 /* Turn off power. */ 438 disable3 = RTSX_PULL_CTL_DISABLE3; 439 if (sc->flags & RTSX_F_5209) 440 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 441 else { 442 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | 443 RTSX_LDO3318_VCC2); 444 if (sc->flags & RTSX_F_5229_TYPE_C) 445 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; 446 } 447 448 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 449 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 450 451 /* Disable pull control. */ 452 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 453 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 454 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); 455 456 return 0; 457 } 458 459 int 460 rtsx_bus_power_on(struct rtsx_softc *sc) 461 { 462 u_int8_t enable3; 463 464 /* Select SD card. */ 465 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); 466 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); 467 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 468 469 /* Enable pull control. */ 470 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 471 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 472 if (sc->flags & RTSX_F_5229_TYPE_C) 473 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; 474 else 475 enable3 = RTSX_PULL_CTL_ENABLE3; 476 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); 477 478 /* 479 * To avoid a current peak, enable card power in two phases with a 480 * delay in between. 481 */ 482 483 /* Partial power. */ 484 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); 485 if (sc->flags & RTSX_F_5229) 486 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); 487 else 488 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); 489 490 delay(200); 491 492 /* Full power. */ 493 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 494 if (sc->flags & RTSX_F_5209) 495 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 496 else 497 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); 498 499 /* Enable SD card output. */ 500 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 501 502 return 0; 503 } 504 505 int 506 rtsx_set_bus_width(struct rtsx_softc *sc, int w) 507 { 508 u_int32_t bus_width; 509 510 switch (w) { 511 case 8: 512 bus_width = RTSX_BUS_WIDTH_8; 513 break; 514 case 4: 515 bus_width = RTSX_BUS_WIDTH_4; 516 break; 517 case 1: 518 default: 519 bus_width = RTSX_BUS_WIDTH_1; 520 break; 521 } 522 523 if (bus_width == RTSX_BUS_WIDTH_1) 524 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK); 525 else 526 RTSX_SET(sc, RTSX_SD_CFG1, bus_width); 527 528 return 0; 529 } 530 531 int 532 rtsx_stop_sd_clock(struct rtsx_softc *sc) 533 { 534 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 535 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 536 537 return 0; 538 } 539 540 int 541 rtsx_switch_sd_clock(struct rtsx_softc *sc, u_int8_t n, int div, int mcu) 542 { 543 /* Enable SD 2.0 mode. */ 544 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); 545 546 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 547 548 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 549 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 550 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); 551 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 552 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 553 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 554 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); 555 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 556 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); 557 delay(100); 558 559 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 560 561 return 0; 562 } 563 564 /* 565 * Set or change SD bus voltage and enable or disable SD bus power. 566 * Return zero on success. 567 */ 568 int 569 rtsx_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 570 { 571 struct rtsx_softc *sc = sch; 572 int s, error = 0; 573 574 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr)); 575 576 s = splsdmmc(); 577 578 /* 579 * Disable bus power before voltage change. 580 */ 581 error = rtsx_bus_power_off(sc); 582 if (error) 583 goto ret; 584 585 delay(200); 586 587 /* If power is disabled, reset the host and return now. */ 588 if (ocr == 0) { 589 splx(s); 590 (void)rtsx_host_reset(sc); 591 return 0; 592 } 593 594 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { 595 /* Unsupported voltage level requested. */ 596 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n", 597 DEVNAME(sc), ocr)); 598 error = EINVAL; 599 goto ret; 600 } 601 602 error = rtsx_set_bus_width(sc, 1); 603 if (error) 604 goto ret; 605 606 error = rtsx_bus_power_on(sc); 607 ret: 608 splx(s); 609 return error; 610 } 611 612 /* 613 * Set or change SDCLK frequency or disable the SD clock. 614 * Return zero on success. 615 */ 616 int 617 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq) 618 { 619 struct rtsx_softc *sc = sch; 620 int s; 621 u_int8_t n; 622 int div; 623 int mcu; 624 int error = 0; 625 626 s = splsdmmc(); 627 628 if (freq == SDMMC_SDCLK_OFF) { 629 error = rtsx_stop_sd_clock(sc); 630 goto ret; 631 } 632 633 /* 634 * Configure the clock frequency. 635 */ 636 switch (freq) { 637 case SDMMC_SDCLK_400KHZ: 638 n = 80; /* minimum */ 639 div = RTSX_CLK_DIV_8; 640 mcu = 7; 641 RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128); 642 break; 643 case SDMMC_SDCLK_25MHZ: 644 n = 100; 645 div = RTSX_CLK_DIV_4; 646 mcu = 7; 647 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 648 break; 649 default: 650 error = EINVAL; 651 goto ret; 652 } 653 654 /* 655 * Enable SD clock. 656 */ 657 error = rtsx_switch_sd_clock(sc, n, div, mcu); 658 ret: 659 splx(s); 660 return error; 661 } 662 663 int 664 rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val) 665 { 666 int tries = 1024; 667 u_int32_t reg; 668 669 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 670 (u_int32_t)((addr & 0x3FFF) << 16)); 671 672 while (tries--) { 673 reg = READ4(sc, RTSX_HAIMR); 674 if (!(reg & RTSX_HAIMR_BUSY)) 675 break; 676 } 677 678 *val = (reg & 0xff); 679 return (tries == 0) ? ETIMEDOUT : 0; 680 } 681 682 int 683 rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val) 684 { 685 int tries = 1024; 686 u_int32_t reg; 687 688 WRITE4(sc, RTSX_HAIMR, 689 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 690 (u_int32_t)(((addr & 0x3FFF) << 16) | 691 (mask << 8) | val)); 692 693 while (tries--) { 694 reg = READ4(sc, RTSX_HAIMR); 695 if (!(reg & RTSX_HAIMR_BUSY)) { 696 if (val != (reg & 0xff)) 697 return EIO; 698 return 0; 699 } 700 } 701 702 return ETIMEDOUT; 703 } 704 705 #ifdef notyet 706 int 707 rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val) 708 { 709 int timeout = 100000; 710 u_int8_t data0; 711 u_int8_t data1; 712 u_int8_t rwctl; 713 714 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 715 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); 716 717 while (timeout--) { 718 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 719 if (!(rwctl & RTSX_PHY_BUSY)) 720 break; 721 } 722 723 if (timeout == 0) 724 return ETIMEDOUT; 725 726 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 727 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 728 *val = data0 | (data1 << 8); 729 730 return 0; 731 } 732 #endif 733 734 int 735 rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val) 736 { 737 int timeout = 100000; 738 u_int8_t rwctl; 739 740 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 741 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 742 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 743 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); 744 745 while (timeout--) { 746 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 747 if (!(rwctl & RTSX_PHY_BUSY)) 748 break; 749 } 750 751 if (timeout == 0) 752 return ETIMEDOUT; 753 754 return 0; 755 } 756 757 int 758 rtsx_read_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 759 u_int32_t *val) 760 { 761 int tries = 1024; 762 u_int8_t data0, data1, data2, data3, rwctl; 763 764 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 765 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 766 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 767 768 while (tries--) { 769 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 770 if (!(rwctl & RTSX_CFG_BUSY)) 771 break; 772 } 773 774 if (tries == 0) 775 return EIO; 776 777 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 778 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 779 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 780 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 781 782 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 783 784 return 0; 785 } 786 787 #ifdef notyet 788 int 789 rtsx_write_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 790 u_int32_t mask, u_int32_t val) 791 { 792 int i, writemask = 0, tries = 1024; 793 u_int8_t rwctl; 794 795 for (i = 0; i < 4; i++) { 796 if (mask & 0xff) { 797 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); 798 writemask |= (1 << i); 799 } 800 mask >>= 8; 801 val >>= 8; 802 } 803 804 if (writemask) { 805 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 806 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 807 RTSX_WRITE(sc, RTSX_CFGRWCTL, 808 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); 809 } 810 811 while (tries--) { 812 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 813 if (!(rwctl & RTSX_CFG_BUSY)) 814 break; 815 } 816 817 if (tries == 0) 818 return EIO; 819 820 return 0; 821 } 822 #endif 823 824 /* Append a properly encoded host command to the host command buffer. */ 825 void 826 rtsx_hostcmd(u_int32_t *cmdbuf, int *n, u_int8_t cmd, u_int16_t reg, 827 u_int8_t mask, u_int8_t data) 828 { 829 KASSERT(*n < RTSX_HOSTCMD_MAX); 830 831 cmdbuf[(*n)++] = htole32((u_int32_t)(cmd & 0x3) << 30) | 832 ((u_int32_t)(reg & 0x3fff) << 16) | 833 ((u_int32_t)(mask) << 8) | 834 ((u_int32_t)data); 835 } 836 837 void 838 rtsx_save_regs(struct rtsx_softc *sc) 839 { 840 int s, i; 841 u_int16_t reg; 842 843 s = splsdmmc(); 844 845 i = 0; 846 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 847 (void)rtsx_read(sc, reg, &sc->regs[i++]); 848 for (reg = 0xFD52; reg < 0xFD69; reg++) 849 (void)rtsx_read(sc, reg, &sc->regs[i++]); 850 for (reg = 0xFE20; reg < 0xFE34; reg++) 851 (void)rtsx_read(sc, reg, &sc->regs[i++]); 852 853 sc->regs4[0] = READ4(sc, RTSX_HCBAR); 854 sc->regs4[1] = READ4(sc, RTSX_HCBCTLR); 855 sc->regs4[2] = READ4(sc, RTSX_HDBAR); 856 sc->regs4[3] = READ4(sc, RTSX_HDBCTLR); 857 sc->regs4[4] = READ4(sc, RTSX_HAIMR); 858 sc->regs4[5] = READ4(sc, RTSX_BIER); 859 /* Not saving RTSX_BIPR. */ 860 861 splx(s); 862 } 863 864 void 865 rtsx_restore_regs(struct rtsx_softc *sc) 866 { 867 int s, i; 868 u_int16_t reg; 869 870 s = splsdmmc(); 871 872 WRITE4(sc, RTSX_HCBAR, sc->regs4[0]); 873 WRITE4(sc, RTSX_HCBCTLR, sc->regs4[1]); 874 WRITE4(sc, RTSX_HDBAR, sc->regs4[2]); 875 WRITE4(sc, RTSX_HDBCTLR, sc->regs4[3]); 876 WRITE4(sc, RTSX_HAIMR, sc->regs4[4]); 877 WRITE4(sc, RTSX_BIER, sc->regs4[5]); 878 /* Not writing RTSX_BIPR since doing so would clear it. */ 879 880 i = 0; 881 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 882 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 883 for (reg = 0xFD52; reg < 0xFD69; reg++) 884 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 885 for (reg = 0xFE20; reg < 0xFE34; reg++) 886 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 887 888 splx(s); 889 } 890 891 u_int8_t 892 rtsx_response_type(u_int16_t sdmmc_rsp) 893 { 894 int i; 895 struct rsp_type { 896 u_int16_t sdmmc_rsp; 897 u_int8_t rtsx_rsp; 898 } rsp_types[] = { 899 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, 900 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 901 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 902 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 903 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 904 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 905 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 906 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 907 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 908 }; 909 910 for (i = 0; i < nitems(rsp_types); i++) { 911 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) 912 return rsp_types[i].rtsx_rsp; 913 } 914 915 return 0; 916 } 917 918 int 919 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) 920 { 921 int s; 922 923 s = splsdmmc(); 924 925 /* Tell the chip where the command buffer is and run the commands. */ 926 WRITE4(sc, RTSX_HCBAR, sc->dmap_cmd->dm_segs[0].ds_addr); 927 WRITE4(sc, RTSX_HCBCTLR, 928 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 929 930 splx(s); 931 932 return 0; 933 } 934 935 int 936 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, u_int32_t *cmdbuf) 937 { 938 caddr_t datakvap; 939 bus_dma_segment_t segs; 940 int ncmd, s, dma_dir, error, rsegs, tmode; 941 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 942 u_int8_t cfg2; 943 944 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc), 945 read ? "read" : "write", 946 cmd->c_datalen, cmd->c_blklen)); 947 948 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { 949 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 950 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); 951 return ENOMEM; 952 } 953 954 /* Configure DMA transfer mode parameters. */ 955 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | 956 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 957 if (read) { 958 dma_dir = RTSX_DMA_DIR_FROM_CARD; 959 /* Use transfer mode AUTO_READ3, which assumes we've already 960 * sent the read command and gotten the response, and will 961 * send CMD 12 manually after reading multiple blocks. */ 962 tmode = RTSX_TM_AUTO_READ3; 963 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 964 } else { 965 dma_dir = RTSX_DMA_DIR_TO_CARD; 966 /* Use transfer mode AUTO_WRITE3, which assumes we've already 967 * sent the write command and gotten the response, and will 968 * send CMD 12 manually after writing multiple blocks. */ 969 tmode = RTSX_TM_AUTO_WRITE3; 970 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 971 } 972 973 ncmd = 0; 974 975 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 976 0xff, cfg2); 977 978 /* Queue commands to configure data transfer size. */ 979 rtsx_hostcmd(cmdbuf, &ncmd, 980 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 0xff, 0); 981 rtsx_hostcmd(cmdbuf, &ncmd, 982 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 0xff, 0x02); 983 rtsx_hostcmd(cmdbuf, &ncmd, 984 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 0xff, 985 ((cmd->c_datalen / cmd->c_blklen) & 0xff)); 986 rtsx_hostcmd(cmdbuf, &ncmd, 987 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 0xff, 988 ((cmd->c_datalen / cmd->c_blklen) >> 8)); 989 990 /* Use the DMA ring buffer for commands which transfer data. */ 991 rtsx_hostcmd(cmdbuf, &ncmd, 992 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 0x01, RTSX_RING_BUFFER); 993 994 /* Configure DMA controller. */ 995 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 996 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 997 rtsx_hostcmd(cmdbuf, &ncmd, 998 RTSX_WRITE_REG_CMD, RTSX_DMATC3, 0xff, cmd->c_datalen >> 24); 999 rtsx_hostcmd(cmdbuf, &ncmd, 1000 RTSX_WRITE_REG_CMD, RTSX_DMATC2, 0xff, cmd->c_datalen >> 16); 1001 rtsx_hostcmd(cmdbuf, &ncmd, 1002 RTSX_WRITE_REG_CMD, RTSX_DMATC1, 0xff, cmd->c_datalen >> 8); 1003 rtsx_hostcmd(cmdbuf, &ncmd, 1004 RTSX_WRITE_REG_CMD, RTSX_DMATC0, 0xff, cmd->c_datalen); 1005 rtsx_hostcmd(cmdbuf, &ncmd, 1006 RTSX_WRITE_REG_CMD, RTSX_DMACTL, 1007 0x03 | RTSX_DMA_PACK_SIZE_MASK, 1008 dma_dir | RTSX_DMA_EN | RTSX_DMA_512); 1009 1010 /* Queue commands to perform SD transfer. */ 1011 rtsx_hostcmd(cmdbuf, &ncmd, 1012 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1013 0xff, tmode | RTSX_SD_TRANSFER_START); 1014 rtsx_hostcmd(cmdbuf, &ncmd, 1015 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1016 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1017 1018 error = rtsx_hostcmd_send(sc, ncmd); 1019 if (error) 1020 goto ret; 1021 1022 /* Allocate and map DMA memory for data transfer. */ 1023 error = bus_dmamem_alloc(sc->dmat, cmd->c_datalen, 0, 0, &segs, 1, 1024 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1025 if (error) { 1026 DPRINTF(3, ("%s: could not allocate %d bytes\n", 1027 DEVNAME(sc), cmd->c_datalen)); 1028 goto ret; 1029 } 1030 error = bus_dmamem_map(sc->dmat, &segs, rsegs, cmd->c_datalen, 1031 &datakvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1032 if (error) { 1033 DPRINTF(3, ("%s: could not map data buffer\n", DEVNAME(sc))); 1034 goto free_databuf; 1035 } 1036 1037 /* If this is a write, copy data from sdmmc-provided buffer. */ 1038 if (!read) 1039 memcpy(datakvap, cmd->c_data, cmd->c_datalen); 1040 1041 /* Load the data buffer and sync it. */ 1042 error = bus_dmamap_load(sc->dmat, sc->dmap_data, datakvap, 1043 cmd->c_datalen, NULL, BUS_DMA_WAITOK); 1044 if (error) { 1045 DPRINTF(3, ("%s: could not load DMA map\n", DEVNAME(sc))); 1046 goto unmap_databuf; 1047 } 1048 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1049 BUS_DMASYNC_PREREAD); 1050 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1051 BUS_DMASYNC_PREWRITE); 1052 1053 s = splsdmmc(); 1054 1055 /* Tell the chip where the data buffer is and run the transfer. */ 1056 WRITE4(sc, RTSX_HDBAR, sc->dmap_data->dm_segs[0].ds_addr); 1057 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 1058 (sc->dmap_data->dm_segs[0].ds_len & 0x00ffffff)); 1059 1060 splx(s); 1061 1062 /* Wait for completion. */ 1063 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz); 1064 if (error) 1065 goto unload_databuf; 1066 1067 /* Sync and unload data DMA buffer. */ 1068 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1069 BUS_DMASYNC_POSTREAD); 1070 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1071 BUS_DMASYNC_POSTWRITE); 1072 1073 unload_databuf: 1074 bus_dmamap_unload(sc->dmat, sc->dmap_data); 1075 1076 /* If this is a read, copy data into sdmmc-provided buffer. */ 1077 if (error == 0 && read) 1078 memcpy(cmd->c_data, datakvap, cmd->c_datalen); 1079 1080 /* Free DMA data buffer. */ 1081 unmap_databuf: 1082 bus_dmamem_unmap(sc->dmat, datakvap, cmd->c_datalen); 1083 free_databuf: 1084 bus_dmamem_free(sc->dmat, &segs, rsegs); 1085 ret: 1086 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error)); 1087 return error; 1088 } 1089 1090 void 1091 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1092 { 1093 struct rtsx_softc *sc = sch; 1094 bus_dma_segment_t segs; 1095 int rsegs; 1096 caddr_t cmdkvap; 1097 u_int32_t *cmdbuf; 1098 u_int8_t rsp_type; 1099 u_int16_t r; 1100 int ncmd; 1101 int error = 0; 1102 1103 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode)); 1104 1105 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 1106 if (cmd->c_opcode == SD_IO_SEND_OP_COND && 1107 !ISSET(sc->flags, RTSX_F_SDIO_SUPPORT)) { 1108 error = ENOTSUP; 1109 goto ret; 1110 } 1111 1112 rsp_type = rtsx_response_type(cmd->c_flags & 0xff00); 1113 if (rsp_type == 0) { 1114 printf("%s: unknown response type 0x%x\n", DEVNAME(sc), 1115 (cmd->c_flags & 0xff00)); 1116 error = EINVAL; 1117 goto ret; 1118 } 1119 1120 /* Allocate and map the host command buffer. */ 1121 error = bus_dmamem_alloc(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, &segs, 1, 1122 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1123 if (error) 1124 goto ret; 1125 error = bus_dmamem_map(sc->dmat, &segs, rsegs, RTSX_HOSTCMD_BUFSIZE, 1126 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1127 if (error) 1128 goto free_cmdbuf; 1129 1130 /* The command buffer queues commands the host controller will 1131 * run asynchronously. */ 1132 cmdbuf = (u_int32_t *)cmdkvap; 1133 ncmd = 0; 1134 1135 /* Queue commands to set SD command index and argument. */ 1136 rtsx_hostcmd(cmdbuf, &ncmd, 1137 RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode); 1138 rtsx_hostcmd(cmdbuf, &ncmd, 1139 RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 0xff, cmd->c_arg >> 24); 1140 rtsx_hostcmd(cmdbuf, &ncmd, 1141 RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 0xff, cmd->c_arg >> 16); 1142 rtsx_hostcmd(cmdbuf, &ncmd, 1143 RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 0xff, cmd->c_arg >> 8); 1144 rtsx_hostcmd(cmdbuf, &ncmd, 1145 RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 0xff, cmd->c_arg); 1146 1147 /* Queue command to set response type. */ 1148 rtsx_hostcmd(cmdbuf, &ncmd, 1149 RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 1150 1151 /* Use the ping-pong buffer for commands which do not transfer data. */ 1152 rtsx_hostcmd(cmdbuf, &ncmd, 1153 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1154 0x01, RTSX_PINGPONG_BUFFER); 1155 1156 /* Queue commands to perform SD transfer. */ 1157 rtsx_hostcmd(cmdbuf, &ncmd, 1158 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1159 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 1160 rtsx_hostcmd(cmdbuf, &ncmd, 1161 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1162 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 1163 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 1164 1165 /* Queue commands to read back card status response.*/ 1166 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 1167 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) 1168 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1169 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, 1170 0, 0); 1171 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 1172 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) 1173 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1174 } 1175 1176 /* Load and sync command DMA buffer. */ 1177 error = bus_dmamap_load(sc->dmat, sc->dmap_cmd, cmdkvap, 1178 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); 1179 if (error) 1180 goto unmap_cmdbuf; 1181 1182 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1183 BUS_DMASYNC_PREREAD); 1184 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1185 BUS_DMASYNC_PREWRITE); 1186 1187 /* Run the command queue and wait for completion. */ 1188 error = rtsx_hostcmd_send(sc, ncmd); 1189 if (error == 0) 1190 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz); 1191 if (error) 1192 goto unload_cmdbuf; 1193 1194 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1195 BUS_DMASYNC_POSTREAD); 1196 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1197 BUS_DMASYNC_POSTWRITE); 1198 1199 /* Copy card response into sdmmc response buffer. */ 1200 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1201 /* Copy bytes like sdhc(4), which on little-endian uses 1202 * different byte order for short and long responses... */ 1203 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1204 memcpy(cmd->c_resp, cmdkvap + 1, sizeof(cmd->c_resp)); 1205 } else { 1206 /* First byte is CHECK_REG_CMD return value, second 1207 * one is the command op code -- we skip those. */ 1208 cmd->c_resp[0] = 1209 ((betoh32(cmdbuf[0]) & 0x0000ffff) << 16) | 1210 ((betoh32(cmdbuf[1]) & 0xffff0000) >> 16); 1211 } 1212 } 1213 1214 if (cmd->c_data) { 1215 error = rtsx_xfer(sc, cmd, cmdbuf); 1216 if (error) { 1217 u_int8_t stat1; 1218 1219 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 1220 (stat1 & RTSX_SD_CRC_ERR)) 1221 printf("%s: CRC error\n", DEVNAME(sc)); 1222 } 1223 } 1224 1225 unload_cmdbuf: 1226 bus_dmamap_unload(sc->dmat, sc->dmap_cmd); 1227 unmap_cmdbuf: 1228 bus_dmamem_unmap(sc->dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); 1229 free_cmdbuf: 1230 bus_dmamem_free(sc->dmat, &segs, rsegs); 1231 ret: 1232 SET(cmd->c_flags, SCF_ITSDONE); 1233 cmd->c_error = error; 1234 } 1235 1236 /* Prepare for another command. */ 1237 void 1238 rtsx_soft_reset(struct rtsx_softc *sc) 1239 { 1240 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc))); 1241 1242 /* Stop command transfer. */ 1243 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 1244 1245 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, 1246 RTSX_SD_STOP|RTSX_SD_CLR_ERR); 1247 1248 /* Stop DMA transfer. */ 1249 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 1250 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 1251 1252 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 1253 } 1254 1255 int 1256 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo) 1257 { 1258 int status; 1259 int error = 0; 1260 int s; 1261 1262 mask |= RTSX_TRANS_FAIL_INT; 1263 1264 s = splsdmmc(); 1265 status = sc->intr_status & mask; 1266 while (status == 0) { 1267 if (tsleep(&sc->intr_status, PRIBIO, "rtsxintr", timo) 1268 == EWOULDBLOCK) { 1269 rtsx_soft_reset(sc); 1270 error = ETIMEDOUT; 1271 break; 1272 } 1273 status = sc->intr_status & mask; 1274 } 1275 sc->intr_status &= ~status; 1276 1277 /* Has the card disappeared? */ 1278 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1279 error = ENODEV; 1280 1281 splx(s); 1282 1283 if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) 1284 error = EIO; 1285 1286 return error; 1287 } 1288 1289 void 1290 rtsx_card_insert(struct rtsx_softc *sc) 1291 { 1292 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc))); 1293 1294 sc->flags |= RTSX_F_CARD_PRESENT; 1295 (void)rtsx_led_enable(sc); 1296 1297 /* Schedule card discovery task. */ 1298 sdmmc_needs_discover(sc->sdmmc); 1299 } 1300 1301 void 1302 rtsx_card_eject(struct rtsx_softc *sc) 1303 { 1304 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc))); 1305 1306 sc->flags &= ~RTSX_F_CARD_PRESENT; 1307 (void)rtsx_led_disable(sc); 1308 1309 /* Schedule card discovery task. */ 1310 sdmmc_needs_discover(sc->sdmmc); 1311 } 1312 1313 /* 1314 * Established by attachment driver at interrupt priority IPL_SDMMC. 1315 */ 1316 int 1317 rtsx_intr(void *arg) 1318 { 1319 struct rtsx_softc *sc = arg; 1320 u_int32_t enabled, status; 1321 1322 enabled = READ4(sc, RTSX_BIER); 1323 status = READ4(sc, RTSX_BIPR); 1324 1325 /* Ack interrupts. */ 1326 WRITE4(sc, RTSX_BIPR, status); 1327 1328 if (((enabled & status) == 0) || status == 0xffffffff) 1329 return 0; 1330 1331 if (status & RTSX_SD_INT) { 1332 if (status & RTSX_SD_EXIST) { 1333 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1334 rtsx_card_insert(sc); 1335 } else { 1336 rtsx_card_eject(sc); 1337 } 1338 } 1339 1340 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { 1341 sc->intr_status |= status; 1342 wakeup(&sc->intr_status); 1343 } 1344 1345 return 1; 1346 } 1347