1 /* $OpenBSD: rtsx.c,v 1.17 2016/05/06 08:17:13 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Realtek RTS52xx/RTL84xx Card Reader driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/systm.h> 28 29 #include <dev/ic/rtsxreg.h> 30 #include <dev/ic/rtsxvar.h> 31 #include <dev/sdmmc/sdmmcvar.h> 32 #include <dev/sdmmc/sdmmc_ioreg.h> 33 34 /* 35 * We use two DMA buffers, a command buffer and a data buffer. 36 * 37 * The command buffer contains a command queue for the host controller, 38 * which describes SD/MMC commands to run, and other parameters. The chip 39 * runs the command queue when a special bit in the RTSX_HCBAR register is set 40 * and signals completion with the TRANS_OK interrupt. 41 * Each command is encoded as a 4 byte sequence containing command number 42 * (read, write, or check a host controller register), a register address, 43 * and a data bit-mask and value. 44 * 45 * The data buffer is used to transfer data sectors to or from the SD card. 46 * Data transfer is controlled via the RTSX_HDBAR register. Completion is 47 * also signalled by the TRANS_OK interrupt. 48 * 49 * The chip is unable to perform DMA above 4GB. 50 * 51 * SD/MMC commands which do not transfer any data from/to the card only use 52 * the command buffer. 53 */ 54 55 #define RTSX_DMA_MAX_SEGSIZE 0x80000 56 #define RTSX_HOSTCMD_MAX 256 57 #define RTSX_HOSTCMD_BUFSIZE (sizeof(u_int32_t) * RTSX_HOSTCMD_MAX) 58 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 59 60 #define READ4(sc, reg) \ 61 (bus_space_read_4((sc)->iot, (sc)->ioh, (reg))) 62 #define WRITE4(sc, reg, val) \ 63 bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val)) 64 65 #define RTSX_READ(sc, reg, val) \ 66 do { \ 67 int err = rtsx_read((sc), (reg), (val)); \ 68 if (err) \ 69 return (err); \ 70 } while (0) 71 72 #define RTSX_WRITE(sc, reg, val) \ 73 do { \ 74 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 75 if (err) \ 76 return (err); \ 77 } while (0) 78 79 #define RTSX_CLR(sc, reg, bits) \ 80 do { \ 81 int err = rtsx_write((sc), (reg), (bits), 0); \ 82 if (err) \ 83 return (err); \ 84 } while (0) 85 86 #define RTSX_SET(sc, reg, bits) \ 87 do { \ 88 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 89 if (err) \ 90 return (err); \ 91 } while (0) 92 93 int rtsx_host_reset(sdmmc_chipset_handle_t); 94 u_int32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 95 int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 96 int rtsx_card_detect(sdmmc_chipset_handle_t); 97 int rtsx_bus_power(sdmmc_chipset_handle_t, u_int32_t); 98 int rtsx_bus_clock(sdmmc_chipset_handle_t, int, int); 99 int rtsx_bus_width(sdmmc_chipset_handle_t, int); 100 void rtsx_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 101 int rtsx_init(struct rtsx_softc *, int); 102 void rtsx_soft_reset(struct rtsx_softc *); 103 int rtsx_bus_power_off(struct rtsx_softc *); 104 int rtsx_bus_power_on(struct rtsx_softc *); 105 int rtsx_set_bus_width(struct rtsx_softc *, int); 106 int rtsx_stop_sd_clock(struct rtsx_softc *); 107 int rtsx_switch_sd_clock(struct rtsx_softc *, u_int8_t, int, int); 108 int rtsx_wait_intr(struct rtsx_softc *, int, int); 109 int rtsx_read(struct rtsx_softc *, u_int16_t, u_int8_t *); 110 int rtsx_write(struct rtsx_softc *, u_int16_t, u_int8_t, u_int8_t); 111 #ifdef notyet 112 int rtsx_read_phy(struct rtsx_softc *, u_int8_t, u_int16_t *); 113 #endif 114 int rtsx_write_phy(struct rtsx_softc *, u_int8_t, u_int16_t); 115 int rtsx_read_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t *); 116 #ifdef notyet 117 int rtsx_write_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t, 118 u_int32_t); 119 #endif 120 void rtsx_hostcmd(u_int32_t *, int *, u_int8_t, u_int16_t, u_int8_t, 121 u_int8_t); 122 int rtsx_hostcmd_send(struct rtsx_softc *, int); 123 u_int8_t rtsx_response_type(u_int16_t); 124 int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, u_int32_t *); 125 void rtsx_card_insert(struct rtsx_softc *); 126 void rtsx_card_eject(struct rtsx_softc *); 127 int rtsx_led_enable(struct rtsx_softc *); 128 int rtsx_led_disable(struct rtsx_softc *); 129 void rtsx_save_regs(struct rtsx_softc *); 130 void rtsx_restore_regs(struct rtsx_softc *); 131 132 #ifdef RTSX_DEBUG 133 int rtsxdebug = 0; 134 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 135 #else 136 #define DPRINTF(n,s) do {} while(0) 137 #endif 138 139 struct sdmmc_chip_functions rtsx_functions = { 140 /* host controller reset */ 141 rtsx_host_reset, 142 /* host controller capabilities */ 143 rtsx_host_ocr, 144 rtsx_host_maxblklen, 145 /* card detection */ 146 rtsx_card_detect, 147 /* bus power and clock frequency */ 148 rtsx_bus_power, 149 rtsx_bus_clock, 150 rtsx_bus_width, 151 /* command execution */ 152 rtsx_exec_command, 153 /* card interrupt */ 154 NULL, NULL 155 }; 156 157 struct cfdriver rtsx_cd = { 158 NULL, "rtsx", DV_DULL 159 }; 160 161 /* 162 * Called by attachment driver. 163 */ 164 int 165 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, 166 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) 167 { 168 struct sdmmcbus_attach_args saa; 169 u_int32_t sdio_cfg; 170 171 sc->iot = iot; 172 sc->ioh = ioh; 173 sc->dmat = dmat; 174 sc->flags = flags; 175 176 if (rtsx_init(sc, 1)) 177 return 1; 178 179 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 180 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 181 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 182 sc->flags |= RTSX_F_SDIO_SUPPORT; 183 } 184 185 if (bus_dmamap_create(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 1, 186 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 187 &sc->dmap_cmd) != 0) 188 return 1; 189 if (bus_dmamap_create(sc->dmat, RTSX_DMA_DATA_BUFSIZE, 1, 190 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 191 &sc->dmap_data) != 0) 192 return 1; 193 194 /* 195 * Attach the generic SD/MMC bus driver. (The bus driver must 196 * not invoke any chipset functions before it is attached.) 197 */ 198 bzero(&saa, sizeof(saa)); 199 saa.saa_busname = "sdmmc"; 200 saa.sct = &rtsx_functions; 201 saa.sch = sc; 202 saa.flags = SMF_STOP_AFTER_MULTIPLE; 203 saa.caps = SMC_CAPS_4BIT_MODE; 204 205 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 206 if (sc->sdmmc == NULL) 207 return 1; 208 209 /* Now handle cards discovered during attachment. */ 210 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 211 rtsx_card_insert(sc); 212 213 return 0; 214 } 215 216 int 217 rtsx_init(struct rtsx_softc *sc, int attaching) 218 { 219 u_int32_t status; 220 u_int8_t version; 221 int error; 222 223 /* Read IC version from dummy register. */ 224 if (sc->flags & RTSX_F_5229) { 225 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 226 switch (version & 0x0F) { 227 case RTSX_IC_VERSION_A: 228 case RTSX_IC_VERSION_B: 229 case RTSX_IC_VERSION_D: 230 break; 231 case RTSX_IC_VERSION_C: 232 sc->flags |= RTSX_F_5229_TYPE_C; 233 break; 234 default: 235 printf("rtsx_init: unknown ic %02x\n", version); 236 return (1); 237 } 238 } 239 240 /* Enable interrupt write-clear (default is read-clear). */ 241 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 242 243 /* Clear any pending interrupts. */ 244 status = READ4(sc, RTSX_BIPR); 245 WRITE4(sc, RTSX_BIPR, status); 246 247 /* Check for cards already inserted at attach time. */ 248 if (attaching && (status & RTSX_SD_EXIST)) 249 sc->flags |= RTSX_F_CARD_PRESENT; 250 251 /* Enable interrupts. */ 252 WRITE4(sc, RTSX_BIER, 253 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); 254 255 /* Power on SSC clock. */ 256 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 257 delay(200); 258 259 /* XXX magic numbers from linux driver */ 260 if (sc->flags & RTSX_F_5209) 261 error = rtsx_write_phy(sc, 0x00, 0xB966); 262 else 263 error = rtsx_write_phy(sc, 0x00, 0xBA42); 264 if (error) { 265 printf("%s: cannot write phy register\n", DEVNAME(sc)); 266 return (1); 267 } 268 269 RTSX_SET(sc, RTSX_CLK_DIV, 0x07); 270 271 /* Disable sleep mode. */ 272 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 273 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 274 275 /* Disable card clock. */ 276 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 277 278 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 279 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); 280 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); 281 282 /* Enable SSC clock. */ 283 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 284 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 285 286 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); 287 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); 288 289 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 290 291 /* Set RC oscillator to 400K. */ 292 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 293 294 /* Request clock by driving CLKREQ pin to zero. */ 295 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); 296 297 /* Set up LED GPIO. */ 298 if (sc->flags & RTSX_F_5209) { 299 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 300 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 301 } else { 302 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 303 /* Switch LDO3318 source from DV33 to 3V3. */ 304 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 305 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); 306 /* Set default OLT blink period. */ 307 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); 308 } 309 310 return (0); 311 } 312 313 int 314 rtsx_activate(struct device *self, int act) 315 { 316 struct rtsx_softc *sc = (struct rtsx_softc *)self; 317 int rv = 0; 318 319 switch (act) { 320 case DVACT_SUSPEND: 321 rv = config_activate_children(self, act); 322 rtsx_save_regs(sc); 323 break; 324 case DVACT_RESUME: 325 rtsx_restore_regs(sc); 326 327 /* Handle cards ejected/inserted during suspend. */ 328 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) 329 rtsx_card_insert(sc); 330 else 331 rtsx_card_eject(sc); 332 333 rv = config_activate_children(self, act); 334 break; 335 default: 336 rv = config_activate_children(self, act); 337 break; 338 } 339 return (rv); 340 } 341 342 int 343 rtsx_led_enable(struct rtsx_softc *sc) 344 { 345 if (sc->flags & RTSX_F_5209) { 346 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 347 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 348 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 349 } else { 350 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 351 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 352 } 353 354 return 0; 355 } 356 357 int 358 rtsx_led_disable(struct rtsx_softc *sc) 359 { 360 if (sc->flags & RTSX_F_5209) { 361 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 362 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 363 } else { 364 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 365 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 366 } 367 368 return 0; 369 } 370 371 /* 372 * Reset the host controller. Called during initialization, when 373 * cards are removed, upon resume, and during error recovery. 374 */ 375 int 376 rtsx_host_reset(sdmmc_chipset_handle_t sch) 377 { 378 struct rtsx_softc *sc = sch; 379 int s; 380 381 DPRINTF(1,("%s: host reset\n", DEVNAME(sc))); 382 383 s = splsdmmc(); 384 385 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 386 rtsx_soft_reset(sc); 387 388 if (rtsx_init(sc, 0)) { 389 splx(s); 390 return 1; 391 } 392 393 splx(s); 394 return 0; 395 } 396 397 u_int32_t 398 rtsx_host_ocr(sdmmc_chipset_handle_t sch) 399 { 400 return RTSX_SUPPORT_VOLTAGE; 401 } 402 403 int 404 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) 405 { 406 return 512; 407 } 408 409 /* 410 * Return non-zero if the card is currently inserted. 411 */ 412 int 413 rtsx_card_detect(sdmmc_chipset_handle_t sch) 414 { 415 struct rtsx_softc *sc = sch; 416 417 return ISSET(sc->flags, RTSX_F_CARD_PRESENT); 418 } 419 420 /* 421 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 422 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 423 * it is a mask of *enabled* gates. 424 */ 425 426 int 427 rtsx_bus_power_off(struct rtsx_softc *sc) 428 { 429 int error; 430 u_int8_t disable3; 431 432 error = rtsx_stop_sd_clock(sc); 433 if (error) 434 return error; 435 436 /* Disable SD output. */ 437 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); 438 439 /* Turn off power. */ 440 disable3 = RTSX_PULL_CTL_DISABLE3; 441 if (sc->flags & RTSX_F_5209) 442 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 443 else { 444 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | 445 RTSX_LDO3318_VCC2); 446 if (sc->flags & RTSX_F_5229_TYPE_C) 447 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; 448 } 449 450 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 451 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 452 453 /* Disable pull control. */ 454 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 455 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 456 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); 457 458 return 0; 459 } 460 461 int 462 rtsx_bus_power_on(struct rtsx_softc *sc) 463 { 464 u_int8_t enable3; 465 466 /* Select SD card. */ 467 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); 468 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); 469 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 470 471 /* Enable pull control. */ 472 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 473 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 474 if (sc->flags & RTSX_F_5229_TYPE_C) 475 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; 476 else 477 enable3 = RTSX_PULL_CTL_ENABLE3; 478 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); 479 480 /* 481 * To avoid a current peak, enable card power in two phases with a 482 * delay in between. 483 */ 484 485 /* Partial power. */ 486 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); 487 if (sc->flags & RTSX_F_5209) 488 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); 489 else 490 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); 491 492 delay(200); 493 494 /* Full power. */ 495 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 496 if (sc->flags & RTSX_F_5209) 497 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 498 else 499 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); 500 501 /* Enable SD card output. */ 502 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 503 504 return 0; 505 } 506 507 int 508 rtsx_set_bus_width(struct rtsx_softc *sc, int w) 509 { 510 u_int32_t bus_width; 511 int error; 512 513 switch (w) { 514 case 8: 515 bus_width = RTSX_BUS_WIDTH_8; 516 break; 517 case 4: 518 bus_width = RTSX_BUS_WIDTH_4; 519 break; 520 case 1: 521 default: 522 bus_width = RTSX_BUS_WIDTH_1; 523 break; 524 } 525 526 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 527 return error; 528 } 529 530 int 531 rtsx_stop_sd_clock(struct rtsx_softc *sc) 532 { 533 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 534 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 535 536 return 0; 537 } 538 539 int 540 rtsx_switch_sd_clock(struct rtsx_softc *sc, u_int8_t n, int div, int mcu) 541 { 542 /* Enable SD 2.0 mode. */ 543 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); 544 545 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 546 547 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 548 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 549 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); 550 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 551 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 552 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 553 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); 554 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 555 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); 556 delay(100); 557 558 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 559 560 return 0; 561 } 562 563 /* 564 * Set or change SD bus voltage and enable or disable SD bus power. 565 * Return zero on success. 566 */ 567 int 568 rtsx_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 569 { 570 struct rtsx_softc *sc = sch; 571 int s, error = 0; 572 573 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr)); 574 575 s = splsdmmc(); 576 577 /* 578 * Disable bus power before voltage change. 579 */ 580 error = rtsx_bus_power_off(sc); 581 if (error) 582 goto ret; 583 584 delay(200); 585 586 /* If power is disabled, reset the host and return now. */ 587 if (ocr == 0) { 588 splx(s); 589 (void)rtsx_host_reset(sc); 590 return 0; 591 } 592 593 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { 594 /* Unsupported voltage level requested. */ 595 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n", 596 DEVNAME(sc), ocr)); 597 error = EINVAL; 598 goto ret; 599 } 600 601 error = rtsx_bus_power_on(sc); 602 if (error) 603 goto ret; 604 605 error = rtsx_set_bus_width(sc, 1); 606 ret: 607 splx(s); 608 return error; 609 } 610 611 /* 612 * Set or change SDCLK frequency or disable the SD clock. 613 * Return zero on success. 614 */ 615 int 616 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 617 { 618 struct rtsx_softc *sc = sch; 619 int s; 620 u_int8_t n; 621 int div; 622 int mcu; 623 int error = 0; 624 625 s = splsdmmc(); 626 627 if (freq == SDMMC_SDCLK_OFF) { 628 error = rtsx_stop_sd_clock(sc); 629 goto ret; 630 } 631 632 /* Round down to a supported frequency. */ 633 if (freq >= SDMMC_SDCLK_50MHZ) 634 freq = SDMMC_SDCLK_50MHZ; 635 else if (freq >= SDMMC_SDCLK_25MHZ) 636 freq = SDMMC_SDCLK_25MHZ; 637 else 638 freq = SDMMC_SDCLK_400KHZ; 639 640 /* 641 * Configure the clock frequency. 642 */ 643 switch (freq) { 644 case SDMMC_SDCLK_400KHZ: 645 n = 80; /* minimum */ 646 div = RTSX_CLK_DIV_8; 647 mcu = 7; 648 RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128); 649 break; 650 case SDMMC_SDCLK_25MHZ: 651 n = 100; 652 div = RTSX_CLK_DIV_4; 653 mcu = 7; 654 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 655 break; 656 case SDMMC_SDCLK_50MHZ: 657 n = 100; 658 div = RTSX_CLK_DIV_2; 659 mcu = 7; 660 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 661 break; 662 default: 663 error = EINVAL; 664 goto ret; 665 } 666 667 /* 668 * Enable SD clock. 669 */ 670 error = rtsx_switch_sd_clock(sc, n, div, mcu); 671 ret: 672 splx(s); 673 return error; 674 } 675 676 int 677 rtsx_bus_width(sdmmc_chipset_handle_t sch, int width) 678 { 679 struct rtsx_softc *sc = sch; 680 681 return rtsx_set_bus_width(sc, width); 682 } 683 684 int 685 rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val) 686 { 687 int tries = 1024; 688 u_int32_t reg; 689 690 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 691 (u_int32_t)((addr & 0x3FFF) << 16)); 692 693 while (tries--) { 694 reg = READ4(sc, RTSX_HAIMR); 695 if (!(reg & RTSX_HAIMR_BUSY)) 696 break; 697 } 698 699 *val = (reg & 0xff); 700 return (tries == 0) ? ETIMEDOUT : 0; 701 } 702 703 int 704 rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val) 705 { 706 int tries = 1024; 707 u_int32_t reg; 708 709 WRITE4(sc, RTSX_HAIMR, 710 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 711 (u_int32_t)(((addr & 0x3FFF) << 16) | 712 (mask << 8) | val)); 713 714 while (tries--) { 715 reg = READ4(sc, RTSX_HAIMR); 716 if (!(reg & RTSX_HAIMR_BUSY)) { 717 if (val != (reg & 0xff)) 718 return EIO; 719 return 0; 720 } 721 } 722 723 return ETIMEDOUT; 724 } 725 726 #ifdef notyet 727 int 728 rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val) 729 { 730 int timeout = 100000; 731 u_int8_t data0; 732 u_int8_t data1; 733 u_int8_t rwctl; 734 735 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 736 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); 737 738 while (timeout--) { 739 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 740 if (!(rwctl & RTSX_PHY_BUSY)) 741 break; 742 } 743 744 if (timeout == 0) 745 return ETIMEDOUT; 746 747 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 748 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 749 *val = data0 | (data1 << 8); 750 751 return 0; 752 } 753 #endif 754 755 int 756 rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val) 757 { 758 int timeout = 100000; 759 u_int8_t rwctl; 760 761 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 762 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 763 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 764 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); 765 766 while (timeout--) { 767 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 768 if (!(rwctl & RTSX_PHY_BUSY)) 769 break; 770 } 771 772 if (timeout == 0) 773 return ETIMEDOUT; 774 775 return 0; 776 } 777 778 int 779 rtsx_read_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 780 u_int32_t *val) 781 { 782 int tries = 1024; 783 u_int8_t data0, data1, data2, data3, rwctl; 784 785 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 786 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 787 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 788 789 while (tries--) { 790 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 791 if (!(rwctl & RTSX_CFG_BUSY)) 792 break; 793 } 794 795 if (tries == 0) 796 return EIO; 797 798 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 799 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 800 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 801 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 802 803 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 804 805 return 0; 806 } 807 808 #ifdef notyet 809 int 810 rtsx_write_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 811 u_int32_t mask, u_int32_t val) 812 { 813 int i, writemask = 0, tries = 1024; 814 u_int8_t rwctl; 815 816 for (i = 0; i < 4; i++) { 817 if (mask & 0xff) { 818 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); 819 writemask |= (1 << i); 820 } 821 mask >>= 8; 822 val >>= 8; 823 } 824 825 if (writemask) { 826 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 827 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 828 RTSX_WRITE(sc, RTSX_CFGRWCTL, 829 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); 830 } 831 832 while (tries--) { 833 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 834 if (!(rwctl & RTSX_CFG_BUSY)) 835 break; 836 } 837 838 if (tries == 0) 839 return EIO; 840 841 return 0; 842 } 843 #endif 844 845 /* Append a properly encoded host command to the host command buffer. */ 846 void 847 rtsx_hostcmd(u_int32_t *cmdbuf, int *n, u_int8_t cmd, u_int16_t reg, 848 u_int8_t mask, u_int8_t data) 849 { 850 KASSERT(*n < RTSX_HOSTCMD_MAX); 851 852 cmdbuf[(*n)++] = htole32((u_int32_t)(cmd & 0x3) << 30) | 853 ((u_int32_t)(reg & 0x3fff) << 16) | 854 ((u_int32_t)(mask) << 8) | 855 ((u_int32_t)data); 856 } 857 858 void 859 rtsx_save_regs(struct rtsx_softc *sc) 860 { 861 int s, i; 862 u_int16_t reg; 863 864 s = splsdmmc(); 865 866 i = 0; 867 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 868 (void)rtsx_read(sc, reg, &sc->regs[i++]); 869 for (reg = 0xFD52; reg < 0xFD69; reg++) 870 (void)rtsx_read(sc, reg, &sc->regs[i++]); 871 for (reg = 0xFE20; reg < 0xFE34; reg++) 872 (void)rtsx_read(sc, reg, &sc->regs[i++]); 873 874 sc->regs4[0] = READ4(sc, RTSX_HCBAR); 875 sc->regs4[1] = READ4(sc, RTSX_HCBCTLR); 876 sc->regs4[2] = READ4(sc, RTSX_HDBAR); 877 sc->regs4[3] = READ4(sc, RTSX_HDBCTLR); 878 sc->regs4[4] = READ4(sc, RTSX_HAIMR); 879 sc->regs4[5] = READ4(sc, RTSX_BIER); 880 /* Not saving RTSX_BIPR. */ 881 882 splx(s); 883 } 884 885 void 886 rtsx_restore_regs(struct rtsx_softc *sc) 887 { 888 int s, i; 889 u_int16_t reg; 890 891 s = splsdmmc(); 892 893 WRITE4(sc, RTSX_HCBAR, sc->regs4[0]); 894 WRITE4(sc, RTSX_HCBCTLR, sc->regs4[1]); 895 WRITE4(sc, RTSX_HDBAR, sc->regs4[2]); 896 WRITE4(sc, RTSX_HDBCTLR, sc->regs4[3]); 897 WRITE4(sc, RTSX_HAIMR, sc->regs4[4]); 898 WRITE4(sc, RTSX_BIER, sc->regs4[5]); 899 /* Not writing RTSX_BIPR since doing so would clear it. */ 900 901 i = 0; 902 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 903 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 904 for (reg = 0xFD52; reg < 0xFD69; reg++) 905 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 906 for (reg = 0xFE20; reg < 0xFE34; reg++) 907 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 908 909 splx(s); 910 } 911 912 u_int8_t 913 rtsx_response_type(u_int16_t sdmmc_rsp) 914 { 915 int i; 916 struct rsp_type { 917 u_int16_t sdmmc_rsp; 918 u_int8_t rtsx_rsp; 919 } rsp_types[] = { 920 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, 921 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 922 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 923 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 924 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 925 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 926 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 927 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 928 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 929 }; 930 931 for (i = 0; i < nitems(rsp_types); i++) { 932 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) 933 return rsp_types[i].rtsx_rsp; 934 } 935 936 return 0; 937 } 938 939 int 940 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) 941 { 942 int s; 943 944 s = splsdmmc(); 945 946 /* Tell the chip where the command buffer is and run the commands. */ 947 WRITE4(sc, RTSX_HCBAR, sc->dmap_cmd->dm_segs[0].ds_addr); 948 WRITE4(sc, RTSX_HCBCTLR, 949 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 950 951 splx(s); 952 953 return 0; 954 } 955 956 int 957 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, u_int32_t *cmdbuf) 958 { 959 caddr_t datakvap; 960 bus_dma_segment_t segs; 961 int ncmd, s, dma_dir, error, rsegs, tmode; 962 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 963 u_int8_t cfg2; 964 965 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc), 966 read ? "read" : "write", 967 cmd->c_datalen, cmd->c_blklen)); 968 969 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { 970 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 971 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); 972 return ENOMEM; 973 } 974 975 /* Configure DMA transfer mode parameters. */ 976 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | 977 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 978 if (read) { 979 dma_dir = RTSX_DMA_DIR_FROM_CARD; 980 /* Use transfer mode AUTO_READ3, which assumes we've already 981 * sent the read command and gotten the response, and will 982 * send CMD 12 manually after reading multiple blocks. */ 983 tmode = RTSX_TM_AUTO_READ3; 984 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 985 } else { 986 dma_dir = RTSX_DMA_DIR_TO_CARD; 987 /* Use transfer mode AUTO_WRITE3, which assumes we've already 988 * sent the write command and gotten the response, and will 989 * send CMD 12 manually after writing multiple blocks. */ 990 tmode = RTSX_TM_AUTO_WRITE3; 991 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 992 } 993 994 ncmd = 0; 995 996 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 997 0xff, cfg2); 998 999 /* Queue commands to configure data transfer size. */ 1000 rtsx_hostcmd(cmdbuf, &ncmd, 1001 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 0xff, 1002 (cmd->c_blklen & 0xff)); 1003 rtsx_hostcmd(cmdbuf, &ncmd, 1004 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 0xff, 1005 (cmd->c_blklen >> 8)); 1006 rtsx_hostcmd(cmdbuf, &ncmd, 1007 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 0xff, 1008 ((cmd->c_datalen / cmd->c_blklen) & 0xff)); 1009 rtsx_hostcmd(cmdbuf, &ncmd, 1010 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 0xff, 1011 ((cmd->c_datalen / cmd->c_blklen) >> 8)); 1012 1013 /* Use the DMA ring buffer for commands which transfer data. */ 1014 rtsx_hostcmd(cmdbuf, &ncmd, 1015 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 0x01, RTSX_RING_BUFFER); 1016 1017 /* Configure DMA controller. */ 1018 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 1019 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 1020 rtsx_hostcmd(cmdbuf, &ncmd, 1021 RTSX_WRITE_REG_CMD, RTSX_DMATC3, 0xff, cmd->c_datalen >> 24); 1022 rtsx_hostcmd(cmdbuf, &ncmd, 1023 RTSX_WRITE_REG_CMD, RTSX_DMATC2, 0xff, cmd->c_datalen >> 16); 1024 rtsx_hostcmd(cmdbuf, &ncmd, 1025 RTSX_WRITE_REG_CMD, RTSX_DMATC1, 0xff, cmd->c_datalen >> 8); 1026 rtsx_hostcmd(cmdbuf, &ncmd, 1027 RTSX_WRITE_REG_CMD, RTSX_DMATC0, 0xff, cmd->c_datalen); 1028 rtsx_hostcmd(cmdbuf, &ncmd, 1029 RTSX_WRITE_REG_CMD, RTSX_DMACTL, 1030 0x03 | RTSX_DMA_PACK_SIZE_MASK, 1031 dma_dir | RTSX_DMA_EN | RTSX_DMA_512); 1032 1033 /* Queue commands to perform SD transfer. */ 1034 rtsx_hostcmd(cmdbuf, &ncmd, 1035 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1036 0xff, tmode | RTSX_SD_TRANSFER_START); 1037 rtsx_hostcmd(cmdbuf, &ncmd, 1038 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1039 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1040 1041 error = rtsx_hostcmd_send(sc, ncmd); 1042 if (error) 1043 goto ret; 1044 1045 /* Allocate and map DMA memory for data transfer. */ 1046 error = bus_dmamem_alloc(sc->dmat, cmd->c_datalen, 0, 0, &segs, 1, 1047 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1048 if (error) { 1049 DPRINTF(3, ("%s: could not allocate %d bytes\n", 1050 DEVNAME(sc), cmd->c_datalen)); 1051 goto ret; 1052 } 1053 error = bus_dmamem_map(sc->dmat, &segs, rsegs, cmd->c_datalen, 1054 &datakvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1055 if (error) { 1056 DPRINTF(3, ("%s: could not map data buffer\n", DEVNAME(sc))); 1057 goto free_databuf; 1058 } 1059 1060 /* If this is a write, copy data from sdmmc-provided buffer. */ 1061 if (!read) 1062 memcpy(datakvap, cmd->c_data, cmd->c_datalen); 1063 1064 /* Load the data buffer and sync it. */ 1065 error = bus_dmamap_load(sc->dmat, sc->dmap_data, datakvap, 1066 cmd->c_datalen, NULL, BUS_DMA_WAITOK); 1067 if (error) { 1068 DPRINTF(3, ("%s: could not load DMA map\n", DEVNAME(sc))); 1069 goto unmap_databuf; 1070 } 1071 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1072 BUS_DMASYNC_PREREAD); 1073 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1074 BUS_DMASYNC_PREWRITE); 1075 1076 s = splsdmmc(); 1077 1078 /* Tell the chip where the data buffer is and run the transfer. */ 1079 WRITE4(sc, RTSX_HDBAR, sc->dmap_data->dm_segs[0].ds_addr); 1080 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 1081 (sc->dmap_data->dm_segs[0].ds_len & 0x00ffffff)); 1082 1083 splx(s); 1084 1085 /* Wait for completion. */ 1086 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz); 1087 if (error) 1088 goto unload_databuf; 1089 1090 /* Sync and unload data DMA buffer. */ 1091 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1092 BUS_DMASYNC_POSTREAD); 1093 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1094 BUS_DMASYNC_POSTWRITE); 1095 1096 unload_databuf: 1097 bus_dmamap_unload(sc->dmat, sc->dmap_data); 1098 1099 /* If this is a read, copy data into sdmmc-provided buffer. */ 1100 if (error == 0 && read) 1101 memcpy(cmd->c_data, datakvap, cmd->c_datalen); 1102 1103 /* Free DMA data buffer. */ 1104 unmap_databuf: 1105 bus_dmamem_unmap(sc->dmat, datakvap, cmd->c_datalen); 1106 free_databuf: 1107 bus_dmamem_free(sc->dmat, &segs, rsegs); 1108 ret: 1109 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error)); 1110 return error; 1111 } 1112 1113 void 1114 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1115 { 1116 struct rtsx_softc *sc = sch; 1117 bus_dma_segment_t segs; 1118 int rsegs; 1119 caddr_t cmdkvap; 1120 u_int32_t *cmdbuf; 1121 u_int8_t rsp_type; 1122 u_int16_t r; 1123 int ncmd; 1124 int error = 0; 1125 1126 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode)); 1127 1128 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 1129 if (cmd->c_opcode == SD_IO_SEND_OP_COND && 1130 !ISSET(sc->flags, RTSX_F_SDIO_SUPPORT)) { 1131 error = ENOTSUP; 1132 goto ret; 1133 } 1134 1135 rsp_type = rtsx_response_type(cmd->c_flags & 0xff00); 1136 if (rsp_type == 0) { 1137 printf("%s: unknown response type 0x%x\n", DEVNAME(sc), 1138 (cmd->c_flags & 0xff00)); 1139 error = EINVAL; 1140 goto ret; 1141 } 1142 1143 /* Allocate and map the host command buffer. */ 1144 error = bus_dmamem_alloc(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, &segs, 1, 1145 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1146 if (error) 1147 goto ret; 1148 error = bus_dmamem_map(sc->dmat, &segs, rsegs, RTSX_HOSTCMD_BUFSIZE, 1149 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1150 if (error) 1151 goto free_cmdbuf; 1152 1153 /* The command buffer queues commands the host controller will 1154 * run asynchronously. */ 1155 cmdbuf = (u_int32_t *)cmdkvap; 1156 ncmd = 0; 1157 1158 /* Queue commands to set SD command index and argument. */ 1159 rtsx_hostcmd(cmdbuf, &ncmd, 1160 RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode); 1161 rtsx_hostcmd(cmdbuf, &ncmd, 1162 RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 0xff, cmd->c_arg >> 24); 1163 rtsx_hostcmd(cmdbuf, &ncmd, 1164 RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 0xff, cmd->c_arg >> 16); 1165 rtsx_hostcmd(cmdbuf, &ncmd, 1166 RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 0xff, cmd->c_arg >> 8); 1167 rtsx_hostcmd(cmdbuf, &ncmd, 1168 RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 0xff, cmd->c_arg); 1169 1170 /* Queue command to set response type. */ 1171 rtsx_hostcmd(cmdbuf, &ncmd, 1172 RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 1173 1174 /* Use the ping-pong buffer for commands which do not transfer data. */ 1175 rtsx_hostcmd(cmdbuf, &ncmd, 1176 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1177 0x01, RTSX_PINGPONG_BUFFER); 1178 1179 /* Queue commands to perform SD transfer. */ 1180 rtsx_hostcmd(cmdbuf, &ncmd, 1181 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1182 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 1183 rtsx_hostcmd(cmdbuf, &ncmd, 1184 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1185 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 1186 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 1187 1188 /* Queue commands to read back card status response.*/ 1189 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 1190 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) 1191 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1192 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, 1193 0, 0); 1194 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 1195 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) 1196 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1197 } 1198 1199 /* Load and sync command DMA buffer. */ 1200 error = bus_dmamap_load(sc->dmat, sc->dmap_cmd, cmdkvap, 1201 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); 1202 if (error) 1203 goto unmap_cmdbuf; 1204 1205 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1206 BUS_DMASYNC_PREREAD); 1207 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1208 BUS_DMASYNC_PREWRITE); 1209 1210 /* Run the command queue and wait for completion. */ 1211 error = rtsx_hostcmd_send(sc, ncmd); 1212 if (error == 0) 1213 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz); 1214 if (error) 1215 goto unload_cmdbuf; 1216 1217 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1218 BUS_DMASYNC_POSTREAD); 1219 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1220 BUS_DMASYNC_POSTWRITE); 1221 1222 /* Copy card response into sdmmc response buffer. */ 1223 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1224 /* Copy bytes like sdhc(4), which on little-endian uses 1225 * different byte order for short and long responses... */ 1226 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1227 memcpy(cmd->c_resp, cmdkvap + 1, sizeof(cmd->c_resp)); 1228 } else { 1229 /* First byte is CHECK_REG_CMD return value, second 1230 * one is the command op code -- we skip those. */ 1231 cmd->c_resp[0] = 1232 ((betoh32(cmdbuf[0]) & 0x0000ffff) << 16) | 1233 ((betoh32(cmdbuf[1]) & 0xffff0000) >> 16); 1234 } 1235 } 1236 1237 if (cmd->c_data) { 1238 error = rtsx_xfer(sc, cmd, cmdbuf); 1239 if (error) { 1240 u_int8_t stat1; 1241 1242 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 1243 (stat1 & RTSX_SD_CRC_ERR)) 1244 printf("%s: CRC error\n", DEVNAME(sc)); 1245 } 1246 } 1247 1248 unload_cmdbuf: 1249 bus_dmamap_unload(sc->dmat, sc->dmap_cmd); 1250 unmap_cmdbuf: 1251 bus_dmamem_unmap(sc->dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); 1252 free_cmdbuf: 1253 bus_dmamem_free(sc->dmat, &segs, rsegs); 1254 ret: 1255 SET(cmd->c_flags, SCF_ITSDONE); 1256 cmd->c_error = error; 1257 } 1258 1259 /* Prepare for another command. */ 1260 void 1261 rtsx_soft_reset(struct rtsx_softc *sc) 1262 { 1263 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc))); 1264 1265 /* Stop command transfer. */ 1266 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 1267 1268 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, 1269 RTSX_SD_STOP|RTSX_SD_CLR_ERR); 1270 1271 /* Stop DMA transfer. */ 1272 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 1273 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 1274 1275 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 1276 } 1277 1278 int 1279 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo) 1280 { 1281 int status; 1282 int error = 0; 1283 int s; 1284 1285 mask |= RTSX_TRANS_FAIL_INT; 1286 1287 s = splsdmmc(); 1288 status = sc->intr_status & mask; 1289 while (status == 0) { 1290 if (tsleep(&sc->intr_status, PRIBIO, "rtsxintr", timo) 1291 == EWOULDBLOCK) { 1292 rtsx_soft_reset(sc); 1293 error = ETIMEDOUT; 1294 break; 1295 } 1296 status = sc->intr_status & mask; 1297 } 1298 sc->intr_status &= ~status; 1299 1300 /* Has the card disappeared? */ 1301 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1302 error = ENODEV; 1303 1304 splx(s); 1305 1306 if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) 1307 error = EIO; 1308 1309 return error; 1310 } 1311 1312 void 1313 rtsx_card_insert(struct rtsx_softc *sc) 1314 { 1315 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc))); 1316 1317 sc->flags |= RTSX_F_CARD_PRESENT; 1318 (void)rtsx_led_enable(sc); 1319 1320 /* Schedule card discovery task. */ 1321 sdmmc_needs_discover(sc->sdmmc); 1322 } 1323 1324 void 1325 rtsx_card_eject(struct rtsx_softc *sc) 1326 { 1327 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc))); 1328 1329 sc->flags &= ~RTSX_F_CARD_PRESENT; 1330 (void)rtsx_led_disable(sc); 1331 1332 /* Schedule card discovery task. */ 1333 sdmmc_needs_discover(sc->sdmmc); 1334 } 1335 1336 /* 1337 * Established by attachment driver at interrupt priority IPL_SDMMC. 1338 */ 1339 int 1340 rtsx_intr(void *arg) 1341 { 1342 struct rtsx_softc *sc = arg; 1343 u_int32_t enabled, status; 1344 1345 enabled = READ4(sc, RTSX_BIER); 1346 status = READ4(sc, RTSX_BIPR); 1347 1348 /* Ack interrupts. */ 1349 WRITE4(sc, RTSX_BIPR, status); 1350 1351 if (((enabled & status) == 0) || status == 0xffffffff) 1352 return 0; 1353 1354 if (status & RTSX_SD_INT) { 1355 if (status & RTSX_SD_EXIST) { 1356 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1357 rtsx_card_insert(sc); 1358 } else { 1359 rtsx_card_eject(sc); 1360 } 1361 } 1362 1363 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { 1364 sc->intr_status |= status; 1365 wakeup(&sc->intr_status); 1366 } 1367 1368 return 1; 1369 } 1370