1 /* $OpenBSD: rtl81x9.c,v 1.75 2011/06/21 16:52:45 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400MHz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include "bpfilter.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/device.h> 96 #include <sys/timeout.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_types.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #include <netinet/if_ether.h> 108 #endif 109 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 116 #include <machine/bus.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/ic/rtl81x9reg.h> 125 126 /* 127 * Various supported PHY vendors/types and their names. Note that 128 * this driver will work with pretty much any MII-compliant PHY, 129 * so failure to positively identify the chip is not a fatal error. 130 */ 131 132 void rl_tick(void *); 133 134 int rl_encap(struct rl_softc *, struct mbuf * ); 135 136 void rl_rxeof(struct rl_softc *); 137 void rl_txeof(struct rl_softc *); 138 void rl_start(struct ifnet *); 139 int rl_ioctl(struct ifnet *, u_long, caddr_t); 140 void rl_init(void *); 141 void rl_stop(struct rl_softc *); 142 void rl_watchdog(struct ifnet *); 143 int rl_ifmedia_upd(struct ifnet *); 144 void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 145 146 void rl_eeprom_getword(struct rl_softc *, int, int, u_int16_t *); 147 void rl_eeprom_putbyte(struct rl_softc *, int, int); 148 void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int, int); 149 150 void rl_mii_sync(struct rl_softc *); 151 void rl_mii_send(struct rl_softc *, u_int32_t, int); 152 int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 153 int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 154 155 int rl_miibus_readreg(struct device *, int, int); 156 void rl_miibus_writereg(struct device *, int, int, int); 157 void rl_miibus_statchg(struct device *); 158 159 void rl_iff(struct rl_softc *); 160 void rl_reset(struct rl_softc *); 161 int rl_list_tx_init(struct rl_softc *); 162 163 #define EE_SET(x) \ 164 CSR_WRITE_1(sc, RL_EECMD, \ 165 CSR_READ_1(sc, RL_EECMD) | x) 166 167 #define EE_CLR(x) \ 168 CSR_WRITE_1(sc, RL_EECMD, \ 169 CSR_READ_1(sc, RL_EECMD) & ~x) 170 171 /* 172 * Send a read command and address to the EEPROM, check for ACK. 173 */ 174 void 175 rl_eeprom_putbyte(struct rl_softc *sc, int addr, int addr_len) 176 { 177 int d, i; 178 179 d = (RL_EECMD_READ << addr_len) | addr; 180 181 /* 182 * Feed in each bit and strobe the clock. 183 */ 184 for (i = RL_EECMD_LEN + addr_len; i; i--) { 185 if (d & (1 << (i - 1))) 186 EE_SET(RL_EE_DATAIN); 187 else 188 EE_CLR(RL_EE_DATAIN); 189 190 DELAY(100); 191 EE_SET(RL_EE_CLK); 192 DELAY(150); 193 EE_CLR(RL_EE_CLK); 194 DELAY(100); 195 } 196 } 197 198 /* 199 * Read a word of data stored in the EEPROM at address 'addr.' 200 */ 201 void 202 rl_eeprom_getword(struct rl_softc *sc, int addr, int addr_len, 203 u_int16_t *dest) 204 { 205 int i; 206 u_int16_t word = 0; 207 208 /* Enter EEPROM access mode. */ 209 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 210 211 /* 212 * Send address of word we want to read. 213 */ 214 rl_eeprom_putbyte(sc, addr, addr_len); 215 216 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 217 218 /* 219 * Start reading bits from EEPROM. 220 */ 221 for (i = 16; i > 0; i--) { 222 EE_SET(RL_EE_CLK); 223 DELAY(100); 224 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 225 word |= 1 << (i - 1); 226 EE_CLR(RL_EE_CLK); 227 DELAY(100); 228 } 229 230 /* Turn off EEPROM access mode. */ 231 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 232 233 *dest = word; 234 } 235 236 /* 237 * Read a sequence of words from the EEPROM. 238 */ 239 void 240 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int addr_len, 241 int cnt, int swap) 242 { 243 int i; 244 u_int16_t word = 0, *ptr; 245 246 for (i = 0; i < cnt; i++) { 247 rl_eeprom_getword(sc, off + i, addr_len, &word); 248 ptr = (u_int16_t *)(dest + (i * 2)); 249 if (swap) 250 *ptr = letoh16(word); 251 else 252 *ptr = word; 253 } 254 } 255 256 /* 257 * MII access routines are provided for the 8129, which 258 * doesn't have a built-in PHY. For the 8139, we fake things 259 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 260 * direct access PHY registers. 261 */ 262 #define MII_SET(x) \ 263 CSR_WRITE_1(sc, RL_MII, \ 264 CSR_READ_1(sc, RL_MII) | x) 265 266 #define MII_CLR(x) \ 267 CSR_WRITE_1(sc, RL_MII, \ 268 CSR_READ_1(sc, RL_MII) & ~x) 269 270 /* 271 * Sync the PHYs by setting data bit and strobing the clock 32 times. 272 */ 273 void 274 rl_mii_sync(struct rl_softc *sc) 275 { 276 int i; 277 278 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 279 280 for (i = 0; i < 32; i++) { 281 MII_SET(RL_MII_CLK); 282 DELAY(1); 283 MII_CLR(RL_MII_CLK); 284 DELAY(1); 285 } 286 } 287 288 /* 289 * Clock a series of bits through the MII. 290 */ 291 void 292 rl_mii_send(struct rl_softc *sc, u_int32_t bits, int cnt) 293 { 294 int i; 295 296 MII_CLR(RL_MII_CLK); 297 298 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 299 if (bits & i) 300 MII_SET(RL_MII_DATAOUT); 301 else 302 MII_CLR(RL_MII_DATAOUT); 303 DELAY(1); 304 MII_CLR(RL_MII_CLK); 305 DELAY(1); 306 MII_SET(RL_MII_CLK); 307 } 308 } 309 310 /* 311 * Read an PHY register through the MII. 312 */ 313 int 314 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 315 { 316 int i, ack, s; 317 318 s = splnet(); 319 320 /* 321 * Set up frame for RX. 322 */ 323 frame->mii_stdelim = RL_MII_STARTDELIM; 324 frame->mii_opcode = RL_MII_READOP; 325 frame->mii_turnaround = 0; 326 frame->mii_data = 0; 327 328 CSR_WRITE_2(sc, RL_MII, 0); 329 330 /* 331 * Turn on data xmit. 332 */ 333 MII_SET(RL_MII_DIR); 334 335 rl_mii_sync(sc); 336 337 /* 338 * Send command/address info. 339 */ 340 rl_mii_send(sc, frame->mii_stdelim, 2); 341 rl_mii_send(sc, frame->mii_opcode, 2); 342 rl_mii_send(sc, frame->mii_phyaddr, 5); 343 rl_mii_send(sc, frame->mii_regaddr, 5); 344 345 /* Idle bit */ 346 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 347 DELAY(1); 348 MII_SET(RL_MII_CLK); 349 DELAY(1); 350 351 /* Turn off xmit. */ 352 MII_CLR(RL_MII_DIR); 353 354 /* Check for ack */ 355 MII_CLR(RL_MII_CLK); 356 DELAY(1); 357 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 358 MII_SET(RL_MII_CLK); 359 DELAY(1); 360 361 /* 362 * Now try reading data bits. If the ack failed, we still 363 * need to clock through 16 cycles to keep the PHY(s) in sync. 364 */ 365 if (ack) { 366 for(i = 0; i < 16; i++) { 367 MII_CLR(RL_MII_CLK); 368 DELAY(1); 369 MII_SET(RL_MII_CLK); 370 DELAY(1); 371 } 372 goto fail; 373 } 374 375 for (i = 0x8000; i; i >>= 1) { 376 MII_CLR(RL_MII_CLK); 377 DELAY(1); 378 if (!ack) { 379 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 380 frame->mii_data |= i; 381 DELAY(1); 382 } 383 MII_SET(RL_MII_CLK); 384 DELAY(1); 385 } 386 387 fail: 388 389 MII_CLR(RL_MII_CLK); 390 DELAY(1); 391 MII_SET(RL_MII_CLK); 392 DELAY(1); 393 394 splx(s); 395 396 if (ack) 397 return(1); 398 return(0); 399 } 400 401 /* 402 * Write to a PHY register through the MII. 403 */ 404 int 405 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 406 { 407 int s; 408 409 s = splnet(); 410 /* 411 * Set up frame for TX. 412 */ 413 414 frame->mii_stdelim = RL_MII_STARTDELIM; 415 frame->mii_opcode = RL_MII_WRITEOP; 416 frame->mii_turnaround = RL_MII_TURNAROUND; 417 418 /* 419 * Turn on data output. 420 */ 421 MII_SET(RL_MII_DIR); 422 423 rl_mii_sync(sc); 424 425 rl_mii_send(sc, frame->mii_stdelim, 2); 426 rl_mii_send(sc, frame->mii_opcode, 2); 427 rl_mii_send(sc, frame->mii_phyaddr, 5); 428 rl_mii_send(sc, frame->mii_regaddr, 5); 429 rl_mii_send(sc, frame->mii_turnaround, 2); 430 rl_mii_send(sc, frame->mii_data, 16); 431 432 /* Idle bit. */ 433 MII_SET(RL_MII_CLK); 434 DELAY(1); 435 MII_CLR(RL_MII_CLK); 436 DELAY(1); 437 438 /* 439 * Turn off xmit. 440 */ 441 MII_CLR(RL_MII_DIR); 442 443 splx(s); 444 445 return(0); 446 } 447 448 void 449 rl_iff(struct rl_softc *sc) 450 { 451 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 452 int h = 0; 453 u_int32_t hashes[2]; 454 struct arpcom *ac = &sc->sc_arpcom; 455 struct ether_multi *enm; 456 struct ether_multistep step; 457 u_int32_t rxfilt; 458 459 rxfilt = CSR_READ_4(sc, RL_RXCFG); 460 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | 461 RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI); 462 ifp->if_flags &= ~IFF_ALLMULTI; 463 464 /* 465 * Always accept frames destined to our station address. 466 * Always accept broadcast frames. 467 */ 468 rxfilt |= RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 469 470 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 471 ifp ->if_flags |= IFF_ALLMULTI; 472 rxfilt |= RL_RXCFG_RX_MULTI; 473 if (ifp->if_flags & IFF_PROMISC) 474 rxfilt |= RL_RXCFG_RX_ALLPHYS; 475 hashes[0] = hashes[1] = 0xFFFFFFFF; 476 } else { 477 rxfilt |= RL_RXCFG_RX_MULTI; 478 /* Program new filter. */ 479 bzero(hashes, sizeof(hashes)); 480 481 ETHER_FIRST_MULTI(step, ac, enm); 482 while (enm != NULL) { 483 h = ether_crc32_be(enm->enm_addrlo, 484 ETHER_ADDR_LEN) >> 26; 485 486 if (h < 32) 487 hashes[0] |= (1 << h); 488 else 489 hashes[1] |= (1 << (h - 32)); 490 491 ETHER_NEXT_MULTI(step, enm); 492 } 493 } 494 495 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 496 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 497 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 498 } 499 500 void 501 rl_reset(struct rl_softc *sc) 502 { 503 int i; 504 505 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 506 507 for (i = 0; i < RL_TIMEOUT; i++) { 508 DELAY(10); 509 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 510 break; 511 } 512 if (i == RL_TIMEOUT) 513 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 514 515 } 516 517 /* 518 * Initialize the transmit descriptors. 519 */ 520 int 521 rl_list_tx_init(struct rl_softc *sc) 522 { 523 struct rl_chain_data *cd = &sc->rl_cdata; 524 int i; 525 526 for (i = 0; i < RL_TX_LIST_CNT; i++) { 527 cd->rl_tx_chain[i] = NULL; 528 CSR_WRITE_4(sc, 529 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 530 } 531 532 sc->rl_cdata.cur_tx = 0; 533 sc->rl_cdata.last_tx = 0; 534 535 return(0); 536 } 537 538 /* 539 * A frame has been uploaded: pass the resulting mbuf chain up to 540 * the higher level protocols. 541 * 542 * You know there's something wrong with a PCI bus-master chip design 543 * when you have to use m_devget(). 544 * 545 * The receive operation is badly documented in the datasheet, so I'll 546 * attempt to document it here. The driver provides a buffer area and 547 * places its base address in the RX buffer start address register. 548 * The chip then begins copying frames into the RX buffer. Each frame 549 * is preceded by a 32-bit RX status word which specifies the length 550 * of the frame and certain other status bits. Each frame (starting with 551 * the status word) is also 32-bit aligned. The frame length is in the 552 * first 16 bits of the status word; the lower 15 bits correspond with 553 * the 'rx status register' mentioned in the datasheet. 554 * 555 * Note: to make the Alpha happy, the frame payload needs to be aligned 556 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 557 * the ring buffer starting at an address two bytes before the actual 558 * data location. We can then shave off the first two bytes using m_adj(). 559 * The reason we do this is because m_devget() doesn't let us specify an 560 * offset into the mbuf storage space, so we have to artificially create 561 * one. The ring is allocated in such a way that there are a few unused 562 * bytes of space preceding it so that it will be safe for us to do the 563 * 2-byte backstep even if reading from the ring at offset 0. 564 */ 565 void 566 rl_rxeof(struct rl_softc *sc) 567 { 568 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 569 struct mbuf *m; 570 int total_len; 571 u_int32_t rxstat; 572 caddr_t rxbufpos; 573 int wrap = 0; 574 u_int16_t cur_rx; 575 u_int16_t limit; 576 u_int16_t rx_bytes = 0, max_bytes; 577 578 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 579 580 /* Do not try to read past this point. */ 581 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 582 583 if (limit < cur_rx) 584 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 585 else 586 max_bytes = limit - cur_rx; 587 588 while ((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 589 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 590 0, sc->sc_rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 591 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 592 rxstat = *(u_int32_t *)rxbufpos; 593 594 /* 595 * Here's a totally undocumented fact for you. When the 596 * RealTek chip is in the process of copying a packet into 597 * RAM for you, the length will be 0xfff0. If you spot a 598 * packet header with this value, you need to stop. The 599 * datasheet makes absolutely no mention of this and 600 * RealTek should be shot for this. 601 */ 602 rxstat = htole32(rxstat); 603 total_len = rxstat >> 16; 604 if (total_len == RL_RXSTAT_UNFINISHED) { 605 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 606 0, sc->sc_rx_dmamap->dm_mapsize, 607 BUS_DMASYNC_PREREAD); 608 break; 609 } 610 611 if (!(rxstat & RL_RXSTAT_RXOK) || 612 total_len < ETHER_MIN_LEN || 613 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 614 ifp->if_ierrors++; 615 rl_init(sc); 616 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 617 0, sc->sc_rx_dmamap->dm_mapsize, 618 BUS_DMASYNC_PREREAD); 619 return; 620 } 621 622 /* No errors; receive the packet. */ 623 rx_bytes += total_len + 4; 624 625 /* 626 * XXX The RealTek chip includes the CRC with every 627 * received frame, and there's no way to turn this 628 * behavior off (at least, I can't find anything in 629 * the manual that explains how to do it) so we have 630 * to trim off the CRC manually. 631 */ 632 total_len -= ETHER_CRC_LEN; 633 634 /* 635 * Avoid trying to read more bytes than we know 636 * the chip has prepared for us. 637 */ 638 if (rx_bytes > max_bytes) { 639 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 640 0, sc->sc_rx_dmamap->dm_mapsize, 641 BUS_DMASYNC_PREREAD); 642 break; 643 } 644 645 rxbufpos = sc->rl_cdata.rl_rx_buf + 646 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 647 648 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 649 rxbufpos = sc->rl_cdata.rl_rx_buf; 650 651 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 652 653 if (total_len > wrap) { 654 m = m_devget(rxbufpos, wrap, ETHER_ALIGN, ifp, NULL); 655 if (m != NULL) { 656 m_copyback(m, wrap, total_len - wrap, 657 sc->rl_cdata.rl_rx_buf, M_NOWAIT); 658 if (m->m_pkthdr.len < total_len) { 659 m_freem(m); 660 m = NULL; 661 } 662 } 663 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 664 } else { 665 m = m_devget(rxbufpos, total_len, ETHER_ALIGN, ifp, 666 NULL); 667 cur_rx += total_len + 4 + ETHER_CRC_LEN; 668 } 669 670 /* 671 * Round up to 32-bit boundary. 672 */ 673 cur_rx = (cur_rx + 3) & ~3; 674 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 675 676 if (m == NULL) { 677 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 678 0, sc->sc_rx_dmamap->dm_mapsize, 679 BUS_DMASYNC_PREREAD); 680 ifp->if_ierrors++; 681 continue; 682 } 683 684 ifp->if_ipackets++; 685 686 #if NBPFILTER > 0 687 /* 688 * Handle BPF listeners. Let the BPF user see the packet. 689 */ 690 if (ifp->if_bpf) 691 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 692 #endif 693 ether_input_mbuf(ifp, m); 694 695 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 696 0, sc->sc_rx_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 697 } 698 } 699 700 /* 701 * A frame was downloaded to the chip. It's safe for us to clean up 702 * the list buffers. 703 */ 704 void 705 rl_txeof(struct rl_softc *sc) 706 { 707 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 708 u_int32_t txstat; 709 710 /* 711 * Go through our tx list and free mbufs for those 712 * frames that have been uploaded. 713 */ 714 do { 715 if (RL_LAST_TXMBUF(sc) == NULL) 716 break; 717 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 718 if (!(txstat & (RL_TXSTAT_TX_OK| 719 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 720 break; 721 722 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 723 724 bus_dmamap_sync(sc->sc_dmat, RL_LAST_TXMAP(sc), 725 0, RL_LAST_TXMAP(sc)->dm_mapsize, 726 BUS_DMASYNC_POSTWRITE); 727 bus_dmamap_unload(sc->sc_dmat, RL_LAST_TXMAP(sc)); 728 m_freem(RL_LAST_TXMBUF(sc)); 729 RL_LAST_TXMBUF(sc) = NULL; 730 /* 731 * If there was a transmit underrun, bump the TX threshold. 732 * Make sure not to overflow the 63 * 32byte we can address 733 * with the 6 available bit. 734 */ 735 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 736 (sc->rl_txthresh < 2016)) 737 sc->rl_txthresh += 32; 738 if (txstat & RL_TXSTAT_TX_OK) 739 ifp->if_opackets++; 740 else { 741 int oldthresh; 742 743 ifp->if_oerrors++; 744 if ((txstat & RL_TXSTAT_TXABRT) || 745 (txstat & RL_TXSTAT_OUTOFWIN)) 746 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 747 oldthresh = sc->rl_txthresh; 748 /* error recovery */ 749 rl_reset(sc); 750 rl_init(sc); 751 /* restore original threshold */ 752 sc->rl_txthresh = oldthresh; 753 return; 754 } 755 RL_INC(sc->rl_cdata.last_tx); 756 ifp->if_flags &= ~IFF_OACTIVE; 757 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 758 759 if (RL_LAST_TXMBUF(sc) == NULL) 760 ifp->if_timer = 0; 761 else if (ifp->if_timer == 0) 762 ifp->if_timer = 5; 763 } 764 765 int 766 rl_intr(void *arg) 767 { 768 struct rl_softc *sc = arg; 769 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 770 int claimed = 0; 771 u_int16_t status; 772 773 /* Disable interrupts. */ 774 CSR_WRITE_2(sc, RL_IMR, 0x0000); 775 776 for (;;) { 777 status = CSR_READ_2(sc, RL_ISR); 778 /* If the card has gone away, the read returns 0xffff. */ 779 if (status == 0xffff) 780 break; 781 if (status != 0) 782 CSR_WRITE_2(sc, RL_ISR, status); 783 if ((status & RL_INTRS) == 0) 784 break; 785 if ((status & RL_ISR_RX_OK) || (status & RL_ISR_RX_ERR)) 786 rl_rxeof(sc); 787 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 788 rl_txeof(sc); 789 if (status & RL_ISR_SYSTEM_ERR) { 790 rl_reset(sc); 791 rl_init(sc); 792 } 793 claimed = 1; 794 } 795 796 /* Re-enable interrupts. */ 797 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 798 799 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 800 rl_start(ifp); 801 802 return (claimed); 803 } 804 805 /* 806 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 807 * pointers to the fragment pointers. 808 */ 809 int 810 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 811 { 812 struct mbuf *m_new; 813 814 /* 815 * The RealTek is brain damaged and wants longword-aligned 816 * TX buffers, plus we can only have one fragment buffer 817 * per packet. We have to copy pretty much all the time. 818 */ 819 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 820 if (m_new == NULL) { 821 m_freem(m_head); 822 return(1); 823 } 824 if (m_head->m_pkthdr.len > MHLEN) { 825 MCLGET(m_new, M_DONTWAIT); 826 if (!(m_new->m_flags & M_EXT)) { 827 m_freem(m_new); 828 m_freem(m_head); 829 return(1); 830 } 831 } 832 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 833 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 834 835 /* Pad frames to at least 60 bytes. */ 836 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 837 /* 838 * Make security-conscious people happy: zero out the 839 * bytes in the pad area, since we don't know what 840 * this mbuf cluster buffer's previous user might 841 * have left in it. 842 */ 843 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 844 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 845 m_new->m_pkthdr.len += 846 (RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 847 m_new->m_len = m_new->m_pkthdr.len; 848 } 849 850 if (bus_dmamap_load_mbuf(sc->sc_dmat, RL_CUR_TXMAP(sc), 851 m_new, BUS_DMA_NOWAIT) != 0) { 852 m_freem(m_new); 853 m_freem(m_head); 854 return (1); 855 } 856 m_freem(m_head); 857 858 RL_CUR_TXMBUF(sc) = m_new; 859 bus_dmamap_sync(sc->sc_dmat, RL_CUR_TXMAP(sc), 0, 860 RL_CUR_TXMAP(sc)->dm_mapsize, BUS_DMASYNC_PREWRITE); 861 return(0); 862 } 863 864 /* 865 * Main transmit routine. 866 */ 867 void 868 rl_start(struct ifnet *ifp) 869 { 870 struct rl_softc *sc = ifp->if_softc; 871 struct mbuf *m_head = NULL; 872 int pkts = 0; 873 874 while (RL_CUR_TXMBUF(sc) == NULL) { 875 IFQ_DEQUEUE(&ifp->if_snd, m_head); 876 if (m_head == NULL) 877 break; 878 879 /* Pack the data into the descriptor. */ 880 if (rl_encap(sc, m_head)) 881 break; 882 pkts++; 883 884 #if NBPFILTER > 0 885 /* 886 * If there's a BPF listener, bounce a copy of this frame 887 * to him. 888 */ 889 if (ifp->if_bpf) 890 bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc), 891 BPF_DIRECTION_OUT); 892 #endif 893 /* 894 * Transmit the frame. 895 */ 896 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 897 RL_CUR_TXMAP(sc)->dm_segs[0].ds_addr); 898 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 899 RL_TXTHRESH(sc->rl_txthresh) | 900 RL_CUR_TXMAP(sc)->dm_segs[0].ds_len); 901 902 RL_INC(sc->rl_cdata.cur_tx); 903 904 /* 905 * Set a timeout in case the chip goes out to lunch. 906 */ 907 ifp->if_timer = 5; 908 } 909 910 if (pkts == 0) 911 return; 912 913 /* 914 * We broke out of the loop because all our TX slots are 915 * full. Mark the NIC as busy until it drains some of the 916 * packets from the queue. 917 */ 918 if (RL_CUR_TXMBUF(sc) != NULL) 919 ifp->if_flags |= IFF_OACTIVE; 920 } 921 922 void 923 rl_init(void *xsc) 924 { 925 struct rl_softc *sc = xsc; 926 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 927 int s; 928 929 s = splnet(); 930 931 /* 932 * Cancel pending I/O and free all RX/TX buffers. 933 */ 934 rl_stop(sc); 935 936 /* 937 * Init our MAC address. Even though the chipset 938 * documentation doesn't mention it, we need to enter "Config 939 * register write enable" mode to modify the ID registers. 940 */ 941 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 942 CSR_WRITE_RAW_4(sc, RL_IDR0, 943 (u_int8_t *)(&sc->sc_arpcom.ac_enaddr[0])); 944 CSR_WRITE_RAW_4(sc, RL_IDR4, 945 (u_int8_t *)(&sc->sc_arpcom.ac_enaddr[4])); 946 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 947 948 /* Init the RX buffer pointer register. */ 949 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_pa); 950 951 /* Init TX descriptors. */ 952 rl_list_tx_init(sc); 953 954 /* 955 * Enable transmit and receive. 956 */ 957 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 958 959 /* 960 * Set the initial TX and RX configuration. 961 */ 962 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 963 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 964 965 /* 966 * Program promiscuous mode and multicast filters. 967 */ 968 rl_iff(sc); 969 970 /* 971 * Enable interrupts. 972 */ 973 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 974 975 /* Set initial TX threshold */ 976 sc->rl_txthresh = RL_TX_THRESH_INIT; 977 978 /* Start RX/TX process. */ 979 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 980 981 /* Enable receiver and transmitter. */ 982 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 983 984 mii_mediachg(&sc->sc_mii); 985 986 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 987 988 ifp->if_flags |= IFF_RUNNING; 989 ifp->if_flags &= ~IFF_OACTIVE; 990 991 splx(s); 992 993 timeout_add_sec(&sc->sc_tick_tmo, 1); 994 } 995 996 /* 997 * Set media options. 998 */ 999 int 1000 rl_ifmedia_upd(struct ifnet *ifp) 1001 { 1002 struct rl_softc *sc = (struct rl_softc *)ifp->if_softc; 1003 1004 mii_mediachg(&sc->sc_mii); 1005 return (0); 1006 } 1007 1008 /* 1009 * Report current media status. 1010 */ 1011 void 1012 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1013 { 1014 struct rl_softc *sc = ifp->if_softc; 1015 1016 mii_pollstat(&sc->sc_mii); 1017 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1018 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1019 } 1020 1021 int 1022 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1023 { 1024 struct rl_softc *sc = ifp->if_softc; 1025 struct ifreq *ifr = (struct ifreq *) data; 1026 struct ifaddr *ifa = (struct ifaddr *) data; 1027 int s, error = 0; 1028 1029 s = splnet(); 1030 1031 switch(command) { 1032 case SIOCSIFADDR: 1033 ifp->if_flags |= IFF_UP; 1034 if (!(ifp->if_flags & IFF_RUNNING)) 1035 rl_init(sc); 1036 #ifdef INET 1037 if (ifa->ifa_addr->sa_family == AF_INET) 1038 arp_ifinit(&sc->sc_arpcom, ifa); 1039 #endif 1040 break; 1041 1042 case SIOCSIFFLAGS: 1043 if (ifp->if_flags & IFF_UP) { 1044 if (ifp->if_flags & IFF_RUNNING) 1045 error = ENETRESET; 1046 else 1047 rl_init(sc); 1048 } else { 1049 if (ifp->if_flags & IFF_RUNNING) 1050 rl_stop(sc); 1051 } 1052 break; 1053 1054 case SIOCGIFMEDIA: 1055 case SIOCSIFMEDIA: 1056 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1057 break; 1058 1059 default: 1060 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1061 } 1062 1063 if (error == ENETRESET) { 1064 if (ifp->if_flags & IFF_RUNNING) 1065 rl_iff(sc); 1066 error = 0; 1067 } 1068 1069 splx(s); 1070 return(error); 1071 } 1072 1073 void 1074 rl_watchdog(struct ifnet *ifp) 1075 { 1076 struct rl_softc *sc = ifp->if_softc; 1077 1078 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1079 ifp->if_oerrors++; 1080 rl_txeof(sc); 1081 rl_rxeof(sc); 1082 rl_init(sc); 1083 } 1084 1085 /* 1086 * Stop the adapter and free any mbufs allocated to the 1087 * RX and TX lists. 1088 */ 1089 void 1090 rl_stop(struct rl_softc *sc) 1091 { 1092 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1093 int i; 1094 1095 ifp->if_timer = 0; 1096 1097 timeout_del(&sc->sc_tick_tmo); 1098 1099 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1100 1101 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1102 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1103 1104 /* 1105 * Free the TX list buffers. 1106 */ 1107 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1108 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1109 bus_dmamap_sync(sc->sc_dmat, 1110 sc->rl_cdata.rl_tx_dmamap[i], 0, 1111 sc->rl_cdata.rl_tx_dmamap[i]->dm_mapsize, 1112 BUS_DMASYNC_POSTWRITE); 1113 bus_dmamap_unload(sc->sc_dmat, 1114 sc->rl_cdata.rl_tx_dmamap[i]); 1115 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1116 sc->rl_cdata.rl_tx_chain[i] = NULL; 1117 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), 1118 0x00000000); 1119 } 1120 } 1121 } 1122 1123 int 1124 rl_attach(struct rl_softc *sc) 1125 { 1126 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1127 int rseg, i; 1128 u_int16_t rl_id, rl_did; 1129 caddr_t kva; 1130 int addr_len; 1131 1132 rl_reset(sc); 1133 1134 /* 1135 * Check EEPROM type 9346 or 9356. 1136 */ 1137 rl_read_eeprom(sc, (caddr_t)&rl_id, RL_EE_ID, RL_EEADDR_LEN1, 1, 0); 1138 if (rl_id == 0x8129) 1139 addr_len = RL_EEADDR_LEN1; 1140 else 1141 addr_len = RL_EEADDR_LEN0; 1142 1143 /* 1144 * Get station address. 1145 */ 1146 rl_read_eeprom(sc, (caddr_t)sc->sc_arpcom.ac_enaddr, RL_EE_EADDR, 1147 addr_len, 3, 1); 1148 1149 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 1150 1151 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, addr_len, 1, 0); 1152 1153 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 1154 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 1155 rl_did == DLINK_DEVICEID_8139 || rl_did == DLINK_DEVICEID_8139_2 || 1156 rl_did == ABOCOM_DEVICEID_8139) 1157 sc->rl_type = RL_8139; 1158 else if (rl_did == RT_DEVICEID_8129) 1159 sc->rl_type = RL_8129; 1160 else 1161 sc->rl_type = RL_UNKNOWN; /* could be 8138 or other */ 1162 1163 if (bus_dmamem_alloc(sc->sc_dmat, RL_RXBUFLEN + 32, PAGE_SIZE, 0, 1164 &sc->sc_rx_seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1165 printf("\n%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); 1166 return (1); 1167 } 1168 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_rx_seg, rseg, 1169 RL_RXBUFLEN + 32, &kva, BUS_DMA_NOWAIT)) { 1170 printf("%s: can't map dma buffers (%d bytes)\n", 1171 sc->sc_dev.dv_xname, RL_RXBUFLEN + 32); 1172 bus_dmamem_free(sc->sc_dmat, &sc->sc_rx_seg, rseg); 1173 return (1); 1174 } 1175 if (bus_dmamap_create(sc->sc_dmat, RL_RXBUFLEN + 32, 1, 1176 RL_RXBUFLEN + 32, 0, BUS_DMA_NOWAIT, &sc->sc_rx_dmamap)) { 1177 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 1178 bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32); 1179 bus_dmamem_free(sc->sc_dmat, &sc->sc_rx_seg, rseg); 1180 return (1); 1181 } 1182 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_dmamap, kva, 1183 RL_RXBUFLEN + 32, NULL, BUS_DMA_NOWAIT)) { 1184 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 1185 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamap); 1186 bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32); 1187 bus_dmamem_free(sc->sc_dmat, &sc->sc_rx_seg, rseg); 1188 return (1); 1189 } 1190 sc->rl_cdata.rl_rx_buf = kva; 1191 sc->rl_cdata.rl_rx_buf_pa = sc->sc_rx_dmamap->dm_segs[0].ds_addr; 1192 1193 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap, 1194 0, sc->sc_rx_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1195 1196 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1197 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1198 BUS_DMA_NOWAIT, &sc->rl_cdata.rl_tx_dmamap[i]) != 0) { 1199 printf("%s: can't create tx maps\n", 1200 sc->sc_dev.dv_xname); 1201 /* XXX free any allocated... */ 1202 return (1); 1203 } 1204 } 1205 1206 /* Leave a few bytes before the start of the RX ring buffer. */ 1207 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1208 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1209 sc->rl_cdata.rl_rx_buf_pa += sizeof(u_int64_t); 1210 1211 ifp->if_softc = sc; 1212 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1213 ifp->if_ioctl = rl_ioctl; 1214 ifp->if_start = rl_start; 1215 ifp->if_watchdog = rl_watchdog; 1216 ifp->if_baudrate = 10000000; 1217 IFQ_SET_READY(&ifp->if_snd); 1218 1219 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1220 1221 ifp->if_capabilities = IFCAP_VLAN_MTU; 1222 1223 timeout_set(&sc->sc_tick_tmo, rl_tick, sc); 1224 1225 /* 1226 * Initialize our media structures and probe the MII. 1227 */ 1228 sc->sc_mii.mii_ifp = ifp; 1229 sc->sc_mii.mii_readreg = rl_miibus_readreg; 1230 sc->sc_mii.mii_writereg = rl_miibus_writereg; 1231 sc->sc_mii.mii_statchg = rl_miibus_statchg; 1232 ifmedia_init(&sc->sc_mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts); 1233 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1234 MII_OFFSET_ANY, 0); 1235 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1236 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1237 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1238 } else 1239 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1240 1241 /* 1242 * Attach us everywhere 1243 */ 1244 if_attach(ifp); 1245 ether_ifattach(ifp); 1246 1247 return (0); 1248 } 1249 1250 int 1251 rl_activate(struct device *self, int act) 1252 { 1253 struct rl_softc *sc = (struct rl_softc *)self; 1254 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1255 int rv = 0; 1256 1257 switch (act) { 1258 case DVACT_QUIESCE: 1259 rv = config_activate_children(self, act); 1260 break; 1261 case DVACT_SUSPEND: 1262 if (ifp->if_flags & IFF_RUNNING) 1263 rl_stop(sc); 1264 rv = config_activate_children(self, act); 1265 break; 1266 case DVACT_RESUME: 1267 rv = config_activate_children(self, act); 1268 if (ifp->if_flags & IFF_UP) 1269 rl_init(sc); 1270 break; 1271 } 1272 return (rv); 1273 } 1274 1275 int 1276 rl_miibus_readreg(struct device *self, int phy, int reg) 1277 { 1278 struct rl_softc *sc = (struct rl_softc *)self; 1279 struct rl_mii_frame frame; 1280 u_int16_t rl8139_reg; 1281 1282 if (sc->rl_type == RL_8139) { 1283 /* 1284 * The RTL8139 PHY is mapped into PCI registers, unfortunately 1285 * it has no phyid, or phyaddr, so assume it is phyaddr 0. 1286 */ 1287 if (phy != 0) 1288 return(0); 1289 1290 switch (reg) { 1291 case MII_BMCR: 1292 rl8139_reg = RL_BMCR; 1293 break; 1294 case MII_BMSR: 1295 rl8139_reg = RL_BMSR; 1296 break; 1297 case MII_ANAR: 1298 rl8139_reg = RL_ANAR; 1299 break; 1300 case MII_ANER: 1301 rl8139_reg = RL_ANER; 1302 break; 1303 case MII_ANLPAR: 1304 rl8139_reg = RL_LPAR; 1305 break; 1306 case RL_MEDIASTAT: 1307 return (CSR_READ_1(sc, RL_MEDIASTAT)); 1308 case MII_PHYIDR1: 1309 case MII_PHYIDR2: 1310 default: 1311 return (0); 1312 } 1313 return (CSR_READ_2(sc, rl8139_reg)); 1314 } 1315 1316 bzero(&frame, sizeof(frame)); 1317 1318 frame.mii_phyaddr = phy; 1319 frame.mii_regaddr = reg; 1320 rl_mii_readreg(sc, &frame); 1321 1322 return(frame.mii_data); 1323 } 1324 1325 void 1326 rl_miibus_writereg(struct device *self, int phy, int reg, int val) 1327 { 1328 struct rl_softc *sc = (struct rl_softc *)self; 1329 struct rl_mii_frame frame; 1330 u_int16_t rl8139_reg = 0; 1331 1332 if (sc->rl_type == RL_8139) { 1333 if (phy) 1334 return; 1335 1336 switch (reg) { 1337 case MII_BMCR: 1338 rl8139_reg = RL_BMCR; 1339 break; 1340 case MII_BMSR: 1341 rl8139_reg = RL_BMSR; 1342 break; 1343 case MII_ANAR: 1344 rl8139_reg = RL_ANAR; 1345 break; 1346 case MII_ANER: 1347 rl8139_reg = RL_ANER; 1348 break; 1349 case MII_ANLPAR: 1350 rl8139_reg = RL_LPAR; 1351 break; 1352 case MII_PHYIDR1: 1353 case MII_PHYIDR2: 1354 return; 1355 } 1356 CSR_WRITE_2(sc, rl8139_reg, val); 1357 return; 1358 } 1359 1360 bzero(&frame, sizeof(frame)); 1361 frame.mii_phyaddr = phy; 1362 frame.mii_regaddr = reg; 1363 frame.mii_data = val; 1364 rl_mii_writereg(sc, &frame); 1365 } 1366 1367 void 1368 rl_miibus_statchg(struct device *self) 1369 { 1370 } 1371 1372 void 1373 rl_tick(void *v) 1374 { 1375 struct rl_softc *sc = v; 1376 int s; 1377 1378 s = splnet(); 1379 mii_tick(&sc->sc_mii); 1380 splx(s); 1381 1382 timeout_add_sec(&sc->sc_tick_tmo, 1); 1383 } 1384 1385 int 1386 rl_detach(struct rl_softc *sc) 1387 { 1388 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1389 1390 /* Unhook our tick handler. */ 1391 timeout_del(&sc->sc_tick_tmo); 1392 1393 /* Detach any PHYs we might have. */ 1394 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL) 1395 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1396 1397 /* Delete any remaining media. */ 1398 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1399 1400 ether_ifdetach(ifp); 1401 if_detach(ifp); 1402 1403 return (0); 1404 } 1405 1406 struct cfdriver rl_cd = { 1407 0, "rl", DV_IFNET 1408 }; 1409