1 /* $OpenBSD: rtl81x9.c,v 1.8 2001/08/12 20:12:12 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include "bpfilter.h" 87 #include "vlan.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/device.h> 97 #include <sys/timeout.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #include <netinet/if_ether.h> 109 #endif 110 111 #include <net/if_media.h> 112 113 #if NBPFILTER > 0 114 #include <net/bpf.h> 115 #endif 116 117 #include <vm/vm.h> /* for vtophys */ 118 #include <vm/vm_kern.h> 119 #include <machine/bus.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/ic/rtl81x9reg.h> 128 129 /* 130 * Various supported PHY vendors/types and their names. Note that 131 * this driver will work with pretty much any MII-compliant PHY, 132 * so failure to positively identify the chip is not a fatal error. 133 */ 134 135 void rl_tick __P((void *)); 136 void rl_shutdown __P((void *)); 137 138 int rl_encap __P((struct rl_softc *, struct mbuf * )); 139 140 void rl_rxeof __P((struct rl_softc *)); 141 void rl_txeof __P((struct rl_softc *)); 142 void rl_start __P((struct ifnet *)); 143 int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 144 void rl_init __P((void *)); 145 void rl_stop __P((struct rl_softc *)); 146 void rl_watchdog __P((struct ifnet *)); 147 int rl_ifmedia_upd __P((struct ifnet *)); 148 void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 149 150 void rl_eeprom_putbyte __P((struct rl_softc *, int)); 151 void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 152 void rl_read_eeprom __P((struct rl_softc *, caddr_t, int, int, int)); 153 154 void rl_mii_sync __P((struct rl_softc *)); 155 void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 156 int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 157 int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 158 159 int rl_miibus_readreg __P((struct device *, int, int)); 160 void rl_miibus_writereg __P((struct device *, int, int, int)); 161 void rl_miibus_statchg __P((struct device *)); 162 163 u_int8_t rl_calchash __P((caddr_t)); 164 void rl_setmulti __P((struct rl_softc *)); 165 void rl_reset __P((struct rl_softc *)); 166 int rl_list_tx_init __P((struct rl_softc *)); 167 168 #define EE_SET(x) \ 169 CSR_WRITE_1(sc, RL_EECMD, \ 170 CSR_READ_1(sc, RL_EECMD) | x) 171 172 #define EE_CLR(x) \ 173 CSR_WRITE_1(sc, RL_EECMD, \ 174 CSR_READ_1(sc, RL_EECMD) & ~x) 175 176 /* 177 * Send a read command and address to the EEPROM, check for ACK. 178 */ 179 void rl_eeprom_putbyte(sc, addr) 180 struct rl_softc *sc; 181 int addr; 182 { 183 register int d, i; 184 185 d = addr | RL_EECMD_READ; 186 187 /* 188 * Feed in each bit and strobe the clock. 189 */ 190 for (i = 0x400; i; i >>= 1) { 191 if (d & i) { 192 EE_SET(RL_EE_DATAIN); 193 } else { 194 EE_CLR(RL_EE_DATAIN); 195 } 196 DELAY(100); 197 EE_SET(RL_EE_CLK); 198 DELAY(150); 199 EE_CLR(RL_EE_CLK); 200 DELAY(100); 201 } 202 203 return; 204 } 205 206 /* 207 * Read a word of data stored in the EEPROM at address 'addr.' 208 */ 209 void rl_eeprom_getword(sc, addr, dest) 210 struct rl_softc *sc; 211 int addr; 212 u_int16_t *dest; 213 { 214 register int i; 215 u_int16_t word = 0; 216 217 /* Enter EEPROM access mode. */ 218 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 219 220 /* 221 * Send address of word we want to read. 222 */ 223 rl_eeprom_putbyte(sc, addr); 224 225 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 226 227 /* 228 * Start reading bits from EEPROM. 229 */ 230 for (i = 0x8000; i; i >>= 1) { 231 EE_SET(RL_EE_CLK); 232 DELAY(100); 233 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 234 word |= i; 235 EE_CLR(RL_EE_CLK); 236 DELAY(100); 237 } 238 239 /* Turn off EEPROM access mode. */ 240 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 241 242 *dest = word; 243 244 return; 245 } 246 247 /* 248 * Read a sequence of words from the EEPROM. 249 */ 250 void rl_read_eeprom(sc, dest, off, cnt, swap) 251 struct rl_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256 { 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 rl_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270 } 271 272 273 /* 274 * MII access routines are provided for the 8129, which 275 * doesn't have a built-in PHY. For the 8139, we fake things 276 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 277 * direct access PHY registers. 278 */ 279 #define MII_SET(x) \ 280 CSR_WRITE_1(sc, RL_MII, \ 281 CSR_READ_1(sc, RL_MII) | x) 282 283 #define MII_CLR(x) \ 284 CSR_WRITE_1(sc, RL_MII, \ 285 CSR_READ_1(sc, RL_MII) & ~x) 286 287 /* 288 * Sync the PHYs by setting data bit and strobing the clock 32 times. 289 */ 290 void rl_mii_sync(sc) 291 struct rl_softc *sc; 292 { 293 register int i; 294 295 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 296 297 for (i = 0; i < 32; i++) { 298 MII_SET(RL_MII_CLK); 299 DELAY(1); 300 MII_CLR(RL_MII_CLK); 301 DELAY(1); 302 } 303 304 return; 305 } 306 307 /* 308 * Clock a series of bits through the MII. 309 */ 310 void rl_mii_send(sc, bits, cnt) 311 struct rl_softc *sc; 312 u_int32_t bits; 313 int cnt; 314 { 315 int i; 316 317 MII_CLR(RL_MII_CLK); 318 319 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 320 if (bits & i) { 321 MII_SET(RL_MII_DATAOUT); 322 } else { 323 MII_CLR(RL_MII_DATAOUT); 324 } 325 DELAY(1); 326 MII_CLR(RL_MII_CLK); 327 DELAY(1); 328 MII_SET(RL_MII_CLK); 329 } 330 } 331 332 /* 333 * Read an PHY register through the MII. 334 */ 335 int rl_mii_readreg(sc, frame) 336 struct rl_softc *sc; 337 struct rl_mii_frame *frame; 338 339 { 340 int i, ack, s; 341 342 s = splimp(); 343 344 /* 345 * Set up frame for RX. 346 */ 347 frame->mii_stdelim = RL_MII_STARTDELIM; 348 frame->mii_opcode = RL_MII_READOP; 349 frame->mii_turnaround = 0; 350 frame->mii_data = 0; 351 352 CSR_WRITE_2(sc, RL_MII, 0); 353 354 /* 355 * Turn on data xmit. 356 */ 357 MII_SET(RL_MII_DIR); 358 359 rl_mii_sync(sc); 360 361 /* 362 * Send command/address info. 363 */ 364 rl_mii_send(sc, frame->mii_stdelim, 2); 365 rl_mii_send(sc, frame->mii_opcode, 2); 366 rl_mii_send(sc, frame->mii_phyaddr, 5); 367 rl_mii_send(sc, frame->mii_regaddr, 5); 368 369 /* Idle bit */ 370 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 371 DELAY(1); 372 MII_SET(RL_MII_CLK); 373 DELAY(1); 374 375 /* Turn off xmit. */ 376 MII_CLR(RL_MII_DIR); 377 378 /* Check for ack */ 379 MII_CLR(RL_MII_CLK); 380 DELAY(1); 381 MII_SET(RL_MII_CLK); 382 DELAY(1); 383 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 384 385 /* 386 * Now try reading data bits. If the ack failed, we still 387 * need to clock through 16 cycles to keep the PHY(s) in sync. 388 */ 389 if (ack) { 390 for(i = 0; i < 16; i++) { 391 MII_CLR(RL_MII_CLK); 392 DELAY(1); 393 MII_SET(RL_MII_CLK); 394 DELAY(1); 395 } 396 goto fail; 397 } 398 399 for (i = 0x8000; i; i >>= 1) { 400 MII_CLR(RL_MII_CLK); 401 DELAY(1); 402 if (!ack) { 403 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 404 frame->mii_data |= i; 405 DELAY(1); 406 } 407 MII_SET(RL_MII_CLK); 408 DELAY(1); 409 } 410 411 fail: 412 413 MII_CLR(RL_MII_CLK); 414 DELAY(1); 415 MII_SET(RL_MII_CLK); 416 DELAY(1); 417 418 splx(s); 419 420 if (ack) 421 return(1); 422 return(0); 423 } 424 425 /* 426 * Write to a PHY register through the MII. 427 */ 428 int rl_mii_writereg(sc, frame) 429 struct rl_softc *sc; 430 struct rl_mii_frame *frame; 431 432 { 433 int s; 434 435 s = splimp(); 436 /* 437 * Set up frame for TX. 438 */ 439 440 frame->mii_stdelim = RL_MII_STARTDELIM; 441 frame->mii_opcode = RL_MII_WRITEOP; 442 frame->mii_turnaround = RL_MII_TURNAROUND; 443 444 /* 445 * Turn on data output. 446 */ 447 MII_SET(RL_MII_DIR); 448 449 rl_mii_sync(sc); 450 451 rl_mii_send(sc, frame->mii_stdelim, 2); 452 rl_mii_send(sc, frame->mii_opcode, 2); 453 rl_mii_send(sc, frame->mii_phyaddr, 5); 454 rl_mii_send(sc, frame->mii_regaddr, 5); 455 rl_mii_send(sc, frame->mii_turnaround, 2); 456 rl_mii_send(sc, frame->mii_data, 16); 457 458 /* Idle bit. */ 459 MII_SET(RL_MII_CLK); 460 DELAY(1); 461 MII_CLR(RL_MII_CLK); 462 DELAY(1); 463 464 /* 465 * Turn off xmit. 466 */ 467 MII_CLR(RL_MII_DIR); 468 469 splx(s); 470 471 return(0); 472 } 473 474 /* 475 * Calculate CRC of a multicast group address, return the upper 6 bits. 476 */ 477 u_int8_t rl_calchash(addr) 478 caddr_t addr; 479 { 480 u_int32_t crc, carry; 481 int i, j; 482 u_int8_t c; 483 484 /* Compute CRC for the address value. */ 485 crc = 0xFFFFFFFF; /* initial value */ 486 487 for (i = 0; i < 6; i++) { 488 c = *(addr + i); 489 for (j = 0; j < 8; j++) { 490 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 491 crc <<= 1; 492 c >>= 1; 493 if (carry) 494 crc = (crc ^ 0x04c11db6) | carry; 495 } 496 } 497 498 /* return the filter bit position */ 499 return(crc >> 26); 500 } 501 502 /* 503 * Program the 64-bit multicast hash filter. 504 */ 505 void rl_setmulti(sc) 506 struct rl_softc *sc; 507 { 508 struct ifnet *ifp; 509 int h = 0; 510 u_int32_t hashes[2] = { 0, 0 }; 511 struct arpcom *ac = &sc->arpcom; 512 struct ether_multi *enm; 513 struct ether_multistep step; 514 u_int32_t rxfilt; 515 int mcnt = 0; 516 517 ifp = &sc->arpcom.ac_if; 518 519 rxfilt = CSR_READ_4(sc, RL_RXCFG); 520 521 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 522 rxfilt |= RL_RXCFG_RX_MULTI; 523 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 524 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 525 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 526 return; 527 } 528 529 /* first, zot all the existing hash bits */ 530 CSR_WRITE_4(sc, RL_MAR0, 0); 531 CSR_WRITE_4(sc, RL_MAR4, 0); 532 533 /* now program new ones */ 534 ETHER_FIRST_MULTI(step, ac, enm); 535 while (enm != NULL) { 536 mcnt++; 537 h = rl_calchash(enm->enm_addrlo); 538 if (h < 32) 539 hashes[0] |= (1 << h); 540 else 541 hashes[1] |= (1 << (h - 32)); 542 mcnt++; 543 ETHER_NEXT_MULTI(step, enm); 544 } 545 546 if (mcnt) 547 rxfilt |= RL_RXCFG_RX_MULTI; 548 else 549 rxfilt &= ~RL_RXCFG_RX_MULTI; 550 551 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 552 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 553 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 554 555 return; 556 } 557 558 void rl_reset(sc) 559 struct rl_softc *sc; 560 { 561 register int i; 562 563 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 564 565 for (i = 0; i < RL_TIMEOUT; i++) { 566 DELAY(10); 567 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 568 break; 569 } 570 if (i == RL_TIMEOUT) 571 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 572 573 return; 574 } 575 576 /* 577 * Initialize the transmit descriptors. 578 */ 579 int rl_list_tx_init(sc) 580 struct rl_softc *sc; 581 { 582 struct rl_chain_data *cd; 583 int i; 584 585 cd = &sc->rl_cdata; 586 for (i = 0; i < RL_TX_LIST_CNT; i++) { 587 cd->rl_tx_chain[i] = NULL; 588 CSR_WRITE_4(sc, 589 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 590 } 591 592 sc->rl_cdata.cur_tx = 0; 593 sc->rl_cdata.last_tx = 0; 594 595 return(0); 596 } 597 598 /* 599 * A frame has been uploaded: pass the resulting mbuf chain up to 600 * the higher level protocols. 601 * 602 * You know there's something wrong with a PCI bus-master chip design 603 * when you have to use m_devget(). 604 * 605 * The receive operation is badly documented in the datasheet, so I'll 606 * attempt to document it here. The driver provides a buffer area and 607 * places its base address in the RX buffer start address register. 608 * The chip then begins copying frames into the RX buffer. Each frame 609 * is preceeded by a 32-bit RX status word which specifies the length 610 * of the frame and certain other status bits. Each frame (starting with 611 * the status word) is also 32-bit aligned. The frame length is in the 612 * first 16 bits of the status word; the lower 15 bits correspond with 613 * the 'rx status register' mentioned in the datasheet. 614 * 615 * Note: to make the Alpha happy, the frame payload needs to be aligned 616 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 617 * the ring buffer starting at an address two bytes before the actual 618 * data location. We can then shave off the first two bytes using m_adj(). 619 * The reason we do this is because m_devget() doesn't let us specify an 620 * offset into the mbuf storage space, so we have to artificially create 621 * one. The ring is allocated in such a way that there are a few unused 622 * bytes of space preceecing it so that it will be safe for us to do the 623 * 2-byte backstep even if reading from the ring at offset 0. 624 */ 625 void rl_rxeof(sc) 626 struct rl_softc *sc; 627 { 628 struct mbuf *m; 629 struct ifnet *ifp; 630 int total_len = 0; 631 u_int32_t rxstat; 632 caddr_t rxbufpos; 633 int wrap = 0; 634 u_int16_t cur_rx; 635 u_int16_t limit; 636 u_int16_t rx_bytes = 0, max_bytes; 637 638 ifp = &sc->arpcom.ac_if; 639 640 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 641 642 /* Do not try to read past this point. */ 643 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 644 645 if (limit < cur_rx) 646 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 647 else 648 max_bytes = limit - cur_rx; 649 650 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 651 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 652 rxstat = *(u_int32_t *)rxbufpos; 653 654 /* 655 * Here's a totally undocumented fact for you. When the 656 * RealTek chip is in the process of copying a packet into 657 * RAM for you, the length will be 0xfff0. If you spot a 658 * packet header with this value, you need to stop. The 659 * datasheet makes absolutely no mention of this and 660 * RealTek should be shot for this. 661 */ 662 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 663 break; 664 665 if (!(rxstat & RL_RXSTAT_RXOK)) { 666 ifp->if_ierrors++; 667 rl_init(sc); 668 return; 669 } 670 671 /* No errors; receive the packet. */ 672 total_len = rxstat >> 16; 673 rx_bytes += total_len + 4; 674 675 /* 676 * XXX The RealTek chip includes the CRC with every 677 * received frame, and there's no way to turn this 678 * behavior off (at least, I can't find anything in 679 * the manual that explains how to do it) so we have 680 * to trim off the CRC manually. 681 */ 682 total_len -= ETHER_CRC_LEN; 683 684 /* 685 * Avoid trying to read more bytes than we know 686 * the chip has prepared for us. 687 */ 688 if (rx_bytes > max_bytes) 689 break; 690 691 rxbufpos = sc->rl_cdata.rl_rx_buf + 692 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 693 694 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 695 rxbufpos = sc->rl_cdata.rl_rx_buf; 696 697 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 698 699 if (total_len > wrap) { 700 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 701 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 702 if (m == NULL) 703 ifp->if_ierrors++; 704 else { 705 m_adj(m, RL_ETHER_ALIGN); 706 m_copyback(m, wrap, total_len - wrap, 707 sc->rl_cdata.rl_rx_buf); 708 m = m_pullup(m, sizeof(struct ether_header)); 709 if (m == NULL) 710 ifp->if_ierrors++; 711 } 712 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 713 } else { 714 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 715 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 716 if (m == NULL) 717 ifp->if_ierrors++; 718 else 719 m_adj(m, RL_ETHER_ALIGN); 720 cur_rx += total_len + 4 + ETHER_CRC_LEN; 721 } 722 723 /* 724 * Round up to 32-bit boundary. 725 */ 726 cur_rx = (cur_rx + 3) & ~3; 727 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 728 729 if (m == NULL) 730 continue; 731 732 ifp->if_ipackets++; 733 734 #if NBPFILTER > 0 735 /* 736 * Handle BPF listeners. Let the BPF user see the packet. 737 */ 738 if (ifp->if_bpf) 739 bpf_mtap(ifp->if_bpf, m); 740 #endif 741 ether_input_mbuf(ifp, m); 742 } 743 744 return; 745 } 746 747 /* 748 * A frame was downloaded to the chip. It's safe for us to clean up 749 * the list buffers. 750 */ 751 void rl_txeof(sc) 752 struct rl_softc *sc; 753 { 754 struct ifnet *ifp; 755 u_int32_t txstat; 756 757 ifp = &sc->arpcom.ac_if; 758 759 /* Clear the timeout timer. */ 760 ifp->if_timer = 0; 761 762 /* 763 * Go through our tx list and free mbufs for those 764 * frames that have been uploaded. 765 */ 766 do { 767 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 768 if (!(txstat & (RL_TXSTAT_TX_OK| 769 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 770 break; 771 772 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 773 774 if (RL_LAST_TXMBUF(sc) != NULL) { 775 m_freem(RL_LAST_TXMBUF(sc)); 776 RL_LAST_TXMBUF(sc) = NULL; 777 } 778 if (txstat & RL_TXSTAT_TX_OK) 779 ifp->if_opackets++; 780 else { 781 int oldthresh; 782 783 ifp->if_oerrors++; 784 if ((txstat & RL_TXSTAT_TXABRT) || 785 (txstat & RL_TXSTAT_OUTOFWIN)) 786 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 787 oldthresh = sc->rl_txthresh; 788 /* error recovery */ 789 rl_reset(sc); 790 rl_init(sc); 791 /* 792 * If there was a transmit underrun, 793 * bump the TX threshold. 794 */ 795 if (txstat & RL_TXSTAT_TX_UNDERRUN) 796 sc->rl_txthresh = oldthresh + 32; 797 return; 798 } 799 RL_INC(sc->rl_cdata.last_tx); 800 ifp->if_flags &= ~IFF_OACTIVE; 801 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 802 } 803 804 int rl_intr(arg) 805 void *arg; 806 { 807 struct rl_softc *sc; 808 struct ifnet *ifp; 809 int claimed = 0; 810 u_int16_t status; 811 812 sc = arg; 813 ifp = &sc->arpcom.ac_if; 814 815 /* Disable interrupts. */ 816 CSR_WRITE_2(sc, RL_IMR, 0x0000); 817 818 for (;;) { 819 820 status = CSR_READ_2(sc, RL_ISR); 821 if (status) 822 CSR_WRITE_2(sc, RL_ISR, status); 823 824 if ((status & RL_INTRS) == 0) 825 break; 826 827 if (status & RL_ISR_RX_OK) 828 rl_rxeof(sc); 829 830 if (status & RL_ISR_RX_ERR) 831 rl_rxeof(sc); 832 833 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 834 rl_txeof(sc); 835 836 if (status & RL_ISR_SYSTEM_ERR) { 837 rl_reset(sc); 838 rl_init(sc); 839 } 840 claimed = 1; 841 } 842 843 /* Re-enable interrupts. */ 844 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 845 846 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 847 rl_start(ifp); 848 849 return (claimed); 850 } 851 852 /* 853 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 854 * pointers to the fragment pointers. 855 */ 856 int rl_encap(sc, m_head) 857 struct rl_softc *sc; 858 struct mbuf *m_head; 859 { 860 struct mbuf *m_new = NULL; 861 862 /* 863 * The RealTek is brain damaged and wants longword-aligned 864 * TX buffers, plus we can only have one fragment buffer 865 * per packet. We have to copy pretty much all the time. 866 */ 867 868 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 869 if (m_new == NULL) 870 return(1); 871 if (m_head->m_pkthdr.len > MHLEN) { 872 MCLGET(m_new, M_DONTWAIT); 873 874 if (!(m_new->m_flags & M_EXT)) { 875 m_freem(m_new); 876 return(1); 877 } 878 } 879 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 880 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 881 m_freem(m_head); 882 m_head = m_new; 883 884 /* Pad frames to at least 60 bytes. */ 885 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 886 /* 887 * Make security concious people happy: zero out the 888 * bytes in the pad area, since we don't know what 889 * this mbuf cluster buffer's previous user might 890 * have left in it. 891 */ 892 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 893 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 894 m_head->m_pkthdr.len += 895 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 896 m_head->m_len = m_head->m_pkthdr.len; 897 } 898 899 RL_CUR_TXMBUF(sc) = m_head; 900 901 return(0); 902 } 903 904 /* 905 * Main transmit routine. 906 */ 907 908 void rl_start(ifp) 909 struct ifnet *ifp; 910 { 911 struct rl_softc *sc; 912 struct mbuf *m_head = NULL; 913 int pkts = 0; 914 915 sc = ifp->if_softc; 916 917 while(RL_CUR_TXMBUF(sc) == NULL) { 918 IFQ_DEQUEUE(&ifp->if_snd, m_head); 919 if (m_head == NULL) 920 break; 921 922 /* Pack the data into the descriptor. */ 923 rl_encap(sc, m_head); 924 pkts++; 925 926 #if NBPFILTER > 0 927 /* 928 * If there's a BPF listener, bounce a copy of this frame 929 * to him. 930 */ 931 if (ifp->if_bpf) 932 bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc)); 933 #endif 934 /* 935 * Transmit the frame. 936 */ 937 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 938 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 939 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 940 RL_TXTHRESH(sc->rl_txthresh) | 941 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 942 943 RL_INC(sc->rl_cdata.cur_tx); 944 } 945 if (pkts == 0) 946 return; 947 948 /* 949 * We broke out of the loop because all our TX slots are 950 * full. Mark the NIC as busy until it drains some of the 951 * packets from the queue. 952 */ 953 if (RL_CUR_TXMBUF(sc) != NULL) 954 ifp->if_flags |= IFF_OACTIVE; 955 956 /* 957 * Set a timeout in case the chip goes out to lunch. 958 */ 959 ifp->if_timer = 5; 960 961 return; 962 } 963 964 void rl_init(xsc) 965 void *xsc; 966 { 967 struct rl_softc *sc = xsc; 968 struct ifnet *ifp = &sc->arpcom.ac_if; 969 int s, i; 970 u_int32_t rxcfg = 0; 971 972 s = splimp(); 973 974 /* 975 * Cancel pending I/O and free all RX/TX buffers. 976 */ 977 rl_stop(sc); 978 979 /* Init our MAC address */ 980 for (i = 0; i < ETHER_ADDR_LEN; i++) { 981 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 982 } 983 984 /* Init the RX buffer pointer register. */ 985 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 986 987 /* Init TX descriptors. */ 988 rl_list_tx_init(sc); 989 990 /* 991 * Enable transmit and receive. 992 */ 993 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 994 995 /* 996 * Set the inital TX and RX configuration. 997 */ 998 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 999 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1000 1001 /* Set the individual bit to receive frames for this host only. */ 1002 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1003 rxcfg |= RL_RXCFG_RX_INDIV; 1004 1005 /* If we want promiscuous mode, set the allframes bit. */ 1006 if (ifp->if_flags & IFF_PROMISC) { 1007 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1008 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1009 } else { 1010 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1011 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1012 } 1013 1014 /* 1015 * Set capture broadcast bit to capture broadcast frames. 1016 */ 1017 if (ifp->if_flags & IFF_BROADCAST) { 1018 rxcfg |= RL_RXCFG_RX_BROAD; 1019 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1020 } else { 1021 rxcfg &= ~RL_RXCFG_RX_BROAD; 1022 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1023 } 1024 1025 /* 1026 * Program the multicast filter, if necessary. 1027 */ 1028 rl_setmulti(sc); 1029 1030 /* 1031 * Enable interrupts. 1032 */ 1033 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1034 1035 /* Set initial TX threshold */ 1036 sc->rl_txthresh = RL_TX_THRESH_INIT; 1037 1038 /* Start RX/TX process. */ 1039 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1040 1041 /* Enable receiver and transmitter. */ 1042 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1043 1044 mii_mediachg(&sc->sc_mii); 1045 1046 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1047 1048 ifp->if_flags |= IFF_RUNNING; 1049 ifp->if_flags &= ~IFF_OACTIVE; 1050 1051 (void)splx(s); 1052 1053 timeout_set(&sc->sc_tick_tmo, rl_tick, sc); 1054 timeout_add(&sc->sc_tick_tmo, hz); 1055 1056 return; 1057 } 1058 1059 /* 1060 * Set media options. 1061 */ 1062 int rl_ifmedia_upd(ifp) 1063 struct ifnet *ifp; 1064 { 1065 struct rl_softc *sc = (struct rl_softc *)ifp->if_softc; 1066 1067 mii_mediachg(&sc->sc_mii); 1068 return (0); 1069 } 1070 1071 /* 1072 * Report current media status. 1073 */ 1074 void rl_ifmedia_sts(ifp, ifmr) 1075 struct ifnet *ifp; 1076 struct ifmediareq *ifmr; 1077 { 1078 struct rl_softc *sc = ifp->if_softc; 1079 1080 mii_pollstat(&sc->sc_mii); 1081 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1082 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1083 } 1084 1085 int rl_ioctl(ifp, command, data) 1086 struct ifnet *ifp; 1087 u_long command; 1088 caddr_t data; 1089 { 1090 struct rl_softc *sc = ifp->if_softc; 1091 struct ifreq *ifr = (struct ifreq *) data; 1092 struct ifaddr *ifa = (struct ifaddr *)data; 1093 int s, error = 0; 1094 1095 s = splimp(); 1096 1097 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1098 splx(s); 1099 return error; 1100 } 1101 1102 switch(command) { 1103 case SIOCSIFADDR: 1104 ifp->if_flags |= IFF_UP; 1105 switch (ifa->ifa_addr->sa_family) { 1106 #ifdef INET 1107 case AF_INET: 1108 rl_init(sc); 1109 arp_ifinit(&sc->arpcom, ifa); 1110 break; 1111 #endif /* INET */ 1112 default: 1113 rl_init(sc); 1114 break; 1115 } 1116 break; 1117 case SIOCSIFFLAGS: 1118 if (ifp->if_flags & IFF_UP) { 1119 rl_init(sc); 1120 } else { 1121 if (ifp->if_flags & IFF_RUNNING) 1122 rl_stop(sc); 1123 } 1124 error = 0; 1125 break; 1126 case SIOCADDMULTI: 1127 case SIOCDELMULTI: 1128 error = (command == SIOCADDMULTI) ? 1129 ether_addmulti(ifr, &sc->arpcom) : 1130 ether_delmulti(ifr, &sc->arpcom); 1131 1132 if (error == ENETRESET) { 1133 /* 1134 * Multicast list has changed; set the hardware 1135 * filter accordingly. 1136 */ 1137 rl_setmulti(sc); 1138 error = 0; 1139 } 1140 break; 1141 case SIOCGIFMEDIA: 1142 case SIOCSIFMEDIA: 1143 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1144 break; 1145 default: 1146 error = EINVAL; 1147 break; 1148 } 1149 1150 (void)splx(s); 1151 1152 return(error); 1153 } 1154 1155 void rl_watchdog(ifp) 1156 struct ifnet *ifp; 1157 { 1158 struct rl_softc *sc; 1159 1160 sc = ifp->if_softc; 1161 1162 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1163 ifp->if_oerrors++; 1164 rl_txeof(sc); 1165 rl_rxeof(sc); 1166 rl_init(sc); 1167 1168 return; 1169 } 1170 1171 /* 1172 * Stop the adapter and free any mbufs allocated to the 1173 * RX and TX lists. 1174 */ 1175 void rl_stop(sc) 1176 struct rl_softc *sc; 1177 { 1178 register int i; 1179 struct ifnet *ifp; 1180 1181 ifp = &sc->arpcom.ac_if; 1182 ifp->if_timer = 0; 1183 1184 timeout_del(&sc->sc_tick_tmo); 1185 1186 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1187 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1188 1189 /* 1190 * Free the TX list buffers. 1191 */ 1192 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1193 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1194 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1195 sc->rl_cdata.rl_tx_chain[i] = NULL; 1196 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x00000000); 1197 } 1198 } 1199 1200 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1201 1202 return; 1203 } 1204 1205 int 1206 rl_attach(sc) 1207 struct rl_softc *sc; 1208 { 1209 struct ifnet *ifp = &sc->arpcom.ac_if; 1210 bus_dma_segment_t seg; 1211 bus_dmamap_t dmamap; 1212 int rseg; 1213 u_int16_t rl_did; 1214 caddr_t kva; 1215 1216 rl_reset(sc); 1217 1218 rl_read_eeprom(sc, (caddr_t)sc->arpcom.ac_enaddr, RL_EE_EADDR, 3, 0); 1219 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 1220 1221 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1222 1223 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 1224 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 1225 || rl_did == DLINK_DEVICEID_8139) 1226 sc->rl_type = RL_8139; 1227 else if (rl_did == RT_DEVICEID_8129) 1228 sc->rl_type = RL_8129; 1229 else { 1230 printf("\n%s: unknown device id: %x\n", sc->sc_dev.dv_xname, 1231 rl_did); 1232 return (1); 1233 } 1234 1235 if (bus_dmamem_alloc(sc->sc_dmat, RL_RXBUFLEN + 32, PAGE_SIZE, 0, 1236 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1237 printf("\n%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); 1238 return (1); 1239 } 1240 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RL_RXBUFLEN + 32, &kva, 1241 BUS_DMA_NOWAIT)) { 1242 printf("%s: can't map dma buffers (%d bytes)\n", 1243 sc->sc_dev.dv_xname, RL_RXBUFLEN + 32); 1244 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1245 return (1); 1246 } 1247 if (bus_dmamap_create(sc->sc_dmat, RL_RXBUFLEN + 32, 1, 1248 RL_RXBUFLEN + 32, 0, BUS_DMA_NOWAIT, &dmamap)) { 1249 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 1250 bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32); 1251 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1252 return (1); 1253 } 1254 if (bus_dmamap_load(sc->sc_dmat, dmamap, kva, RL_RXBUFLEN + 32, 1255 NULL, BUS_DMA_NOWAIT)) { 1256 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 1257 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1258 bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32); 1259 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1260 return (1); 1261 } 1262 sc->rl_cdata.rl_rx_buf = kva; 1263 bzero(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32); 1264 1265 /* Leave a few bytes before the start of the RX ring buffer. */ 1266 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1267 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1268 1269 ifp->if_softc = sc; 1270 ifp->if_mtu = ETHERMTU; 1271 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1272 ifp->if_ioctl = rl_ioctl; 1273 ifp->if_output = ether_output; 1274 ifp->if_start = rl_start; 1275 ifp->if_watchdog = rl_watchdog; 1276 ifp->if_baudrate = 10000000; 1277 IFQ_SET_READY(&ifp->if_snd); 1278 1279 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1280 1281 #if NVLAN > 0 1282 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1283 #endif 1284 1285 /* 1286 * Initialize our media structures and probe the MII. 1287 */ 1288 sc->sc_mii.mii_ifp = ifp; 1289 sc->sc_mii.mii_readreg = rl_miibus_readreg; 1290 sc->sc_mii.mii_writereg = rl_miibus_writereg; 1291 sc->sc_mii.mii_statchg = rl_miibus_statchg; 1292 ifmedia_init(&sc->sc_mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts); 1293 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1294 MII_OFFSET_ANY, 0); 1295 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1296 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1297 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1298 } else 1299 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1300 1301 /* 1302 * Attach us everywhere 1303 */ 1304 if_attach(ifp); 1305 ether_ifattach(ifp); 1306 1307 shutdownhook_establish(rl_shutdown, sc); 1308 1309 return (0); 1310 } 1311 1312 void rl_shutdown(arg) 1313 void *arg; 1314 { 1315 struct rl_softc *sc = (struct rl_softc *)arg; 1316 1317 rl_stop(sc); 1318 } 1319 1320 int 1321 rl_miibus_readreg(self, phy, reg) 1322 struct device *self; 1323 int phy, reg; 1324 { 1325 struct rl_softc *sc = (struct rl_softc *)self; 1326 struct rl_mii_frame frame; 1327 u_int16_t rl8139_reg; 1328 1329 if (sc->rl_type == RL_8139) { 1330 /* 1331 * The RTL8139 PHY is mapped into PCI registers, unforunately 1332 * it has no phyid, or phyaddr, so assume it is phyaddr 0. 1333 */ 1334 if (phy != 0) 1335 return(0); 1336 1337 switch (reg) { 1338 case MII_BMCR: 1339 rl8139_reg = RL_BMCR; 1340 break; 1341 case MII_BMSR: 1342 rl8139_reg = RL_BMSR; 1343 break; 1344 case MII_ANAR: 1345 rl8139_reg = RL_ANAR; 1346 break; 1347 case MII_ANER: 1348 rl8139_reg = RL_ANER; 1349 break; 1350 case MII_ANLPAR: 1351 rl8139_reg = RL_LPAR; 1352 break; 1353 case MII_PHYIDR1: 1354 case MII_PHYIDR2: 1355 return (0); 1356 break; 1357 } 1358 return (CSR_READ_2(sc, rl8139_reg)); 1359 } 1360 1361 bzero((char *)&frame, sizeof(frame)); 1362 1363 frame.mii_phyaddr = phy; 1364 frame.mii_regaddr = reg; 1365 rl_mii_readreg(sc, &frame); 1366 1367 return(frame.mii_data); 1368 } 1369 1370 void 1371 rl_miibus_writereg(self, phy, reg, val) 1372 struct device *self; 1373 int phy, reg, val; 1374 { 1375 struct rl_softc *sc = (struct rl_softc *)self; 1376 struct rl_mii_frame frame; 1377 u_int16_t rl8139_reg = 0; 1378 1379 if (sc->rl_type == RL_8139) { 1380 if (phy) 1381 return; 1382 1383 switch (reg) { 1384 case MII_BMCR: 1385 rl8139_reg = RL_BMCR; 1386 break; 1387 case MII_BMSR: 1388 rl8139_reg = RL_BMSR; 1389 break; 1390 case MII_ANAR: 1391 rl8139_reg = RL_ANAR; 1392 break; 1393 case MII_ANER: 1394 rl8139_reg = RL_ANER; 1395 break; 1396 case MII_ANLPAR: 1397 rl8139_reg = RL_LPAR; 1398 break; 1399 case MII_PHYIDR1: 1400 case MII_PHYIDR2: 1401 return; 1402 } 1403 CSR_WRITE_2(sc, rl8139_reg, val); 1404 return; 1405 } 1406 1407 bzero((char *)&frame, sizeof(frame)); 1408 frame.mii_phyaddr = phy; 1409 frame.mii_regaddr = reg; 1410 frame.mii_data = val; 1411 rl_mii_writereg(sc, &frame); 1412 } 1413 1414 void 1415 rl_miibus_statchg(self) 1416 struct device *self; 1417 { 1418 return; 1419 } 1420 1421 void 1422 rl_tick(v) 1423 void *v; 1424 { 1425 struct rl_softc *sc = v; 1426 1427 mii_tick(&sc->sc_mii); 1428 timeout_add(&sc->sc_tick_tmo, hz); 1429 } 1430 1431 struct cfdriver rl_cd = { 1432 0, "rl", DV_IFNET 1433 }; 1434