1 /* $OpenBSD: rt2860.c,v 1.91 2016/08/17 11:50:52 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 21 * http://www.ralinktech.com/ 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/queue.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/ic/rt2860var.h> 57 #include <dev/ic/rt2860reg.h> 58 59 #include <dev/pci/pcidevs.h> 60 61 #ifdef RAL_DEBUG 62 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 64 int rt2860_debug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 void rt2860_attachhook(struct device *); 71 int rt2860_alloc_tx_ring(struct rt2860_softc *, 72 struct rt2860_tx_ring *); 73 void rt2860_reset_tx_ring(struct rt2860_softc *, 74 struct rt2860_tx_ring *); 75 void rt2860_free_tx_ring(struct rt2860_softc *, 76 struct rt2860_tx_ring *); 77 int rt2860_alloc_tx_pool(struct rt2860_softc *); 78 void rt2860_free_tx_pool(struct rt2860_softc *); 79 int rt2860_alloc_rx_ring(struct rt2860_softc *, 80 struct rt2860_rx_ring *); 81 void rt2860_reset_rx_ring(struct rt2860_softc *, 82 struct rt2860_rx_ring *); 83 void rt2860_free_rx_ring(struct rt2860_softc *, 84 struct rt2860_rx_ring *); 85 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *); 86 int rt2860_media_change(struct ifnet *); 87 void rt2860_iter_func(void *, struct ieee80211_node *); 88 void rt2860_updatestats(struct rt2860_softc *); 89 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *, 90 int); 91 void rt2860_node_leave(struct ieee80211com *, 92 struct ieee80211_node *); 93 int rt2860_ampdu_rx_start(struct ieee80211com *, 94 struct ieee80211_node *, uint8_t); 95 void rt2860_ampdu_rx_stop(struct ieee80211com *, 96 struct ieee80211_node *, uint8_t); 97 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 98 int); 99 uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 100 uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 101 void rt2860_intr_coherent(struct rt2860_softc *); 102 void rt2860_drain_stats_fifo(struct rt2860_softc *); 103 void rt2860_tx_intr(struct rt2860_softc *, int); 104 void rt2860_rx_intr(struct rt2860_softc *); 105 void rt2860_tbtt_intr(struct rt2860_softc *); 106 void rt2860_gp_intr(struct rt2860_softc *); 107 int rt2860_tx(struct rt2860_softc *, struct mbuf *, 108 struct ieee80211_node *); 109 void rt2860_start(struct ifnet *); 110 void rt2860_watchdog(struct ifnet *); 111 int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 112 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 113 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 114 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 115 uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 116 void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 117 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 118 void rt2860_enable_mrr(struct rt2860_softc *); 119 void rt2860_set_txpreamble(struct rt2860_softc *); 120 void rt2860_set_basicrates(struct rt2860_softc *); 121 void rt2860_select_chan_group(struct rt2860_softc *, int); 122 void rt2860_set_chan(struct rt2860_softc *, u_int); 123 void rt3090_set_chan(struct rt2860_softc *, u_int); 124 void rt5390_set_chan(struct rt2860_softc *, u_int); 125 int rt3090_rf_init(struct rt2860_softc *); 126 void rt5390_rf_init(struct rt2860_softc *); 127 void rt3090_rf_wakeup(struct rt2860_softc *); 128 void rt5390_rf_wakeup(struct rt2860_softc *); 129 int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 130 uint8_t *); 131 void rt3090_rf_setup(struct rt2860_softc *); 132 void rt2860_set_leds(struct rt2860_softc *, uint16_t); 133 void rt2860_set_gp_timer(struct rt2860_softc *, int); 134 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 135 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 136 void rt2860_updateslot(struct ieee80211com *); 137 void rt2860_updateprot(struct ieee80211com *); 138 void rt2860_updateedca(struct ieee80211com *); 139 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 140 struct ieee80211_key *); 141 void rt2860_delete_key(struct ieee80211com *, 142 struct ieee80211_node *, struct ieee80211_key *); 143 #if NBPFILTER > 0 144 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 145 #endif 146 const char * rt2860_get_rf(uint16_t); 147 int rt2860_read_eeprom(struct rt2860_softc *); 148 int rt2860_bbp_init(struct rt2860_softc *); 149 void rt5390_bbp_init(struct rt2860_softc *); 150 int rt2860_txrx_enable(struct rt2860_softc *); 151 int rt2860_init(struct ifnet *); 152 void rt2860_stop(struct ifnet *, int); 153 int rt2860_load_microcode(struct rt2860_softc *); 154 void rt2860_calib(struct rt2860_softc *); 155 void rt3090_set_rx_antenna(struct rt2860_softc *, int); 156 void rt2860_switch_chan(struct rt2860_softc *, 157 struct ieee80211_channel *); 158 #ifndef IEEE80211_STA_ONLY 159 int rt2860_setup_beacon(struct rt2860_softc *); 160 #endif 161 void rt2860_enable_tsf_sync(struct rt2860_softc *); 162 163 static const struct { 164 uint32_t reg; 165 uint32_t val; 166 } rt2860_def_mac[] = { 167 RT2860_DEF_MAC 168 }; 169 170 static const struct { 171 uint8_t reg; 172 uint8_t val; 173 } rt2860_def_bbp[] = { 174 RT2860_DEF_BBP 175 },rt5390_def_bbp[] = { 176 RT5390_DEF_BBP 177 }; 178 179 static const struct rfprog { 180 uint8_t chan; 181 uint32_t r1, r2, r3, r4; 182 } rt2860_rf2850[] = { 183 RT2860_RF2850 184 }; 185 186 struct { 187 uint8_t n, r, k; 188 } rt3090_freqs[] = { 189 RT3070_RF3052 190 }; 191 192 static const struct { 193 uint8_t reg; 194 uint8_t val; 195 } rt3090_def_rf[] = { 196 RT3070_DEF_RF 197 }, rt3572_def_rf[] = { 198 RT3572_DEF_RF 199 }, rt5390_def_rf[] = { 200 RT5390_DEF_RF 201 }, rt5392_def_rf[] = { 202 RT5392_DEF_RF 203 }; 204 205 int 206 rt2860_attach(void *xsc, int id) 207 { 208 struct rt2860_softc *sc = xsc; 209 struct ieee80211com *ic = &sc->sc_ic; 210 int qid, ntries, error; 211 uint32_t tmp; 212 213 sc->amrr.amrr_min_success_threshold = 1; 214 sc->amrr.amrr_max_success_threshold = 15; 215 216 /* wait for NIC to initialize */ 217 for (ntries = 0; ntries < 100; ntries++) { 218 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 219 if (tmp != 0 && tmp != 0xffffffff) 220 break; 221 DELAY(10); 222 } 223 if (ntries == 100) { 224 printf("%s: timeout waiting for NIC to initialize\n", 225 sc->sc_dev.dv_xname); 226 return ETIMEDOUT; 227 } 228 sc->mac_ver = tmp >> 16; 229 sc->mac_rev = tmp & 0xffff; 230 231 if (sc->mac_ver != 0x2860 && 232 (id == PCI_PRODUCT_RALINK_RT2890 || 233 id == PCI_PRODUCT_RALINK_RT2790 || 234 id == PCI_PRODUCT_AWT_RT2890)) 235 sc->sc_flags |= RT2860_ADVANCED_PS; 236 237 /* retrieve RF rev. no and various other things from EEPROM */ 238 rt2860_read_eeprom(sc); 239 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 240 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n", 241 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev, 242 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains); 243 244 /* 245 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 246 */ 247 for (qid = 0; qid < 6; qid++) { 248 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 249 printf("%s: could not allocate Tx ring %d\n", 250 sc->sc_dev.dv_xname, qid); 251 goto fail1; 252 } 253 } 254 255 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 256 printf("%s: could not allocate Rx ring\n", 257 sc->sc_dev.dv_xname); 258 goto fail1; 259 } 260 261 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 262 printf("%s: could not allocate Tx pool\n", 263 sc->sc_dev.dv_xname); 264 goto fail2; 265 } 266 267 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 268 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 269 EDCA_AC_VO : 5; 270 271 config_mountroot(xsc, rt2860_attachhook); 272 273 return 0; 274 275 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 276 fail1: while (--qid >= 0) 277 rt2860_free_tx_ring(sc, &sc->txq[qid]); 278 return error; 279 } 280 281 void 282 rt2860_attachhook(struct device *self) 283 { 284 struct rt2860_softc *sc = (struct rt2860_softc *)self; 285 struct ieee80211com *ic = &sc->sc_ic; 286 struct ifnet *ifp = &ic->ic_if; 287 int i, error; 288 289 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize); 290 if (error != 0) { 291 printf("%s: error %d, could not read firmware file %s\n", 292 sc->sc_dev.dv_xname, error, "ral-rt2860"); 293 return; 294 } 295 296 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 297 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 298 ic->ic_state = IEEE80211_S_INIT; 299 300 /* set device capabilities */ 301 ic->ic_caps = 302 IEEE80211_C_MONITOR | /* monitor mode supported */ 303 #ifndef IEEE80211_STA_ONLY 304 IEEE80211_C_IBSS | /* IBSS mode supported */ 305 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 306 IEEE80211_C_APPMGT | /* HostAP power management */ 307 #endif 308 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 309 IEEE80211_C_SHSLOT | /* short slot time supported */ 310 IEEE80211_C_WEP | /* s/w WEP */ 311 IEEE80211_C_RSN; /* WPA/RSN */ 312 313 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 314 /* set supported .11a rates */ 315 ic->ic_sup_rates[IEEE80211_MODE_11A] = 316 ieee80211_std_rateset_11a; 317 318 /* set supported .11a channels */ 319 for (i = 14; i < nitems(rt2860_rf2850); i++) { 320 uint8_t chan = rt2860_rf2850[i].chan; 321 ic->ic_channels[chan].ic_freq = 322 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 323 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 324 } 325 } 326 327 /* set supported .11b and .11g rates */ 328 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 329 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 330 331 /* set supported .11b and .11g channels (1 through 14) */ 332 for (i = 1; i <= 14; i++) { 333 ic->ic_channels[i].ic_freq = 334 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 335 ic->ic_channels[i].ic_flags = 336 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 337 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 338 } 339 340 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 341 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 342 343 ifp->if_softc = sc; 344 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 345 ifp->if_ioctl = rt2860_ioctl; 346 ifp->if_start = rt2860_start; 347 ifp->if_watchdog = rt2860_watchdog; 348 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 349 350 if_attach(ifp); 351 ieee80211_ifattach(ifp); 352 ic->ic_node_alloc = rt2860_node_alloc; 353 ic->ic_newassoc = rt2860_newassoc; 354 #ifndef IEEE80211_STA_ONLY 355 ic->ic_node_leave = rt2860_node_leave; 356 #endif 357 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 358 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 359 ic->ic_updateslot = rt2860_updateslot; 360 ic->ic_updateedca = rt2860_updateedca; 361 ic->ic_set_key = rt2860_set_key; 362 ic->ic_delete_key = rt2860_delete_key; 363 /* override state transition machine */ 364 sc->sc_newstate = ic->ic_newstate; 365 ic->ic_newstate = rt2860_newstate; 366 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status); 367 368 #if NBPFILTER > 0 369 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 370 sizeof (struct ieee80211_frame) + 64); 371 372 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 373 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 374 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 375 376 sc->sc_txtap_len = sizeof sc->sc_txtapu; 377 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 378 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 379 #endif 380 } 381 382 int 383 rt2860_detach(void *xsc) 384 { 385 struct rt2860_softc *sc = xsc; 386 struct ifnet *ifp = &sc->sc_ic.ic_if; 387 int qid; 388 389 ieee80211_ifdetach(ifp); /* free all nodes */ 390 if_detach(ifp); 391 392 for (qid = 0; qid < 6; qid++) 393 rt2860_free_tx_ring(sc, &sc->txq[qid]); 394 rt2860_free_rx_ring(sc, &sc->rxq); 395 rt2860_free_tx_pool(sc); 396 397 if (sc->ucode != NULL) 398 free(sc->ucode, M_DEVBUF, sc->ucsize); 399 400 return 0; 401 } 402 403 void 404 rt2860_suspend(void *xsc) 405 { 406 struct rt2860_softc *sc = xsc; 407 struct ifnet *ifp = &sc->sc_ic.ic_if; 408 409 if (ifp->if_flags & IFF_RUNNING) 410 rt2860_stop(ifp, 1); 411 } 412 413 void 414 rt2860_wakeup(void *xsc) 415 { 416 struct rt2860_softc *sc = xsc; 417 struct ifnet *ifp = &sc->sc_ic.ic_if; 418 419 if (ifp->if_flags & IFF_UP) 420 rt2860_init(ifp); 421 } 422 423 int 424 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 425 { 426 int nsegs, size, error; 427 428 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 429 430 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 431 BUS_DMA_NOWAIT, &ring->map); 432 if (error != 0) { 433 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 434 goto fail; 435 } 436 437 /* Tx rings must be 4-DWORD aligned */ 438 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 439 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 440 if (error != 0) { 441 printf("%s: could not allocate DMA memory\n", 442 sc->sc_dev.dv_xname); 443 goto fail; 444 } 445 446 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 447 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT); 448 if (error != 0) { 449 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 450 goto fail; 451 } 452 453 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 454 BUS_DMA_NOWAIT); 455 if (error != 0) { 456 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 457 goto fail; 458 } 459 460 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 461 462 ring->paddr = ring->map->dm_segs[0].ds_addr; 463 464 return 0; 465 466 fail: rt2860_free_tx_ring(sc, ring); 467 return error; 468 } 469 470 void 471 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 472 { 473 struct rt2860_tx_data *data; 474 int i; 475 476 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 477 if ((data = ring->data[i]) == NULL) 478 continue; /* nothing mapped in this slot */ 479 480 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 481 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 482 bus_dmamap_unload(sc->sc_dmat, data->map); 483 m_freem(data->m); 484 data->m= NULL; 485 data->ni = NULL; /* node already freed */ 486 487 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 488 ring->data[i] = NULL; 489 } 490 491 ring->queued = 0; 492 ring->cur = ring->next = 0; 493 } 494 495 void 496 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 497 { 498 struct rt2860_tx_data *data; 499 int i; 500 501 if (ring->txd != NULL) { 502 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 503 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 504 bus_dmamap_unload(sc->sc_dmat, ring->map); 505 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd, 506 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 507 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 508 } 509 if (ring->map != NULL) 510 bus_dmamap_destroy(sc->sc_dmat, ring->map); 511 512 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 513 if ((data = ring->data[i]) == NULL) 514 continue; /* nothing mapped in this slot */ 515 516 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 517 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 518 bus_dmamap_unload(sc->sc_dmat, data->map); 519 m_freem(data->m); 520 521 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 522 } 523 } 524 525 /* 526 * Allocate a pool of TX Wireless Information blocks. 527 */ 528 int 529 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 530 { 531 caddr_t vaddr; 532 bus_addr_t paddr; 533 int i, nsegs, size, error; 534 535 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 536 537 /* init data_pool early in case of failure.. */ 538 SLIST_INIT(&sc->data_pool); 539 540 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 541 BUS_DMA_NOWAIT, &sc->txwi_map); 542 if (error != 0) { 543 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 544 goto fail; 545 } 546 547 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 548 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 549 if (error != 0) { 550 printf("%s: could not allocate DMA memory\n", 551 sc->sc_dev.dv_xname); 552 goto fail; 553 } 554 555 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 556 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 557 if (error != 0) { 558 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 559 goto fail; 560 } 561 562 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 563 size, NULL, BUS_DMA_NOWAIT); 564 if (error != 0) { 565 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 566 goto fail; 567 } 568 569 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 570 BUS_DMASYNC_PREWRITE); 571 572 vaddr = sc->txwi_vaddr; 573 paddr = sc->txwi_map->dm_segs[0].ds_addr; 574 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 575 struct rt2860_tx_data *data = &sc->data[i]; 576 577 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 578 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 579 &data->map); /* <0> */ 580 if (error != 0) { 581 printf("%s: could not create DMA map\n", 582 sc->sc_dev.dv_xname); 583 goto fail; 584 } 585 data->txwi = (struct rt2860_txwi *)vaddr; 586 data->paddr = paddr; 587 vaddr += RT2860_TXWI_DMASZ; 588 paddr += RT2860_TXWI_DMASZ; 589 590 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 591 } 592 593 return 0; 594 595 fail: rt2860_free_tx_pool(sc); 596 return error; 597 } 598 599 void 600 rt2860_free_tx_pool(struct rt2860_softc *sc) 601 { 602 if (sc->txwi_vaddr != NULL) { 603 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 604 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 605 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 606 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 607 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 608 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 609 } 610 if (sc->txwi_map != NULL) 611 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 612 613 while (!SLIST_EMPTY(&sc->data_pool)) { 614 struct rt2860_tx_data *data; 615 data = SLIST_FIRST(&sc->data_pool); 616 bus_dmamap_destroy(sc->sc_dmat, data->map); 617 SLIST_REMOVE_HEAD(&sc->data_pool, next); 618 } 619 } 620 621 int 622 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 623 { 624 int i, nsegs, size, error; 625 626 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 627 628 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 629 BUS_DMA_NOWAIT, &ring->map); 630 if (error != 0) { 631 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 632 goto fail; 633 } 634 635 /* Rx ring must be 4-DWORD aligned */ 636 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 637 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 638 if (error != 0) { 639 printf("%s: could not allocate DMA memory\n", 640 sc->sc_dev.dv_xname); 641 goto fail; 642 } 643 644 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 645 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT); 646 if (error != 0) { 647 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 648 goto fail; 649 } 650 651 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 652 BUS_DMA_NOWAIT); 653 if (error != 0) { 654 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 655 goto fail; 656 } 657 658 ring->paddr = ring->map->dm_segs[0].ds_addr; 659 660 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 661 struct rt2860_rx_data *data = &ring->data[i]; 662 struct rt2860_rxd *rxd = &ring->rxd[i]; 663 664 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 665 0, BUS_DMA_NOWAIT, &data->map); 666 if (error != 0) { 667 printf("%s: could not create DMA map\n", 668 sc->sc_dev.dv_xname); 669 goto fail; 670 } 671 672 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 673 if (data->m == NULL) { 674 printf("%s: could not allocate Rx mbuf\n", 675 sc->sc_dev.dv_xname); 676 error = ENOBUFS; 677 goto fail; 678 } 679 680 error = bus_dmamap_load(sc->sc_dmat, data->map, 681 mtod(data->m, void *), MCLBYTES, NULL, 682 BUS_DMA_READ | BUS_DMA_NOWAIT); 683 if (error != 0) { 684 printf("%s: could not load DMA map\n", 685 sc->sc_dev.dv_xname); 686 goto fail; 687 } 688 689 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 690 rxd->sdl0 = htole16(MCLBYTES); 691 } 692 693 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 694 695 return 0; 696 697 fail: rt2860_free_rx_ring(sc, ring); 698 return error; 699 } 700 701 void 702 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 703 { 704 int i; 705 706 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 707 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 708 709 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 710 BUS_DMASYNC_PREWRITE); 711 712 ring->cur = 0; 713 } 714 715 void 716 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 717 { 718 int i; 719 720 if (ring->rxd != NULL) { 721 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 722 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 723 bus_dmamap_unload(sc->sc_dmat, ring->map); 724 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd, 725 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 726 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 727 } 728 if (ring->map != NULL) 729 bus_dmamap_destroy(sc->sc_dmat, ring->map); 730 731 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 732 struct rt2860_rx_data *data = &ring->data[i]; 733 734 if (data->m != NULL) { 735 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 736 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 737 bus_dmamap_unload(sc->sc_dmat, data->map); 738 m_freem(data->m); 739 } 740 if (data->map != NULL) 741 bus_dmamap_destroy(sc->sc_dmat, data->map); 742 } 743 } 744 745 struct ieee80211_node * 746 rt2860_node_alloc(struct ieee80211com *ic) 747 { 748 return malloc(sizeof (struct rt2860_node), M_DEVBUF, 749 M_NOWAIT | M_ZERO); 750 } 751 752 int 753 rt2860_media_change(struct ifnet *ifp) 754 { 755 struct rt2860_softc *sc = ifp->if_softc; 756 struct ieee80211com *ic = &sc->sc_ic; 757 uint8_t rate, ridx; 758 int error; 759 760 error = ieee80211_media_change(ifp); 761 if (error != ENETRESET) 762 return error; 763 764 if (ic->ic_fixed_rate != -1) { 765 rate = ic->ic_sup_rates[ic->ic_curmode]. 766 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 767 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 768 if (rt2860_rates[ridx].rate == rate) 769 break; 770 sc->fixed_ridx = ridx; 771 } 772 773 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 774 (IFF_UP | IFF_RUNNING)) { 775 rt2860_stop(ifp, 0); 776 rt2860_init(ifp); 777 } 778 return 0; 779 } 780 781 void 782 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 783 { 784 struct rt2860_softc *sc = arg; 785 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 786 787 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 788 } 789 790 void 791 rt2860_updatestats(struct rt2860_softc *sc) 792 { 793 struct ieee80211com *ic = &sc->sc_ic; 794 795 #ifndef IEEE80211_STA_ONLY 796 /* 797 * In IBSS or HostAP modes (when the hardware sends beacons), the 798 * MAC can run into a livelock and start sending CTS-to-self frames 799 * like crazy if protection is enabled. Fortunately, we can detect 800 * when such a situation occurs and reset the MAC. 801 */ 802 if (ic->ic_curmode != IEEE80211_M_STA) { 803 /* check if we're in a livelock situation.. */ 804 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 805 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 806 /* ..and reset MAC/BBP for a while.. */ 807 DPRINTF(("CTS-to-self livelock detected\n")); 808 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 809 RAL_BARRIER_WRITE(sc); 810 DELAY(1); 811 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 812 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 813 } 814 } 815 #endif 816 if (ic->ic_opmode == IEEE80211_M_STA) 817 rt2860_iter_func(sc, ic->ic_bss); 818 #ifndef IEEE80211_STA_ONLY 819 else 820 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc); 821 #endif 822 } 823 824 void 825 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 826 { 827 struct rt2860_softc *sc = ic->ic_softc; 828 struct rt2860_node *rn = (void *)ni; 829 struct ieee80211_rateset *rs = &ni->ni_rates; 830 uint8_t rate, wcid = 0; 831 int ridx, i, j; 832 833 if (isnew && ni->ni_associd != 0) { 834 /* only interested in true associations */ 835 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 836 837 /* init WCID table entry */ 838 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 839 ni->ni_macaddr, IEEE80211_ADDR_LEN); 840 } 841 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 842 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 843 844 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 845 /* start at lowest available bit-rate, AMRR will raise */ 846 ni->ni_txrate = 0; 847 848 for (i = 0; i < rs->rs_nrates; i++) { 849 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 850 /* convert 802.11 rate to hardware rate index */ 851 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 852 if (rt2860_rates[ridx].rate == rate) 853 break; 854 rn->ridx[i] = ridx; 855 /* determine rate of control response frames */ 856 for (j = i; j >= 0; j--) { 857 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 858 rt2860_rates[rn->ridx[i]].phy == 859 rt2860_rates[rn->ridx[j]].phy) 860 break; 861 } 862 if (j >= 0) { 863 rn->ctl_ridx[i] = rn->ridx[j]; 864 } else { 865 /* no basic rate found, use mandatory one */ 866 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 867 } 868 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 869 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 870 } 871 } 872 873 #ifndef IEEE80211_STA_ONLY 874 void 875 rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni) 876 { 877 struct rt2860_softc *sc = ic->ic_softc; 878 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 879 880 /* clear Rx WCID search table entry */ 881 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 882 } 883 #endif 884 885 int 886 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 887 uint8_t tid) 888 { 889 struct rt2860_softc *sc = ic->ic_softc; 890 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 891 uint32_t tmp; 892 893 /* update BA session mask */ 894 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 895 tmp |= (1 << tid) << 16; 896 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 897 return 0; 898 } 899 900 void 901 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 902 uint8_t tid) 903 { 904 struct rt2860_softc *sc = ic->ic_softc; 905 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 906 uint32_t tmp; 907 908 /* update BA session mask */ 909 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 910 tmp &= ~((1 << tid) << 16); 911 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 912 } 913 914 int 915 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 916 { 917 struct rt2860_softc *sc = ic->ic_if.if_softc; 918 enum ieee80211_state ostate; 919 uint32_t tmp; 920 921 ostate = ic->ic_state; 922 923 if (ostate == IEEE80211_S_RUN) { 924 /* turn link LED off */ 925 rt2860_set_leds(sc, RT2860_LED_RADIO); 926 } 927 928 switch (nstate) { 929 case IEEE80211_S_INIT: 930 if (ostate == IEEE80211_S_RUN) { 931 /* abort TSF synchronization */ 932 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 933 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 934 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 935 RT2860_TBTT_TIMER_EN)); 936 } 937 rt2860_set_gp_timer(sc, 0); 938 break; 939 940 case IEEE80211_S_SCAN: 941 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 942 if (ostate != IEEE80211_S_SCAN) 943 rt2860_set_gp_timer(sc, 150); 944 break; 945 946 case IEEE80211_S_AUTH: 947 case IEEE80211_S_ASSOC: 948 rt2860_set_gp_timer(sc, 0); 949 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 950 break; 951 952 case IEEE80211_S_RUN: 953 rt2860_set_gp_timer(sc, 0); 954 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 955 956 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 957 rt2860_updateslot(ic); 958 rt2860_enable_mrr(sc); 959 rt2860_set_txpreamble(sc); 960 rt2860_set_basicrates(sc); 961 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 962 } 963 964 #ifndef IEEE80211_STA_ONLY 965 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 966 ic->ic_opmode == IEEE80211_M_IBSS) 967 (void)rt2860_setup_beacon(sc); 968 #endif 969 970 if (ic->ic_opmode == IEEE80211_M_STA) { 971 /* fake a join to init the tx rate */ 972 rt2860_newassoc(ic, ic->ic_bss, 1); 973 } 974 975 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 976 rt2860_enable_tsf_sync(sc); 977 rt2860_set_gp_timer(sc, 500); 978 } 979 980 /* turn link LED on */ 981 rt2860_set_leds(sc, RT2860_LED_RADIO | 982 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 983 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 984 break; 985 } 986 987 return sc->sc_newstate(ic, nstate, arg); 988 } 989 990 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 991 uint16_t 992 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 993 { 994 uint32_t tmp; 995 uint16_t reg; 996 int ntries; 997 998 addr *= 2; 999 /*- 1000 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1001 * DATA0: F E D C 1002 * DATA1: B A 9 8 1003 * DATA2: 7 6 5 4 1004 * DATA3: 3 2 1 0 1005 */ 1006 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1007 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1008 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1009 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1010 for (ntries = 0; ntries < 500; ntries++) { 1011 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1012 if (!(tmp & RT3070_EFSROM_KICK)) 1013 break; 1014 DELAY(2); 1015 } 1016 if (ntries == 500) 1017 return 0xffff; 1018 1019 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1020 return 0xffff; /* address not found */ 1021 1022 /* determine to which 32-bit register our 16-bit word belongs */ 1023 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1024 tmp = RAL_READ(sc, reg); 1025 1026 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1027 } 1028 1029 /* 1030 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1031 * 93C66 or 93C86). 1032 */ 1033 uint16_t 1034 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1035 { 1036 uint32_t tmp; 1037 uint16_t val; 1038 int n; 1039 1040 /* clock C once before the first command */ 1041 RT2860_EEPROM_CTL(sc, 0); 1042 1043 RT2860_EEPROM_CTL(sc, RT2860_S); 1044 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1045 RT2860_EEPROM_CTL(sc, RT2860_S); 1046 1047 /* write start bit (1) */ 1048 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1049 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1050 1051 /* write READ opcode (10) */ 1052 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1053 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1054 RT2860_EEPROM_CTL(sc, RT2860_S); 1055 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1056 1057 /* write address (A5-A0 or A7-A0) */ 1058 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1059 for (; n >= 0; n--) { 1060 RT2860_EEPROM_CTL(sc, RT2860_S | 1061 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1062 RT2860_EEPROM_CTL(sc, RT2860_S | 1063 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1064 } 1065 1066 RT2860_EEPROM_CTL(sc, RT2860_S); 1067 1068 /* read data Q15-Q0 */ 1069 val = 0; 1070 for (n = 15; n >= 0; n--) { 1071 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1072 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1073 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1074 RT2860_EEPROM_CTL(sc, RT2860_S); 1075 } 1076 1077 RT2860_EEPROM_CTL(sc, 0); 1078 1079 /* clear Chip Select and clock C */ 1080 RT2860_EEPROM_CTL(sc, RT2860_S); 1081 RT2860_EEPROM_CTL(sc, 0); 1082 RT2860_EEPROM_CTL(sc, RT2860_C); 1083 1084 return val; 1085 } 1086 1087 static __inline uint16_t 1088 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1089 { 1090 /* either eFUSE ROM or EEPROM */ 1091 return sc->sc_srom_read(sc, addr); 1092 } 1093 1094 void 1095 rt2860_intr_coherent(struct rt2860_softc *sc) 1096 { 1097 uint32_t tmp; 1098 1099 /* DMA finds data coherent event when checking the DDONE bit */ 1100 1101 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1102 1103 /* restart DMA engine */ 1104 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1105 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1106 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1107 1108 (void)rt2860_txrx_enable(sc); 1109 } 1110 1111 void 1112 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1113 { 1114 struct ifnet *ifp = &sc->sc_ic.ic_if; 1115 struct ieee80211_amrr_node *amn; 1116 uint32_t stat; 1117 uint8_t wcid, mcs, pid; 1118 1119 /* drain Tx status FIFO (maxsize = 16) */ 1120 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1121 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1122 1123 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1124 1125 /* if no ACK was requested, no feedback is available */ 1126 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1127 continue; 1128 1129 /* update per-STA AMRR stats */ 1130 amn = &sc->amn[wcid]; 1131 amn->amn_txcnt++; 1132 if (stat & RT2860_TXQ_OK) { 1133 /* 1134 * Check if there were retries, ie if the Tx success 1135 * rate is different from the requested rate. Note 1136 * that it works only because we do not allow rate 1137 * fallback from OFDM to CCK. 1138 */ 1139 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1140 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1141 if (mcs + 1 != pid) 1142 amn->amn_retrycnt++; 1143 } else { 1144 amn->amn_retrycnt++; 1145 ifp->if_oerrors++; 1146 } 1147 } 1148 } 1149 1150 void 1151 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1152 { 1153 struct ieee80211com *ic = &sc->sc_ic; 1154 struct ifnet *ifp = &ic->ic_if; 1155 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1156 uint32_t hw; 1157 1158 rt2860_drain_stats_fifo(sc); 1159 1160 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1161 while (ring->next != hw) { 1162 struct rt2860_tx_data *data = ring->data[ring->next]; 1163 1164 if (data != NULL) { 1165 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1166 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1167 bus_dmamap_unload(sc->sc_dmat, data->map); 1168 m_freem(data->m); 1169 data->m= NULL; 1170 ieee80211_release_node(ic, data->ni); 1171 data->ni = NULL; 1172 1173 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1174 ring->data[ring->next] = NULL; 1175 1176 ifp->if_opackets++; 1177 } 1178 ring->queued--; 1179 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1180 } 1181 1182 sc->sc_tx_timer = 0; 1183 if (ring->queued <= RT2860_TX_RING_ONEMORE) 1184 sc->qfullmsk &= ~(1 << qid); 1185 ifq_clr_oactive(&ifp->if_snd); 1186 rt2860_start(ifp); 1187 } 1188 1189 /* 1190 * Return the Rx chain with the highest RSSI for a given frame. 1191 */ 1192 static __inline uint8_t 1193 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1194 { 1195 uint8_t rxchain = 0; 1196 1197 if (sc->nrxchains > 1) { 1198 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1199 rxchain = 1; 1200 if (sc->nrxchains > 2) 1201 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1202 rxchain = 2; 1203 } 1204 return rxchain; 1205 } 1206 1207 void 1208 rt2860_rx_intr(struct rt2860_softc *sc) 1209 { 1210 struct ieee80211com *ic = &sc->sc_ic; 1211 struct ifnet *ifp = &ic->ic_if; 1212 struct ieee80211_frame *wh; 1213 struct ieee80211_rxinfo rxi; 1214 struct ieee80211_node *ni; 1215 struct mbuf *m, *m1; 1216 uint32_t hw; 1217 uint8_t ant, rssi; 1218 int error; 1219 #if NBPFILTER > 0 1220 struct rt2860_rx_radiotap_header *tap; 1221 struct mbuf mb; 1222 uint16_t phy; 1223 #endif 1224 1225 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1226 while (sc->rxq.cur != hw) { 1227 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1228 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1229 struct rt2860_rxwi *rxwi; 1230 1231 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1232 sc->rxq.cur * sizeof (struct rt2860_rxd), 1233 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1234 1235 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1236 DPRINTF(("RXD DDONE bit not set!\n")); 1237 break; /* should not happen */ 1238 } 1239 1240 if (__predict_false(rxd->flags & 1241 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1242 ifp->if_ierrors++; 1243 goto skip; 1244 } 1245 1246 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1247 /* report MIC failures to net80211 for TKIP */ 1248 ic->ic_stats.is_rx_locmicfail++; 1249 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1250 ifp->if_ierrors++; 1251 goto skip; 1252 } 1253 1254 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1255 if (__predict_false(m1 == NULL)) { 1256 ifp->if_ierrors++; 1257 goto skip; 1258 } 1259 1260 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1261 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1262 bus_dmamap_unload(sc->sc_dmat, data->map); 1263 1264 error = bus_dmamap_load(sc->sc_dmat, data->map, 1265 mtod(m1, void *), MCLBYTES, NULL, 1266 BUS_DMA_READ | BUS_DMA_NOWAIT); 1267 if (__predict_false(error != 0)) { 1268 m_freem(m1); 1269 1270 /* try to reload the old mbuf */ 1271 error = bus_dmamap_load(sc->sc_dmat, data->map, 1272 mtod(data->m, void *), MCLBYTES, NULL, 1273 BUS_DMA_READ | BUS_DMA_NOWAIT); 1274 if (__predict_false(error != 0)) { 1275 panic("%s: could not load old rx mbuf", 1276 sc->sc_dev.dv_xname); 1277 } 1278 /* physical address may have changed */ 1279 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1280 ifp->if_ierrors++; 1281 goto skip; 1282 } 1283 1284 /* 1285 * New mbuf successfully loaded, update Rx ring and continue 1286 * processing. 1287 */ 1288 m = data->m; 1289 data->m = m1; 1290 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1291 1292 rxwi = mtod(m, struct rt2860_rxwi *); 1293 1294 /* finalize mbuf */ 1295 m->m_data = (caddr_t)(rxwi + 1); 1296 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff; 1297 1298 wh = mtod(m, struct ieee80211_frame *); 1299 rxi.rxi_flags = 0; 1300 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1301 /* frame is decrypted by hardware */ 1302 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1303 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1304 } 1305 1306 /* HW may insert 2 padding bytes after 802.11 header */ 1307 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1308 u_int hdrlen = ieee80211_get_hdrlen(wh); 1309 memmove((caddr_t)wh + 2, wh, hdrlen); 1310 m->m_data += 2; 1311 wh = mtod(m, struct ieee80211_frame *); 1312 } 1313 1314 ant = rt2860_maxrssi_chain(sc, rxwi); 1315 rssi = rxwi->rssi[ant]; 1316 1317 #if NBPFILTER > 0 1318 if (__predict_true(sc->sc_drvbpf == NULL)) 1319 goto skipbpf; 1320 1321 tap = &sc->sc_rxtap; 1322 tap->wr_flags = 0; 1323 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1324 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1325 tap->wr_antsignal = rssi; 1326 tap->wr_antenna = ant; 1327 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1328 tap->wr_rate = 2; /* in case it can't be found below */ 1329 phy = letoh16(rxwi->phy); 1330 switch (phy & RT2860_PHY_MODE) { 1331 case RT2860_PHY_CCK: 1332 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1333 case 0: tap->wr_rate = 2; break; 1334 case 1: tap->wr_rate = 4; break; 1335 case 2: tap->wr_rate = 11; break; 1336 case 3: tap->wr_rate = 22; break; 1337 } 1338 if (phy & RT2860_PHY_SHPRE) 1339 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1340 break; 1341 case RT2860_PHY_OFDM: 1342 switch (phy & RT2860_PHY_MCS) { 1343 case 0: tap->wr_rate = 12; break; 1344 case 1: tap->wr_rate = 18; break; 1345 case 2: tap->wr_rate = 24; break; 1346 case 3: tap->wr_rate = 36; break; 1347 case 4: tap->wr_rate = 48; break; 1348 case 5: tap->wr_rate = 72; break; 1349 case 6: tap->wr_rate = 96; break; 1350 case 7: tap->wr_rate = 108; break; 1351 } 1352 break; 1353 } 1354 mb.m_data = (caddr_t)tap; 1355 mb.m_len = sc->sc_rxtap_len; 1356 mb.m_next = m; 1357 mb.m_nextpkt = NULL; 1358 mb.m_type = 0; 1359 mb.m_flags = 0; 1360 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1361 skipbpf: 1362 #endif 1363 /* grab a reference to the source node */ 1364 ni = ieee80211_find_rxnode(ic, wh); 1365 1366 /* send the frame to the 802.11 layer */ 1367 rxi.rxi_rssi = rssi; 1368 rxi.rxi_tstamp = 0; /* unused */ 1369 ieee80211_input(ifp, m, ni, &rxi); 1370 1371 /* node is no longer needed */ 1372 ieee80211_release_node(ic, ni); 1373 1374 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1375 1376 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1377 sc->rxq.cur * sizeof (struct rt2860_rxd), 1378 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1379 1380 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1381 } 1382 1383 /* tell HW what we have processed */ 1384 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1385 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1386 } 1387 1388 void 1389 rt2860_tbtt_intr(struct rt2860_softc *sc) 1390 { 1391 struct ieee80211com *ic = &sc->sc_ic; 1392 1393 #ifndef IEEE80211_STA_ONLY 1394 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1395 /* one less beacon until next DTIM */ 1396 if (ic->ic_dtim_count == 0) 1397 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1398 else 1399 ic->ic_dtim_count--; 1400 1401 /* update dynamic parts of beacon */ 1402 rt2860_setup_beacon(sc); 1403 1404 /* flush buffered multicast frames */ 1405 if (ic->ic_dtim_count == 0) 1406 ieee80211_notify_dtim(ic); 1407 } 1408 #endif 1409 /* check if protection mode has changed */ 1410 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1411 rt2860_updateprot(ic); 1412 sc->sc_ic_flags = ic->ic_flags; 1413 } 1414 } 1415 1416 void 1417 rt2860_gp_intr(struct rt2860_softc *sc) 1418 { 1419 struct ieee80211com *ic = &sc->sc_ic; 1420 1421 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1422 1423 if (ic->ic_state == IEEE80211_S_SCAN) 1424 ieee80211_next_scan(&ic->ic_if); 1425 else if (ic->ic_state == IEEE80211_S_RUN) 1426 rt2860_updatestats(sc); 1427 } 1428 1429 int 1430 rt2860_intr(void *arg) 1431 { 1432 struct rt2860_softc *sc = arg; 1433 uint32_t r; 1434 1435 r = RAL_READ(sc, RT2860_INT_STATUS); 1436 if (__predict_false(r == 0xffffffff)) 1437 return 0; /* device likely went away */ 1438 if (r == 0) 1439 return 0; /* not for us */ 1440 1441 /* acknowledge interrupts */ 1442 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1443 1444 if (r & RT2860_TX_RX_COHERENT) 1445 rt2860_intr_coherent(sc); 1446 1447 if (r & RT2860_MAC_INT_2) /* TX status */ 1448 rt2860_drain_stats_fifo(sc); 1449 1450 if (r & RT2860_TX_DONE_INT5) 1451 rt2860_tx_intr(sc, 5); 1452 1453 if (r & RT2860_RX_DONE_INT) 1454 rt2860_rx_intr(sc); 1455 1456 if (r & RT2860_TX_DONE_INT4) 1457 rt2860_tx_intr(sc, 4); 1458 1459 if (r & RT2860_TX_DONE_INT3) 1460 rt2860_tx_intr(sc, 3); 1461 1462 if (r & RT2860_TX_DONE_INT2) 1463 rt2860_tx_intr(sc, 2); 1464 1465 if (r & RT2860_TX_DONE_INT1) 1466 rt2860_tx_intr(sc, 1); 1467 1468 if (r & RT2860_TX_DONE_INT0) 1469 rt2860_tx_intr(sc, 0); 1470 1471 if (r & RT2860_MAC_INT_0) /* TBTT */ 1472 rt2860_tbtt_intr(sc); 1473 1474 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1475 /* TBD wakeup */; 1476 1477 if (r & RT2860_MAC_INT_4) /* GP timer */ 1478 rt2860_gp_intr(sc); 1479 1480 return 1; 1481 } 1482 1483 int 1484 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1485 { 1486 struct ieee80211com *ic = &sc->sc_ic; 1487 struct rt2860_node *rn = (void *)ni; 1488 struct rt2860_tx_ring *ring; 1489 struct rt2860_tx_data *data; 1490 struct rt2860_txd *txd; 1491 struct rt2860_txwi *txwi; 1492 struct ieee80211_frame *wh; 1493 bus_dma_segment_t *seg; 1494 u_int hdrlen; 1495 uint16_t qos, dur; 1496 uint8_t type, qsel, mcs, pid, tid, qid; 1497 int nsegs, hasqos, ridx, ctl_ridx; 1498 1499 /* the data pool contains at least one element, pick the first */ 1500 data = SLIST_FIRST(&sc->data_pool); 1501 1502 wh = mtod(m, struct ieee80211_frame *); 1503 hdrlen = ieee80211_get_hdrlen(wh); 1504 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1505 1506 if ((hasqos = ieee80211_has_qos(wh))) { 1507 qos = ieee80211_get_qos(wh); 1508 tid = qos & IEEE80211_QOS_TID; 1509 qid = ieee80211_up_to_ac(ic, tid); 1510 } else { 1511 qos = 0; 1512 tid = 0; 1513 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1514 sc->mgtqid : EDCA_AC_BE; 1515 } 1516 ring = &sc->txq[qid]; 1517 1518 /* pickup a rate index */ 1519 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1520 type != IEEE80211_FC0_TYPE_DATA) { 1521 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1522 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1523 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1524 } else if (ic->ic_fixed_rate != -1) { 1525 ridx = sc->fixed_ridx; 1526 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1527 } else { 1528 ridx = rn->ridx[ni->ni_txrate]; 1529 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1530 } 1531 1532 /* get MCS code from rate index */ 1533 mcs = rt2860_rates[ridx].mcs; 1534 1535 /* setup TX Wireless Information */ 1536 txwi = data->txwi; 1537 txwi->flags = 0; 1538 /* let HW generate seq numbers for non-QoS frames */ 1539 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1540 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1541 txwi->len = htole16(m->m_pkthdr.len); 1542 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1543 txwi->phy = htole16(RT2860_PHY_CCK); 1544 if (ridx != RT2860_RIDX_CCK1 && 1545 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1546 mcs |= RT2860_PHY_SHPRE; 1547 } else 1548 txwi->phy = htole16(RT2860_PHY_OFDM); 1549 txwi->phy |= htole16(mcs); 1550 1551 /* 1552 * We store the MCS code into the driver-private PacketID field. 1553 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1554 * that we know at which initial rate the frame was transmitted. 1555 * We add 1 to the MCS code because setting the PacketID field to 1556 * 0 means that we don't want feedback in TX_STAT_FIFO. 1557 */ 1558 pid = (mcs + 1) & 0xf; 1559 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1560 1561 /* check if RTS/CTS or CTS-to-self protection is required */ 1562 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1563 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1564 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1565 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1566 txwi->txop = RT2860_TX_TXOP_HT; 1567 else 1568 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1569 1570 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1571 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 1572 IEEE80211_QOS_ACK_POLICY_NOACK)) { 1573 txwi->xflags |= RT2860_TX_ACK; 1574 1575 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1576 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1577 else 1578 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1579 *(uint16_t *)wh->i_dur = htole16(dur); 1580 } 1581 #ifndef IEEE80211_STA_ONLY 1582 /* ask MAC to insert timestamp into probe responses */ 1583 if ((wh->i_fc[0] & 1584 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1585 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1586 /* NOTE: beacons do not pass through tx_data() */ 1587 txwi->flags |= RT2860_TX_TS; 1588 #endif 1589 1590 #if NBPFILTER > 0 1591 if (__predict_false(sc->sc_drvbpf != NULL)) { 1592 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1593 struct mbuf mb; 1594 1595 tap->wt_flags = 0; 1596 tap->wt_rate = rt2860_rates[ridx].rate; 1597 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1598 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1599 tap->wt_hwqueue = qid; 1600 if (mcs & RT2860_PHY_SHPRE) 1601 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1602 1603 mb.m_data = (caddr_t)tap; 1604 mb.m_len = sc->sc_txtap_len; 1605 mb.m_next = m; 1606 mb.m_nextpkt = NULL; 1607 mb.m_type = 0; 1608 mb.m_flags = 0; 1609 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1610 } 1611 #endif 1612 1613 /* copy and trim 802.11 header */ 1614 memcpy(txwi + 1, wh, hdrlen); 1615 m_adj(m, hdrlen); 1616 1617 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */ 1618 1619 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) { 1620 if (m_defrag(m, M_DONTWAIT)) 1621 return (ENOBUFS); 1622 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1623 data->map, m, BUS_DMA_NOWAIT)) 1624 return (EFBIG); 1625 } 1626 1627 /* The map will fit into the tx ring: (a "full" ring may have a few 1628 * unused descriptors, at most (txds(MAX_SCATTER) - 1)) 1629 * 1630 * ring->queued + txds(data->map->nsegs) 1631 * <= { <0> data->map->nsegs <= MAX_SCATTER } 1632 * ring->queued + txds(MAX_SCATTER) 1633 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) } 1634 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER) 1635 * <= { arithmetic } 1636 * TX_RING_MAX 1637 */ 1638 1639 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1640 1641 /* first segment is TXWI + 802.11 header */ 1642 txd = &ring->txd[ring->cur]; 1643 txd->sdp0 = htole32(data->paddr); 1644 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1645 txd->flags = qsel; 1646 1647 /* setup payload segments */ 1648 seg = data->map->dm_segs; 1649 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1650 txd->sdp1 = htole32(seg->ds_addr); 1651 txd->sdl1 = htole16(seg->ds_len); 1652 seg++; 1653 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1654 /* grab a new Tx descriptor */ 1655 txd = &ring->txd[ring->cur]; 1656 txd->sdp0 = htole32(seg->ds_addr); 1657 txd->sdl0 = htole16(seg->ds_len); 1658 txd->flags = qsel; 1659 seg++; 1660 } 1661 /* finalize last segment */ 1662 if (nsegs > 0) { 1663 txd->sdp1 = htole32(seg->ds_addr); 1664 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1665 } else { 1666 txd->sdl0 |= htole16(RT2860_TX_LS0); 1667 txd->sdl1 = 0; 1668 } 1669 1670 /* remove from the free pool and link it into the SW Tx slot */ 1671 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1672 data->m = m; 1673 data->ni = ni; 1674 ring->data[ring->cur] = data; 1675 1676 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1677 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1678 BUS_DMASYNC_PREWRITE); 1679 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1680 BUS_DMASYNC_PREWRITE); 1681 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1682 BUS_DMASYNC_PREWRITE); 1683 1684 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1685 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1686 1687 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1688 ring->queued += 1 + (data->map->dm_nsegs / 2); 1689 if (ring->queued > RT2860_TX_RING_ONEMORE) 1690 sc->qfullmsk |= 1 << qid; 1691 1692 /* kick Tx */ 1693 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1694 1695 return 0; 1696 } 1697 1698 void 1699 rt2860_start(struct ifnet *ifp) 1700 { 1701 struct rt2860_softc *sc = ifp->if_softc; 1702 struct ieee80211com *ic = &sc->sc_ic; 1703 struct ieee80211_node *ni; 1704 struct mbuf *m; 1705 1706 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1707 return; 1708 1709 for (;;) { 1710 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1711 ifq_set_oactive(&ifp->if_snd); 1712 break; 1713 } 1714 /* send pending management frames first */ 1715 m = mq_dequeue(&ic->ic_mgtq); 1716 if (m != NULL) { 1717 ni = m->m_pkthdr.ph_cookie; 1718 goto sendit; 1719 } 1720 if (ic->ic_state != IEEE80211_S_RUN) 1721 break; 1722 1723 /* send buffered frames for power-save mode */ 1724 m = mq_dequeue(&ic->ic_pwrsaveq); 1725 if (m != NULL) { 1726 ni = m->m_pkthdr.ph_cookie; 1727 goto sendit; 1728 } 1729 1730 /* encapsulate and send data frames */ 1731 IFQ_DEQUEUE(&ifp->if_snd, m); 1732 if (m == NULL) 1733 break; 1734 #if NBPFILTER > 0 1735 if (ifp->if_bpf != NULL) 1736 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1737 #endif 1738 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1739 continue; 1740 sendit: 1741 #if NBPFILTER > 0 1742 if (ic->ic_rawbpf != NULL) 1743 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1744 #endif 1745 if (rt2860_tx(sc, m, ni) != 0) { 1746 m_freem(m); 1747 ieee80211_release_node(ic, ni); 1748 ifp->if_oerrors++; 1749 continue; 1750 } 1751 1752 sc->sc_tx_timer = 5; 1753 ifp->if_timer = 1; 1754 } 1755 } 1756 1757 void 1758 rt2860_watchdog(struct ifnet *ifp) 1759 { 1760 struct rt2860_softc *sc = ifp->if_softc; 1761 1762 ifp->if_timer = 0; 1763 1764 if (sc->sc_tx_timer > 0) { 1765 if (--sc->sc_tx_timer == 0) { 1766 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1767 rt2860_stop(ifp, 0); 1768 rt2860_init(ifp); 1769 ifp->if_oerrors++; 1770 return; 1771 } 1772 ifp->if_timer = 1; 1773 } 1774 1775 ieee80211_watchdog(ifp); 1776 } 1777 1778 int 1779 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1780 { 1781 struct rt2860_softc *sc = ifp->if_softc; 1782 struct ieee80211com *ic = &sc->sc_ic; 1783 struct ifreq *ifr; 1784 int s, error = 0; 1785 1786 s = splnet(); 1787 1788 switch (cmd) { 1789 case SIOCSIFADDR: 1790 ifp->if_flags |= IFF_UP; 1791 /* FALLTHROUGH */ 1792 case SIOCSIFFLAGS: 1793 if (ifp->if_flags & IFF_UP) { 1794 if (!(ifp->if_flags & IFF_RUNNING)) 1795 rt2860_init(ifp); 1796 } else { 1797 if (ifp->if_flags & IFF_RUNNING) 1798 rt2860_stop(ifp, 1); 1799 } 1800 break; 1801 1802 case SIOCADDMULTI: 1803 case SIOCDELMULTI: 1804 ifr = (struct ifreq *)data; 1805 error = (cmd == SIOCADDMULTI) ? 1806 ether_addmulti(ifr, &ic->ic_ac) : 1807 ether_delmulti(ifr, &ic->ic_ac); 1808 1809 if (error == ENETRESET) 1810 error = 0; 1811 break; 1812 1813 case SIOCS80211CHANNEL: 1814 /* 1815 * This allows for fast channel switching in monitor mode 1816 * (used by kismet). In IBSS mode, we must explicitly reset 1817 * the interface to generate a new beacon frame. 1818 */ 1819 error = ieee80211_ioctl(ifp, cmd, data); 1820 if (error == ENETRESET && 1821 ic->ic_opmode == IEEE80211_M_MONITOR) { 1822 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1823 (IFF_UP | IFF_RUNNING)) 1824 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1825 error = 0; 1826 } 1827 break; 1828 1829 default: 1830 error = ieee80211_ioctl(ifp, cmd, data); 1831 } 1832 1833 if (error == ENETRESET) { 1834 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1835 (IFF_UP | IFF_RUNNING)) { 1836 rt2860_stop(ifp, 0); 1837 rt2860_init(ifp); 1838 } 1839 error = 0; 1840 } 1841 1842 splx(s); 1843 1844 return error; 1845 } 1846 1847 /* 1848 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1849 * We access the BBP through the 8051 microcontroller unit which means that 1850 * the microcode must be loaded first. 1851 */ 1852 void 1853 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1854 { 1855 int ntries; 1856 1857 for (ntries = 0; ntries < 100; ntries++) { 1858 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1859 break; 1860 DELAY(1); 1861 } 1862 if (ntries == 100) { 1863 printf("%s: could not write to BBP through MCU\n", 1864 sc->sc_dev.dv_xname); 1865 return; 1866 } 1867 1868 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1869 RT2860_BBP_CSR_KICK | reg << 8 | val); 1870 RAL_BARRIER_WRITE(sc); 1871 1872 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1873 DELAY(1000); 1874 } 1875 1876 uint8_t 1877 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1878 { 1879 uint32_t val; 1880 int ntries; 1881 1882 for (ntries = 0; ntries < 100; ntries++) { 1883 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1884 break; 1885 DELAY(1); 1886 } 1887 if (ntries == 100) { 1888 printf("%s: could not read from BBP through MCU\n", 1889 sc->sc_dev.dv_xname); 1890 return 0; 1891 } 1892 1893 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1894 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1895 RAL_BARRIER_WRITE(sc); 1896 1897 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1898 DELAY(1000); 1899 1900 for (ntries = 0; ntries < 100; ntries++) { 1901 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1902 if (!(val & RT2860_BBP_CSR_KICK)) 1903 return val & 0xff; 1904 DELAY(1); 1905 } 1906 printf("%s: could not read from BBP through MCU\n", 1907 sc->sc_dev.dv_xname); 1908 1909 return 0; 1910 } 1911 1912 /* 1913 * Write to one of the 4 programmable 24-bit RF registers. 1914 */ 1915 void 1916 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 1917 { 1918 uint32_t tmp; 1919 int ntries; 1920 1921 for (ntries = 0; ntries < 100; ntries++) { 1922 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 1923 break; 1924 DELAY(1); 1925 } 1926 if (ntries == 100) { 1927 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1928 return; 1929 } 1930 1931 /* RF registers are 24-bit on the RT2860 */ 1932 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1933 (val & 0x3fffff) << 2 | (reg & 3); 1934 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 1935 } 1936 1937 uint8_t 1938 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 1939 { 1940 uint32_t tmp; 1941 int ntries; 1942 1943 for (ntries = 0; ntries < 100; ntries++) { 1944 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 1945 break; 1946 DELAY(1); 1947 } 1948 if (ntries == 100) { 1949 printf("%s: could not read RF register\n", 1950 sc->sc_dev.dv_xname); 1951 return 0xff; 1952 } 1953 tmp = RT3070_RF_KICK | reg << 8; 1954 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 1955 1956 for (ntries = 0; ntries < 100; ntries++) { 1957 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 1958 if (!(tmp & RT3070_RF_KICK)) 1959 break; 1960 DELAY(1); 1961 } 1962 if (ntries == 100) { 1963 printf("%s: could not read RF register\n", 1964 sc->sc_dev.dv_xname); 1965 return 0xff; 1966 } 1967 return tmp & 0xff; 1968 } 1969 1970 void 1971 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1972 { 1973 uint32_t tmp; 1974 int ntries; 1975 1976 for (ntries = 0; ntries < 10; ntries++) { 1977 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 1978 break; 1979 DELAY(10); 1980 } 1981 if (ntries == 10) { 1982 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1983 return; 1984 } 1985 1986 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1987 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 1988 } 1989 1990 /* 1991 * Send a command to the 8051 microcontroller unit. 1992 */ 1993 int 1994 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 1995 { 1996 int slot, ntries; 1997 uint32_t tmp; 1998 uint8_t cid; 1999 2000 for (ntries = 0; ntries < 100; ntries++) { 2001 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2002 break; 2003 DELAY(2); 2004 } 2005 if (ntries == 100) 2006 return EIO; 2007 2008 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2009 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2010 RAL_BARRIER_WRITE(sc); 2011 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2012 2013 if (!wait) 2014 return 0; 2015 /* wait for the command to complete */ 2016 for (ntries = 0; ntries < 200; ntries++) { 2017 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2018 /* find the command slot */ 2019 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2020 if ((tmp & 0xff) == cid) 2021 break; 2022 if (slot < 4) 2023 break; 2024 DELAY(100); 2025 } 2026 if (ntries == 200) { 2027 /* clear command and status */ 2028 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2029 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2030 return ETIMEDOUT; 2031 } 2032 /* get command status (1 means success) */ 2033 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2034 tmp = (tmp >> (slot * 8)) & 0xff; 2035 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2036 cmd, slot, tmp)); 2037 /* clear command and status */ 2038 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2039 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2040 return (tmp == 1) ? 0 : EIO; 2041 } 2042 2043 void 2044 rt2860_enable_mrr(struct rt2860_softc *sc) 2045 { 2046 #define CCK(mcs) (mcs) 2047 #define OFDM(mcs) (1 << 3 | (mcs)) 2048 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2049 OFDM(6) << 28 | /* 54->48 */ 2050 OFDM(5) << 24 | /* 48->36 */ 2051 OFDM(4) << 20 | /* 36->24 */ 2052 OFDM(3) << 16 | /* 24->18 */ 2053 OFDM(2) << 12 | /* 18->12 */ 2054 OFDM(1) << 8 | /* 12-> 9 */ 2055 OFDM(0) << 4 | /* 9-> 6 */ 2056 OFDM(0)); /* 6-> 6 */ 2057 2058 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2059 CCK(2) << 12 | /* 11->5.5 */ 2060 CCK(1) << 8 | /* 5.5-> 2 */ 2061 CCK(0) << 4 | /* 2-> 1 */ 2062 CCK(0)); /* 1-> 1 */ 2063 #undef OFDM 2064 #undef CCK 2065 } 2066 2067 void 2068 rt2860_set_txpreamble(struct rt2860_softc *sc) 2069 { 2070 uint32_t tmp; 2071 2072 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2073 tmp &= ~RT2860_CCK_SHORT_EN; 2074 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2075 tmp |= RT2860_CCK_SHORT_EN; 2076 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2077 } 2078 2079 void 2080 rt2860_set_basicrates(struct rt2860_softc *sc) 2081 { 2082 struct ieee80211com *ic = &sc->sc_ic; 2083 2084 /* set basic rates mask */ 2085 if (ic->ic_curmode == IEEE80211_MODE_11B) 2086 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2087 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2088 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2089 else /* 11g */ 2090 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2091 } 2092 2093 void 2094 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2095 { 2096 uint32_t tmp; 2097 uint8_t agc; 2098 2099 /* Wait for BBP to settle */ 2100 DELAY(1000); 2101 2102 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2103 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2104 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2105 rt2860_mcu_bbp_write(sc, 86, 0x00); 2106 2107 if (group == 0) { 2108 if (sc->ext_2ghz_lna) { 2109 rt2860_mcu_bbp_write(sc, 82, 0x62); 2110 rt2860_mcu_bbp_write(sc, 75, 0x46); 2111 } else { 2112 rt2860_mcu_bbp_write(sc, 82, 0x84); 2113 rt2860_mcu_bbp_write(sc, 75, 0x50); 2114 } 2115 } else { 2116 if (sc->mac_ver == 0x3572) 2117 rt2860_mcu_bbp_write(sc, 82, 0x94); 2118 else 2119 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2120 2121 if (sc->ext_5ghz_lna) 2122 rt2860_mcu_bbp_write(sc, 75, 0x46); 2123 else 2124 rt2860_mcu_bbp_write(sc, 75, 0x50); 2125 } 2126 2127 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2128 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2129 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2130 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2131 2132 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2133 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2134 if (sc->nrxchains > 1) 2135 tmp |= RT2860_LNA_PE1_EN; 2136 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2137 tmp |= RT3593_LNA_PE2_EN; 2138 if (group == 0) { /* 2GHz */ 2139 tmp |= RT2860_PA_PE_G0_EN; 2140 if (sc->ntxchains > 1) 2141 tmp |= RT2860_PA_PE_G1_EN; 2142 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2143 tmp |= RT3593_PA_PE_G2_EN; 2144 } else { /* 5GHz */ 2145 tmp |= RT2860_PA_PE_A0_EN; 2146 if (sc->ntxchains > 1) 2147 tmp |= RT2860_PA_PE_A1_EN; 2148 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2149 tmp |= RT3593_PA_PE_A2_EN; 2150 } 2151 if (sc->mac_ver == 0x3572) { 2152 rt3090_rf_write(sc, 8, 0x00); 2153 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2154 rt3090_rf_write(sc, 8, 0x80); 2155 } else 2156 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2157 2158 if (sc->mac_ver == 0x3593) { 2159 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2160 if (sc->sc_flags & RT2860_PCIE) { 2161 tmp &= ~0x01010000; 2162 if (group == 0) 2163 tmp |= 0x00010000; 2164 } else { 2165 tmp &= ~0x00008080; 2166 if (group == 0) 2167 tmp |= 0x00000080; 2168 } 2169 tmp = (tmp & ~0x00001000) | 0x00000010; 2170 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2171 } 2172 2173 /* set initial AGC value */ 2174 if (group == 0) { /* 2GHz band */ 2175 if (sc->mac_ver >= 0x3071) 2176 agc = 0x1c + sc->lna[0] * 2; 2177 else 2178 agc = 0x2e + sc->lna[0]; 2179 } else { /* 5GHz band */ 2180 if (sc->mac_ver == 0x3572) 2181 agc = 0x22 + (sc->lna[group] * 5) / 3; 2182 else 2183 agc = 0x32 + (sc->lna[group] * 5) / 3; 2184 } 2185 rt2860_mcu_bbp_write(sc, 66, agc); 2186 2187 DELAY(1000); 2188 } 2189 2190 void 2191 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2192 { 2193 const struct rfprog *rfprog = rt2860_rf2850; 2194 uint32_t r2, r3, r4; 2195 int8_t txpow1, txpow2; 2196 u_int i; 2197 2198 /* find the settings for this channel (we know it exists) */ 2199 for (i = 0; rfprog[i].chan != chan; i++); 2200 2201 r2 = rfprog[i].r2; 2202 if (sc->ntxchains == 1) 2203 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2204 if (sc->nrxchains == 1) 2205 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2206 else if (sc->nrxchains == 2) 2207 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2208 2209 /* use Tx power values from EEPROM */ 2210 txpow1 = sc->txpow1[i]; 2211 txpow2 = sc->txpow2[i]; 2212 if (chan > 14) { 2213 if (txpow1 >= 0) 2214 txpow1 = txpow1 << 1 | 1; 2215 else 2216 txpow1 = (7 + txpow1) << 1; 2217 if (txpow2 >= 0) 2218 txpow2 = txpow2 << 1 | 1; 2219 else 2220 txpow2 = (7 + txpow2) << 1; 2221 } 2222 r3 = rfprog[i].r3 | txpow1 << 7; 2223 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2224 2225 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2226 rt2860_rf_write(sc, RT2860_RF2, r2); 2227 rt2860_rf_write(sc, RT2860_RF3, r3); 2228 rt2860_rf_write(sc, RT2860_RF4, r4); 2229 2230 DELAY(200); 2231 2232 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2233 rt2860_rf_write(sc, RT2860_RF2, r2); 2234 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2235 rt2860_rf_write(sc, RT2860_RF4, r4); 2236 2237 DELAY(200); 2238 2239 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2240 rt2860_rf_write(sc, RT2860_RF2, r2); 2241 rt2860_rf_write(sc, RT2860_RF3, r3); 2242 rt2860_rf_write(sc, RT2860_RF4, r4); 2243 } 2244 2245 void 2246 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2247 { 2248 int8_t txpow1, txpow2; 2249 uint8_t rf; 2250 int i; 2251 2252 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2253 2254 /* find the settings for this channel (we know it exists) */ 2255 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2256 2257 /* use Tx power values from EEPROM */ 2258 txpow1 = sc->txpow1[i]; 2259 txpow2 = sc->txpow2[i]; 2260 2261 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2262 rf = rt3090_rf_read(sc, 3); 2263 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2264 rt3090_rf_write(sc, 3, rf); 2265 rf = rt3090_rf_read(sc, 6); 2266 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2267 rt3090_rf_write(sc, 6, rf); 2268 2269 /* set Tx0 power */ 2270 rf = rt3090_rf_read(sc, 12); 2271 rf = (rf & ~0x1f) | txpow1; 2272 rt3090_rf_write(sc, 12, rf); 2273 2274 /* set Tx1 power */ 2275 rf = rt3090_rf_read(sc, 13); 2276 rf = (rf & ~0x1f) | txpow2; 2277 rt3090_rf_write(sc, 13, rf); 2278 2279 rf = rt3090_rf_read(sc, 1); 2280 rf &= ~0xfc; 2281 if (sc->ntxchains == 1) 2282 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2283 else if (sc->ntxchains == 2) 2284 rf |= RT3070_TX2_PD; 2285 if (sc->nrxchains == 1) 2286 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2287 else if (sc->nrxchains == 2) 2288 rf |= RT3070_RX2_PD; 2289 rt3090_rf_write(sc, 1, rf); 2290 2291 /* set RF offset */ 2292 rf = rt3090_rf_read(sc, 23); 2293 rf = (rf & ~0x7f) | sc->freq; 2294 rt3090_rf_write(sc, 23, rf); 2295 2296 /* program RF filter */ 2297 rf = rt3090_rf_read(sc, 24); /* Tx */ 2298 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2299 rt3090_rf_write(sc, 24, rf); 2300 rf = rt3090_rf_read(sc, 31); /* Rx */ 2301 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2302 rt3090_rf_write(sc, 31, rf); 2303 2304 /* enable RF tuning */ 2305 rf = rt3090_rf_read(sc, 7); 2306 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2307 } 2308 2309 void 2310 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2311 { 2312 uint8_t h20mhz, rf, tmp; 2313 int8_t txpow1, txpow2; 2314 int i; 2315 2316 /* RT5390 is 2GHz only */ 2317 KASSERT(chan >= 1 && chan <= 14); 2318 2319 /* find the settings for this channel (we know it exists) */ 2320 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2321 2322 /* use Tx power values from EEPROM */ 2323 txpow1 = sc->txpow1[i]; 2324 txpow2 = sc->txpow2[i]; 2325 2326 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2327 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2328 rf = rt3090_rf_read(sc, 11); 2329 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2330 rt3090_rf_write(sc, 11, rf); 2331 2332 rf = rt3090_rf_read(sc, 49); 2333 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2334 /* the valid range of the RF R49 is 0x00~0x27 */ 2335 if ((rf & 0x3f) > 0x27) 2336 rf = (rf & ~0x3f) | 0x27; 2337 rt3090_rf_write(sc, 49, rf); 2338 if (sc->mac_ver == 0x5392) { 2339 rf = rt3090_rf_read(sc, 50); 2340 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2341 /* the valid range of the RF R50 is 0x00~0x27 */ 2342 if ((rf & 0x3f) > 0x27) 2343 rf = (rf & ~0x3f) | 0x27; 2344 rt3090_rf_write(sc, 50, rf); 2345 } 2346 2347 rf = rt3090_rf_read(sc, 1); 2348 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2349 if (sc->mac_ver == 0x5392) 2350 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2351 rt3090_rf_write(sc, 1, rf); 2352 2353 rf = rt3090_rf_read(sc, 2); 2354 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2355 DELAY(1000); 2356 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2357 2358 rf = rt3090_rf_read(sc, 17); 2359 tmp = rf; 2360 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2361 rf = MIN(rf, 0x5f); 2362 if (tmp != rf) 2363 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2364 2365 if (sc->mac_ver == 0x5390) { 2366 if (chan <= 4) 2367 rf = 0x73; 2368 else if (chan >= 5 && chan <= 6) 2369 rf = 0x63; 2370 else if (chan >= 7 && chan <= 10) 2371 rf = 0x53; 2372 else 2373 rf = 43; 2374 rt3090_rf_write(sc, 55, rf); 2375 2376 if (chan == 1) 2377 rf = 0x0c; 2378 else if (chan == 2) 2379 rf = 0x0b; 2380 else if (chan == 3) 2381 rf = 0x0a; 2382 else if (chan >= 4 && chan <= 6) 2383 rf = 0x09; 2384 else if (chan >= 7 && chan <= 12) 2385 rf = 0x08; 2386 else if (chan == 13) 2387 rf = 0x07; 2388 else 2389 rf = 0x06; 2390 rt3090_rf_write(sc, 59, rf); 2391 } 2392 2393 /* Tx/Rx h20M */ 2394 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2395 rf = rt3090_rf_read(sc, 30); 2396 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2397 rt3090_rf_write(sc, 30, rf); 2398 2399 /* Rx BB filter VCM */ 2400 rf = rt3090_rf_read(sc, 30); 2401 rf = (rf & ~0x18) | 0x10; 2402 rt3090_rf_write(sc, 30, rf); 2403 2404 /* Initiate VCO calibration. */ 2405 rf = rt3090_rf_read(sc, 3); 2406 rf |= RT3593_VCOCAL; 2407 rt3090_rf_write(sc, 3, rf); 2408 } 2409 2410 int 2411 rt3090_rf_init(struct rt2860_softc *sc) 2412 { 2413 uint32_t tmp; 2414 uint8_t rf, bbp; 2415 int i; 2416 2417 rf = rt3090_rf_read(sc, 30); 2418 /* toggle RF R30 bit 7 */ 2419 rt3090_rf_write(sc, 30, rf | 0x80); 2420 DELAY(1000); 2421 rt3090_rf_write(sc, 30, rf & ~0x80); 2422 2423 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2424 tmp &= ~0x1f000000; 2425 if (sc->patch_dac && sc->mac_rev < 0x0211) 2426 tmp |= 0x0d000000; /* 1.35V */ 2427 else 2428 tmp |= 0x01000000; /* 1.2V */ 2429 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2430 2431 /* patch LNA_PE_G1 */ 2432 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2433 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2434 2435 /* initialize RF registers to default value */ 2436 if (sc->mac_ver == 0x3572) { 2437 for (i = 0; i < nitems(rt3572_def_rf); i++) { 2438 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2439 rt3572_def_rf[i].val); 2440 } 2441 } else { 2442 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2443 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2444 rt3090_def_rf[i].val); 2445 } 2446 } 2447 2448 /* select 20MHz bandwidth */ 2449 rt3090_rf_write(sc, 31, 0x14); 2450 2451 rf = rt3090_rf_read(sc, 6); 2452 rt3090_rf_write(sc, 6, rf | 0x40); 2453 2454 if (sc->mac_ver != 0x3593) { 2455 /* calibrate filter for 20MHz bandwidth */ 2456 sc->rf24_20mhz = 0x1f; /* default value */ 2457 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2458 2459 /* select 40MHz bandwidth */ 2460 bbp = rt2860_mcu_bbp_read(sc, 4); 2461 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2462 rf = rt3090_rf_read(sc, 31); 2463 rt3090_rf_write(sc, 31, rf | 0x20); 2464 2465 /* calibrate filter for 40MHz bandwidth */ 2466 sc->rf24_40mhz = 0x2f; /* default value */ 2467 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2468 2469 /* go back to 20MHz bandwidth */ 2470 bbp = rt2860_mcu_bbp_read(sc, 4); 2471 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2472 } 2473 if (sc->mac_rev < 0x0211) 2474 rt3090_rf_write(sc, 27, 0x03); 2475 2476 tmp = RAL_READ(sc, RT3070_OPT_14); 2477 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2478 2479 if (sc->rf_rev == RT3070_RF_3020) 2480 rt3090_set_rx_antenna(sc, 0); 2481 2482 bbp = rt2860_mcu_bbp_read(sc, 138); 2483 if (sc->mac_ver == 0x3593) { 2484 if (sc->ntxchains == 1) 2485 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2486 else if (sc->ntxchains == 2) 2487 bbp |= 0x40; /* turn off DAC2 */ 2488 if (sc->nrxchains == 1) 2489 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2490 else if (sc->nrxchains == 2) 2491 bbp &= ~0x04; /* turn off ADC2 */ 2492 } else { 2493 if (sc->ntxchains == 1) 2494 bbp |= 0x20; /* turn off DAC1 */ 2495 if (sc->nrxchains == 1) 2496 bbp &= ~0x02; /* turn off ADC1 */ 2497 } 2498 rt2860_mcu_bbp_write(sc, 138, bbp); 2499 2500 rf = rt3090_rf_read(sc, 1); 2501 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2502 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2503 rt3090_rf_write(sc, 1, rf); 2504 2505 rf = rt3090_rf_read(sc, 15); 2506 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2507 2508 rf = rt3090_rf_read(sc, 17); 2509 rf &= ~RT3070_TX_LO1; 2510 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2511 rf |= 0x20; /* fix for long range Rx issue */ 2512 if (sc->txmixgain_2ghz >= 2) 2513 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2514 rt3090_rf_write(sc, 17, rf); 2515 2516 rf = rt3090_rf_read(sc, 20); 2517 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2518 2519 rf = rt3090_rf_read(sc, 21); 2520 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2521 2522 return 0; 2523 } 2524 2525 void 2526 rt5390_rf_init(struct rt2860_softc *sc) 2527 { 2528 uint8_t rf, bbp; 2529 int i; 2530 2531 rf = rt3090_rf_read(sc, 2); 2532 /* Toggle RF R2 bit 7. */ 2533 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2534 DELAY(1000); 2535 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2536 2537 /* Initialize RF registers to default value. */ 2538 if (sc->mac_ver == 0x5392) { 2539 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2540 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2541 rt5392_def_rf[i].val); 2542 } 2543 } else { 2544 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2545 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2546 rt5390_def_rf[i].val); 2547 } 2548 } 2549 2550 sc->rf24_20mhz = 0x1f; 2551 sc->rf24_40mhz = 0x2f; 2552 2553 if (sc->mac_rev < 0x0211) 2554 rt3090_rf_write(sc, 27, 0x03); 2555 2556 /* Set led open drain enable. */ 2557 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2558 2559 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2560 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2561 2562 if (sc->mac_ver == 0x5390) 2563 rt3090_set_rx_antenna(sc, 0); 2564 2565 /* Patch RSSI inaccurate issue. */ 2566 rt2860_mcu_bbp_write(sc, 79, 0x13); 2567 rt2860_mcu_bbp_write(sc, 80, 0x05); 2568 rt2860_mcu_bbp_write(sc, 81, 0x33); 2569 2570 /* Enable DC filter. */ 2571 if (sc->mac_rev >= 0x0211) 2572 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2573 2574 bbp = rt2860_mcu_bbp_read(sc, 138); 2575 if (sc->ntxchains == 1) 2576 bbp |= 0x20; /* Turn off DAC1. */ 2577 if (sc->nrxchains == 1) 2578 bbp &= ~0x02; /* Turn off ADC1. */ 2579 rt2860_mcu_bbp_write(sc, 138, bbp); 2580 2581 /* Enable RX LO1 and LO2. */ 2582 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2583 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2584 2585 /* Avoid data lost and CRC error. */ 2586 rt2860_mcu_bbp_write(sc, 4, 2587 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2588 2589 rf = rt3090_rf_read(sc, 30); 2590 rf = (rf & ~0x18) | 0x10; 2591 rt3090_rf_write(sc, 30, rf); 2592 2593 /* Disable hardware antenna diversity. */ 2594 if (sc->mac_ver == 0x5390) 2595 rt2860_mcu_bbp_write(sc, 154, 0); 2596 } 2597 2598 void 2599 rt3090_rf_wakeup(struct rt2860_softc *sc) 2600 { 2601 uint32_t tmp; 2602 uint8_t rf; 2603 2604 if (sc->mac_ver == 0x3593) { 2605 /* enable VCO */ 2606 rf = rt3090_rf_read(sc, 1); 2607 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2608 2609 /* initiate VCO calibration */ 2610 rf = rt3090_rf_read(sc, 3); 2611 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2612 2613 /* enable VCO bias current control */ 2614 rf = rt3090_rf_read(sc, 6); 2615 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2616 2617 /* initiate res calibration */ 2618 rf = rt3090_rf_read(sc, 2); 2619 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2620 2621 /* set reference current control to 0.33 mA */ 2622 rf = rt3090_rf_read(sc, 22); 2623 rf &= ~RT3593_CP_IC_MASK; 2624 rf |= 1 << RT3593_CP_IC_SHIFT; 2625 rt3090_rf_write(sc, 22, rf); 2626 2627 /* enable RX CTB */ 2628 rf = rt3090_rf_read(sc, 46); 2629 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2630 2631 rf = rt3090_rf_read(sc, 20); 2632 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2633 rt3090_rf_write(sc, 20, rf); 2634 } else { 2635 /* enable RF block */ 2636 rf = rt3090_rf_read(sc, 1); 2637 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2638 2639 /* enable VCO bias current control */ 2640 rf = rt3090_rf_read(sc, 7); 2641 rt3090_rf_write(sc, 7, rf | 0x30); 2642 2643 rf = rt3090_rf_read(sc, 9); 2644 rt3090_rf_write(sc, 9, rf | 0x0e); 2645 2646 /* enable RX CTB */ 2647 rf = rt3090_rf_read(sc, 21); 2648 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2649 2650 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2651 rf = rt3090_rf_read(sc, 27); 2652 rf &= ~0x77; 2653 if (sc->mac_rev < 0x0211) 2654 rf |= 0x03; 2655 rt3090_rf_write(sc, 27, rf); 2656 } 2657 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2658 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2659 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2660 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2661 } 2662 } 2663 2664 void 2665 rt5390_rf_wakeup(struct rt2860_softc *sc) 2666 { 2667 uint32_t tmp; 2668 uint8_t rf; 2669 2670 rf = rt3090_rf_read(sc, 1); 2671 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2672 RT3070_TX0_PD; 2673 if (sc->mac_ver == 0x5392) 2674 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2675 rt3090_rf_write(sc, 1, rf); 2676 2677 rf = rt3090_rf_read(sc, 6); 2678 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2679 if (sc->mac_ver == 0x5390) 2680 rf &= ~RT3593_VCO_IC; 2681 rt3090_rf_write(sc, 6, rf); 2682 2683 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2684 2685 rf = rt3090_rf_read(sc, 22); 2686 rf = (rf & ~0xe0) | 0x20; 2687 rt3090_rf_write(sc, 22, rf); 2688 2689 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2690 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2691 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2692 2693 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2694 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2695 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2696 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2697 } 2698 } 2699 2700 int 2701 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2702 uint8_t *val) 2703 { 2704 uint8_t rf22, rf24; 2705 uint8_t bbp55_pb, bbp55_sb, delta; 2706 int ntries; 2707 2708 /* program filter */ 2709 rf24 = rt3090_rf_read(sc, 24); 2710 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2711 rt3090_rf_write(sc, 24, rf24); 2712 2713 /* enable baseband loopback mode */ 2714 rf22 = rt3090_rf_read(sc, 22); 2715 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2716 2717 /* set power and frequency of passband test tone */ 2718 rt2860_mcu_bbp_write(sc, 24, 0x00); 2719 for (ntries = 0; ntries < 100; ntries++) { 2720 /* transmit test tone */ 2721 rt2860_mcu_bbp_write(sc, 25, 0x90); 2722 DELAY(1000); 2723 /* read received power */ 2724 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2725 if (bbp55_pb != 0) 2726 break; 2727 } 2728 if (ntries == 100) 2729 return ETIMEDOUT; 2730 2731 /* set power and frequency of stopband test tone */ 2732 rt2860_mcu_bbp_write(sc, 24, 0x06); 2733 for (ntries = 0; ntries < 100; ntries++) { 2734 /* transmit test tone */ 2735 rt2860_mcu_bbp_write(sc, 25, 0x90); 2736 DELAY(1000); 2737 /* read received power */ 2738 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2739 2740 delta = bbp55_pb - bbp55_sb; 2741 if (delta > target) 2742 break; 2743 2744 /* reprogram filter */ 2745 rf24++; 2746 rt3090_rf_write(sc, 24, rf24); 2747 } 2748 if (ntries < 100) { 2749 if (rf24 != init) 2750 rf24--; /* backtrack */ 2751 *val = rf24; 2752 rt3090_rf_write(sc, 24, rf24); 2753 } 2754 2755 /* restore initial state */ 2756 rt2860_mcu_bbp_write(sc, 24, 0x00); 2757 2758 /* disable baseband loopback mode */ 2759 rf22 = rt3090_rf_read(sc, 22); 2760 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2761 2762 return 0; 2763 } 2764 2765 void 2766 rt3090_rf_setup(struct rt2860_softc *sc) 2767 { 2768 uint8_t bbp; 2769 int i; 2770 2771 if (sc->mac_rev >= 0x0211) { 2772 /* enable DC filter */ 2773 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2774 2775 /* improve power consumption */ 2776 bbp = rt2860_mcu_bbp_read(sc, 31); 2777 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2778 } 2779 2780 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2781 if (sc->mac_rev < 0x0211) { 2782 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2783 sc->patch_dac ? 0x2c : 0x0f); 2784 } else 2785 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2786 2787 /* initialize RF registers from ROM */ 2788 if (sc->mac_ver < 0x5390) { 2789 for (i = 0; i < 10; i++) { 2790 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2791 continue; 2792 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2793 } 2794 } 2795 } 2796 2797 void 2798 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2799 { 2800 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2801 which | (sc->leds & 0x7f), 0); 2802 } 2803 2804 /* 2805 * Hardware has a general-purpose programmable timer interrupt that can 2806 * periodically raise MAC_INT_4. 2807 */ 2808 void 2809 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2810 { 2811 uint32_t tmp; 2812 2813 /* disable GP timer before reprogramming it */ 2814 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2815 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2816 2817 if (ms == 0) 2818 return; 2819 2820 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2821 ms *= 16; /* Unit: 64us */ 2822 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2823 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2824 2825 /* enable GP timer */ 2826 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2827 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2828 } 2829 2830 void 2831 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2832 { 2833 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2834 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2835 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2836 bssid[4] | bssid[5] << 8); 2837 } 2838 2839 void 2840 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2841 { 2842 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2843 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2844 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2845 addr[4] | addr[5] << 8 | 0xff << 16); 2846 } 2847 2848 void 2849 rt2860_updateslot(struct ieee80211com *ic) 2850 { 2851 struct rt2860_softc *sc = ic->ic_softc; 2852 uint32_t tmp; 2853 2854 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2855 tmp &= ~0xff; 2856 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2857 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2858 } 2859 2860 void 2861 rt2860_updateprot(struct ieee80211com *ic) 2862 { 2863 struct rt2860_softc *sc = ic->ic_softc; 2864 uint32_t tmp; 2865 2866 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2867 /* setup protection frame rate (MCS code) */ 2868 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2869 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2870 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2871 2872 /* CCK frames don't require protection */ 2873 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2874 2875 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2876 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2877 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2878 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2879 tmp |= RT2860_PROT_CTRL_CTS; 2880 } 2881 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2882 } 2883 2884 void 2885 rt2860_updateedca(struct ieee80211com *ic) 2886 { 2887 struct rt2860_softc *sc = ic->ic_softc; 2888 int aci; 2889 2890 /* update MAC TX configuration registers */ 2891 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2892 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2893 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 2894 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 2895 ic->ic_edca_ac[aci].ac_aifsn << 8 | 2896 ic->ic_edca_ac[aci].ac_txoplimit); 2897 } 2898 2899 /* update SCH/DMA registers too */ 2900 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2901 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 2902 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 2903 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 2904 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 2905 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2906 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 2907 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 2908 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 2909 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 2910 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2911 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 2912 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 2913 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 2914 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 2915 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2916 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 2917 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 2918 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2919 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 2920 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 2921 } 2922 2923 int 2924 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2925 struct ieee80211_key *k) 2926 { 2927 struct rt2860_softc *sc = ic->ic_softc; 2928 bus_size_t base; 2929 uint32_t attr; 2930 uint8_t mode, wcid, iv[8]; 2931 2932 /* defer setting of WEP keys until interface is brought up */ 2933 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2934 (IFF_UP | IFF_RUNNING)) 2935 return 0; 2936 2937 /* map net80211 cipher to RT2860 security mode */ 2938 switch (k->k_cipher) { 2939 case IEEE80211_CIPHER_WEP40: 2940 mode = RT2860_MODE_WEP40; 2941 break; 2942 case IEEE80211_CIPHER_WEP104: 2943 mode = RT2860_MODE_WEP104; 2944 break; 2945 case IEEE80211_CIPHER_TKIP: 2946 mode = RT2860_MODE_TKIP; 2947 break; 2948 case IEEE80211_CIPHER_CCMP: 2949 mode = RT2860_MODE_AES_CCMP; 2950 break; 2951 default: 2952 return EINVAL; 2953 } 2954 2955 if (k->k_flags & IEEE80211_KEY_GROUP) { 2956 wcid = 0; /* NB: update WCID0 for group keys */ 2957 base = RT2860_SKEY(0, k->k_id); 2958 } else { 2959 wcid = ((struct rt2860_node *)ni)->wcid; 2960 base = RT2860_PKEY(wcid); 2961 } 2962 2963 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2964 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 2965 #ifndef IEEE80211_STA_ONLY 2966 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2967 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 2968 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 2969 } else 2970 #endif 2971 { 2972 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 2973 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 2974 } 2975 } else 2976 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 2977 2978 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 2979 (k->k_flags & IEEE80211_KEY_TX)) { 2980 /* set initial packet number in IV+EIV */ 2981 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 2982 k->k_cipher == IEEE80211_CIPHER_WEP104) { 2983 uint32_t val = arc4random(); 2984 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 2985 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 2986 val += 0x000100; 2987 iv[0] = val; 2988 iv[1] = val >> 8; 2989 iv[2] = val >> 16; 2990 iv[3] = k->k_id << 6; 2991 iv[4] = iv[5] = iv[6] = iv[7] = 0; 2992 } else { 2993 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2994 iv[0] = k->k_tsc >> 8; 2995 iv[1] = (iv[0] | 0x20) & 0x7f; 2996 iv[2] = k->k_tsc; 2997 } else /* CCMP */ { 2998 iv[0] = k->k_tsc; 2999 iv[1] = k->k_tsc >> 8; 3000 iv[2] = 0; 3001 } 3002 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3003 iv[4] = k->k_tsc >> 16; 3004 iv[5] = k->k_tsc >> 24; 3005 iv[6] = k->k_tsc >> 32; 3006 iv[7] = k->k_tsc >> 40; 3007 } 3008 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3009 } 3010 3011 if (k->k_flags & IEEE80211_KEY_GROUP) { 3012 /* install group key */ 3013 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3014 attr &= ~(0xf << (k->k_id * 4)); 3015 attr |= mode << (k->k_id * 4); 3016 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3017 } else { 3018 /* install pairwise key */ 3019 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3020 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3021 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3022 } 3023 return 0; 3024 } 3025 3026 void 3027 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3028 struct ieee80211_key *k) 3029 { 3030 struct rt2860_softc *sc = ic->ic_softc; 3031 uint32_t attr; 3032 uint8_t wcid; 3033 3034 if (k->k_flags & IEEE80211_KEY_GROUP) { 3035 /* remove group key */ 3036 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3037 attr &= ~(0xf << (k->k_id * 4)); 3038 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3039 3040 } else { 3041 /* remove pairwise key */ 3042 wcid = ((struct rt2860_node *)ni)->wcid; 3043 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3044 attr &= ~0xf; 3045 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3046 } 3047 } 3048 3049 #if NBPFILTER > 0 3050 int8_t 3051 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3052 { 3053 struct ieee80211com *ic = &sc->sc_ic; 3054 struct ieee80211_channel *c = ic->ic_ibss_chan; 3055 int delta; 3056 3057 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3058 u_int chan = ieee80211_chan2ieee(ic, c); 3059 delta = sc->rssi_5ghz[rxchain]; 3060 3061 /* determine channel group */ 3062 if (chan <= 64) 3063 delta -= sc->lna[1]; 3064 else if (chan <= 128) 3065 delta -= sc->lna[2]; 3066 else 3067 delta -= sc->lna[3]; 3068 } else 3069 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3070 3071 return -12 - delta - rssi; 3072 } 3073 #endif 3074 3075 /* 3076 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3077 * Used to adjust per-rate Tx power registers. 3078 */ 3079 static __inline uint32_t 3080 b4inc(uint32_t b32, int8_t delta) 3081 { 3082 int8_t i, b4; 3083 3084 for (i = 0; i < 8; i++) { 3085 b4 = b32 & 0xf; 3086 b4 += delta; 3087 if (b4 < 0) 3088 b4 = 0; 3089 else if (b4 > 0xf) 3090 b4 = 0xf; 3091 b32 = b32 >> 4 | b4 << 28; 3092 } 3093 return b32; 3094 } 3095 3096 const char * 3097 rt2860_get_rf(uint16_t rev) 3098 { 3099 switch (rev) { 3100 case RT2860_RF_2820: return "RT2820"; 3101 case RT2860_RF_2850: return "RT2850"; 3102 case RT2860_RF_2720: return "RT2720"; 3103 case RT2860_RF_2750: return "RT2750"; 3104 case RT3070_RF_3020: return "RT3020"; 3105 case RT3070_RF_2020: return "RT2020"; 3106 case RT3070_RF_3021: return "RT3021"; 3107 case RT3070_RF_3022: return "RT3022"; 3108 case RT3070_RF_3052: return "RT3052"; 3109 case RT3070_RF_3320: return "RT3320"; 3110 case RT3070_RF_3053: return "RT3053"; 3111 case RT5390_RF_5390: return "RT5390"; 3112 case RT5390_RF_5392: return "RT5392"; 3113 default: return "unknown"; 3114 } 3115 } 3116 3117 int 3118 rt2860_read_eeprom(struct rt2860_softc *sc) 3119 { 3120 struct ieee80211com *ic = &sc->sc_ic; 3121 int8_t delta_2ghz, delta_5ghz; 3122 uint32_t tmp; 3123 uint16_t val; 3124 int ridx, ant, i; 3125 3126 /* check whether the ROM is eFUSE ROM or EEPROM */ 3127 sc->sc_srom_read = rt2860_eeprom_read_2; 3128 if (sc->mac_ver >= 0x3071) { 3129 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3130 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3131 if (tmp & RT3070_SEL_EFUSE) 3132 sc->sc_srom_read = rt3090_efuse_read_2; 3133 } 3134 3135 /* read EEPROM version */ 3136 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3137 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3138 3139 /* read MAC address */ 3140 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3141 ic->ic_myaddr[0] = val & 0xff; 3142 ic->ic_myaddr[1] = val >> 8; 3143 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3144 ic->ic_myaddr[2] = val & 0xff; 3145 ic->ic_myaddr[3] = val >> 8; 3146 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3147 ic->ic_myaddr[4] = val & 0xff; 3148 ic->ic_myaddr[5] = val >> 8; 3149 3150 /* read country code */ 3151 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3152 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3153 3154 /* read vendor BBP settings */ 3155 for (i = 0; i < 8; i++) { 3156 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3157 sc->bbp[i].val = val & 0xff; 3158 sc->bbp[i].reg = val >> 8; 3159 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3160 } 3161 if (sc->mac_ver >= 0x3071) { 3162 /* read vendor RF settings */ 3163 for (i = 0; i < 10; i++) { 3164 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3165 sc->rf[i].val = val & 0xff; 3166 sc->rf[i].reg = val >> 8; 3167 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3168 sc->rf[i].val)); 3169 } 3170 } 3171 3172 /* read RF frequency offset from EEPROM */ 3173 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3174 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3175 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3176 if ((val >> 8) != 0xff) { 3177 /* read LEDs operating mode */ 3178 sc->leds = val >> 8; 3179 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3180 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3181 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3182 } else { 3183 /* broken EEPROM, use default settings */ 3184 sc->leds = 0x01; 3185 sc->led[0] = 0x5555; 3186 sc->led[1] = 0x2221; 3187 sc->led[2] = 0xa9f8; 3188 } 3189 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3190 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3191 3192 /* read RF information */ 3193 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3194 if (sc->mac_ver >= 0x5390) 3195 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3196 else 3197 sc->rf_rev = (val >> 8) & 0xf; 3198 sc->ntxchains = (val >> 4) & 0xf; 3199 sc->nrxchains = val & 0xf; 3200 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3201 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3202 3203 /* check if RF supports automatic Tx access gain control */ 3204 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3205 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3206 /* check if driver should patch the DAC issue */ 3207 if ((val >> 8) != 0xff) 3208 sc->patch_dac = (val >> 15) & 1; 3209 if ((val & 0xff) != 0xff) { 3210 sc->ext_5ghz_lna = (val >> 3) & 1; 3211 sc->ext_2ghz_lna = (val >> 2) & 1; 3212 /* check if RF supports automatic Tx access gain control */ 3213 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3214 /* check if we have a hardware radio switch */ 3215 sc->rfswitch = val & 1; 3216 } 3217 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3218 /* read PCIe power save level */ 3219 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3220 if ((val & 0xff) != 0xff) { 3221 sc->pslevel = val & 0x3; 3222 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3223 if ((val & 0xff80) != 0x9280) 3224 sc->pslevel = MIN(sc->pslevel, 1); 3225 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3226 } 3227 } 3228 3229 /* read power settings for 2GHz channels */ 3230 for (i = 0; i < 14; i += 2) { 3231 val = rt2860_srom_read(sc, 3232 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3233 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3234 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3235 3236 if (sc->mac_ver != 0x5390) { 3237 val = rt2860_srom_read(sc, 3238 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3239 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3240 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3241 } 3242 } 3243 /* fix broken Tx power entries */ 3244 for (i = 0; i < 14; i++) { 3245 if (sc->txpow1[i] < 0 || 3246 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3247 sc->txpow1[i] = 5; 3248 if (sc->mac_ver != 0x5390) { 3249 if (sc->txpow2[i] < 0 || 3250 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3251 sc->txpow2[i] = 5; 3252 } 3253 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3254 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3255 } 3256 /* read power settings for 5GHz channels */ 3257 for (i = 0; i < 40; i += 2) { 3258 val = rt2860_srom_read(sc, 3259 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3260 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3261 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3262 3263 val = rt2860_srom_read(sc, 3264 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3265 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3266 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3267 } 3268 /* fix broken Tx power entries */ 3269 for (i = 0; i < 40; i++) { 3270 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3271 sc->txpow1[14 + i] = 5; 3272 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3273 sc->txpow2[14 + i] = 5; 3274 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3275 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3276 sc->txpow2[14 + i])); 3277 } 3278 3279 /* read Tx power compensation for each Tx rate */ 3280 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3281 delta_2ghz = delta_5ghz = 0; 3282 if ((val & 0xff) != 0xff && (val & 0x80)) { 3283 delta_2ghz = val & 0xf; 3284 if (!(val & 0x40)) /* negative number */ 3285 delta_2ghz = -delta_2ghz; 3286 } 3287 val >>= 8; 3288 if ((val & 0xff) != 0xff && (val & 0x80)) { 3289 delta_5ghz = val & 0xf; 3290 if (!(val & 0x40)) /* negative number */ 3291 delta_5ghz = -delta_5ghz; 3292 } 3293 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3294 delta_2ghz, delta_5ghz)); 3295 3296 for (ridx = 0; ridx < 5; ridx++) { 3297 uint32_t reg; 3298 3299 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3300 reg = val; 3301 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3302 reg |= (uint32_t)val << 16; 3303 3304 sc->txpow20mhz[ridx] = reg; 3305 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3306 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3307 3308 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3309 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3310 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3311 } 3312 3313 /* read factory-calibrated samples for temperature compensation */ 3314 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3315 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3316 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3317 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3318 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3319 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3320 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3321 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3322 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3323 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3324 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3325 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3326 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3327 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3328 sc->step_2ghz = val >> 8; 3329 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3330 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3331 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3332 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3333 sc->tssi_2ghz[8], sc->step_2ghz)); 3334 /* check that ref value is correct, otherwise disable calibration */ 3335 if (sc->tssi_2ghz[4] == 0xff) 3336 sc->calib_2ghz = 0; 3337 3338 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3339 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3340 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3341 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3342 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3343 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3344 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3345 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3346 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3347 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3348 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3349 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3350 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3351 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3352 sc->step_5ghz = val >> 8; 3353 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3354 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3355 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3356 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3357 sc->tssi_5ghz[8], sc->step_5ghz)); 3358 /* check that ref value is correct, otherwise disable calibration */ 3359 if (sc->tssi_5ghz[4] == 0xff) 3360 sc->calib_5ghz = 0; 3361 3362 /* read RSSI offsets and LNA gains from EEPROM */ 3363 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3364 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3365 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3366 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3367 if (sc->mac_ver >= 0x3071) { 3368 /* 3369 * On RT3090 chips (limited to 2 Rx chains), this ROM 3370 * field contains the Tx mixer gain for the 2GHz band. 3371 */ 3372 if ((val & 0xff) != 0xff) 3373 sc->txmixgain_2ghz = val & 0x7; 3374 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3375 } else 3376 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3377 sc->lna[2] = val >> 8; /* channel group 2 */ 3378 3379 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3380 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3381 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3382 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3383 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3384 sc->lna[3] = val >> 8; /* channel group 3 */ 3385 3386 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3387 if (sc->mac_ver >= 0x3071) 3388 sc->lna[0] = RT3090_DEF_LNA; 3389 else /* channel group 0 */ 3390 sc->lna[0] = val & 0xff; 3391 sc->lna[1] = val >> 8; /* channel group 1 */ 3392 3393 /* fix broken 5GHz LNA entries */ 3394 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3395 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3396 sc->lna[2] = sc->lna[1]; 3397 } 3398 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3399 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3400 sc->lna[3] = sc->lna[1]; 3401 } 3402 3403 /* fix broken RSSI offset entries */ 3404 for (ant = 0; ant < 3; ant++) { 3405 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3406 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3407 ant + 1, sc->rssi_2ghz[ant])); 3408 sc->rssi_2ghz[ant] = 0; 3409 } 3410 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3411 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3412 ant + 1, sc->rssi_5ghz[ant])); 3413 sc->rssi_5ghz[ant] = 0; 3414 } 3415 } 3416 3417 return 0; 3418 } 3419 3420 int 3421 rt2860_bbp_init(struct rt2860_softc *sc) 3422 { 3423 int i, ntries; 3424 3425 /* wait for BBP to wake up */ 3426 for (ntries = 0; ntries < 20; ntries++) { 3427 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3428 if (bbp0 != 0 && bbp0 != 0xff) 3429 break; 3430 } 3431 if (ntries == 20) { 3432 printf("%s: timeout waiting for BBP to wake up\n", 3433 sc->sc_dev.dv_xname); 3434 return ETIMEDOUT; 3435 } 3436 3437 /* initialize BBP registers to default values */ 3438 if (sc->mac_ver >= 0x5390) 3439 rt5390_bbp_init(sc); 3440 else { 3441 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3442 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3443 rt2860_def_bbp[i].val); 3444 } 3445 } 3446 3447 /* fix BBP84 for RT2860E */ 3448 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3449 rt2860_mcu_bbp_write(sc, 84, 0x19); 3450 3451 if (sc->mac_ver >= 0x3071) { 3452 rt2860_mcu_bbp_write(sc, 79, 0x13); 3453 rt2860_mcu_bbp_write(sc, 80, 0x05); 3454 rt2860_mcu_bbp_write(sc, 81, 0x33); 3455 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3456 rt2860_mcu_bbp_write(sc, 69, 0x16); 3457 rt2860_mcu_bbp_write(sc, 73, 0x12); 3458 } 3459 3460 return 0; 3461 } 3462 3463 void 3464 rt5390_bbp_init(struct rt2860_softc *sc) 3465 { 3466 uint8_t bbp; 3467 int i; 3468 3469 /* Apply maximum likelihood detection for 2 stream case. */ 3470 if (sc->nrxchains > 1) { 3471 bbp = rt2860_mcu_bbp_read(sc, 105); 3472 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3473 } 3474 3475 /* Avoid data lost and CRC error. */ 3476 bbp = rt2860_mcu_bbp_read(sc, 4); 3477 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3478 3479 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3480 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3481 rt5390_def_bbp[i].val); 3482 } 3483 3484 if (sc->mac_ver == 0x5392) { 3485 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3486 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3487 rt2860_mcu_bbp_write(sc, 98, 0x12); 3488 rt2860_mcu_bbp_write(sc, 106, 0x05); 3489 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3490 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3491 } 3492 3493 bbp = rt2860_mcu_bbp_read(sc, 152); 3494 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3495 3496 /* Disable hardware antenna diversity. */ 3497 if (sc->mac_ver == 0x5390) 3498 rt2860_mcu_bbp_write(sc, 154, 0); 3499 } 3500 3501 int 3502 rt2860_txrx_enable(struct rt2860_softc *sc) 3503 { 3504 uint32_t tmp; 3505 int ntries; 3506 3507 /* enable Tx/Rx DMA engine */ 3508 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3509 RAL_BARRIER_READ_WRITE(sc); 3510 for (ntries = 0; ntries < 200; ntries++) { 3511 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3512 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3513 break; 3514 DELAY(1000); 3515 } 3516 if (ntries == 200) { 3517 printf("%s: timeout waiting for DMA engine\n", 3518 sc->sc_dev.dv_xname); 3519 return ETIMEDOUT; 3520 } 3521 3522 DELAY(50); 3523 3524 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3525 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3526 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3527 3528 /* set Rx filter */ 3529 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3530 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3531 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3532 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3533 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3534 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3535 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3536 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3537 } 3538 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3539 3540 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3541 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3542 3543 return 0; 3544 } 3545 3546 int 3547 rt2860_init(struct ifnet *ifp) 3548 { 3549 struct rt2860_softc *sc = ifp->if_softc; 3550 struct ieee80211com *ic = &sc->sc_ic; 3551 uint32_t tmp; 3552 uint8_t bbp1, bbp3; 3553 int i, qid, ridx, ntries, error; 3554 3555 /* for CardBus, power on the socket */ 3556 if (!(sc->sc_flags & RT2860_ENABLED)) { 3557 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3558 printf("%s: could not enable device\n", 3559 sc->sc_dev.dv_xname); 3560 return EIO; 3561 } 3562 sc->sc_flags |= RT2860_ENABLED; 3563 } 3564 3565 if (sc->rfswitch) { 3566 /* hardware has a radio switch on GPIO pin 2 */ 3567 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3568 printf("%s: radio is disabled by hardware switch\n", 3569 sc->sc_dev.dv_xname); 3570 #ifdef notyet 3571 rt2860_stop(ifp, 1); 3572 return EPERM; 3573 #endif 3574 } 3575 } 3576 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3577 3578 /* disable DMA */ 3579 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3580 tmp &= 0xff0; 3581 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3582 3583 /* PBF hardware reset */ 3584 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3585 RAL_BARRIER_WRITE(sc); 3586 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3587 3588 if ((error = rt2860_load_microcode(sc)) != 0) { 3589 printf("%s: could not load 8051 microcode\n", 3590 sc->sc_dev.dv_xname); 3591 rt2860_stop(ifp, 1); 3592 return error; 3593 } 3594 3595 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3596 rt2860_set_macaddr(sc, ic->ic_myaddr); 3597 3598 /* init Tx power for all Tx rates (from EEPROM) */ 3599 for (ridx = 0; ridx < 5; ridx++) { 3600 if (sc->txpow20mhz[ridx] == 0xffffffff) 3601 continue; 3602 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3603 } 3604 3605 for (ntries = 0; ntries < 100; ntries++) { 3606 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3607 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3608 break; 3609 DELAY(1000); 3610 } 3611 if (ntries == 100) { 3612 printf("%s: timeout waiting for DMA engine\n", 3613 sc->sc_dev.dv_xname); 3614 rt2860_stop(ifp, 1); 3615 return ETIMEDOUT; 3616 } 3617 tmp &= 0xff0; 3618 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3619 3620 /* reset Rx ring and all 6 Tx rings */ 3621 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3622 3623 /* PBF hardware reset */ 3624 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3625 RAL_BARRIER_WRITE(sc); 3626 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3627 3628 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3629 3630 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3631 RAL_BARRIER_WRITE(sc); 3632 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3633 3634 for (i = 0; i < nitems(rt2860_def_mac); i++) 3635 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3636 if (sc->mac_ver >= 0x5390) 3637 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3638 else if (sc->mac_ver >= 0x3071) { 3639 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3640 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3641 4 << RT2860_DLY_PAPE_EN_SHIFT); 3642 } 3643 3644 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3645 sc->sc_flags |= RT2860_PCIE; 3646 /* PCIe has different clock cycle count than PCI */ 3647 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3648 tmp = (tmp & ~0xff) | 0x7d; 3649 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3650 } 3651 3652 /* wait while MAC is busy */ 3653 for (ntries = 0; ntries < 100; ntries++) { 3654 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3655 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3656 break; 3657 DELAY(1000); 3658 } 3659 if (ntries == 100) { 3660 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname); 3661 rt2860_stop(ifp, 1); 3662 return ETIMEDOUT; 3663 } 3664 3665 /* clear Host to MCU mailbox */ 3666 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3667 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3668 3669 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3670 DELAY(1000); 3671 3672 if ((error = rt2860_bbp_init(sc)) != 0) { 3673 rt2860_stop(ifp, 1); 3674 return error; 3675 } 3676 3677 /* clear RX WCID search table */ 3678 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3679 /* clear pairwise key table */ 3680 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3681 /* clear IV/EIV table */ 3682 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3683 /* clear WCID attribute table */ 3684 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3685 /* clear shared key table */ 3686 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3687 /* clear shared key mode */ 3688 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3689 3690 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3691 for (qid = 0; qid < 6; qid++) { 3692 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3693 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3694 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3695 } 3696 3697 /* init Rx ring */ 3698 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3699 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3700 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3701 3702 /* setup maximum buffer sizes */ 3703 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3704 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3705 3706 for (ntries = 0; ntries < 100; ntries++) { 3707 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3708 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3709 break; 3710 DELAY(1000); 3711 } 3712 if (ntries == 100) { 3713 printf("%s: timeout waiting for DMA engine\n", 3714 sc->sc_dev.dv_xname); 3715 rt2860_stop(ifp, 1); 3716 return ETIMEDOUT; 3717 } 3718 tmp &= 0xff0; 3719 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3720 3721 /* disable interrupts mitigation */ 3722 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3723 3724 /* write vendor-specific BBP values (from EEPROM) */ 3725 for (i = 0; i < 8; i++) { 3726 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3727 continue; 3728 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3729 } 3730 3731 /* select Main antenna for 1T1R devices */ 3732 if (sc->rf_rev == RT3070_RF_2020 || 3733 sc->rf_rev == RT3070_RF_3020 || 3734 sc->rf_rev == RT3070_RF_3320 || 3735 sc->rf_rev == RT5390_RF_5390) 3736 rt3090_set_rx_antenna(sc, 0); 3737 3738 /* send LEDs operating mode to microcontroller */ 3739 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3740 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3741 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3742 3743 if (sc->mac_ver >= 0x5390) 3744 rt5390_rf_init(sc); 3745 else if (sc->mac_ver >= 0x3071) 3746 rt3090_rf_init(sc); 3747 3748 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3749 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3750 3751 if (sc->mac_ver >= 0x5390) 3752 rt5390_rf_wakeup(sc); 3753 else if (sc->mac_ver >= 0x3071) 3754 rt3090_rf_wakeup(sc); 3755 3756 /* disable non-existing Rx chains */ 3757 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3758 bbp3 &= ~(1 << 3 | 1 << 4); 3759 if (sc->nrxchains == 2) 3760 bbp3 |= 1 << 3; 3761 else if (sc->nrxchains == 3) 3762 bbp3 |= 1 << 4; 3763 rt2860_mcu_bbp_write(sc, 3, bbp3); 3764 3765 /* disable non-existing Tx chains */ 3766 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3767 if (sc->ntxchains == 1) 3768 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3769 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3770 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3771 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3772 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3773 rt2860_mcu_bbp_write(sc, 1, bbp1); 3774 3775 if (sc->mac_ver >= 0x3071) 3776 rt3090_rf_setup(sc); 3777 3778 /* select default channel */ 3779 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3780 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3781 3782 /* reset RF from MCU */ 3783 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3784 3785 /* set RTS threshold */ 3786 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3787 tmp &= ~0xffff00; 3788 tmp |= ic->ic_rtsthreshold << 8; 3789 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3790 3791 /* setup initial protection mode */ 3792 sc->sc_ic_flags = ic->ic_flags; 3793 rt2860_updateprot(ic); 3794 3795 /* turn radio LED on */ 3796 rt2860_set_leds(sc, RT2860_LED_RADIO); 3797 3798 /* enable Tx/Rx DMA engine */ 3799 if ((error = rt2860_txrx_enable(sc)) != 0) { 3800 rt2860_stop(ifp, 1); 3801 return error; 3802 } 3803 3804 /* clear pending interrupts */ 3805 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3806 /* enable interrupts */ 3807 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3808 3809 if (sc->sc_flags & RT2860_ADVANCED_PS) 3810 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3811 3812 ifp->if_flags |= IFF_RUNNING; 3813 ifq_clr_oactive(&ifp->if_snd); 3814 3815 if (ic->ic_flags & IEEE80211_F_WEPON) { 3816 /* install WEP keys */ 3817 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3818 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3819 } 3820 3821 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3822 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3823 else 3824 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3825 3826 return 0; 3827 } 3828 3829 void 3830 rt2860_stop(struct ifnet *ifp, int disable) 3831 { 3832 struct rt2860_softc *sc = ifp->if_softc; 3833 struct ieee80211com *ic = &sc->sc_ic; 3834 uint32_t tmp; 3835 int qid; 3836 3837 if (ifp->if_flags & IFF_RUNNING) 3838 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3839 3840 sc->sc_tx_timer = 0; 3841 ifp->if_timer = 0; 3842 ifp->if_flags &= ~IFF_RUNNING; 3843 ifq_clr_oactive(&ifp->if_snd); 3844 3845 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 3846 3847 /* disable interrupts */ 3848 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3849 3850 /* disable GP timer */ 3851 rt2860_set_gp_timer(sc, 0); 3852 3853 /* disable Rx */ 3854 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3855 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3856 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3857 3858 /* reset adapter */ 3859 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3860 RAL_BARRIER_WRITE(sc); 3861 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3862 3863 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3864 sc->qfullmsk = 0; 3865 for (qid = 0; qid < 6; qid++) 3866 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3867 rt2860_reset_rx_ring(sc, &sc->rxq); 3868 3869 /* for CardBus, power down the socket */ 3870 if (disable && sc->sc_disable != NULL) { 3871 if (sc->sc_flags & RT2860_ENABLED) { 3872 (*sc->sc_disable)(sc); 3873 sc->sc_flags &= ~RT2860_ENABLED; 3874 } 3875 } 3876 } 3877 3878 int 3879 rt2860_load_microcode(struct rt2860_softc *sc) 3880 { 3881 int ntries; 3882 3883 /* set "host program ram write selection" bit */ 3884 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 3885 /* write microcode image */ 3886 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 3887 /* kick microcontroller unit */ 3888 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 3889 RAL_BARRIER_WRITE(sc); 3890 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 3891 3892 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3893 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3894 3895 /* wait until microcontroller is ready */ 3896 RAL_BARRIER_READ_WRITE(sc); 3897 for (ntries = 0; ntries < 1000; ntries++) { 3898 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 3899 break; 3900 DELAY(1000); 3901 } 3902 if (ntries == 1000) { 3903 printf("%s: timeout waiting for MCU to initialize\n", 3904 sc->sc_dev.dv_xname); 3905 return ETIMEDOUT; 3906 } 3907 return 0; 3908 } 3909 3910 /* 3911 * This function is called periodically to adjust Tx power based on 3912 * temperature variation. 3913 */ 3914 void 3915 rt2860_calib(struct rt2860_softc *sc) 3916 { 3917 struct ieee80211com *ic = &sc->sc_ic; 3918 const uint8_t *tssi; 3919 uint8_t step, bbp49; 3920 int8_t ridx, d; 3921 3922 /* read current temperature */ 3923 bbp49 = rt2860_mcu_bbp_read(sc, 49); 3924 3925 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 3926 tssi = &sc->tssi_2ghz[4]; 3927 step = sc->step_2ghz; 3928 } else { 3929 tssi = &sc->tssi_5ghz[4]; 3930 step = sc->step_5ghz; 3931 } 3932 3933 if (bbp49 < tssi[0]) { /* lower than reference */ 3934 /* use higher Tx power than default */ 3935 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 3936 } else if (bbp49 > tssi[0]) { /* greater than reference */ 3937 /* use lower Tx power than default */ 3938 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 3939 } else { 3940 /* use default Tx power */ 3941 d = 0; 3942 } 3943 d *= step; 3944 3945 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 3946 3947 /* write adjusted Tx power values for each Tx rate */ 3948 for (ridx = 0; ridx < 5; ridx++) { 3949 if (sc->txpow20mhz[ridx] == 0xffffffff) 3950 continue; 3951 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 3952 b4inc(sc->txpow20mhz[ridx], d)); 3953 } 3954 } 3955 3956 void 3957 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 3958 { 3959 uint32_t tmp; 3960 if (aux) { 3961 if (sc->mac_ver == 0x5390) { 3962 rt2860_mcu_bbp_write(sc, 152, 3963 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 3964 } else { 3965 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3966 RAL_WRITE(sc, RT2860_PCI_EECTRL, 3967 tmp & ~RT2860_C); 3968 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3969 RAL_WRITE(sc, RT2860_GPIO_CTRL, 3970 (tmp & ~0x0808) | 0x08); 3971 } 3972 } else { 3973 if (sc->mac_ver == 0x5390) { 3974 rt2860_mcu_bbp_write(sc, 152, 3975 rt2860_mcu_bbp_read(sc, 152) | 0x80); 3976 } else { 3977 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3978 RAL_WRITE(sc, RT2860_PCI_EECTRL, 3979 tmp | RT2860_C); 3980 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3981 RAL_WRITE(sc, RT2860_GPIO_CTRL, 3982 tmp & ~0x0808); 3983 } 3984 } 3985 } 3986 3987 void 3988 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 3989 { 3990 struct ieee80211com *ic = &sc->sc_ic; 3991 u_int chan, group; 3992 3993 chan = ieee80211_chan2ieee(ic, c); 3994 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3995 return; 3996 3997 if (sc->mac_ver >= 0x5390) 3998 rt5390_set_chan(sc, chan); 3999 else if (sc->mac_ver >= 0x3071) 4000 rt3090_set_chan(sc, chan); 4001 else 4002 rt2860_set_chan(sc, chan); 4003 4004 /* determine channel group */ 4005 if (chan <= 14) 4006 group = 0; 4007 else if (chan <= 64) 4008 group = 1; 4009 else if (chan <= 128) 4010 group = 2; 4011 else 4012 group = 3; 4013 4014 /* XXX necessary only when group has changed! */ 4015 if (sc->mac_ver <= 0x5390) 4016 rt2860_select_chan_group(sc, group); 4017 4018 DELAY(1000); 4019 } 4020 4021 #ifndef IEEE80211_STA_ONLY 4022 int 4023 rt2860_setup_beacon(struct rt2860_softc *sc) 4024 { 4025 struct ieee80211com *ic = &sc->sc_ic; 4026 struct rt2860_txwi txwi; 4027 struct mbuf *m; 4028 int ridx; 4029 4030 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL) 4031 return ENOBUFS; 4032 4033 memset(&txwi, 0, sizeof txwi); 4034 txwi.wcid = 0xff; 4035 txwi.len = htole16(m->m_pkthdr.len); 4036 /* send beacons at the lowest available rate */ 4037 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4038 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4039 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4040 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4041 txwi.phy |= htole16(RT2860_PHY_OFDM); 4042 txwi.txop = RT2860_TX_TXOP_HT; 4043 txwi.flags = RT2860_TX_TS; 4044 txwi.xflags = RT2860_TX_NSEQ; 4045 4046 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4047 (uint8_t *)&txwi, sizeof txwi); 4048 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4049 mtod(m, uint8_t *), m->m_pkthdr.len); 4050 4051 m_freem(m); 4052 4053 return 0; 4054 } 4055 #endif 4056 4057 void 4058 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4059 { 4060 struct ieee80211com *ic = &sc->sc_ic; 4061 uint32_t tmp; 4062 4063 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4064 4065 tmp &= ~0x1fffff; 4066 tmp |= ic->ic_bss->ni_intval * 16; 4067 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4068 if (ic->ic_opmode == IEEE80211_M_STA) { 4069 /* 4070 * Local TSF is always updated with remote TSF on beacon 4071 * reception. 4072 */ 4073 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4074 } 4075 #ifndef IEEE80211_STA_ONLY 4076 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 4077 tmp |= RT2860_BCN_TX_EN; 4078 /* 4079 * Local TSF is updated with remote TSF on beacon reception 4080 * only if the remote TSF is greater than local TSF. 4081 */ 4082 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4083 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4084 tmp |= RT2860_BCN_TX_EN; 4085 /* SYNC with nobody */ 4086 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4087 } 4088 #endif 4089 4090 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4091 } 4092