1 /* $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Ralink Technology RT2860/RT3090/RT3390/RT3562 chipset driver 21 * http://www.ralinktech.com/ 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/queue.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 38 #include <machine/bus.h> 39 #include <machine/endian.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/if_ether.h> 55 #include <netinet/ip.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/ic/rt2860var.h> 62 #include <dev/ic/rt2860reg.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/rndvar.h> 69 70 #ifdef RAL_DEBUG 71 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 72 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 73 int rt2860_debug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 void rt2860_attachhook(void *); 80 int rt2860_alloc_tx_ring(struct rt2860_softc *, 81 struct rt2860_tx_ring *); 82 void rt2860_reset_tx_ring(struct rt2860_softc *, 83 struct rt2860_tx_ring *); 84 void rt2860_free_tx_ring(struct rt2860_softc *, 85 struct rt2860_tx_ring *); 86 int rt2860_alloc_tx_pool(struct rt2860_softc *); 87 void rt2860_free_tx_pool(struct rt2860_softc *); 88 int rt2860_alloc_rx_ring(struct rt2860_softc *, 89 struct rt2860_rx_ring *); 90 void rt2860_reset_rx_ring(struct rt2860_softc *, 91 struct rt2860_rx_ring *); 92 void rt2860_free_rx_ring(struct rt2860_softc *, 93 struct rt2860_rx_ring *); 94 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *); 95 int rt2860_media_change(struct ifnet *); 96 void rt2860_iter_func(void *, struct ieee80211_node *); 97 void rt2860_updatestats(struct rt2860_softc *); 98 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *, 99 int); 100 void rt2860_node_leave(struct ieee80211com *, 101 struct ieee80211_node *); 102 int rt2860_ampdu_rx_start(struct ieee80211com *, 103 struct ieee80211_node *, uint8_t); 104 void rt2860_ampdu_rx_stop(struct ieee80211com *, 105 struct ieee80211_node *, uint8_t); 106 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 107 int); 108 uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 void rt2860_intr_coherent(struct rt2860_softc *); 111 void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 void rt2860_tx_intr(struct rt2860_softc *, int); 113 void rt2860_rx_intr(struct rt2860_softc *); 114 void rt2860_tbtt_intr(struct rt2860_softc *); 115 void rt2860_gp_intr(struct rt2860_softc *); 116 int rt2860_tx(struct rt2860_softc *, struct mbuf *, 117 struct ieee80211_node *); 118 void rt2860_start(struct ifnet *); 119 void rt2860_watchdog(struct ifnet *); 120 int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 121 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 122 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 123 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 124 uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 125 void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 126 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 127 void rt2860_enable_mrr(struct rt2860_softc *); 128 void rt2860_set_txpreamble(struct rt2860_softc *); 129 void rt2860_set_basicrates(struct rt2860_softc *); 130 void rt2860_select_chan_group(struct rt2860_softc *, int); 131 void rt2860_set_chan(struct rt2860_softc *, u_int); 132 void rt3090_set_chan(struct rt2860_softc *, u_int); 133 int rt3090_rf_init(struct rt2860_softc *); 134 void rt3090_rf_wakeup(struct rt2860_softc *); 135 int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 136 uint8_t *); 137 void rt3090_rf_setup(struct rt2860_softc *); 138 void rt2860_set_leds(struct rt2860_softc *, uint16_t); 139 void rt2860_set_gp_timer(struct rt2860_softc *, int); 140 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 141 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 142 void rt2860_updateslot(struct ieee80211com *); 143 void rt2860_updateprot(struct ieee80211com *); 144 void rt2860_updateedca(struct ieee80211com *); 145 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 146 struct ieee80211_key *); 147 void rt2860_delete_key(struct ieee80211com *, 148 struct ieee80211_node *, struct ieee80211_key *); 149 #if NBPFILTER > 0 150 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 151 #endif 152 const char * rt2860_get_rf(uint8_t); 153 int rt2860_read_eeprom(struct rt2860_softc *); 154 int rt2860_bbp_init(struct rt2860_softc *); 155 int rt2860_txrx_enable(struct rt2860_softc *); 156 int rt2860_init(struct ifnet *); 157 void rt2860_stop(struct ifnet *, int); 158 int rt2860_load_microcode(struct rt2860_softc *); 159 void rt2860_calib(struct rt2860_softc *); 160 void rt3090_set_rx_antenna(struct rt2860_softc *, int); 161 void rt2860_switch_chan(struct rt2860_softc *, 162 struct ieee80211_channel *); 163 #ifndef IEEE80211_STA_ONLY 164 int rt2860_setup_beacon(struct rt2860_softc *); 165 #endif 166 void rt2860_enable_tsf_sync(struct rt2860_softc *); 167 168 static const struct { 169 uint32_t reg; 170 uint32_t val; 171 } rt2860_def_mac[] = { 172 RT2860_DEF_MAC 173 }; 174 175 static const struct { 176 uint8_t reg; 177 uint8_t val; 178 } rt2860_def_bbp[] = { 179 RT2860_DEF_BBP 180 }; 181 182 static const struct rfprog { 183 uint8_t chan; 184 uint32_t r1, r2, r3, r4; 185 } rt2860_rf2850[] = { 186 RT2860_RF2850 187 }; 188 189 struct { 190 uint8_t n, r, k; 191 } rt3090_freqs[] = { 192 RT3070_RF3052 193 }; 194 195 static const struct { 196 uint8_t reg; 197 uint8_t val; 198 } rt3090_def_rf[] = { 199 RT3070_DEF_RF 200 }; 201 202 int 203 rt2860_attach(void *xsc, int id) 204 { 205 struct rt2860_softc *sc = xsc; 206 struct ieee80211com *ic = &sc->sc_ic; 207 int qid, ntries, error; 208 uint32_t tmp; 209 210 sc->amrr.amrr_min_success_threshold = 1; 211 sc->amrr.amrr_max_success_threshold = 15; 212 213 /* wait for NIC to initialize */ 214 for (ntries = 0; ntries < 100; ntries++) { 215 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 216 if (tmp != 0 && tmp != 0xffffffff) 217 break; 218 DELAY(10); 219 } 220 if (ntries == 100) { 221 printf("%s: timeout waiting for NIC to initialize\n", 222 sc->sc_dev.dv_xname); 223 return ETIMEDOUT; 224 } 225 sc->mac_ver = tmp >> 16; 226 sc->mac_rev = tmp & 0xffff; 227 228 if (sc->mac_ver != 0x2860 && 229 (id == PCI_PRODUCT_RALINK_RT2890 || 230 id == PCI_PRODUCT_RALINK_RT2790 || 231 id == PCI_PRODUCT_AWT_RT2890)) 232 sc->sc_flags |= RT2860_ADVANCED_PS; 233 234 /* retrieve RF rev. no and various other things from EEPROM */ 235 rt2860_read_eeprom(sc); 236 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 237 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n", 238 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev, 239 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains); 240 241 /* 242 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 243 */ 244 for (qid = 0; qid < 6; qid++) { 245 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 246 printf("%s: could not allocate Tx ring %d\n", 247 sc->sc_dev.dv_xname, qid); 248 goto fail1; 249 } 250 } 251 252 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 253 printf("%s: could not allocate Rx ring\n", 254 sc->sc_dev.dv_xname); 255 goto fail1; 256 } 257 258 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 259 printf("%s: could not allocate Tx pool\n", 260 sc->sc_dev.dv_xname); 261 goto fail2; 262 } 263 264 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 265 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 266 EDCA_AC_VO : 5; 267 268 if (rootvp == NULL) 269 mountroothook_establish(rt2860_attachhook, sc); 270 else 271 rt2860_attachhook(sc); 272 273 return 0; 274 275 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 276 fail1: while (--qid >= 0) 277 rt2860_free_tx_ring(sc, &sc->txq[qid]); 278 return error; 279 } 280 281 void 282 rt2860_attachhook(void *xsc) 283 { 284 struct rt2860_softc *sc = xsc; 285 struct ieee80211com *ic = &sc->sc_ic; 286 struct ifnet *ifp = &ic->ic_if; 287 int i, error; 288 289 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize); 290 if (error != 0) { 291 printf("%s: error %d, could not read firmware file %s\n", 292 sc->sc_dev.dv_xname, error, "ral-rt2860"); 293 return; 294 } 295 296 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 297 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 298 ic->ic_state = IEEE80211_S_INIT; 299 300 /* set device capabilities */ 301 ic->ic_caps = 302 IEEE80211_C_MONITOR | /* monitor mode supported */ 303 #ifndef IEEE80211_STA_ONLY 304 IEEE80211_C_IBSS | /* IBSS mode supported */ 305 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 306 #ifdef notyet 307 IEEE80211_C_APPMGT | /* HostAP power management */ 308 #endif 309 #endif 310 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 311 IEEE80211_C_SHSLOT | /* short slot time supported */ 312 IEEE80211_C_WEP | /* s/w WEP */ 313 IEEE80211_C_RSN; /* WPA/RSN */ 314 315 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 316 /* set supported .11a rates */ 317 ic->ic_sup_rates[IEEE80211_MODE_11A] = 318 ieee80211_std_rateset_11a; 319 320 /* set supported .11a channels */ 321 for (i = 14; i < nitems(rt2860_rf2850); i++) { 322 uint8_t chan = rt2860_rf2850[i].chan; 323 ic->ic_channels[chan].ic_freq = 324 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 325 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 326 } 327 } 328 329 /* set supported .11b and .11g rates */ 330 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 331 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 332 333 /* set supported .11b and .11g channels (1 through 14) */ 334 for (i = 1; i <= 14; i++) { 335 ic->ic_channels[i].ic_freq = 336 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 337 ic->ic_channels[i].ic_flags = 338 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 339 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 340 } 341 342 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 343 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 344 345 ifp->if_softc = sc; 346 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 347 ifp->if_ioctl = rt2860_ioctl; 348 ifp->if_start = rt2860_start; 349 ifp->if_watchdog = rt2860_watchdog; 350 IFQ_SET_READY(&ifp->if_snd); 351 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 352 353 if_attach(ifp); 354 ieee80211_ifattach(ifp); 355 ic->ic_node_alloc = rt2860_node_alloc; 356 ic->ic_newassoc = rt2860_newassoc; 357 #ifndef IEEE80211_STA_ONLY 358 ic->ic_node_leave = rt2860_node_leave; 359 #endif 360 #ifndef IEEE80211_NO_HT 361 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 362 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 363 #endif 364 ic->ic_updateslot = rt2860_updateslot; 365 ic->ic_updateedca = rt2860_updateedca; 366 ic->ic_set_key = rt2860_set_key; 367 ic->ic_delete_key = rt2860_delete_key; 368 /* override state transition machine */ 369 sc->sc_newstate = ic->ic_newstate; 370 ic->ic_newstate = rt2860_newstate; 371 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status); 372 373 #if NBPFILTER > 0 374 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 375 sizeof (struct ieee80211_frame) + 64); 376 377 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 378 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 379 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 380 381 sc->sc_txtap_len = sizeof sc->sc_txtapu; 382 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 383 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 384 #endif 385 } 386 387 int 388 rt2860_detach(void *xsc) 389 { 390 struct rt2860_softc *sc = xsc; 391 struct ifnet *ifp = &sc->sc_ic.ic_if; 392 int qid; 393 394 ieee80211_ifdetach(ifp); /* free all nodes */ 395 if_detach(ifp); 396 397 for (qid = 0; qid < 6; qid++) 398 rt2860_free_tx_ring(sc, &sc->txq[qid]); 399 rt2860_free_rx_ring(sc, &sc->rxq); 400 rt2860_free_tx_pool(sc); 401 402 if (sc->ucode != NULL) 403 free(sc->ucode, M_DEVBUF); 404 405 return 0; 406 } 407 408 void 409 rt2860_suspend(void *xsc) 410 { 411 struct rt2860_softc *sc = xsc; 412 struct ifnet *ifp = &sc->sc_ic.ic_if; 413 414 if (ifp->if_flags & IFF_RUNNING) 415 rt2860_stop(ifp, 1); 416 } 417 418 void 419 rt2860_resume(void *xsc) 420 { 421 struct rt2860_softc *sc = xsc; 422 struct ifnet *ifp = &sc->sc_ic.ic_if; 423 424 if (ifp->if_flags & IFF_UP) 425 rt2860_init(ifp); 426 } 427 428 int 429 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 430 { 431 int nsegs, size, error; 432 433 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 434 435 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 436 BUS_DMA_NOWAIT, &ring->map); 437 if (error != 0) { 438 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 439 goto fail; 440 } 441 442 /* Tx rings must be 4-DWORD aligned */ 443 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 444 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 445 if (error != 0) { 446 printf("%s: could not allocate DMA memory\n", 447 sc->sc_dev.dv_xname); 448 goto fail; 449 } 450 451 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 452 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT); 453 if (error != 0) { 454 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 459 BUS_DMA_NOWAIT); 460 if (error != 0) { 461 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 462 goto fail; 463 } 464 465 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 466 467 ring->paddr = ring->map->dm_segs[0].ds_addr; 468 469 return 0; 470 471 fail: rt2860_free_tx_ring(sc, ring); 472 return error; 473 } 474 475 void 476 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 477 { 478 struct rt2860_tx_data *data; 479 int i; 480 481 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 482 if ((data = ring->data[i]) == NULL) 483 continue; /* nothing mapped in this slot */ 484 485 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 486 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 487 bus_dmamap_unload(sc->sc_dmat, data->map); 488 m_freem(data->m); 489 data->m= NULL; 490 data->ni = NULL; /* node already freed */ 491 492 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 493 ring->data[i] = NULL; 494 } 495 496 ring->queued = 0; 497 ring->cur = ring->next = 0; 498 } 499 500 void 501 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 502 { 503 struct rt2860_tx_data *data; 504 int i; 505 506 if (ring->txd != NULL) { 507 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 508 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 509 bus_dmamap_unload(sc->sc_dmat, ring->map); 510 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd, 511 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 512 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 513 } 514 if (ring->map != NULL) 515 bus_dmamap_destroy(sc->sc_dmat, ring->map); 516 517 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 518 if ((data = ring->data[i]) == NULL) 519 continue; /* nothing mapped in this slot */ 520 521 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 522 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 523 bus_dmamap_unload(sc->sc_dmat, data->map); 524 m_freem(data->m); 525 526 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 527 } 528 } 529 530 /* 531 * Allocate a pool of TX Wireless Information blocks. 532 */ 533 int 534 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 535 { 536 caddr_t vaddr; 537 bus_addr_t paddr; 538 int i, nsegs, size, error; 539 540 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 541 542 /* init data_pool early in case of failure.. */ 543 SLIST_INIT(&sc->data_pool); 544 545 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 546 BUS_DMA_NOWAIT, &sc->txwi_map); 547 if (error != 0) { 548 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 549 goto fail; 550 } 551 552 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 553 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 554 if (error != 0) { 555 printf("%s: could not allocate DMA memory\n", 556 sc->sc_dev.dv_xname); 557 goto fail; 558 } 559 560 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 561 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 562 if (error != 0) { 563 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 564 goto fail; 565 } 566 567 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 568 size, NULL, BUS_DMA_NOWAIT); 569 if (error != 0) { 570 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 571 goto fail; 572 } 573 574 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 575 BUS_DMASYNC_PREWRITE); 576 577 vaddr = sc->txwi_vaddr; 578 paddr = sc->txwi_map->dm_segs[0].ds_addr; 579 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 580 struct rt2860_tx_data *data = &sc->data[i]; 581 582 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 583 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 584 &data->map); 585 if (error != 0) { 586 printf("%s: could not create DMA map\n", 587 sc->sc_dev.dv_xname); 588 goto fail; 589 } 590 data->txwi = (struct rt2860_txwi *)vaddr; 591 data->paddr = paddr; 592 vaddr += RT2860_TXWI_DMASZ; 593 paddr += RT2860_TXWI_DMASZ; 594 595 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 596 } 597 598 return 0; 599 600 fail: rt2860_free_tx_pool(sc); 601 return error; 602 } 603 604 void 605 rt2860_free_tx_pool(struct rt2860_softc *sc) 606 { 607 if (sc->txwi_vaddr != NULL) { 608 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 609 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 610 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 611 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 612 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 613 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 614 } 615 if (sc->txwi_map != NULL) 616 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 617 618 while (!SLIST_EMPTY(&sc->data_pool)) { 619 struct rt2860_tx_data *data; 620 data = SLIST_FIRST(&sc->data_pool); 621 bus_dmamap_destroy(sc->sc_dmat, data->map); 622 SLIST_REMOVE_HEAD(&sc->data_pool, next); 623 } 624 } 625 626 int 627 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 628 { 629 int i, nsegs, size, error; 630 631 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 632 633 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 634 BUS_DMA_NOWAIT, &ring->map); 635 if (error != 0) { 636 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 637 goto fail; 638 } 639 640 /* Rx ring must be 4-DWORD aligned */ 641 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 642 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 643 if (error != 0) { 644 printf("%s: could not allocate DMA memory\n", 645 sc->sc_dev.dv_xname); 646 goto fail; 647 } 648 649 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 650 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT); 651 if (error != 0) { 652 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 653 goto fail; 654 } 655 656 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 657 BUS_DMA_NOWAIT); 658 if (error != 0) { 659 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 660 goto fail; 661 } 662 663 ring->paddr = ring->map->dm_segs[0].ds_addr; 664 665 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 666 struct rt2860_rx_data *data = &ring->data[i]; 667 struct rt2860_rxd *rxd = &ring->rxd[i]; 668 669 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 670 0, BUS_DMA_NOWAIT, &data->map); 671 if (error != 0) { 672 printf("%s: could not create DMA map\n", 673 sc->sc_dev.dv_xname); 674 goto fail; 675 } 676 677 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 678 if (data->m == NULL) { 679 printf("%s: could not allocate Rx mbuf\n", 680 sc->sc_dev.dv_xname); 681 error = ENOBUFS; 682 goto fail; 683 } 684 685 error = bus_dmamap_load(sc->sc_dmat, data->map, 686 mtod(data->m, void *), MCLBYTES, NULL, 687 BUS_DMA_READ | BUS_DMA_NOWAIT); 688 if (error != 0) { 689 printf("%s: could not load DMA map\n", 690 sc->sc_dev.dv_xname); 691 goto fail; 692 } 693 694 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 695 rxd->sdl0 = htole16(MCLBYTES); 696 } 697 698 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 699 700 return 0; 701 702 fail: rt2860_free_rx_ring(sc, ring); 703 return error; 704 } 705 706 void 707 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 708 { 709 int i; 710 711 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 712 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 713 714 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 715 BUS_DMASYNC_PREWRITE); 716 717 ring->cur = 0; 718 } 719 720 void 721 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 722 { 723 int i; 724 725 if (ring->rxd != NULL) { 726 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 727 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 728 bus_dmamap_unload(sc->sc_dmat, ring->map); 729 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd, 730 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 731 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 732 } 733 if (ring->map != NULL) 734 bus_dmamap_destroy(sc->sc_dmat, ring->map); 735 736 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 737 struct rt2860_rx_data *data = &ring->data[i]; 738 739 if (data->m != NULL) { 740 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 741 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 742 bus_dmamap_unload(sc->sc_dmat, data->map); 743 m_freem(data->m); 744 } 745 if (data->map != NULL) 746 bus_dmamap_destroy(sc->sc_dmat, data->map); 747 } 748 } 749 750 struct ieee80211_node * 751 rt2860_node_alloc(struct ieee80211com *ic) 752 { 753 return malloc(sizeof (struct rt2860_node), M_DEVBUF, 754 M_NOWAIT | M_ZERO); 755 } 756 757 int 758 rt2860_media_change(struct ifnet *ifp) 759 { 760 struct rt2860_softc *sc = ifp->if_softc; 761 struct ieee80211com *ic = &sc->sc_ic; 762 uint8_t rate, ridx; 763 int error; 764 765 error = ieee80211_media_change(ifp); 766 if (error != ENETRESET) 767 return error; 768 769 if (ic->ic_fixed_rate != -1) { 770 rate = ic->ic_sup_rates[ic->ic_curmode]. 771 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 772 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 773 if (rt2860_rates[ridx].rate == rate) 774 break; 775 sc->fixed_ridx = ridx; 776 } 777 778 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 779 (IFF_UP | IFF_RUNNING)) { 780 rt2860_stop(ifp, 0); 781 rt2860_init(ifp); 782 } 783 return 0; 784 } 785 786 void 787 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 788 { 789 struct rt2860_softc *sc = arg; 790 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 791 792 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 793 } 794 795 void 796 rt2860_updatestats(struct rt2860_softc *sc) 797 { 798 struct ieee80211com *ic = &sc->sc_ic; 799 800 #ifndef IEEE80211_STA_ONLY 801 /* 802 * In IBSS or HostAP modes (when the hardware sends beacons), the 803 * MAC can run into a livelock and start sending CTS-to-self frames 804 * like crazy if protection is enabled. Fortunately, we can detect 805 * when such a situation occurs and reset the MAC. 806 */ 807 if (ic->ic_curmode != IEEE80211_M_STA) { 808 /* check if we're in a livelock situation.. */ 809 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 810 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 811 /* ..and reset MAC/BBP for a while.. */ 812 DPRINTF(("CTS-to-self livelock detected\n")); 813 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 814 RAL_BARRIER_WRITE(sc); 815 DELAY(1); 816 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 817 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 818 } 819 } 820 #endif 821 if (ic->ic_opmode == IEEE80211_M_STA) 822 rt2860_iter_func(sc, ic->ic_bss); 823 #ifndef IEEE80211_STA_ONLY 824 else 825 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc); 826 #endif 827 } 828 829 void 830 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 831 { 832 struct rt2860_softc *sc = ic->ic_softc; 833 struct rt2860_node *rn = (void *)ni; 834 struct ieee80211_rateset *rs = &ni->ni_rates; 835 uint8_t rate, wcid = 0; 836 int ridx, i, j; 837 838 if (isnew && ni->ni_associd != 0) { 839 /* only interested in true associations */ 840 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 841 842 /* init WCID table entry */ 843 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 844 ni->ni_macaddr, IEEE80211_ADDR_LEN); 845 } 846 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 847 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 848 849 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 850 /* start at lowest available bit-rate, AMRR will raise */ 851 ni->ni_txrate = 0; 852 853 for (i = 0; i < rs->rs_nrates; i++) { 854 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 855 /* convert 802.11 rate to hardware rate index */ 856 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 857 if (rt2860_rates[ridx].rate == rate) 858 break; 859 rn->ridx[i] = ridx; 860 /* determine rate of control response frames */ 861 for (j = i; j >= 0; j--) { 862 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 863 rt2860_rates[rn->ridx[i]].phy == 864 rt2860_rates[rn->ridx[j]].phy) 865 break; 866 } 867 if (j >= 0) { 868 rn->ctl_ridx[i] = rn->ridx[j]; 869 } else { 870 /* no basic rate found, use mandatory one */ 871 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 872 } 873 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 874 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 875 } 876 } 877 878 #ifndef IEEE80211_STA_ONLY 879 void 880 rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni) 881 { 882 struct rt2860_softc *sc = ic->ic_softc; 883 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 884 885 /* clear Rx WCID search table entry */ 886 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 887 } 888 #endif 889 890 #ifndef IEEE80211_NO_HT 891 int 892 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 893 uint8_t tid) 894 { 895 struct rt2860_softc *sc = ic->ic_softc; 896 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 897 uint32_t tmp; 898 899 /* update BA session mask */ 900 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 901 tmp |= (1 << tid) << 16; 902 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 903 return 0; 904 } 905 906 void 907 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 908 uint8_t tid) 909 { 910 struct rt2860_softc *sc = ic->ic_softc; 911 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 912 uint32_t tmp; 913 914 /* update BA session mask */ 915 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 916 tmp &= ~((1 << tid) << 16); 917 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 918 } 919 #endif 920 921 int 922 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 923 { 924 struct rt2860_softc *sc = ic->ic_if.if_softc; 925 enum ieee80211_state ostate; 926 uint32_t tmp; 927 928 ostate = ic->ic_state; 929 930 if (ostate == IEEE80211_S_RUN) { 931 /* turn link LED off */ 932 rt2860_set_leds(sc, RT2860_LED_RADIO); 933 } 934 935 switch (nstate) { 936 case IEEE80211_S_INIT: 937 if (ostate == IEEE80211_S_RUN) { 938 /* abort TSF synchronization */ 939 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 940 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 941 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 942 RT2860_TBTT_TIMER_EN)); 943 } 944 rt2860_set_gp_timer(sc, 0); 945 break; 946 947 case IEEE80211_S_SCAN: 948 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 949 if (ostate != IEEE80211_S_SCAN) 950 rt2860_set_gp_timer(sc, 150); 951 break; 952 953 case IEEE80211_S_AUTH: 954 case IEEE80211_S_ASSOC: 955 rt2860_set_gp_timer(sc, 0); 956 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 957 break; 958 959 case IEEE80211_S_RUN: 960 rt2860_set_gp_timer(sc, 0); 961 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 962 963 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 964 rt2860_updateslot(ic); 965 rt2860_enable_mrr(sc); 966 rt2860_set_txpreamble(sc); 967 rt2860_set_basicrates(sc); 968 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 969 } 970 971 #ifndef IEEE80211_STA_ONLY 972 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 973 ic->ic_opmode == IEEE80211_M_IBSS) 974 (void)rt2860_setup_beacon(sc); 975 #endif 976 977 if (ic->ic_opmode == IEEE80211_M_STA) { 978 /* fake a join to init the tx rate */ 979 rt2860_newassoc(ic, ic->ic_bss, 1); 980 } 981 982 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 983 rt2860_enable_tsf_sync(sc); 984 rt2860_set_gp_timer(sc, 500); 985 } 986 987 /* turn link LED on */ 988 rt2860_set_leds(sc, RT2860_LED_RADIO | 989 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 990 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 991 break; 992 } 993 994 return sc->sc_newstate(ic, nstate, arg); 995 } 996 997 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 998 uint16_t 999 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1000 { 1001 uint32_t tmp; 1002 uint16_t reg; 1003 int ntries; 1004 1005 addr *= 2; 1006 /*- 1007 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1008 * DATA0: F E D C 1009 * DATA1: B A 9 8 1010 * DATA2: 7 6 5 4 1011 * DATA3: 3 2 1 0 1012 */ 1013 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1014 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1015 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1016 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1017 for (ntries = 0; ntries < 500; ntries++) { 1018 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1019 if (!(tmp & RT3070_EFSROM_KICK)) 1020 break; 1021 DELAY(2); 1022 } 1023 if (ntries == 500) 1024 return 0xffff; 1025 1026 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1027 return 0xffff; /* address not found */ 1028 1029 /* determine to which 32-bit register our 16-bit word belongs */ 1030 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1031 tmp = RAL_READ(sc, reg); 1032 1033 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1034 } 1035 1036 /* 1037 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1038 * 93C66 or 93C86). 1039 */ 1040 uint16_t 1041 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1042 { 1043 uint32_t tmp; 1044 uint16_t val; 1045 int n; 1046 1047 /* clock C once before the first command */ 1048 RT2860_EEPROM_CTL(sc, 0); 1049 1050 RT2860_EEPROM_CTL(sc, RT2860_S); 1051 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1052 RT2860_EEPROM_CTL(sc, RT2860_S); 1053 1054 /* write start bit (1) */ 1055 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1056 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1057 1058 /* write READ opcode (10) */ 1059 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1060 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1061 RT2860_EEPROM_CTL(sc, RT2860_S); 1062 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1063 1064 /* write address (A5-A0 or A7-A0) */ 1065 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1066 for (; n >= 0; n--) { 1067 RT2860_EEPROM_CTL(sc, RT2860_S | 1068 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1069 RT2860_EEPROM_CTL(sc, RT2860_S | 1070 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1071 } 1072 1073 RT2860_EEPROM_CTL(sc, RT2860_S); 1074 1075 /* read data Q15-Q0 */ 1076 val = 0; 1077 for (n = 15; n >= 0; n--) { 1078 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1079 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1080 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1081 RT2860_EEPROM_CTL(sc, RT2860_S); 1082 } 1083 1084 RT2860_EEPROM_CTL(sc, 0); 1085 1086 /* clear Chip Select and clock C */ 1087 RT2860_EEPROM_CTL(sc, RT2860_S); 1088 RT2860_EEPROM_CTL(sc, 0); 1089 RT2860_EEPROM_CTL(sc, RT2860_C); 1090 1091 return val; 1092 } 1093 1094 static __inline uint16_t 1095 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1096 { 1097 /* either eFUSE ROM or EEPROM */ 1098 return sc->sc_srom_read(sc, addr); 1099 } 1100 1101 void 1102 rt2860_intr_coherent(struct rt2860_softc *sc) 1103 { 1104 uint32_t tmp; 1105 1106 /* DMA finds data coherent event when checking the DDONE bit */ 1107 1108 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1109 1110 /* restart DMA engine */ 1111 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1112 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1113 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1114 1115 (void)rt2860_txrx_enable(sc); 1116 } 1117 1118 void 1119 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1120 { 1121 struct ifnet *ifp = &sc->sc_ic.ic_if; 1122 struct ieee80211_amrr_node *amn; 1123 uint32_t stat; 1124 uint8_t wcid, mcs, pid; 1125 1126 /* drain Tx status FIFO (maxsize = 16) */ 1127 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1128 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1129 1130 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1131 1132 /* if no ACK was requested, no feedback is available */ 1133 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1134 continue; 1135 1136 /* update per-STA AMRR stats */ 1137 amn = &sc->amn[wcid]; 1138 amn->amn_txcnt++; 1139 if (stat & RT2860_TXQ_OK) { 1140 /* 1141 * Check if there were retries, ie if the Tx success 1142 * rate is different from the requested rate. Note 1143 * that it works only because we do not allow rate 1144 * fallback from OFDM to CCK. 1145 */ 1146 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1147 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1148 if (mcs + 1 != pid) 1149 amn->amn_retrycnt++; 1150 } else { 1151 amn->amn_retrycnt++; 1152 ifp->if_oerrors++; 1153 } 1154 } 1155 } 1156 1157 void 1158 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1159 { 1160 struct ieee80211com *ic = &sc->sc_ic; 1161 struct ifnet *ifp = &ic->ic_if; 1162 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1163 uint32_t hw; 1164 1165 rt2860_drain_stats_fifo(sc); 1166 1167 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1168 while (ring->next != hw) { 1169 struct rt2860_tx_data *data = ring->data[ring->next]; 1170 1171 if (data != NULL) { 1172 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1173 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1174 bus_dmamap_unload(sc->sc_dmat, data->map); 1175 m_freem(data->m); 1176 data->m= NULL; 1177 ieee80211_release_node(ic, data->ni); 1178 data->ni = NULL; 1179 1180 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1181 ring->data[ring->next] = NULL; 1182 1183 ifp->if_opackets++; 1184 } 1185 ring->queued--; 1186 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1187 } 1188 1189 sc->sc_tx_timer = 0; 1190 if (ring->queued < RT2860_TX_RING_COUNT) 1191 sc->qfullmsk &= ~(1 << qid); 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 rt2860_start(ifp); 1194 } 1195 1196 /* 1197 * Return the Rx chain with the highest RSSI for a given frame. 1198 */ 1199 static __inline uint8_t 1200 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1201 { 1202 uint8_t rxchain = 0; 1203 1204 if (sc->nrxchains > 1) { 1205 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1206 rxchain = 1; 1207 if (sc->nrxchains > 2) 1208 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1209 rxchain = 2; 1210 } 1211 return rxchain; 1212 } 1213 1214 void 1215 rt2860_rx_intr(struct rt2860_softc *sc) 1216 { 1217 struct ieee80211com *ic = &sc->sc_ic; 1218 struct ifnet *ifp = &ic->ic_if; 1219 struct ieee80211_frame *wh; 1220 struct ieee80211_rxinfo rxi; 1221 struct ieee80211_node *ni; 1222 struct mbuf *m, *m1; 1223 uint32_t hw; 1224 uint8_t ant, rssi; 1225 int error; 1226 #if NBPFILTER > 0 1227 struct rt2860_rx_radiotap_header *tap; 1228 struct mbuf mb; 1229 uint16_t phy; 1230 #endif 1231 1232 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1233 while (sc->rxq.cur != hw) { 1234 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1235 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1236 struct rt2860_rxwi *rxwi; 1237 1238 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1239 sc->rxq.cur * sizeof (struct rt2860_rxd), 1240 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1241 1242 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1243 DPRINTF(("RXD DDONE bit not set!\n")); 1244 break; /* should not happen */ 1245 } 1246 1247 if (__predict_false(rxd->flags & 1248 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1249 ifp->if_ierrors++; 1250 goto skip; 1251 } 1252 1253 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1254 /* report MIC failures to net80211 for TKIP */ 1255 ic->ic_stats.is_rx_locmicfail++; 1256 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1257 ifp->if_ierrors++; 1258 goto skip; 1259 } 1260 1261 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1262 if (__predict_false(m1 == NULL)) { 1263 ifp->if_ierrors++; 1264 goto skip; 1265 } 1266 1267 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1268 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1269 bus_dmamap_unload(sc->sc_dmat, data->map); 1270 1271 error = bus_dmamap_load(sc->sc_dmat, data->map, 1272 mtod(m1, void *), MCLBYTES, NULL, 1273 BUS_DMA_READ | BUS_DMA_NOWAIT); 1274 if (__predict_false(error != 0)) { 1275 m_freem(m1); 1276 1277 /* try to reload the old mbuf */ 1278 error = bus_dmamap_load(sc->sc_dmat, data->map, 1279 mtod(data->m, void *), MCLBYTES, NULL, 1280 BUS_DMA_READ | BUS_DMA_NOWAIT); 1281 if (__predict_false(error != 0)) { 1282 panic("%s: could not load old rx mbuf", 1283 sc->sc_dev.dv_xname); 1284 } 1285 /* physical address may have changed */ 1286 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1287 ifp->if_ierrors++; 1288 goto skip; 1289 } 1290 1291 /* 1292 * New mbuf successfully loaded, update Rx ring and continue 1293 * processing. 1294 */ 1295 m = data->m; 1296 data->m = m1; 1297 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1298 1299 rxwi = mtod(m, struct rt2860_rxwi *); 1300 1301 /* finalize mbuf */ 1302 m->m_pkthdr.rcvif = ifp; 1303 m->m_data = (caddr_t)(rxwi + 1); 1304 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff; 1305 1306 wh = mtod(m, struct ieee80211_frame *); 1307 rxi.rxi_flags = 0; 1308 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1309 /* frame is decrypted by hardware */ 1310 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1311 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1312 } 1313 1314 /* HW may insert 2 padding bytes after 802.11 header */ 1315 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1316 u_int hdrlen = ieee80211_get_hdrlen(wh); 1317 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1318 m->m_data += 2; 1319 wh = mtod(m, struct ieee80211_frame *); 1320 } 1321 1322 ant = rt2860_maxrssi_chain(sc, rxwi); 1323 rssi = rxwi->rssi[ant]; 1324 1325 #if NBPFILTER > 0 1326 if (__predict_true(sc->sc_drvbpf == NULL)) 1327 goto skipbpf; 1328 1329 tap = &sc->sc_rxtap; 1330 tap->wr_flags = 0; 1331 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1332 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1333 tap->wr_antsignal = rssi; 1334 tap->wr_antenna = ant; 1335 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1336 tap->wr_rate = 2; /* in case it can't be found below */ 1337 phy = letoh16(rxwi->phy); 1338 switch (phy & RT2860_PHY_MODE) { 1339 case RT2860_PHY_CCK: 1340 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1341 case 0: tap->wr_rate = 2; break; 1342 case 1: tap->wr_rate = 4; break; 1343 case 2: tap->wr_rate = 11; break; 1344 case 3: tap->wr_rate = 22; break; 1345 } 1346 if (phy & RT2860_PHY_SHPRE) 1347 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1348 break; 1349 case RT2860_PHY_OFDM: 1350 switch (phy & RT2860_PHY_MCS) { 1351 case 0: tap->wr_rate = 12; break; 1352 case 1: tap->wr_rate = 18; break; 1353 case 2: tap->wr_rate = 24; break; 1354 case 3: tap->wr_rate = 36; break; 1355 case 4: tap->wr_rate = 48; break; 1356 case 5: tap->wr_rate = 72; break; 1357 case 6: tap->wr_rate = 96; break; 1358 case 7: tap->wr_rate = 108; break; 1359 } 1360 break; 1361 } 1362 mb.m_data = (caddr_t)tap; 1363 mb.m_len = sc->sc_rxtap_len; 1364 mb.m_next = m; 1365 mb.m_nextpkt = NULL; 1366 mb.m_type = 0; 1367 mb.m_flags = 0; 1368 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1369 skipbpf: 1370 #endif 1371 /* grab a reference to the source node */ 1372 ni = ieee80211_find_rxnode(ic, wh); 1373 1374 /* send the frame to the 802.11 layer */ 1375 rxi.rxi_rssi = rssi; 1376 rxi.rxi_tstamp = 0; /* unused */ 1377 ieee80211_input(ifp, m, ni, &rxi); 1378 1379 /* node is no longer needed */ 1380 ieee80211_release_node(ic, ni); 1381 1382 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1383 1384 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1385 sc->rxq.cur * sizeof (struct rt2860_rxd), 1386 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1387 1388 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1389 } 1390 1391 /* tell HW what we have processed */ 1392 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1393 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1394 } 1395 1396 void 1397 rt2860_tbtt_intr(struct rt2860_softc *sc) 1398 { 1399 struct ieee80211com *ic = &sc->sc_ic; 1400 1401 #ifndef IEEE80211_STA_ONLY 1402 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1403 /* one less beacon until next DTIM */ 1404 if (ic->ic_dtim_count == 0) 1405 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1406 else 1407 ic->ic_dtim_count--; 1408 1409 /* update dynamic parts of beacon */ 1410 rt2860_setup_beacon(sc); 1411 1412 /* flush buffered multicast frames */ 1413 if (ic->ic_dtim_count == 0) 1414 ieee80211_notify_dtim(ic); 1415 } 1416 #endif 1417 /* check if protection mode has changed */ 1418 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1419 rt2860_updateprot(ic); 1420 sc->sc_ic_flags = ic->ic_flags; 1421 } 1422 } 1423 1424 void 1425 rt2860_gp_intr(struct rt2860_softc *sc) 1426 { 1427 struct ieee80211com *ic = &sc->sc_ic; 1428 1429 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1430 1431 if (ic->ic_state == IEEE80211_S_SCAN) 1432 ieee80211_next_scan(&ic->ic_if); 1433 else if (ic->ic_state == IEEE80211_S_RUN) 1434 rt2860_updatestats(sc); 1435 } 1436 1437 int 1438 rt2860_intr(void *arg) 1439 { 1440 struct rt2860_softc *sc = arg; 1441 uint32_t r; 1442 1443 r = RAL_READ(sc, RT2860_INT_STATUS); 1444 if (__predict_false(r == 0xffffffff)) 1445 return 0; /* device likely went away */ 1446 if (r == 0) 1447 return 0; /* not for us */ 1448 1449 /* acknowledge interrupts */ 1450 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1451 1452 if (r & RT2860_TX_RX_COHERENT) 1453 rt2860_intr_coherent(sc); 1454 1455 if (r & RT2860_MAC_INT_2) /* TX status */ 1456 rt2860_drain_stats_fifo(sc); 1457 1458 if (r & RT2860_TX_DONE_INT5) 1459 rt2860_tx_intr(sc, 5); 1460 1461 if (r & RT2860_RX_DONE_INT) 1462 rt2860_rx_intr(sc); 1463 1464 if (r & RT2860_TX_DONE_INT4) 1465 rt2860_tx_intr(sc, 4); 1466 1467 if (r & RT2860_TX_DONE_INT3) 1468 rt2860_tx_intr(sc, 3); 1469 1470 if (r & RT2860_TX_DONE_INT2) 1471 rt2860_tx_intr(sc, 2); 1472 1473 if (r & RT2860_TX_DONE_INT1) 1474 rt2860_tx_intr(sc, 1); 1475 1476 if (r & RT2860_TX_DONE_INT0) 1477 rt2860_tx_intr(sc, 0); 1478 1479 if (r & RT2860_MAC_INT_0) /* TBTT */ 1480 rt2860_tbtt_intr(sc); 1481 1482 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1483 /* TBD wakeup */; 1484 1485 if (r & RT2860_MAC_INT_4) /* GP timer */ 1486 rt2860_gp_intr(sc); 1487 1488 return 1; 1489 } 1490 1491 int 1492 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1493 { 1494 struct ieee80211com *ic = &sc->sc_ic; 1495 struct rt2860_node *rn = (void *)ni; 1496 struct rt2860_tx_ring *ring; 1497 struct rt2860_tx_data *data; 1498 struct rt2860_txd *txd; 1499 struct rt2860_txwi *txwi; 1500 struct ieee80211_frame *wh; 1501 struct mbuf *m1; 1502 bus_dma_segment_t *seg; 1503 u_int hdrlen; 1504 uint16_t qos, dur; 1505 uint8_t type, qsel, mcs, pid, tid, qid; 1506 int nsegs, ntxds, hasqos, ridx, ctl_ridx, error; 1507 1508 /* the data pool contains at least one element, pick the first */ 1509 data = SLIST_FIRST(&sc->data_pool); 1510 1511 wh = mtod(m, struct ieee80211_frame *); 1512 hdrlen = ieee80211_get_hdrlen(wh); 1513 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1514 1515 if ((hasqos = ieee80211_has_qos(wh))) { 1516 qos = ieee80211_get_qos(wh); 1517 tid = qos & IEEE80211_QOS_TID; 1518 qid = ieee80211_up_to_ac(ic, tid); 1519 } else { 1520 tid = 0; 1521 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1522 sc->mgtqid : EDCA_AC_BE; 1523 } 1524 ring = &sc->txq[qid]; 1525 1526 /* pickup a rate index */ 1527 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1528 type != IEEE80211_FC0_TYPE_DATA) { 1529 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1530 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1531 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1532 } else if (ic->ic_fixed_rate != -1) { 1533 ridx = sc->fixed_ridx; 1534 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1535 } else { 1536 ridx = rn->ridx[ni->ni_txrate]; 1537 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1538 } 1539 1540 /* get MCS code from rate index */ 1541 mcs = rt2860_rates[ridx].mcs; 1542 1543 /* setup TX Wireless Information */ 1544 txwi = data->txwi; 1545 txwi->flags = 0; 1546 /* let HW generate seq numbers for non-QoS frames */ 1547 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1548 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1549 txwi->len = htole16(m->m_pkthdr.len); 1550 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1551 txwi->phy = htole16(RT2860_PHY_CCK); 1552 if (ridx != RT2860_RIDX_CCK1 && 1553 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1554 mcs |= RT2860_PHY_SHPRE; 1555 } else 1556 txwi->phy = htole16(RT2860_PHY_OFDM); 1557 txwi->phy |= htole16(mcs); 1558 1559 /* 1560 * We store the MCS code into the driver-private PacketID field. 1561 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1562 * that we know at which initial rate the frame was transmitted. 1563 * We add 1 to the MCS code because setting the PacketID field to 1564 * 0 means that we don't want feedback in TX_STAT_FIFO. 1565 */ 1566 pid = (mcs + 1) & 0xf; 1567 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1568 1569 /* check if RTS/CTS or CTS-to-self protection is required */ 1570 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1571 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1572 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1573 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1574 txwi->txop = RT2860_TX_TXOP_HT; 1575 else 1576 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1577 1578 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1579 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 1580 IEEE80211_QOS_ACK_POLICY_NOACK)) { 1581 txwi->xflags |= RT2860_TX_ACK; 1582 1583 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1584 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1585 else 1586 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1587 *(uint16_t *)wh->i_dur = htole16(dur); 1588 } 1589 #ifndef IEEE80211_STA_ONLY 1590 /* ask MAC to insert timestamp into probe responses */ 1591 if ((wh->i_fc[0] & 1592 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1593 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1594 /* NOTE: beacons do not pass through tx_data() */ 1595 txwi->flags |= RT2860_TX_TS; 1596 #endif 1597 1598 #if NBPFILTER > 0 1599 if (__predict_false(sc->sc_drvbpf != NULL)) { 1600 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1601 struct mbuf mb; 1602 1603 tap->wt_flags = 0; 1604 tap->wt_rate = rt2860_rates[ridx].rate; 1605 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1606 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1607 tap->wt_hwqueue = qid; 1608 if (mcs & RT2860_PHY_SHPRE) 1609 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1610 1611 mb.m_data = (caddr_t)tap; 1612 mb.m_len = sc->sc_txtap_len; 1613 mb.m_next = m; 1614 mb.m_nextpkt = NULL; 1615 mb.m_type = 0; 1616 mb.m_flags = 0; 1617 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1618 } 1619 #endif 1620 1621 /* copy and trim 802.11 header */ 1622 memcpy(txwi + 1, wh, hdrlen); 1623 m_adj(m, hdrlen); 1624 1625 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1626 BUS_DMA_NOWAIT); 1627 if (__predict_false(error != 0 && error != EFBIG)) { 1628 printf("%s: can't map mbuf (error %d)\n", 1629 sc->sc_dev.dv_xname, error); 1630 m_freem(m); 1631 return error; 1632 } 1633 if (__predict_true(error == 0)) { 1634 /* determine how many TXDs are required */ 1635 ntxds = 1 + (data->map->dm_nsegs / 2); 1636 1637 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1638 /* not enough free TXDs, force mbuf defrag */ 1639 bus_dmamap_unload(sc->sc_dmat, data->map); 1640 error = EFBIG; 1641 } 1642 } 1643 if (__predict_false(error != 0)) { 1644 /* too many fragments, linearize */ 1645 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1646 if (m1 == NULL) { 1647 m_freem(m); 1648 return ENOBUFS; 1649 } 1650 if (m->m_pkthdr.len > MHLEN) { 1651 MCLGET(m1, M_DONTWAIT); 1652 if (!(m1->m_flags & M_EXT)) { 1653 m_freem(m); 1654 m_freem(m1); 1655 return ENOBUFS; 1656 } 1657 } 1658 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1659 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1660 m_freem(m); 1661 m = m1; 1662 1663 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1664 BUS_DMA_NOWAIT); 1665 if (__predict_false(error != 0)) { 1666 printf("%s: can't map mbuf (error %d)\n", 1667 sc->sc_dev.dv_xname, error); 1668 m_freem(m); 1669 return error; 1670 } 1671 1672 /* determine how many TXDs are now required */ 1673 ntxds = 1 + (data->map->dm_nsegs / 2); 1674 1675 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1676 /* this is a hopeless case, drop the mbuf! */ 1677 bus_dmamap_unload(sc->sc_dmat, data->map); 1678 m_freem(m); 1679 return ENOBUFS; 1680 } 1681 } 1682 1683 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1684 1685 /* first segment is TXWI + 802.11 header */ 1686 txd = &ring->txd[ring->cur]; 1687 txd->sdp0 = htole32(data->paddr); 1688 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1689 txd->flags = qsel; 1690 1691 /* setup payload segments */ 1692 seg = data->map->dm_segs; 1693 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1694 txd->sdp1 = htole32(seg->ds_addr); 1695 txd->sdl1 = htole16(seg->ds_len); 1696 seg++; 1697 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1698 /* grab a new Tx descriptor */ 1699 txd = &ring->txd[ring->cur]; 1700 txd->sdp0 = htole32(seg->ds_addr); 1701 txd->sdl0 = htole16(seg->ds_len); 1702 txd->flags = qsel; 1703 seg++; 1704 } 1705 /* finalize last segment */ 1706 if (nsegs > 0) { 1707 txd->sdp1 = htole32(seg->ds_addr); 1708 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1709 } else { 1710 txd->sdl0 |= htole16(RT2860_TX_LS0); 1711 txd->sdl1 = 0; 1712 } 1713 1714 /* remove from the free pool and link it into the SW Tx slot */ 1715 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1716 data->m = m; 1717 data->ni = ni; 1718 ring->data[ring->cur] = data; 1719 1720 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1721 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1722 BUS_DMASYNC_PREWRITE); 1723 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1724 BUS_DMASYNC_PREWRITE); 1725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1726 BUS_DMASYNC_PREWRITE); 1727 1728 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1729 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1730 1731 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1732 ring->queued += ntxds; 1733 if (ring->queued >= RT2860_TX_RING_COUNT) 1734 sc->qfullmsk |= 1 << qid; 1735 1736 /* kick Tx */ 1737 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1738 1739 return 0; 1740 } 1741 1742 void 1743 rt2860_start(struct ifnet *ifp) 1744 { 1745 struct rt2860_softc *sc = ifp->if_softc; 1746 struct ieee80211com *ic = &sc->sc_ic; 1747 struct ieee80211_node *ni; 1748 struct mbuf *m; 1749 1750 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1751 return; 1752 1753 for (;;) { 1754 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1755 ifp->if_flags |= IFF_OACTIVE; 1756 break; 1757 } 1758 /* send pending management frames first */ 1759 IF_DEQUEUE(&ic->ic_mgtq, m); 1760 if (m != NULL) { 1761 ni = (void *)m->m_pkthdr.rcvif; 1762 goto sendit; 1763 } 1764 if (ic->ic_state != IEEE80211_S_RUN) 1765 break; 1766 1767 /* send buffered frames for power-save mode */ 1768 IF_DEQUEUE(&ic->ic_pwrsaveq, m); 1769 if (m != NULL) { 1770 ni = (void *)m->m_pkthdr.rcvif; 1771 goto sendit; 1772 } 1773 1774 /* encapsulate and send data frames */ 1775 IFQ_DEQUEUE(&ifp->if_snd, m); 1776 if (m == NULL) 1777 break; 1778 #if NBPFILTER > 0 1779 if (ifp->if_bpf != NULL) 1780 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1781 #endif 1782 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1783 continue; 1784 sendit: 1785 #if NBPFILTER > 0 1786 if (ic->ic_rawbpf != NULL) 1787 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1788 #endif 1789 if (rt2860_tx(sc, m, ni) != 0) { 1790 ieee80211_release_node(ic, ni); 1791 ifp->if_oerrors++; 1792 continue; 1793 } 1794 1795 sc->sc_tx_timer = 5; 1796 ifp->if_timer = 1; 1797 } 1798 } 1799 1800 void 1801 rt2860_watchdog(struct ifnet *ifp) 1802 { 1803 struct rt2860_softc *sc = ifp->if_softc; 1804 1805 ifp->if_timer = 0; 1806 1807 if (sc->sc_tx_timer > 0) { 1808 if (--sc->sc_tx_timer == 0) { 1809 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1810 rt2860_stop(ifp, 0); 1811 rt2860_init(ifp); 1812 ifp->if_oerrors++; 1813 return; 1814 } 1815 ifp->if_timer = 1; 1816 } 1817 1818 ieee80211_watchdog(ifp); 1819 } 1820 1821 int 1822 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1823 { 1824 struct rt2860_softc *sc = ifp->if_softc; 1825 struct ieee80211com *ic = &sc->sc_ic; 1826 struct ifaddr *ifa; 1827 struct ifreq *ifr; 1828 int s, error = 0; 1829 1830 s = splnet(); 1831 1832 switch (cmd) { 1833 case SIOCSIFADDR: 1834 ifa = (struct ifaddr *)data; 1835 ifp->if_flags |= IFF_UP; 1836 #ifdef INET 1837 if (ifa->ifa_addr->sa_family == AF_INET) 1838 arp_ifinit(&ic->ic_ac, ifa); 1839 #endif 1840 /* FALLTHROUGH */ 1841 case SIOCSIFFLAGS: 1842 if (ifp->if_flags & IFF_UP) { 1843 if (!(ifp->if_flags & IFF_RUNNING)) 1844 rt2860_init(ifp); 1845 } else { 1846 if (ifp->if_flags & IFF_RUNNING) 1847 rt2860_stop(ifp, 1); 1848 } 1849 break; 1850 1851 case SIOCADDMULTI: 1852 case SIOCDELMULTI: 1853 ifr = (struct ifreq *)data; 1854 error = (cmd == SIOCADDMULTI) ? 1855 ether_addmulti(ifr, &ic->ic_ac) : 1856 ether_delmulti(ifr, &ic->ic_ac); 1857 1858 if (error == ENETRESET) 1859 error = 0; 1860 break; 1861 1862 case SIOCS80211CHANNEL: 1863 /* 1864 * This allows for fast channel switching in monitor mode 1865 * (used by kismet). In IBSS mode, we must explicitly reset 1866 * the interface to generate a new beacon frame. 1867 */ 1868 error = ieee80211_ioctl(ifp, cmd, data); 1869 if (error == ENETRESET && 1870 ic->ic_opmode == IEEE80211_M_MONITOR) { 1871 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1872 (IFF_UP | IFF_RUNNING)) 1873 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1874 error = 0; 1875 } 1876 break; 1877 1878 default: 1879 error = ieee80211_ioctl(ifp, cmd, data); 1880 } 1881 1882 if (error == ENETRESET) { 1883 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1884 (IFF_UP | IFF_RUNNING)) { 1885 rt2860_stop(ifp, 0); 1886 rt2860_init(ifp); 1887 } 1888 error = 0; 1889 } 1890 1891 splx(s); 1892 1893 return error; 1894 } 1895 1896 /* 1897 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1898 * We access the BBP through the 8051 microcontroller unit which means that 1899 * the microcode must be loaded first. 1900 */ 1901 void 1902 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1903 { 1904 int ntries; 1905 1906 for (ntries = 0; ntries < 100; ntries++) { 1907 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1908 break; 1909 DELAY(1); 1910 } 1911 if (ntries == 100) { 1912 printf("%s: could not write to BBP through MCU\n", 1913 sc->sc_dev.dv_xname); 1914 return; 1915 } 1916 1917 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1918 RT2860_BBP_CSR_KICK | reg << 8 | val); 1919 RAL_BARRIER_WRITE(sc); 1920 1921 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1922 DELAY(1000); 1923 } 1924 1925 uint8_t 1926 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1927 { 1928 uint32_t val; 1929 int ntries; 1930 1931 for (ntries = 0; ntries < 100; ntries++) { 1932 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1933 break; 1934 DELAY(1); 1935 } 1936 if (ntries == 100) { 1937 printf("%s: could not read from BBP through MCU\n", 1938 sc->sc_dev.dv_xname); 1939 return 0; 1940 } 1941 1942 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1943 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1944 RAL_BARRIER_WRITE(sc); 1945 1946 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1947 DELAY(1000); 1948 1949 for (ntries = 0; ntries < 100; ntries++) { 1950 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1951 if (!(val & RT2860_BBP_CSR_KICK)) 1952 return val & 0xff; 1953 DELAY(1); 1954 } 1955 printf("%s: could not read from BBP through MCU\n", 1956 sc->sc_dev.dv_xname); 1957 1958 return 0; 1959 } 1960 1961 /* 1962 * Write to one of the 4 programmable 24-bit RF registers. 1963 */ 1964 void 1965 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 1966 { 1967 uint32_t tmp; 1968 int ntries; 1969 1970 for (ntries = 0; ntries < 100; ntries++) { 1971 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 1972 break; 1973 DELAY(1); 1974 } 1975 if (ntries == 100) { 1976 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1977 return; 1978 } 1979 1980 /* RF registers are 24-bit on the RT2860 */ 1981 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1982 (val & 0x3fffff) << 2 | (reg & 3); 1983 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 1984 } 1985 1986 uint8_t 1987 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 1988 { 1989 uint32_t tmp; 1990 int ntries; 1991 1992 for (ntries = 0; ntries < 100; ntries++) { 1993 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 1994 break; 1995 DELAY(1); 1996 } 1997 if (ntries == 100) { 1998 printf("%s: could not read RF register\n", 1999 sc->sc_dev.dv_xname); 2000 return 0xff; 2001 } 2002 tmp = RT3070_RF_KICK | reg << 8; 2003 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2004 2005 for (ntries = 0; ntries < 100; ntries++) { 2006 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2007 if (!(tmp & RT3070_RF_KICK)) 2008 break; 2009 DELAY(1); 2010 } 2011 if (ntries == 100) { 2012 printf("%s: could not read RF register\n", 2013 sc->sc_dev.dv_xname); 2014 return 0xff; 2015 } 2016 return tmp & 0xff; 2017 } 2018 2019 void 2020 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2021 { 2022 uint32_t tmp; 2023 int ntries; 2024 2025 for (ntries = 0; ntries < 10; ntries++) { 2026 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2027 break; 2028 DELAY(10); 2029 } 2030 if (ntries == 10) { 2031 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2032 return; 2033 } 2034 2035 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2036 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2037 } 2038 2039 /* 2040 * Send a command to the 8051 microcontroller unit. 2041 */ 2042 int 2043 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2044 { 2045 int slot, ntries; 2046 uint32_t tmp; 2047 uint8_t cid; 2048 2049 for (ntries = 0; ntries < 100; ntries++) { 2050 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2051 break; 2052 DELAY(2); 2053 } 2054 if (ntries == 100) 2055 return EIO; 2056 2057 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2058 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2059 RAL_BARRIER_WRITE(sc); 2060 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2061 2062 if (!wait) 2063 return 0; 2064 /* wait for the command to complete */ 2065 for (ntries = 0; ntries < 200; ntries++) { 2066 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2067 /* find the command slot */ 2068 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2069 if ((tmp & 0xff) == cid) 2070 break; 2071 if (slot < 4) 2072 break; 2073 DELAY(100); 2074 } 2075 if (ntries == 200) { 2076 /* clear command and status */ 2077 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2078 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2079 return ETIMEDOUT; 2080 } 2081 /* get command status (1 means success) */ 2082 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2083 tmp = (tmp >> (slot * 8)) & 0xff; 2084 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2085 cmd, slot, tmp)); 2086 /* clear command and status */ 2087 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2088 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2089 return (tmp == 1) ? 0 : EIO; 2090 } 2091 2092 void 2093 rt2860_enable_mrr(struct rt2860_softc *sc) 2094 { 2095 #define CCK(mcs) (mcs) 2096 #define OFDM(mcs) (1 << 3 | (mcs)) 2097 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2098 OFDM(6) << 28 | /* 54->48 */ 2099 OFDM(5) << 24 | /* 48->36 */ 2100 OFDM(4) << 20 | /* 36->24 */ 2101 OFDM(3) << 16 | /* 24->18 */ 2102 OFDM(2) << 12 | /* 18->12 */ 2103 OFDM(1) << 8 | /* 12-> 9 */ 2104 OFDM(0) << 4 | /* 9-> 6 */ 2105 OFDM(0)); /* 6-> 6 */ 2106 2107 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2108 CCK(2) << 12 | /* 11->5.5 */ 2109 CCK(1) << 8 | /* 5.5-> 2 */ 2110 CCK(0) << 4 | /* 2-> 1 */ 2111 CCK(0)); /* 1-> 1 */ 2112 #undef OFDM 2113 #undef CCK 2114 } 2115 2116 void 2117 rt2860_set_txpreamble(struct rt2860_softc *sc) 2118 { 2119 uint32_t tmp; 2120 2121 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2122 tmp &= ~RT2860_CCK_SHORT_EN; 2123 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2124 tmp |= RT2860_CCK_SHORT_EN; 2125 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2126 } 2127 2128 void 2129 rt2860_set_basicrates(struct rt2860_softc *sc) 2130 { 2131 struct ieee80211com *ic = &sc->sc_ic; 2132 2133 /* set basic rates mask */ 2134 if (ic->ic_curmode == IEEE80211_MODE_11B) 2135 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2136 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2137 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2138 else /* 11g */ 2139 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2140 } 2141 2142 void 2143 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2144 { 2145 uint32_t tmp; 2146 uint8_t agc; 2147 2148 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2149 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2150 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2151 rt2860_mcu_bbp_write(sc, 86, 0x00); 2152 2153 if (group == 0) { 2154 if (sc->ext_2ghz_lna) { 2155 rt2860_mcu_bbp_write(sc, 82, 0x62); 2156 rt2860_mcu_bbp_write(sc, 75, 0x46); 2157 } else { 2158 rt2860_mcu_bbp_write(sc, 82, 0x84); 2159 rt2860_mcu_bbp_write(sc, 75, 0x50); 2160 } 2161 } else { 2162 if (sc->ext_5ghz_lna) { 2163 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2164 rt2860_mcu_bbp_write(sc, 75, 0x46); 2165 } else { 2166 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2167 rt2860_mcu_bbp_write(sc, 75, 0x50); 2168 } 2169 } 2170 2171 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2172 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2173 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2174 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2175 2176 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2177 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2178 if (sc->nrxchains > 1) 2179 tmp |= RT2860_LNA_PE1_EN; 2180 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2181 tmp |= RT3593_LNA_PE2_EN; 2182 if (group == 0) { /* 2GHz */ 2183 tmp |= RT2860_PA_PE_G0_EN; 2184 if (sc->ntxchains > 1) 2185 tmp |= RT2860_PA_PE_G1_EN; 2186 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2187 tmp |= RT3593_PA_PE_G2_EN; 2188 } else { /* 5GHz */ 2189 tmp |= RT2860_PA_PE_A0_EN; 2190 if (sc->ntxchains > 1) 2191 tmp |= RT2860_PA_PE_A1_EN; 2192 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2193 tmp |= RT3593_PA_PE_A2_EN; 2194 } 2195 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2196 2197 if (sc->mac_ver == 0x3593) { 2198 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2199 if (sc->sc_flags & RT2860_PCIE) { 2200 tmp &= ~0x01010000; 2201 if (group == 0) 2202 tmp |= 0x00010000; 2203 } else { 2204 tmp &= ~0x00008080; 2205 if (group == 0) 2206 tmp |= 0x00000080; 2207 } 2208 tmp = (tmp & ~0x00001000) | 0x00000010; 2209 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2210 } 2211 2212 /* set initial AGC value */ 2213 if (group == 0) { /* 2GHz band */ 2214 if (sc->mac_ver >= 0x3071) 2215 agc = 0x1c + sc->lna[0] * 2; 2216 else 2217 agc = 0x2e + sc->lna[0]; 2218 } else { /* 5GHz band */ 2219 agc = 0x32 + (sc->lna[group] * 5) / 3; 2220 } 2221 rt2860_mcu_bbp_write(sc, 66, agc); 2222 2223 DELAY(1000); 2224 } 2225 2226 void 2227 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2228 { 2229 const struct rfprog *rfprog = rt2860_rf2850; 2230 uint32_t r2, r3, r4; 2231 int8_t txpow1, txpow2; 2232 u_int i; 2233 2234 /* find the settings for this channel (we know it exists) */ 2235 for (i = 0; rfprog[i].chan != chan; i++); 2236 2237 r2 = rfprog[i].r2; 2238 if (sc->ntxchains == 1) 2239 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2240 if (sc->nrxchains == 1) 2241 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2242 else if (sc->nrxchains == 2) 2243 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2244 2245 /* use Tx power values from EEPROM */ 2246 txpow1 = sc->txpow1[i]; 2247 txpow2 = sc->txpow2[i]; 2248 if (chan > 14) { 2249 if (txpow1 >= 0) 2250 txpow1 = txpow1 << 1 | 1; 2251 else 2252 txpow1 = (7 + txpow1) << 1; 2253 if (txpow2 >= 0) 2254 txpow2 = txpow2 << 1 | 1; 2255 else 2256 txpow2 = (7 + txpow2) << 1; 2257 } 2258 r3 = rfprog[i].r3 | txpow1 << 7; 2259 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2260 2261 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2262 rt2860_rf_write(sc, RT2860_RF2, r2); 2263 rt2860_rf_write(sc, RT2860_RF3, r3); 2264 rt2860_rf_write(sc, RT2860_RF4, r4); 2265 2266 DELAY(200); 2267 2268 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2269 rt2860_rf_write(sc, RT2860_RF2, r2); 2270 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2271 rt2860_rf_write(sc, RT2860_RF4, r4); 2272 2273 DELAY(200); 2274 2275 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2276 rt2860_rf_write(sc, RT2860_RF2, r2); 2277 rt2860_rf_write(sc, RT2860_RF3, r3); 2278 rt2860_rf_write(sc, RT2860_RF4, r4); 2279 } 2280 2281 void 2282 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2283 { 2284 int8_t txpow1, txpow2; 2285 uint8_t rf; 2286 int i; 2287 2288 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2289 2290 /* find the settings for this channel (we know it exists) */ 2291 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2292 2293 /* use Tx power values from EEPROM */ 2294 txpow1 = sc->txpow1[i]; 2295 txpow2 = sc->txpow2[i]; 2296 2297 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2298 rf = rt3090_rf_read(sc, 3); 2299 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2300 rt3090_rf_write(sc, 3, rf); 2301 rf = rt3090_rf_read(sc, 6); 2302 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2303 rt3090_rf_write(sc, 6, rf); 2304 2305 /* set Tx0 power */ 2306 rf = rt3090_rf_read(sc, 12); 2307 rf = (rf & ~0x1f) | txpow1; 2308 rt3090_rf_write(sc, 12, rf); 2309 2310 /* set Tx1 power */ 2311 rf = rt3090_rf_read(sc, 13); 2312 rf = (rf & ~0x1f) | txpow2; 2313 rt3090_rf_write(sc, 13, rf); 2314 2315 rf = rt3090_rf_read(sc, 1); 2316 rf &= ~0xfc; 2317 if (sc->ntxchains == 1) 2318 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2319 else if (sc->ntxchains == 2) 2320 rf |= RT3070_TX2_PD; 2321 if (sc->nrxchains == 1) 2322 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2323 else if (sc->nrxchains == 2) 2324 rf |= RT3070_RX2_PD; 2325 rt3090_rf_write(sc, 1, rf); 2326 2327 /* set RF offset */ 2328 rf = rt3090_rf_read(sc, 23); 2329 rf = (rf & ~0x7f) | sc->freq; 2330 rt3090_rf_write(sc, 23, rf); 2331 2332 /* program RF filter */ 2333 rf = rt3090_rf_read(sc, 24); /* Tx */ 2334 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2335 rt3090_rf_write(sc, 24, rf); 2336 rf = rt3090_rf_read(sc, 31); /* Rx */ 2337 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2338 rt3090_rf_write(sc, 31, rf); 2339 2340 /* enable RF tuning */ 2341 rf = rt3090_rf_read(sc, 7); 2342 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2343 } 2344 2345 int 2346 rt3090_rf_init(struct rt2860_softc *sc) 2347 { 2348 uint32_t tmp; 2349 uint8_t rf, bbp; 2350 int i; 2351 2352 rf = rt3090_rf_read(sc, 30); 2353 /* toggle RF R30 bit 7 */ 2354 rt3090_rf_write(sc, 30, rf | 0x80); 2355 DELAY(1000); 2356 rt3090_rf_write(sc, 30, rf & ~0x80); 2357 2358 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2359 tmp &= ~0x1f000000; 2360 if (sc->patch_dac && sc->mac_rev < 0x0211) 2361 tmp |= 0x0d000000; /* 1.35V */ 2362 else 2363 tmp |= 0x01000000; /* 1.2V */ 2364 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2365 2366 /* patch LNA_PE_G1 */ 2367 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2368 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2369 2370 /* initialize RF registers to default value */ 2371 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2372 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2373 rt3090_def_rf[i].val); 2374 } 2375 2376 /* select 20MHz bandwidth */ 2377 rt3090_rf_write(sc, 31, 0x14); 2378 2379 rf = rt3090_rf_read(sc, 6); 2380 rt3090_rf_write(sc, 6, rf | 0x40); 2381 2382 if (sc->mac_ver != 0x3593) { 2383 /* calibrate filter for 20MHz bandwidth */ 2384 sc->rf24_20mhz = 0x1f; /* default value */ 2385 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2386 2387 /* select 40MHz bandwidth */ 2388 bbp = rt2860_mcu_bbp_read(sc, 4); 2389 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2390 rf = rt3090_rf_read(sc, 31); 2391 rt3090_rf_write(sc, 31, rf | 0x20); 2392 2393 /* calibrate filter for 40MHz bandwidth */ 2394 sc->rf24_40mhz = 0x2f; /* default value */ 2395 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2396 2397 /* go back to 20MHz bandwidth */ 2398 bbp = rt2860_mcu_bbp_read(sc, 4); 2399 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2400 } 2401 if (sc->mac_rev < 0x0211) 2402 rt3090_rf_write(sc, 27, 0x03); 2403 2404 tmp = RAL_READ(sc, RT3070_OPT_14); 2405 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2406 2407 if (sc->rf_rev == RT3070_RF_3020) 2408 rt3090_set_rx_antenna(sc, 0); 2409 2410 bbp = rt2860_mcu_bbp_read(sc, 138); 2411 if (sc->mac_ver == 0x3593) { 2412 if (sc->ntxchains == 1) 2413 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2414 else if (sc->ntxchains == 2) 2415 bbp |= 0x40; /* turn off DAC2 */ 2416 if (sc->nrxchains == 1) 2417 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2418 else if (sc->nrxchains == 2) 2419 bbp &= ~0x04; /* turn off ADC2 */ 2420 } else { 2421 if (sc->ntxchains == 1) 2422 bbp |= 0x20; /* turn off DAC1 */ 2423 if (sc->nrxchains == 1) 2424 bbp &= ~0x02; /* turn off ADC1 */ 2425 } 2426 rt2860_mcu_bbp_write(sc, 138, bbp); 2427 2428 rf = rt3090_rf_read(sc, 1); 2429 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2430 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2431 rt3090_rf_write(sc, 1, rf); 2432 2433 rf = rt3090_rf_read(sc, 15); 2434 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2435 2436 rf = rt3090_rf_read(sc, 17); 2437 rf &= ~RT3070_TX_LO1; 2438 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2439 rf |= 0x20; /* fix for long range Rx issue */ 2440 if (sc->txmixgain_2ghz >= 2) 2441 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2442 rt3090_rf_write(sc, 17, rf); 2443 2444 rf = rt3090_rf_read(sc, 20); 2445 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2446 2447 rf = rt3090_rf_read(sc, 21); 2448 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2449 2450 return 0; 2451 } 2452 2453 void 2454 rt3090_rf_wakeup(struct rt2860_softc *sc) 2455 { 2456 uint32_t tmp; 2457 uint8_t rf; 2458 2459 if (sc->mac_ver == 0x3593) { 2460 /* enable VCO */ 2461 rf = rt3090_rf_read(sc, 1); 2462 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2463 2464 /* initiate VCO calibration */ 2465 rf = rt3090_rf_read(sc, 3); 2466 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2467 2468 /* enable VCO bias current control */ 2469 rf = rt3090_rf_read(sc, 6); 2470 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2471 2472 /* initiate res calibration */ 2473 rf = rt3090_rf_read(sc, 2); 2474 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2475 2476 /* set reference current control to 0.33 mA */ 2477 rf = rt3090_rf_read(sc, 22); 2478 rf &= ~RT3593_CP_IC_MASK; 2479 rf |= 1 << RT3593_CP_IC_SHIFT; 2480 rt3090_rf_write(sc, 22, rf); 2481 2482 /* enable RX CTB */ 2483 rf = rt3090_rf_read(sc, 46); 2484 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2485 2486 rf = rt3090_rf_read(sc, 20); 2487 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2488 rt3090_rf_write(sc, 20, rf); 2489 } else { 2490 /* enable RF block */ 2491 rf = rt3090_rf_read(sc, 1); 2492 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2493 2494 /* enable VCO bias current control */ 2495 rf = rt3090_rf_read(sc, 7); 2496 rt3090_rf_write(sc, 7, rf | 0x30); 2497 2498 rf = rt3090_rf_read(sc, 9); 2499 rt3090_rf_write(sc, 9, rf | 0x0e); 2500 2501 /* enable RX CTB */ 2502 rf = rt3090_rf_read(sc, 21); 2503 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2504 2505 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2506 rf = rt3090_rf_read(sc, 27); 2507 rf &= ~0x77; 2508 if (sc->mac_rev < 0x0211) 2509 rf |= 0x03; 2510 rt3090_rf_write(sc, 27, rf); 2511 } 2512 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2513 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2514 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2515 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2516 } 2517 } 2518 2519 int 2520 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2521 uint8_t *val) 2522 { 2523 uint8_t rf22, rf24; 2524 uint8_t bbp55_pb, bbp55_sb, delta; 2525 int ntries; 2526 2527 /* program filter */ 2528 rf24 = rt3090_rf_read(sc, 24); 2529 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2530 rt3090_rf_write(sc, 24, rf24); 2531 2532 /* enable baseband loopback mode */ 2533 rf22 = rt3090_rf_read(sc, 22); 2534 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2535 2536 /* set power and frequency of passband test tone */ 2537 rt2860_mcu_bbp_write(sc, 24, 0x00); 2538 for (ntries = 0; ntries < 100; ntries++) { 2539 /* transmit test tone */ 2540 rt2860_mcu_bbp_write(sc, 25, 0x90); 2541 DELAY(1000); 2542 /* read received power */ 2543 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2544 if (bbp55_pb != 0) 2545 break; 2546 } 2547 if (ntries == 100) 2548 return ETIMEDOUT; 2549 2550 /* set power and frequency of stopband test tone */ 2551 rt2860_mcu_bbp_write(sc, 24, 0x06); 2552 for (ntries = 0; ntries < 100; ntries++) { 2553 /* transmit test tone */ 2554 rt2860_mcu_bbp_write(sc, 25, 0x90); 2555 DELAY(1000); 2556 /* read received power */ 2557 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2558 2559 delta = bbp55_pb - bbp55_sb; 2560 if (delta > target) 2561 break; 2562 2563 /* reprogram filter */ 2564 rf24++; 2565 rt3090_rf_write(sc, 24, rf24); 2566 } 2567 if (ntries < 100) { 2568 if (rf24 != init) 2569 rf24--; /* backtrack */ 2570 *val = rf24; 2571 rt3090_rf_write(sc, 24, rf24); 2572 } 2573 2574 /* restore initial state */ 2575 rt2860_mcu_bbp_write(sc, 24, 0x00); 2576 2577 /* disable baseband loopback mode */ 2578 rf22 = rt3090_rf_read(sc, 22); 2579 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2580 2581 return 0; 2582 } 2583 2584 void 2585 rt3090_rf_setup(struct rt2860_softc *sc) 2586 { 2587 uint8_t bbp; 2588 int i; 2589 2590 if (sc->mac_rev >= 0x0211) { 2591 /* enable DC filter */ 2592 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2593 2594 /* improve power consumption */ 2595 bbp = rt2860_mcu_bbp_read(sc, 31); 2596 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2597 } 2598 2599 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2600 if (sc->mac_rev < 0x0211) { 2601 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2602 sc->patch_dac ? 0x2c : 0x0f); 2603 } else 2604 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2605 2606 /* initialize RF registers from ROM */ 2607 for (i = 0; i < 10; i++) { 2608 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2609 continue; 2610 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2611 } 2612 } 2613 2614 void 2615 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2616 { 2617 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2618 which | (sc->leds & 0x7f), 0); 2619 } 2620 2621 /* 2622 * Hardware has a general-purpose programmable timer interrupt that can 2623 * periodically raise MAC_INT_4. 2624 */ 2625 void 2626 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2627 { 2628 uint32_t tmp; 2629 2630 /* disable GP timer before reprogramming it */ 2631 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2632 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2633 2634 if (ms == 0) 2635 return; 2636 2637 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2638 ms *= 16; /* Unit: 64us */ 2639 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2640 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2641 2642 /* enable GP timer */ 2643 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2644 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2645 } 2646 2647 void 2648 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2649 { 2650 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2651 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2652 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2653 bssid[4] | bssid[5] << 8); 2654 } 2655 2656 void 2657 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2658 { 2659 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2660 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2661 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2662 addr[4] | addr[5] << 8 | 0xff << 16); 2663 } 2664 2665 void 2666 rt2860_updateslot(struct ieee80211com *ic) 2667 { 2668 struct rt2860_softc *sc = ic->ic_softc; 2669 uint32_t tmp; 2670 2671 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2672 tmp &= ~0xff; 2673 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2674 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2675 } 2676 2677 void 2678 rt2860_updateprot(struct ieee80211com *ic) 2679 { 2680 struct rt2860_softc *sc = ic->ic_softc; 2681 uint32_t tmp; 2682 2683 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2684 /* setup protection frame rate (MCS code) */ 2685 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2686 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2687 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2688 2689 /* CCK frames don't require protection */ 2690 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2691 2692 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2693 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2694 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2695 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2696 tmp |= RT2860_PROT_CTRL_CTS; 2697 } 2698 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2699 } 2700 2701 void 2702 rt2860_updateedca(struct ieee80211com *ic) 2703 { 2704 struct rt2860_softc *sc = ic->ic_softc; 2705 int aci; 2706 2707 /* update MAC TX configuration registers */ 2708 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2709 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2710 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 2711 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 2712 ic->ic_edca_ac[aci].ac_aifsn << 8 | 2713 ic->ic_edca_ac[aci].ac_txoplimit); 2714 } 2715 2716 /* update SCH/DMA registers too */ 2717 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2718 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 2719 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 2720 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 2721 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 2722 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2723 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 2724 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 2725 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 2726 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 2727 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2728 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 2729 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 2730 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 2731 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 2732 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2733 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 2734 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 2735 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2736 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 2737 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 2738 } 2739 2740 int 2741 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2742 struct ieee80211_key *k) 2743 { 2744 struct rt2860_softc *sc = ic->ic_softc; 2745 bus_size_t base; 2746 uint32_t attr; 2747 uint8_t mode, wcid, iv[8]; 2748 2749 /* defer setting of WEP keys until interface is brought up */ 2750 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2751 (IFF_UP | IFF_RUNNING)) 2752 return 0; 2753 2754 /* map net80211 cipher to RT2860 security mode */ 2755 switch (k->k_cipher) { 2756 case IEEE80211_CIPHER_WEP40: 2757 mode = RT2860_MODE_WEP40; 2758 break; 2759 case IEEE80211_CIPHER_WEP104: 2760 mode = RT2860_MODE_WEP104; 2761 break; 2762 case IEEE80211_CIPHER_TKIP: 2763 mode = RT2860_MODE_TKIP; 2764 break; 2765 case IEEE80211_CIPHER_CCMP: 2766 mode = RT2860_MODE_AES_CCMP; 2767 break; 2768 default: 2769 return EINVAL; 2770 } 2771 2772 if (k->k_flags & IEEE80211_KEY_GROUP) { 2773 wcid = 0; /* NB: update WCID0 for group keys */ 2774 base = RT2860_SKEY(0, k->k_id); 2775 } else { 2776 wcid = ((struct rt2860_node *)ni)->wcid; 2777 base = RT2860_PKEY(wcid); 2778 } 2779 2780 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2781 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 2782 #ifndef IEEE80211_STA_ONLY 2783 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2784 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 2785 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 2786 } else 2787 #endif 2788 { 2789 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 2790 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 2791 } 2792 } else 2793 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 2794 2795 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 2796 (k->k_flags & IEEE80211_KEY_TX)) { 2797 /* set initial packet number in IV+EIV */ 2798 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 2799 k->k_cipher == IEEE80211_CIPHER_WEP104) { 2800 uint32_t val = arc4random(); 2801 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 2802 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 2803 val += 0x000100; 2804 iv[0] = val; 2805 iv[1] = val >> 8; 2806 iv[2] = val >> 16; 2807 iv[3] = k->k_id << 6; 2808 iv[4] = iv[5] = iv[6] = iv[7] = 0; 2809 } else { 2810 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2811 iv[0] = k->k_tsc >> 8; 2812 iv[1] = (iv[0] | 0x20) & 0x7f; 2813 iv[2] = k->k_tsc; 2814 } else /* CCMP */ { 2815 iv[0] = k->k_tsc; 2816 iv[1] = k->k_tsc >> 8; 2817 iv[2] = 0; 2818 } 2819 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 2820 iv[4] = k->k_tsc >> 16; 2821 iv[5] = k->k_tsc >> 24; 2822 iv[6] = k->k_tsc >> 32; 2823 iv[7] = k->k_tsc >> 40; 2824 } 2825 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 2826 } 2827 2828 if (k->k_flags & IEEE80211_KEY_GROUP) { 2829 /* install group key */ 2830 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 2831 attr &= ~(0xf << (k->k_id * 4)); 2832 attr |= mode << (k->k_id * 4); 2833 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 2834 } else { 2835 /* install pairwise key */ 2836 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 2837 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2838 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 2839 } 2840 return 0; 2841 } 2842 2843 void 2844 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2845 struct ieee80211_key *k) 2846 { 2847 struct rt2860_softc *sc = ic->ic_softc; 2848 uint32_t attr; 2849 uint8_t wcid; 2850 2851 if (k->k_flags & IEEE80211_KEY_GROUP) { 2852 /* remove group key */ 2853 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 2854 attr &= ~(0xf << (k->k_id * 4)); 2855 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 2856 2857 } else { 2858 /* remove pairwise key */ 2859 wcid = ((struct rt2860_node *)ni)->wcid; 2860 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 2861 attr &= ~0xf; 2862 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 2863 } 2864 } 2865 2866 #if NBPFILTER > 0 2867 int8_t 2868 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 2869 { 2870 struct ieee80211com *ic = &sc->sc_ic; 2871 struct ieee80211_channel *c = ic->ic_ibss_chan; 2872 int delta; 2873 2874 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2875 u_int chan = ieee80211_chan2ieee(ic, c); 2876 delta = sc->rssi_5ghz[rxchain]; 2877 2878 /* determine channel group */ 2879 if (chan <= 64) 2880 delta -= sc->lna[1]; 2881 else if (chan <= 128) 2882 delta -= sc->lna[2]; 2883 else 2884 delta -= sc->lna[3]; 2885 } else 2886 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 2887 2888 return -12 - delta - rssi; 2889 } 2890 #endif 2891 2892 /* 2893 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 2894 * Used to adjust per-rate Tx power registers. 2895 */ 2896 static __inline uint32_t 2897 b4inc(uint32_t b32, int8_t delta) 2898 { 2899 int8_t i, b4; 2900 2901 for (i = 0; i < 8; i++) { 2902 b4 = b32 & 0xf; 2903 b4 += delta; 2904 if (b4 < 0) 2905 b4 = 0; 2906 else if (b4 > 0xf) 2907 b4 = 0xf; 2908 b32 = b32 >> 4 | b4 << 28; 2909 } 2910 return b32; 2911 } 2912 2913 const char * 2914 rt2860_get_rf(uint8_t rev) 2915 { 2916 switch (rev) { 2917 case RT2860_RF_2820: return "RT2820"; 2918 case RT2860_RF_2850: return "RT2850"; 2919 case RT2860_RF_2720: return "RT2720"; 2920 case RT2860_RF_2750: return "RT2750"; 2921 case RT3070_RF_3020: return "RT3020"; 2922 case RT3070_RF_2020: return "RT2020"; 2923 case RT3070_RF_3021: return "RT3021"; 2924 case RT3070_RF_3022: return "RT3022"; 2925 case RT3070_RF_3052: return "RT3052"; 2926 case RT3070_RF_3320: return "RT3320"; 2927 case RT3070_RF_3053: return "RT3053"; 2928 default: return "unknown"; 2929 } 2930 } 2931 2932 int 2933 rt2860_read_eeprom(struct rt2860_softc *sc) 2934 { 2935 struct ieee80211com *ic = &sc->sc_ic; 2936 int8_t delta_2ghz, delta_5ghz; 2937 uint32_t tmp; 2938 uint16_t val; 2939 int ridx, ant, i; 2940 2941 /* check whether the ROM is eFUSE ROM or EEPROM */ 2942 sc->sc_srom_read = rt2860_eeprom_read_2; 2943 if (sc->mac_ver >= 0x3071) { 2944 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 2945 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 2946 if (tmp & RT3070_SEL_EFUSE) 2947 sc->sc_srom_read = rt3090_efuse_read_2; 2948 } 2949 2950 /* read EEPROM version */ 2951 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 2952 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 2953 2954 /* read MAC address */ 2955 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 2956 ic->ic_myaddr[0] = val & 0xff; 2957 ic->ic_myaddr[1] = val >> 8; 2958 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 2959 ic->ic_myaddr[2] = val & 0xff; 2960 ic->ic_myaddr[3] = val >> 8; 2961 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 2962 ic->ic_myaddr[4] = val & 0xff; 2963 ic->ic_myaddr[5] = val >> 8; 2964 2965 /* read country code */ 2966 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 2967 DPRINTF(("EEPROM region code=0x%04x\n", val)); 2968 2969 /* read vendor BBP settings */ 2970 for (i = 0; i < 8; i++) { 2971 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 2972 sc->bbp[i].val = val & 0xff; 2973 sc->bbp[i].reg = val >> 8; 2974 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 2975 } 2976 if (sc->mac_ver >= 0x3071) { 2977 /* read vendor RF settings */ 2978 for (i = 0; i < 10; i++) { 2979 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 2980 sc->rf[i].val = val & 0xff; 2981 sc->rf[i].reg = val >> 8; 2982 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 2983 sc->rf[i].val)); 2984 } 2985 } 2986 2987 /* read RF frequency offset from EEPROM */ 2988 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 2989 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 2990 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 2991 if ((val >> 8) != 0xff) { 2992 /* read LEDs operating mode */ 2993 sc->leds = val >> 8; 2994 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 2995 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 2996 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 2997 } else { 2998 /* broken EEPROM, use default settings */ 2999 sc->leds = 0x01; 3000 sc->led[0] = 0x5555; 3001 sc->led[1] = 0x2221; 3002 sc->led[2] = 0xa9f8; 3003 } 3004 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3005 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3006 3007 /* read RF information */ 3008 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3009 if (val == 0xffff) { 3010 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3011 if (sc->mac_ver == 0x3593) { 3012 /* default to RF3053 3T3R */ 3013 sc->rf_rev = RT3070_RF_3053; 3014 sc->ntxchains = 3; 3015 sc->nrxchains = 3; 3016 } else if (sc->mac_ver >= 0x3071) { 3017 /* default to RF3020 1T1R */ 3018 sc->rf_rev = RT3070_RF_3020; 3019 sc->ntxchains = 1; 3020 sc->nrxchains = 1; 3021 } else { 3022 /* default to RF2820 1T2R */ 3023 sc->rf_rev = RT2860_RF_2820; 3024 sc->ntxchains = 1; 3025 sc->nrxchains = 2; 3026 } 3027 } else { 3028 sc->rf_rev = (val >> 8) & 0xf; 3029 sc->ntxchains = (val >> 4) & 0xf; 3030 sc->nrxchains = val & 0xf; 3031 } 3032 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3033 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3034 3035 /* check if RF supports automatic Tx access gain control */ 3036 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3037 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3038 /* check if driver should patch the DAC issue */ 3039 if ((val >> 8) != 0xff) 3040 sc->patch_dac = (val >> 15) & 1; 3041 if ((val & 0xff) != 0xff) { 3042 sc->ext_5ghz_lna = (val >> 3) & 1; 3043 sc->ext_2ghz_lna = (val >> 2) & 1; 3044 /* check if RF supports automatic Tx access gain control */ 3045 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3046 /* check if we have a hardware radio switch */ 3047 sc->rfswitch = val & 1; 3048 } 3049 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3050 /* read PCIe power save level */ 3051 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3052 if ((val & 0xff) != 0xff) { 3053 sc->pslevel = val & 0x3; 3054 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3055 if ((val & 0xff80) != 0x9280) 3056 sc->pslevel = MIN(sc->pslevel, 1); 3057 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3058 } 3059 } 3060 3061 /* read power settings for 2GHz channels */ 3062 for (i = 0; i < 14; i += 2) { 3063 val = rt2860_srom_read(sc, 3064 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3065 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3066 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3067 3068 val = rt2860_srom_read(sc, 3069 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3070 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3071 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3072 } 3073 /* fix broken Tx power entries */ 3074 for (i = 0; i < 14; i++) { 3075 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 3076 sc->txpow1[i] = 5; 3077 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 3078 sc->txpow2[i] = 5; 3079 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3080 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3081 } 3082 /* read power settings for 5GHz channels */ 3083 for (i = 0; i < 40; i += 2) { 3084 val = rt2860_srom_read(sc, 3085 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3086 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3087 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3088 3089 val = rt2860_srom_read(sc, 3090 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3091 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3092 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3093 } 3094 /* fix broken Tx power entries */ 3095 for (i = 0; i < 40; i++) { 3096 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3097 sc->txpow1[14 + i] = 5; 3098 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3099 sc->txpow2[14 + i] = 5; 3100 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3101 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3102 sc->txpow2[14 + i])); 3103 } 3104 3105 /* read Tx power compensation for each Tx rate */ 3106 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3107 delta_2ghz = delta_5ghz = 0; 3108 if ((val & 0xff) != 0xff && (val & 0x80)) { 3109 delta_2ghz = val & 0xf; 3110 if (!(val & 0x40)) /* negative number */ 3111 delta_2ghz = -delta_2ghz; 3112 } 3113 val >>= 8; 3114 if ((val & 0xff) != 0xff && (val & 0x80)) { 3115 delta_5ghz = val & 0xf; 3116 if (!(val & 0x40)) /* negative number */ 3117 delta_5ghz = -delta_5ghz; 3118 } 3119 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3120 delta_2ghz, delta_5ghz)); 3121 3122 for (ridx = 0; ridx < 5; ridx++) { 3123 uint32_t reg; 3124 3125 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3126 reg = val; 3127 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3128 reg |= (uint32_t)val << 16; 3129 3130 sc->txpow20mhz[ridx] = reg; 3131 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3132 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3133 3134 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3135 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3136 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3137 } 3138 3139 /* read factory-calibrated samples for temperature compensation */ 3140 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3141 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3142 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3143 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3144 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3145 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3146 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3147 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3148 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3149 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3150 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3151 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3152 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3153 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3154 sc->step_2ghz = val >> 8; 3155 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3156 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3157 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3158 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3159 sc->tssi_2ghz[8], sc->step_2ghz)); 3160 /* check that ref value is correct, otherwise disable calibration */ 3161 if (sc->tssi_2ghz[4] == 0xff) 3162 sc->calib_2ghz = 0; 3163 3164 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3165 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3166 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3167 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3168 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3169 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3170 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3171 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3172 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3173 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3174 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3175 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3176 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3177 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3178 sc->step_5ghz = val >> 8; 3179 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3180 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3181 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3182 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3183 sc->tssi_5ghz[8], sc->step_5ghz)); 3184 /* check that ref value is correct, otherwise disable calibration */ 3185 if (sc->tssi_5ghz[4] == 0xff) 3186 sc->calib_5ghz = 0; 3187 3188 /* read RSSI offsets and LNA gains from EEPROM */ 3189 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3190 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3191 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3192 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3193 if (sc->mac_ver >= 0x3071) { 3194 /* 3195 * On RT3090 chips (limited to 2 Rx chains), this ROM 3196 * field contains the Tx mixer gain for the 2GHz band. 3197 */ 3198 if ((val & 0xff) != 0xff) 3199 sc->txmixgain_2ghz = val & 0x7; 3200 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3201 } else 3202 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3203 sc->lna[2] = val >> 8; /* channel group 2 */ 3204 3205 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3206 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3207 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3208 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3209 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3210 sc->lna[3] = val >> 8; /* channel group 3 */ 3211 3212 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3213 if (sc->mac_ver >= 0x3071) 3214 sc->lna[0] = RT3090_DEF_LNA; 3215 else /* channel group 0 */ 3216 sc->lna[0] = val & 0xff; 3217 sc->lna[1] = val >> 8; /* channel group 1 */ 3218 3219 /* fix broken 5GHz LNA entries */ 3220 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3221 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3222 sc->lna[2] = sc->lna[1]; 3223 } 3224 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3225 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3226 sc->lna[3] = sc->lna[1]; 3227 } 3228 3229 /* fix broken RSSI offset entries */ 3230 for (ant = 0; ant < 3; ant++) { 3231 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3232 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3233 ant + 1, sc->rssi_2ghz[ant])); 3234 sc->rssi_2ghz[ant] = 0; 3235 } 3236 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3237 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3238 ant + 1, sc->rssi_5ghz[ant])); 3239 sc->rssi_5ghz[ant] = 0; 3240 } 3241 } 3242 3243 return 0; 3244 } 3245 3246 int 3247 rt2860_bbp_init(struct rt2860_softc *sc) 3248 { 3249 int i, ntries; 3250 3251 /* wait for BBP to wake up */ 3252 for (ntries = 0; ntries < 20; ntries++) { 3253 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3254 if (bbp0 != 0 && bbp0 != 0xff) 3255 break; 3256 } 3257 if (ntries == 20) { 3258 printf("%s: timeout waiting for BBP to wake up\n", 3259 sc->sc_dev.dv_xname); 3260 return ETIMEDOUT; 3261 } 3262 3263 /* initialize BBP registers to default values */ 3264 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3265 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3266 rt2860_def_bbp[i].val); 3267 } 3268 3269 /* fix BBP84 for RT2860E */ 3270 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3271 rt2860_mcu_bbp_write(sc, 84, 0x19); 3272 3273 if (sc->mac_ver >= 0x3071) { 3274 rt2860_mcu_bbp_write(sc, 79, 0x13); 3275 rt2860_mcu_bbp_write(sc, 80, 0x05); 3276 rt2860_mcu_bbp_write(sc, 81, 0x33); 3277 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3278 rt2860_mcu_bbp_write(sc, 69, 0x16); 3279 rt2860_mcu_bbp_write(sc, 73, 0x12); 3280 } 3281 3282 return 0; 3283 } 3284 3285 int 3286 rt2860_txrx_enable(struct rt2860_softc *sc) 3287 { 3288 uint32_t tmp; 3289 int ntries; 3290 3291 /* enable Tx/Rx DMA engine */ 3292 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3293 RAL_BARRIER_READ_WRITE(sc); 3294 for (ntries = 0; ntries < 200; ntries++) { 3295 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3296 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3297 break; 3298 DELAY(1000); 3299 } 3300 if (ntries == 200) { 3301 printf("%s: timeout waiting for DMA engine\n", 3302 sc->sc_dev.dv_xname); 3303 return ETIMEDOUT; 3304 } 3305 3306 DELAY(50); 3307 3308 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3309 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3310 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3311 3312 /* set Rx filter */ 3313 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3314 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3315 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3316 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3317 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3318 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3319 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3320 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3321 } 3322 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3323 3324 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3325 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3326 3327 return 0; 3328 } 3329 3330 int 3331 rt2860_init(struct ifnet *ifp) 3332 { 3333 struct rt2860_softc *sc = ifp->if_softc; 3334 struct ieee80211com *ic = &sc->sc_ic; 3335 uint32_t tmp; 3336 uint8_t bbp1, bbp3; 3337 int i, qid, ridx, ntries, error; 3338 3339 /* for CardBus, power on the socket */ 3340 if (!(sc->sc_flags & RT2860_ENABLED)) { 3341 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3342 printf("%s: could not enable device\n", 3343 sc->sc_dev.dv_xname); 3344 return EIO; 3345 } 3346 sc->sc_flags |= RT2860_ENABLED; 3347 } 3348 3349 if (sc->rfswitch) { 3350 /* hardware has a radio switch on GPIO pin 2 */ 3351 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3352 printf("%s: radio is disabled by hardware switch\n", 3353 sc->sc_dev.dv_xname); 3354 #ifdef notyet 3355 rt2860_stop(ifp, 1); 3356 return EPERM; 3357 #endif 3358 } 3359 } 3360 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3361 3362 /* disable DMA */ 3363 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3364 tmp &= 0xff0; 3365 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3366 3367 /* PBF hardware reset */ 3368 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3369 RAL_BARRIER_WRITE(sc); 3370 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3371 3372 if ((error = rt2860_load_microcode(sc)) != 0) { 3373 printf("%s: could not load 8051 microcode\n", 3374 sc->sc_dev.dv_xname); 3375 rt2860_stop(ifp, 1); 3376 return error; 3377 } 3378 3379 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3380 rt2860_set_macaddr(sc, ic->ic_myaddr); 3381 3382 /* init Tx power for all Tx rates (from EEPROM) */ 3383 for (ridx = 0; ridx < 5; ridx++) { 3384 if (sc->txpow20mhz[ridx] == 0xffffffff) 3385 continue; 3386 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3387 } 3388 3389 for (ntries = 0; ntries < 100; ntries++) { 3390 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3391 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3392 break; 3393 DELAY(1000); 3394 } 3395 if (ntries == 100) { 3396 printf("%s: timeout waiting for DMA engine\n", 3397 sc->sc_dev.dv_xname); 3398 rt2860_stop(ifp, 1); 3399 return ETIMEDOUT; 3400 } 3401 tmp &= 0xff0; 3402 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3403 3404 /* reset Rx ring and all 6 Tx rings */ 3405 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3406 3407 /* PBF hardware reset */ 3408 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3409 RAL_BARRIER_WRITE(sc); 3410 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3411 3412 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3413 3414 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3415 RAL_BARRIER_WRITE(sc); 3416 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3417 3418 for (i = 0; i < nitems(rt2860_def_mac); i++) 3419 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3420 if (sc->mac_ver >= 0x3071) { 3421 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3422 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3423 4 << RT2860_DLY_PAPE_EN_SHIFT); 3424 } 3425 3426 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3427 sc->sc_flags |= RT2860_PCIE; 3428 /* PCIe has different clock cycle count than PCI */ 3429 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3430 tmp = (tmp & ~0xff) | 0x7d; 3431 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3432 } 3433 3434 /* wait while MAC is busy */ 3435 for (ntries = 0; ntries < 100; ntries++) { 3436 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3437 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3438 break; 3439 DELAY(1000); 3440 } 3441 if (ntries == 100) { 3442 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname); 3443 rt2860_stop(ifp, 1); 3444 return ETIMEDOUT; 3445 } 3446 3447 /* clear Host to MCU mailbox */ 3448 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3449 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3450 3451 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3452 DELAY(1000); 3453 3454 if ((error = rt2860_bbp_init(sc)) != 0) { 3455 rt2860_stop(ifp, 1); 3456 return error; 3457 } 3458 3459 /* clear RX WCID search table */ 3460 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3461 /* clear pairwise key table */ 3462 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3463 /* clear IV/EIV table */ 3464 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3465 /* clear WCID attribute table */ 3466 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3467 /* clear shared key table */ 3468 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3469 /* clear shared key mode */ 3470 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3471 3472 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3473 for (qid = 0; qid < 6; qid++) { 3474 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3475 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3476 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3477 } 3478 3479 /* init Rx ring */ 3480 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3481 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3482 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3483 3484 /* setup maximum buffer sizes */ 3485 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3486 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3487 3488 for (ntries = 0; ntries < 100; ntries++) { 3489 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3490 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3491 break; 3492 DELAY(1000); 3493 } 3494 if (ntries == 100) { 3495 printf("%s: timeout waiting for DMA engine\n", 3496 sc->sc_dev.dv_xname); 3497 rt2860_stop(ifp, 1); 3498 return ETIMEDOUT; 3499 } 3500 tmp &= 0xff0; 3501 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3502 3503 /* disable interrupts mitigation */ 3504 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3505 3506 /* write vendor-specific BBP values (from EEPROM) */ 3507 for (i = 0; i < 8; i++) { 3508 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3509 continue; 3510 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3511 } 3512 3513 /* select Main antenna for 1T1R devices */ 3514 if (sc->rf_rev == RT3070_RF_2020 || 3515 sc->rf_rev == RT3070_RF_3020 || 3516 sc->rf_rev == RT3070_RF_3320) 3517 rt3090_set_rx_antenna(sc, 0); 3518 3519 /* send LEDs operating mode to microcontroller */ 3520 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3521 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3522 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3523 3524 if (sc->mac_ver >= 0x3071) 3525 rt3090_rf_init(sc); 3526 3527 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3528 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3529 3530 if (sc->mac_ver >= 0x3071) 3531 rt3090_rf_wakeup(sc); 3532 3533 /* disable non-existing Rx chains */ 3534 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3535 bbp3 &= ~(1 << 3 | 1 << 4); 3536 if (sc->nrxchains == 2) 3537 bbp3 |= 1 << 3; 3538 else if (sc->nrxchains == 3) 3539 bbp3 |= 1 << 4; 3540 rt2860_mcu_bbp_write(sc, 3, bbp3); 3541 3542 /* disable non-existing Tx chains */ 3543 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3544 if (sc->ntxchains == 1) 3545 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3546 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3547 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3548 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3549 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3550 rt2860_mcu_bbp_write(sc, 1, bbp1); 3551 3552 if (sc->mac_ver >= 0x3071) 3553 rt3090_rf_setup(sc); 3554 3555 /* select default channel */ 3556 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3557 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3558 3559 /* reset RF from MCU */ 3560 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3561 3562 /* set RTS threshold */ 3563 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3564 tmp &= ~0xffff00; 3565 tmp |= ic->ic_rtsthreshold << 8; 3566 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3567 3568 /* setup initial protection mode */ 3569 sc->sc_ic_flags = ic->ic_flags; 3570 rt2860_updateprot(ic); 3571 3572 /* turn radio LED on */ 3573 rt2860_set_leds(sc, RT2860_LED_RADIO); 3574 3575 /* enable Tx/Rx DMA engine */ 3576 if ((error = rt2860_txrx_enable(sc)) != 0) { 3577 rt2860_stop(ifp, 1); 3578 return error; 3579 } 3580 3581 /* clear pending interrupts */ 3582 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3583 /* enable interrupts */ 3584 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3585 3586 if (sc->sc_flags & RT2860_ADVANCED_PS) 3587 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3588 3589 ifp->if_flags &= ~IFF_OACTIVE; 3590 ifp->if_flags |= IFF_RUNNING; 3591 3592 if (ic->ic_flags & IEEE80211_F_WEPON) { 3593 /* install WEP keys */ 3594 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3595 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3596 } 3597 3598 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3599 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3600 else 3601 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3602 3603 return 0; 3604 } 3605 3606 void 3607 rt2860_stop(struct ifnet *ifp, int disable) 3608 { 3609 struct rt2860_softc *sc = ifp->if_softc; 3610 struct ieee80211com *ic = &sc->sc_ic; 3611 uint32_t tmp; 3612 int qid; 3613 3614 if (ifp->if_flags & IFF_RUNNING) 3615 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3616 3617 sc->sc_tx_timer = 0; 3618 ifp->if_timer = 0; 3619 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3620 3621 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 3622 3623 /* disable interrupts */ 3624 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3625 3626 /* disable GP timer */ 3627 rt2860_set_gp_timer(sc, 0); 3628 3629 /* disable Rx */ 3630 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3631 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3632 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3633 3634 /* reset adapter */ 3635 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3636 RAL_BARRIER_WRITE(sc); 3637 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3638 3639 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3640 sc->qfullmsk = 0; 3641 for (qid = 0; qid < 6; qid++) 3642 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3643 rt2860_reset_rx_ring(sc, &sc->rxq); 3644 3645 /* for CardBus, power down the socket */ 3646 if (disable && sc->sc_disable != NULL) { 3647 if (sc->sc_flags & RT2860_ENABLED) { 3648 (*sc->sc_disable)(sc); 3649 sc->sc_flags &= ~RT2860_ENABLED; 3650 } 3651 } 3652 } 3653 3654 int 3655 rt2860_load_microcode(struct rt2860_softc *sc) 3656 { 3657 int ntries; 3658 3659 /* set "host program ram write selection" bit */ 3660 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 3661 /* write microcode image */ 3662 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 3663 /* kick microcontroller unit */ 3664 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 3665 RAL_BARRIER_WRITE(sc); 3666 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 3667 3668 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3669 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3670 3671 /* wait until microcontroller is ready */ 3672 RAL_BARRIER_READ_WRITE(sc); 3673 for (ntries = 0; ntries < 1000; ntries++) { 3674 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 3675 break; 3676 DELAY(1000); 3677 } 3678 if (ntries == 1000) { 3679 printf("%s: timeout waiting for MCU to initialize\n", 3680 sc->sc_dev.dv_xname); 3681 return ETIMEDOUT; 3682 } 3683 return 0; 3684 } 3685 3686 /* 3687 * This function is called periodically to adjust Tx power based on 3688 * temperature variation. 3689 */ 3690 void 3691 rt2860_calib(struct rt2860_softc *sc) 3692 { 3693 struct ieee80211com *ic = &sc->sc_ic; 3694 const uint8_t *tssi; 3695 uint8_t step, bbp49; 3696 int8_t ridx, d; 3697 3698 /* read current temperature */ 3699 bbp49 = rt2860_mcu_bbp_read(sc, 49); 3700 3701 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 3702 tssi = &sc->tssi_2ghz[4]; 3703 step = sc->step_2ghz; 3704 } else { 3705 tssi = &sc->tssi_5ghz[4]; 3706 step = sc->step_5ghz; 3707 } 3708 3709 if (bbp49 < tssi[0]) { /* lower than reference */ 3710 /* use higher Tx power than default */ 3711 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 3712 } else if (bbp49 > tssi[0]) { /* greater than reference */ 3713 /* use lower Tx power than default */ 3714 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 3715 } else { 3716 /* use default Tx power */ 3717 d = 0; 3718 } 3719 d *= step; 3720 3721 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 3722 3723 /* write adjusted Tx power values for each Tx rate */ 3724 for (ridx = 0; ridx < 5; ridx++) { 3725 if (sc->txpow20mhz[ridx] == 0xffffffff) 3726 continue; 3727 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 3728 b4inc(sc->txpow20mhz[ridx], d)); 3729 } 3730 } 3731 3732 void 3733 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 3734 { 3735 uint32_t tmp; 3736 3737 if (aux) { 3738 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3739 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 3740 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3741 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3742 } else { 3743 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3744 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 3745 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3746 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3747 } 3748 } 3749 3750 void 3751 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 3752 { 3753 struct ieee80211com *ic = &sc->sc_ic; 3754 u_int chan, group; 3755 3756 chan = ieee80211_chan2ieee(ic, c); 3757 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3758 return; 3759 3760 if (sc->mac_ver >= 0x3071) 3761 rt3090_set_chan(sc, chan); 3762 else 3763 rt2860_set_chan(sc, chan); 3764 3765 /* determine channel group */ 3766 if (chan <= 14) 3767 group = 0; 3768 else if (chan <= 64) 3769 group = 1; 3770 else if (chan <= 128) 3771 group = 2; 3772 else 3773 group = 3; 3774 3775 /* XXX necessary only when group has changed! */ 3776 rt2860_select_chan_group(sc, group); 3777 3778 DELAY(1000); 3779 } 3780 3781 #ifndef IEEE80211_STA_ONLY 3782 int 3783 rt2860_setup_beacon(struct rt2860_softc *sc) 3784 { 3785 struct ieee80211com *ic = &sc->sc_ic; 3786 struct rt2860_txwi txwi; 3787 struct mbuf *m; 3788 int ridx; 3789 3790 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL) 3791 return ENOBUFS; 3792 3793 memset(&txwi, 0, sizeof txwi); 3794 txwi.wcid = 0xff; 3795 txwi.len = htole16(m->m_pkthdr.len); 3796 /* send beacons at the lowest available rate */ 3797 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 3798 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 3799 txwi.phy = htole16(rt2860_rates[ridx].mcs); 3800 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 3801 txwi.phy |= htole16(RT2860_PHY_OFDM); 3802 txwi.txop = RT2860_TX_TXOP_HT; 3803 txwi.flags = RT2860_TX_TS; 3804 txwi.xflags = RT2860_TX_NSEQ; 3805 3806 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 3807 (uint8_t *)&txwi, sizeof txwi); 3808 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 3809 mtod(m, uint8_t *), m->m_pkthdr.len); 3810 3811 m_freem(m); 3812 3813 return 0; 3814 } 3815 #endif 3816 3817 void 3818 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 3819 { 3820 struct ieee80211com *ic = &sc->sc_ic; 3821 uint32_t tmp; 3822 3823 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 3824 3825 tmp &= ~0x1fffff; 3826 tmp |= ic->ic_bss->ni_intval * 16; 3827 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3828 if (ic->ic_opmode == IEEE80211_M_STA) { 3829 /* 3830 * Local TSF is always updated with remote TSF on beacon 3831 * reception. 3832 */ 3833 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3834 } 3835 #ifndef IEEE80211_STA_ONLY 3836 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3837 tmp |= RT2860_BCN_TX_EN; 3838 /* 3839 * Local TSF is updated with remote TSF on beacon reception 3840 * only if the remote TSF is greater than local TSF. 3841 */ 3842 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3843 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3844 tmp |= RT2860_BCN_TX_EN; 3845 /* SYNC with nobody */ 3846 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3847 } 3848 #endif 3849 3850 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 3851 } 3852