1 /* $OpenBSD: rt2860.c,v 1.33 2009/03/29 21:53:52 sthen Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2860 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/sysctl.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #include <sys/timeout.h> 37 #include <sys/conf.h> 38 #include <sys/device.h> 39 40 #include <machine/bus.h> 41 #include <machine/endian.h> 42 #include <machine/intr.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/if_ether.h> 57 #include <netinet/ip.h> 58 59 #include <net80211/ieee80211_var.h> 60 #include <net80211/ieee80211_amrr.h> 61 #include <net80211/ieee80211_radiotap.h> 62 63 #include <dev/ic/rt2860var.h> 64 #include <dev/ic/rt2860reg.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/rndvar.h> 71 72 #ifdef RAL_DEBUG 73 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 75 int rt2860_debug = 1; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n, x) 79 #endif 80 81 int rt2860_alloc_tx_ring(struct rt2860_softc *, 82 struct rt2860_tx_ring *); 83 void rt2860_reset_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 void rt2860_free_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 int rt2860_alloc_tx_pool(struct rt2860_softc *); 88 void rt2860_free_tx_pool(struct rt2860_softc *); 89 int rt2860_alloc_rx_ring(struct rt2860_softc *, 90 struct rt2860_rx_ring *); 91 void rt2860_reset_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 void rt2860_free_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *); 96 int rt2860_media_change(struct ifnet *); 97 void rt2860_iter_func(void *, struct ieee80211_node *); 98 void rt2860_updatestats(struct rt2860_softc *); 99 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *, 100 int); 101 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 102 int); 103 uint16_t rt2860_eeprom_read(struct rt2860_softc *, uint8_t); 104 void rt2860_intr_coherent(struct rt2860_softc *); 105 void rt2860_drain_stats_fifo(struct rt2860_softc *); 106 void rt2860_tx_intr(struct rt2860_softc *, int); 107 void rt2860_rx_intr(struct rt2860_softc *); 108 void rt2860_tbtt_intr(struct rt2860_softc *); 109 void rt2860_gp_intr(struct rt2860_softc *); 110 int rt2860_tx(struct rt2860_softc *, struct mbuf *, 111 struct ieee80211_node *); 112 void rt2860_start(struct ifnet *); 113 void rt2860_watchdog(struct ifnet *); 114 int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 115 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 116 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 117 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 118 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t); 119 void rt2860_enable_mrr(struct rt2860_softc *); 120 void rt2860_set_txpreamble(struct rt2860_softc *); 121 void rt2860_set_basicrates(struct rt2860_softc *); 122 void rt2860_select_chan_group(struct rt2860_softc *, int); 123 void rt2860_set_chan(struct rt2860_softc *, 124 struct ieee80211_channel *); 125 void rt2860_set_leds(struct rt2860_softc *, uint16_t); 126 void rt2860_set_gp_timer(struct rt2860_softc *, int); 127 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 128 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 129 void rt2860_updateslot(struct ieee80211com *); 130 void rt2860_updateprot(struct ieee80211com *); 131 void rt2860_updateedca(struct ieee80211com *); 132 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 133 struct ieee80211_key *); 134 void rt2860_delete_key(struct ieee80211com *, 135 struct ieee80211_node *, struct ieee80211_key *); 136 #if NBPFILTER > 0 137 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 138 #endif 139 const char * rt2860_get_rf(uint8_t); 140 int rt2860_read_eeprom(struct rt2860_softc *); 141 int rt2860_bbp_init(struct rt2860_softc *); 142 int rt2860_txrx_enable(struct rt2860_softc *); 143 int rt2860_init(struct ifnet *); 144 void rt2860_stop(struct ifnet *, int); 145 int rt2860_load_microcode(struct rt2860_softc *); 146 void rt2860_calib(struct rt2860_softc *); 147 #ifndef IEEE80211_STA_ONLY 148 int rt2860_setup_beacon(struct rt2860_softc *); 149 #endif 150 void rt2860_enable_tsf_sync(struct rt2860_softc *); 151 void rt2860_power(int, void *); 152 153 static const struct { 154 uint32_t reg; 155 uint32_t val; 156 } rt2860_def_mac[] = { 157 RT2860_DEF_MAC 158 }; 159 160 static const struct { 161 uint8_t reg; 162 uint8_t val; 163 } rt2860_def_bbp[] = { 164 RT2860_DEF_BBP 165 }; 166 167 static const struct rfprog { 168 uint8_t chan; 169 uint32_t r1, r2, r3, r4; 170 } rt2860_rf2850[] = { 171 RT2860_RF2850 172 }; 173 174 int 175 rt2860_attach(void *xsc, int id) 176 { 177 struct rt2860_softc *sc = xsc; 178 struct ieee80211com *ic = &sc->sc_ic; 179 struct ifnet *ifp = &ic->ic_if; 180 int i, qid, ntries, error; 181 182 sc->amrr.amrr_min_success_threshold = 1; 183 sc->amrr.amrr_max_success_threshold = 15; 184 185 /* wait for NIC to initialize */ 186 for (ntries = 0; ntries < 100; ntries++) { 187 sc->mac_rev = RAL_READ(sc, RT2860_ASIC_VER_ID); 188 if (sc->mac_rev != 0 && sc->mac_rev != 0xffffffff) 189 break; 190 DELAY(10); 191 } 192 if (ntries == 100) { 193 printf("%s: timeout waiting for NIC to initialize\n", 194 sc->sc_dev.dv_xname); 195 return ETIMEDOUT; 196 } 197 if ((sc->mac_rev >> 16) != 0x2860 && 198 (id == PCI_PRODUCT_RALINK_RT2890 || 199 id == PCI_PRODUCT_RALINK_RT2790 || 200 id == PCI_PRODUCT_AWT_RT2890)) 201 sc->sc_flags |= RT2860_ADVANCED_PS; 202 203 /* retrieve RF rev. no and various other things from EEPROM */ 204 rt2860_read_eeprom(sc); 205 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 206 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n", 207 sc->sc_dev.dv_xname, sc->mac_rev >> 16, sc->mac_rev & 0xffff, 208 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains); 209 210 /* 211 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 212 */ 213 for (qid = 0; qid < 6; qid++) { 214 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 215 printf("%s: could not allocate Tx ring %d\n", 216 sc->sc_dev.dv_xname, qid); 217 goto fail1; 218 } 219 } 220 221 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 222 printf("%s: could not allocate Rx ring\n", 223 sc->sc_dev.dv_xname); 224 goto fail1; 225 } 226 227 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 228 printf("%s: could not allocate Tx pool\n", 229 sc->sc_dev.dv_xname); 230 goto fail2; 231 } 232 233 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 234 sc->mgtqid = (sc->mac_rev == 0x28600100) ? EDCA_AC_VO : 5; 235 236 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 237 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 238 ic->ic_state = IEEE80211_S_INIT; 239 240 /* set device capabilities */ 241 ic->ic_caps = 242 IEEE80211_C_MONITOR | /* monitor mode supported */ 243 #ifndef IEEE80211_STA_ONLY 244 IEEE80211_C_IBSS | /* IBSS mode supported */ 245 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 246 #ifdef notyet 247 IEEE80211_C_APPMGT | /* HostAP power management */ 248 #endif 249 #endif 250 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 251 IEEE80211_C_SHSLOT | /* short slot time supported */ 252 IEEE80211_C_WEP | /* s/w WEP */ 253 IEEE80211_C_RSN; /* WPA/RSN */ 254 255 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 256 /* set supported .11a rates */ 257 ic->ic_sup_rates[IEEE80211_MODE_11A] = 258 ieee80211_std_rateset_11a; 259 260 /* set supported .11a channels */ 261 for (i = 14; i < nitems(rt2860_rf2850); i++) { 262 uint8_t chan = rt2860_rf2850[i].chan; 263 ic->ic_channels[chan].ic_freq = 264 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 265 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 266 } 267 } 268 269 /* set supported .11b and .11g rates */ 270 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 271 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 272 273 /* set supported .11b and .11g channels (1 through 14) */ 274 for (i = 1; i <= 14; i++) { 275 ic->ic_channels[i].ic_freq = 276 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 277 ic->ic_channels[i].ic_flags = 278 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 279 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 280 } 281 282 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 283 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 284 285 ifp->if_softc = sc; 286 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 287 ifp->if_init = rt2860_init; 288 ifp->if_ioctl = rt2860_ioctl; 289 ifp->if_start = rt2860_start; 290 ifp->if_watchdog = rt2860_watchdog; 291 IFQ_SET_READY(&ifp->if_snd); 292 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 293 294 if_attach(ifp); 295 ieee80211_ifattach(ifp); 296 ic->ic_node_alloc = rt2860_node_alloc; 297 ic->ic_newassoc = rt2860_newassoc; 298 ic->ic_updateslot = rt2860_updateslot; 299 ic->ic_updateedca = rt2860_updateedca; 300 ic->ic_set_key = rt2860_set_key; 301 ic->ic_delete_key = rt2860_delete_key; 302 /* override state transition machine */ 303 sc->sc_newstate = ic->ic_newstate; 304 ic->ic_newstate = rt2860_newstate; 305 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status); 306 307 #if NBPFILTER > 0 308 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 309 sizeof (struct ieee80211_frame) + 64); 310 311 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 312 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 313 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 314 315 sc->sc_txtap_len = sizeof sc->sc_txtapu; 316 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 317 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 318 #endif 319 /* 320 * Make sure the interface is shutdown during reboot. 321 */ 322 sc->sc_sdhook = shutdownhook_establish(rt2860_shutdown, sc); 323 if (sc->sc_sdhook == NULL) { 324 printf("%s: WARNING: unable to establish shutdown hook\n", 325 sc->sc_dev.dv_xname); 326 } 327 328 sc->sc_powerhook = powerhook_establish(rt2860_power, sc); 329 if (sc->sc_powerhook == NULL) { 330 printf("%s: WARNING: unable to establish power hook\n", 331 sc->sc_dev.dv_xname); 332 } 333 334 return 0; 335 336 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 337 fail1: while (--qid >= 0) 338 rt2860_free_tx_ring(sc, &sc->txq[qid]); 339 return error; 340 } 341 342 int 343 rt2860_detach(void *xsc) 344 { 345 struct rt2860_softc *sc = xsc; 346 struct ifnet *ifp = &sc->sc_ic.ic_if; 347 int qid; 348 349 ieee80211_ifdetach(ifp); /* free all nodes */ 350 if_detach(ifp); 351 352 if (sc->sc_powerhook != NULL) 353 powerhook_disestablish(sc->sc_powerhook); 354 355 if (sc->sc_sdhook != NULL) 356 shutdownhook_disestablish(sc->sc_sdhook); 357 358 for (qid = 0; qid < 6; qid++) 359 rt2860_free_tx_ring(sc, &sc->txq[qid]); 360 rt2860_free_rx_ring(sc, &sc->rxq); 361 rt2860_free_tx_pool(sc); 362 363 return 0; 364 } 365 366 int 367 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 368 { 369 int nsegs, size, error; 370 371 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 372 373 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 374 BUS_DMA_NOWAIT, &ring->map); 375 if (error != 0) { 376 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 377 goto fail; 378 } 379 380 /* Tx rings must be 4-DWORD aligned */ 381 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 382 &nsegs, BUS_DMA_NOWAIT); 383 if (error != 0) { 384 printf("%s: could not allocate DMA memory\n", 385 sc->sc_dev.dv_xname); 386 goto fail; 387 } 388 389 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 390 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT); 391 if (error != 0) { 392 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 393 goto fail; 394 } 395 396 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 397 BUS_DMA_NOWAIT); 398 if (error != 0) { 399 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 400 goto fail; 401 } 402 403 memset(ring->txd, 0, size); 404 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 405 406 ring->paddr = ring->map->dm_segs[0].ds_addr; 407 408 return 0; 409 410 fail: rt2860_free_tx_ring(sc, ring); 411 return error; 412 } 413 414 void 415 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 416 { 417 struct rt2860_tx_data *data; 418 int i; 419 420 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 421 if ((data = ring->data[i]) == NULL) 422 continue; /* nothing mapped in this slot */ 423 424 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 425 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 426 bus_dmamap_unload(sc->sc_dmat, data->map); 427 m_freem(data->m); 428 data->m= NULL; 429 data->ni = NULL; /* node already freed */ 430 431 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 432 ring->data[i] = NULL; 433 } 434 435 ring->queued = 0; 436 ring->cur = ring->next = 0; 437 } 438 439 void 440 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 441 { 442 struct rt2860_tx_data *data; 443 int i; 444 445 if (ring->txd != NULL) { 446 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 447 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 448 bus_dmamap_unload(sc->sc_dmat, ring->map); 449 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd, 450 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 451 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 452 } 453 if (ring->map != NULL) 454 bus_dmamap_destroy(sc->sc_dmat, ring->map); 455 456 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 457 if ((data = ring->data[i]) == NULL) 458 continue; /* nothing mapped in this slot */ 459 460 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 461 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 462 bus_dmamap_unload(sc->sc_dmat, data->map); 463 m_freem(data->m); 464 465 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 466 } 467 } 468 469 /* 470 * Allocate a pool of TX Wireless Information blocks. 471 */ 472 int 473 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 474 { 475 caddr_t vaddr; 476 bus_addr_t paddr; 477 int i, nsegs, size, error; 478 479 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 480 481 /* init data_pool early in case of failure.. */ 482 SLIST_INIT(&sc->data_pool); 483 484 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 485 BUS_DMA_NOWAIT, &sc->txwi_map); 486 if (error != 0) { 487 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 488 goto fail; 489 } 490 491 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 492 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT); 493 if (error != 0) { 494 printf("%s: could not allocate DMA memory\n", 495 sc->sc_dev.dv_xname); 496 goto fail; 497 } 498 499 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 500 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 501 if (error != 0) { 502 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 503 goto fail; 504 } 505 506 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 507 size, NULL, BUS_DMA_NOWAIT); 508 if (error != 0) { 509 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 510 goto fail; 511 } 512 513 memset(sc->txwi_vaddr, 0, size); 514 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 515 BUS_DMASYNC_PREWRITE); 516 517 vaddr = sc->txwi_vaddr; 518 paddr = sc->txwi_map->dm_segs[0].ds_addr; 519 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 520 struct rt2860_tx_data *data = &sc->data[i]; 521 522 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 523 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 524 &data->map); 525 if (error != 0) { 526 printf("%s: could not create DMA map\n", 527 sc->sc_dev.dv_xname); 528 goto fail; 529 } 530 data->txwi = (struct rt2860_txwi *)vaddr; 531 data->paddr = paddr; 532 vaddr += RT2860_TXWI_DMASZ; 533 paddr += RT2860_TXWI_DMASZ; 534 535 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 536 } 537 538 return 0; 539 540 fail: rt2860_free_tx_pool(sc); 541 return error; 542 } 543 544 void 545 rt2860_free_tx_pool(struct rt2860_softc *sc) 546 { 547 if (sc->txwi_vaddr != NULL) { 548 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 549 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 550 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 551 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 552 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 553 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 554 } 555 if (sc->txwi_map != NULL) 556 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 557 558 while (!SLIST_EMPTY(&sc->data_pool)) { 559 struct rt2860_tx_data *data; 560 data = SLIST_FIRST(&sc->data_pool); 561 bus_dmamap_destroy(sc->sc_dmat, data->map); 562 SLIST_REMOVE_HEAD(&sc->data_pool, next); 563 } 564 } 565 566 int 567 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 568 { 569 int i, nsegs, size, error; 570 571 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 572 573 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 574 BUS_DMA_NOWAIT, &ring->map); 575 if (error != 0) { 576 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 577 goto fail; 578 } 579 580 /* Rx ring must be 4-DWORD aligned */ 581 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 582 &nsegs, BUS_DMA_NOWAIT); 583 if (error != 0) { 584 printf("%s: could not allocate DMA memory\n", 585 sc->sc_dev.dv_xname); 586 goto fail; 587 } 588 589 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 590 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT); 591 if (error != 0) { 592 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 593 goto fail; 594 } 595 596 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 597 BUS_DMA_NOWAIT); 598 if (error != 0) { 599 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 600 goto fail; 601 } 602 603 memset(ring->rxd, 0, size); 604 ring->paddr = ring->map->dm_segs[0].ds_addr; 605 606 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 607 struct rt2860_rx_data *data = &ring->data[i]; 608 struct rt2860_rxd *rxd = &ring->rxd[i]; 609 610 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 611 0, BUS_DMA_NOWAIT, &data->map); 612 if (error != 0) { 613 printf("%s: could not create DMA map\n", 614 sc->sc_dev.dv_xname); 615 goto fail; 616 } 617 618 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 619 if (data->m == NULL) { 620 printf("%s: could not allocate Rx mbuf\n", 621 sc->sc_dev.dv_xname); 622 error = ENOBUFS; 623 goto fail; 624 } 625 MCLGET(data->m, M_DONTWAIT); 626 if (!(data->m->m_flags & M_EXT)) { 627 printf("%s: could not allocate Rx mbuf cluster\n", 628 sc->sc_dev.dv_xname); 629 error = ENOBUFS; 630 goto fail; 631 } 632 633 error = bus_dmamap_load(sc->sc_dmat, data->map, 634 mtod(data->m, void *), MCLBYTES, NULL, 635 BUS_DMA_READ | BUS_DMA_NOWAIT); 636 if (error != 0) { 637 printf("%s: could not load DMA map\n", 638 sc->sc_dev.dv_xname); 639 goto fail; 640 } 641 642 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 643 rxd->sdl0 = htole16(MCLBYTES); 644 } 645 646 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 647 648 return 0; 649 650 fail: rt2860_free_rx_ring(sc, ring); 651 return error; 652 } 653 654 void 655 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 656 { 657 int i; 658 659 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 660 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 661 662 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 663 BUS_DMASYNC_PREWRITE); 664 665 ring->cur = 0; 666 } 667 668 void 669 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 670 { 671 int i; 672 673 if (ring->rxd != NULL) { 674 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 675 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 676 bus_dmamap_unload(sc->sc_dmat, ring->map); 677 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd, 678 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 679 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 680 } 681 if (ring->map != NULL) 682 bus_dmamap_destroy(sc->sc_dmat, ring->map); 683 684 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 685 struct rt2860_rx_data *data = &ring->data[i]; 686 687 if (data->m != NULL) { 688 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 689 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 690 bus_dmamap_unload(sc->sc_dmat, data->map); 691 m_freem(data->m); 692 } 693 if (data->map != NULL) 694 bus_dmamap_destroy(sc->sc_dmat, data->map); 695 } 696 } 697 698 struct ieee80211_node * 699 rt2860_node_alloc(struct ieee80211com *ic) 700 { 701 return malloc(sizeof (struct rt2860_node), M_DEVBUF, 702 M_NOWAIT | M_ZERO); 703 } 704 705 int 706 rt2860_media_change(struct ifnet *ifp) 707 { 708 struct rt2860_softc *sc = ifp->if_softc; 709 struct ieee80211com *ic = &sc->sc_ic; 710 uint8_t rate, ridx; 711 int error; 712 713 error = ieee80211_media_change(ifp); 714 if (error != ENETRESET) 715 return error; 716 717 if (ic->ic_fixed_rate != -1) { 718 rate = ic->ic_sup_rates[ic->ic_curmode]. 719 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 720 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 721 if (rt2860_rates[ridx].rate == rate) 722 break; 723 sc->fixed_ridx = ridx; 724 } 725 726 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 727 rt2860_init(ifp); 728 729 return 0; 730 } 731 732 void 733 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 734 { 735 struct rt2860_softc *sc = arg; 736 uint8_t wcid; 737 738 wcid = RT2860_AID2WCID(ni->ni_associd); 739 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 740 } 741 742 void 743 rt2860_updatestats(struct rt2860_softc *sc) 744 { 745 struct ieee80211com *ic = &sc->sc_ic; 746 747 #ifndef IEEE80211_STA_ONLY 748 /* 749 * In IBSS or HostAP modes (when the hardware sends beacons), the 750 * MAC can run into a livelock and start sending CTS-to-self frames 751 * like crazy if protection is enabled. Fortunately, we can detect 752 * when such a situation occurs and reset the MAC. 753 */ 754 if (ic->ic_curmode != IEEE80211_M_STA) { 755 /* check if we're in a livelock situation.. */ 756 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 757 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 758 /* ..and reset MAC/BBP for a while.. */ 759 DPRINTF(("CTS-to-self livelock detected\n")); 760 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 761 RAL_BARRIER_WRITE(sc); 762 DELAY(1); 763 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 764 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 765 } 766 } 767 #endif 768 if (ic->ic_opmode == IEEE80211_M_STA) 769 rt2860_iter_func(sc, ic->ic_bss); 770 #ifndef IEEE80211_STA_ONLY 771 else 772 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc); 773 #endif 774 } 775 776 void 777 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 778 { 779 struct rt2860_softc *sc = ic->ic_softc; 780 struct rt2860_node *rn = (void *)ni; 781 struct ieee80211_rateset *rs = &ni->ni_rates; 782 uint8_t rate, wcid = 0; 783 int ridx, i, j; 784 785 if (isnew && ni->ni_associd != 0) { 786 /* only interested in true associations */ 787 wcid = RT2860_AID2WCID(ni->ni_associd); 788 789 /* init WCID table entry */ 790 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 791 ni->ni_macaddr, IEEE80211_ADDR_LEN); 792 } 793 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 794 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 795 796 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 797 /* start at lowest available bit-rate, AMRR will raise */ 798 ni->ni_txrate = 0; 799 800 for (i = 0; i < rs->rs_nrates; i++) { 801 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 802 /* convert 802.11 rate to hardware rate index */ 803 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 804 if (rt2860_rates[ridx].rate == rate) 805 break; 806 rn->ridx[i] = ridx; 807 /* determine rate of control response frames */ 808 for (j = i; j >= 0; j--) { 809 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 810 rt2860_rates[rn->ridx[i]].phy == 811 rt2860_rates[rn->ridx[j]].phy) 812 break; 813 } 814 if (j >= 0) { 815 rn->ctl_ridx[i] = rn->ridx[j]; 816 } else { 817 /* no basic rate found, use mandatory one */ 818 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 819 } 820 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 821 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 822 } 823 } 824 825 int 826 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 827 { 828 struct rt2860_softc *sc = ic->ic_if.if_softc; 829 enum ieee80211_state ostate; 830 uint32_t tmp; 831 832 ostate = ic->ic_state; 833 834 if (ostate == IEEE80211_S_RUN) { 835 /* turn link LED off */ 836 rt2860_set_leds(sc, RT2860_LED_RADIO); 837 } 838 839 switch (nstate) { 840 case IEEE80211_S_INIT: 841 if (ostate == IEEE80211_S_RUN) { 842 /* abort TSF synchronization */ 843 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 844 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 845 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 846 RT2860_TBTT_TIMER_EN)); 847 } 848 rt2860_set_gp_timer(sc, 0); 849 break; 850 851 case IEEE80211_S_SCAN: 852 rt2860_set_chan(sc, ic->ic_bss->ni_chan); 853 if (ostate != IEEE80211_S_SCAN) 854 rt2860_set_gp_timer(sc, 150); 855 break; 856 857 case IEEE80211_S_AUTH: 858 case IEEE80211_S_ASSOC: 859 rt2860_set_gp_timer(sc, 0); 860 rt2860_set_chan(sc, ic->ic_bss->ni_chan); 861 break; 862 863 case IEEE80211_S_RUN: 864 rt2860_set_gp_timer(sc, 0); 865 rt2860_set_chan(sc, ic->ic_bss->ni_chan); 866 867 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 868 rt2860_updateslot(ic); 869 rt2860_enable_mrr(sc); 870 rt2860_set_txpreamble(sc); 871 rt2860_set_basicrates(sc); 872 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 873 } 874 875 #ifndef IEEE80211_STA_ONLY 876 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 877 ic->ic_opmode == IEEE80211_M_IBSS) 878 (void)rt2860_setup_beacon(sc); 879 #endif 880 881 if (ic->ic_opmode == IEEE80211_M_STA) { 882 /* fake a join to init the tx rate */ 883 rt2860_newassoc(ic, ic->ic_bss, 1); 884 } 885 886 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 887 rt2860_enable_tsf_sync(sc); 888 rt2860_set_gp_timer(sc, 500); 889 } 890 891 /* turn link LED on */ 892 rt2860_set_leds(sc, RT2860_LED_RADIO | 893 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 894 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 895 break; 896 } 897 898 return sc->sc_newstate(ic, nstate, arg); 899 } 900 901 /* 902 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 903 * 93C66 or 93C86). 904 */ 905 uint16_t 906 rt2860_eeprom_read(struct rt2860_softc *sc, uint8_t addr) 907 { 908 uint32_t tmp; 909 uint16_t val; 910 int n; 911 912 /* clock C once before the first command */ 913 RT2860_EEPROM_CTL(sc, 0); 914 915 RT2860_EEPROM_CTL(sc, RT2860_S); 916 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 917 RT2860_EEPROM_CTL(sc, RT2860_S); 918 919 /* write start bit (1) */ 920 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 921 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 922 923 /* write READ opcode (10) */ 924 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 925 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 926 RT2860_EEPROM_CTL(sc, RT2860_S); 927 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 928 929 /* write address (A5-A0 or A7-A0) */ 930 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 931 for (; n >= 0; n--) { 932 RT2860_EEPROM_CTL(sc, RT2860_S | 933 (((addr >> n) & 1) << RT2860_SHIFT_D)); 934 RT2860_EEPROM_CTL(sc, RT2860_S | 935 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 936 } 937 938 RT2860_EEPROM_CTL(sc, RT2860_S); 939 940 /* read data Q15-Q0 */ 941 val = 0; 942 for (n = 15; n >= 0; n--) { 943 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 944 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 945 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 946 RT2860_EEPROM_CTL(sc, RT2860_S); 947 } 948 949 RT2860_EEPROM_CTL(sc, 0); 950 951 /* clear Chip Select and clock C */ 952 RT2860_EEPROM_CTL(sc, RT2860_S); 953 RT2860_EEPROM_CTL(sc, 0); 954 RT2860_EEPROM_CTL(sc, RT2860_C); 955 956 return val; 957 } 958 959 void 960 rt2860_intr_coherent(struct rt2860_softc *sc) 961 { 962 uint32_t tmp; 963 964 /* DMA finds data coherent event when checking the DDONE bit */ 965 966 DPRINTF(("Tx/Rx Coherent interrupt\n")); 967 968 /* restart DMA engine */ 969 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 970 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 971 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 972 973 (void)rt2860_txrx_enable(sc); 974 } 975 976 void 977 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 978 { 979 struct ifnet *ifp = &sc->sc_ic.ic_if; 980 struct ieee80211_amrr_node *amn; 981 uint32_t stat; 982 uint8_t wcid, mcs, pid; 983 984 /* drain Tx status FIFO (maxsize = 16) */ 985 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 986 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 987 988 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 989 990 /* if no ACK was requested, no feedback is available */ 991 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 992 continue; 993 994 /* update per-STA AMRR stats */ 995 amn = &sc->amn[wcid]; 996 amn->amn_txcnt++; 997 if (stat & RT2860_TXQ_OK) { 998 /* 999 * Check if there were retries, ie if the Tx success 1000 * rate is different from the requested rate. Note 1001 * that it works only because we do not allow rate 1002 * fallback from OFDM to CCK. 1003 */ 1004 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1005 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1006 if (mcs + 1 != pid) 1007 amn->amn_retrycnt++; 1008 } else { 1009 amn->amn_retrycnt++; 1010 ifp->if_oerrors++; 1011 } 1012 } 1013 } 1014 1015 void 1016 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1017 { 1018 struct ieee80211com *ic = &sc->sc_ic; 1019 struct ifnet *ifp = &ic->ic_if; 1020 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1021 uint32_t hw; 1022 1023 rt2860_drain_stats_fifo(sc); 1024 1025 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1026 while (ring->next != hw) { 1027 struct rt2860_tx_data *data = ring->data[ring->next]; 1028 1029 if (data != NULL) { 1030 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1031 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1032 bus_dmamap_unload(sc->sc_dmat, data->map); 1033 m_freem(data->m); 1034 data->m= NULL; 1035 ieee80211_release_node(ic, data->ni); 1036 data->ni = NULL; 1037 1038 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1039 ring->data[ring->next] = NULL; 1040 1041 ifp->if_opackets++; 1042 } 1043 ring->queued--; 1044 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1045 } 1046 1047 sc->sc_tx_timer = 0; 1048 if (ring->queued < RT2860_TX_RING_COUNT) 1049 sc->qfullmsk &= ~(1 << qid); 1050 ifp->if_flags &= ~IFF_OACTIVE; 1051 rt2860_start(ifp); 1052 } 1053 1054 /* 1055 * Return the Rx chain with the highest RSSI for a given frame. 1056 */ 1057 static __inline uint8_t 1058 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1059 { 1060 uint8_t rxchain = 0; 1061 1062 if (sc->nrxchains > 1) { 1063 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1064 rxchain = 1; 1065 if (sc->nrxchains > 2) 1066 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1067 rxchain = 2; 1068 } 1069 return rxchain; 1070 } 1071 1072 void 1073 rt2860_rx_intr(struct rt2860_softc *sc) 1074 { 1075 struct ieee80211com *ic = &sc->sc_ic; 1076 struct ifnet *ifp = &ic->ic_if; 1077 struct ieee80211_frame *wh; 1078 struct ieee80211_rxinfo rxi; 1079 struct ieee80211_node *ni; 1080 struct mbuf *m, *m1; 1081 uint32_t hw; 1082 uint8_t ant, rssi; 1083 int error; 1084 #if NBPFILTER > 0 1085 struct rt2860_rx_radiotap_header *tap; 1086 struct mbuf mb; 1087 uint16_t phy; 1088 #endif 1089 1090 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1091 while (sc->rxq.cur != hw) { 1092 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1093 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1094 struct rt2860_rxwi *rxwi; 1095 1096 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1097 sc->rxq.cur * sizeof (struct rt2860_rxd), 1098 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1099 1100 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1101 DPRINTF(("RXD DDONE bit not set!\n")); 1102 break; /* should not happen */ 1103 } 1104 1105 if (__predict_false(rxd->flags & 1106 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1107 ifp->if_ierrors++; 1108 goto skip; 1109 } 1110 1111 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1112 /* report MIC failures to net80211 for TKIP */ 1113 ic->ic_stats.is_rx_locmicfail++; 1114 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1115 ifp->if_ierrors++; 1116 goto skip; 1117 } 1118 1119 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1120 if (__predict_false(m1 == NULL)) { 1121 ifp->if_ierrors++; 1122 goto skip; 1123 } 1124 MCLGET(m1, M_DONTWAIT); 1125 if (__predict_false(!(m1->m_flags & M_EXT))) { 1126 m_freem(m1); 1127 ifp->if_ierrors++; 1128 goto skip; 1129 } 1130 1131 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1132 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1133 bus_dmamap_unload(sc->sc_dmat, data->map); 1134 1135 error = bus_dmamap_load(sc->sc_dmat, data->map, 1136 mtod(m1, void *), MCLBYTES, NULL, 1137 BUS_DMA_READ | BUS_DMA_NOWAIT); 1138 if (__predict_false(error != 0)) { 1139 m_freem(m1); 1140 1141 /* try to reload the old mbuf */ 1142 error = bus_dmamap_load(sc->sc_dmat, data->map, 1143 mtod(data->m, void *), MCLBYTES, NULL, 1144 BUS_DMA_READ | BUS_DMA_NOWAIT); 1145 if (__predict_false(error != 0)) { 1146 panic("%s: could not load old rx mbuf", 1147 sc->sc_dev.dv_xname); 1148 } 1149 /* physical address may have changed */ 1150 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1151 ifp->if_ierrors++; 1152 goto skip; 1153 } 1154 1155 /* 1156 * New mbuf successfully loaded, update Rx ring and continue 1157 * processing. 1158 */ 1159 m = data->m; 1160 data->m = m1; 1161 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1162 1163 rxwi = mtod(m, struct rt2860_rxwi *); 1164 1165 /* finalize mbuf */ 1166 m->m_pkthdr.rcvif = ifp; 1167 m->m_data = (caddr_t)(rxwi + 1); 1168 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff; 1169 1170 wh = mtod(m, struct ieee80211_frame *); 1171 rxi.rxi_flags = 0; 1172 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1173 /* frame is decrypted by hardware */ 1174 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1175 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1176 } 1177 1178 /* HW may insert 2 padding bytes after 802.11 header */ 1179 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1180 u_int hdrlen = ieee80211_get_hdrlen(wh); 1181 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1182 m->m_data += 2; 1183 wh = mtod(m, struct ieee80211_frame *); 1184 } 1185 1186 ant = rt2860_maxrssi_chain(sc, rxwi); 1187 rssi = rxwi->rssi[ant]; 1188 1189 #if NBPFILTER > 0 1190 if (__predict_true(sc->sc_drvbpf == NULL)) 1191 goto skipbpf; 1192 1193 tap = &sc->sc_rxtap; 1194 tap->wr_flags = 0; 1195 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1196 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1197 tap->wr_antsignal = rssi; 1198 tap->wr_antenna = ant; 1199 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1200 tap->wr_rate = 2; /* in case it can't be found below */ 1201 phy = letoh16(rxwi->phy); 1202 switch (phy & RT2860_PHY_MODE) { 1203 case RT2860_PHY_CCK: 1204 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1205 case 0: tap->wr_rate = 2; break; 1206 case 1: tap->wr_rate = 4; break; 1207 case 2: tap->wr_rate = 11; break; 1208 case 3: tap->wr_rate = 22; break; 1209 } 1210 if (phy & RT2860_PHY_SHPRE) 1211 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1212 break; 1213 case RT2860_PHY_OFDM: 1214 switch (phy & RT2860_PHY_MCS) { 1215 case 0: tap->wr_rate = 12; break; 1216 case 1: tap->wr_rate = 18; break; 1217 case 2: tap->wr_rate = 24; break; 1218 case 3: tap->wr_rate = 36; break; 1219 case 4: tap->wr_rate = 48; break; 1220 case 5: tap->wr_rate = 72; break; 1221 case 6: tap->wr_rate = 96; break; 1222 case 7: tap->wr_rate = 108; break; 1223 } 1224 break; 1225 } 1226 mb.m_data = (caddr_t)tap; 1227 mb.m_len = sc->sc_rxtap_len; 1228 mb.m_next = m; 1229 mb.m_nextpkt = NULL; 1230 mb.m_type = 0; 1231 mb.m_flags = 0; 1232 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1233 skipbpf: 1234 #endif 1235 /* grab a reference to the source node */ 1236 ni = ieee80211_find_rxnode(ic, wh); 1237 1238 /* send the frame to the 802.11 layer */ 1239 rxi.rxi_rssi = rssi; 1240 rxi.rxi_tstamp = 0; /* unused */ 1241 ieee80211_input(ifp, m, ni, &rxi); 1242 1243 /* node is no longer needed */ 1244 ieee80211_release_node(ic, ni); 1245 1246 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1247 1248 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1249 sc->rxq.cur * sizeof (struct rt2860_rxd), 1250 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1251 1252 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1253 } 1254 1255 /* tell HW what we have processed */ 1256 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1257 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1258 } 1259 1260 void 1261 rt2860_tbtt_intr(struct rt2860_softc *sc) 1262 { 1263 struct ieee80211com *ic = &sc->sc_ic; 1264 1265 #ifndef IEEE80211_STA_ONLY 1266 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1267 /* one less beacon until next DTIM */ 1268 if (ic->ic_dtim_count == 0) 1269 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1270 else 1271 ic->ic_dtim_count--; 1272 1273 /* update dynamic parts of beacon */ 1274 rt2860_setup_beacon(sc); 1275 1276 /* flush buffered multicast frames */ 1277 if (ic->ic_dtim_count == 0) 1278 ieee80211_notify_dtim(ic); 1279 } 1280 #endif 1281 /* check if protection mode has changed */ 1282 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1283 rt2860_updateprot(ic); 1284 sc->sc_ic_flags = ic->ic_flags; 1285 } 1286 } 1287 1288 void 1289 rt2860_gp_intr(struct rt2860_softc *sc) 1290 { 1291 struct ieee80211com *ic = &sc->sc_ic; 1292 1293 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1294 1295 if (ic->ic_state == IEEE80211_S_SCAN) 1296 ieee80211_next_scan(&ic->ic_if); 1297 else if (ic->ic_state == IEEE80211_S_RUN) 1298 rt2860_updatestats(sc); 1299 } 1300 1301 int 1302 rt2860_intr(void *arg) 1303 { 1304 struct rt2860_softc *sc = arg; 1305 uint32_t r; 1306 1307 r = RAL_READ(sc, RT2860_INT_STATUS); 1308 if (__predict_false(r == 0xffffffff)) 1309 return 0; /* device likely went away */ 1310 if (r == 0) 1311 return 0; /* not for us */ 1312 1313 /* acknowledge interrupts */ 1314 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1315 1316 if (r & RT2860_TX_RX_COHERENT) 1317 rt2860_intr_coherent(sc); 1318 1319 if (r & RT2860_MAC_INT_2) /* TX status */ 1320 rt2860_drain_stats_fifo(sc); 1321 1322 if (r & RT2860_TX_DONE_INT5) 1323 rt2860_tx_intr(sc, 5); 1324 1325 if (r & RT2860_RX_DONE_INT) 1326 rt2860_rx_intr(sc); 1327 1328 if (r & RT2860_TX_DONE_INT4) 1329 rt2860_tx_intr(sc, 4); 1330 1331 if (r & RT2860_TX_DONE_INT3) 1332 rt2860_tx_intr(sc, 3); 1333 1334 if (r & RT2860_TX_DONE_INT2) 1335 rt2860_tx_intr(sc, 2); 1336 1337 if (r & RT2860_TX_DONE_INT1) 1338 rt2860_tx_intr(sc, 1); 1339 1340 if (r & RT2860_TX_DONE_INT0) 1341 rt2860_tx_intr(sc, 0); 1342 1343 if (r & RT2860_MAC_INT_0) /* TBTT */ 1344 rt2860_tbtt_intr(sc); 1345 1346 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1347 /* TBD wakeup */; 1348 1349 if (r & RT2860_MAC_INT_4) /* GP timer */ 1350 rt2860_gp_intr(sc); 1351 1352 return 1; 1353 } 1354 1355 int 1356 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1357 { 1358 struct ieee80211com *ic = &sc->sc_ic; 1359 struct rt2860_node *rn = (void *)ni; 1360 struct rt2860_tx_ring *ring; 1361 struct rt2860_tx_data *data; 1362 struct rt2860_txd *txd; 1363 struct rt2860_txwi *txwi; 1364 struct ieee80211_frame *wh; 1365 struct mbuf *m1; 1366 bus_dma_segment_t *seg; 1367 u_int hdrlen; 1368 uint16_t qos, dur; 1369 uint8_t type, qsel, mcs, pid, tid, qid; 1370 int nsegs, ntxds, hasqos, ridx, ctl_ridx, error; 1371 1372 /* the data pool contains at least one element, pick the first */ 1373 data = SLIST_FIRST(&sc->data_pool); 1374 1375 wh = mtod(m, struct ieee80211_frame *); 1376 hdrlen = ieee80211_get_hdrlen(wh); 1377 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1378 1379 if ((hasqos = ieee80211_has_qos(wh))) { 1380 qos = ieee80211_get_qos(wh); 1381 tid = qos & IEEE80211_QOS_TID; 1382 qid = ieee80211_up_to_ac(ic, tid); 1383 } else { 1384 tid = 0; 1385 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1386 sc->mgtqid : EDCA_AC_BE; 1387 } 1388 ring = &sc->txq[qid]; 1389 1390 /* pickup a rate index */ 1391 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1392 type != IEEE80211_FC0_TYPE_DATA) { 1393 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1394 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1395 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1396 } else if (ic->ic_fixed_rate != -1) { 1397 ridx = sc->fixed_ridx; 1398 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1399 } else { 1400 ridx = rn->ridx[ni->ni_txrate]; 1401 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1402 } 1403 1404 /* get MCS code from rate index */ 1405 mcs = rt2860_rates[ridx].mcs; 1406 1407 /* setup TX Wireless Information */ 1408 txwi = data->txwi; 1409 txwi->flags = 0; 1410 txwi->xflags = 0; 1411 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 1412 RT2860_AID2WCID(ni->ni_associd) : 0xff; 1413 txwi->len = htole16(m->m_pkthdr.len); 1414 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1415 txwi->phy = htole16(RT2860_PHY_CCK); 1416 if (ridx != RT2860_RIDX_CCK1 && 1417 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1418 mcs |= RT2860_PHY_SHPRE; 1419 } else 1420 txwi->phy = htole16(RT2860_PHY_OFDM); 1421 txwi->phy |= htole16(mcs); 1422 1423 /* 1424 * We store the MCS code into the driver-private PacketID field. 1425 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1426 * that we know at which initial rate the frame was transmitted. 1427 * We add 1 to the MCS code because setting the PacketID field to 1428 * 0 means that we don't want feedback in TX_STAT_FIFO. 1429 */ 1430 pid = (mcs + 1) & 0xf; 1431 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1432 1433 /* check if RTS/CTS or CTS-to-self protection is required */ 1434 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1435 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1436 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1437 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1438 txwi->txop = RT2860_TX_TXOP_HT; 1439 else 1440 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1441 1442 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1443 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 1444 IEEE80211_QOS_ACK_POLICY_NOACK)) { 1445 txwi->xflags |= RT2860_TX_ACK; 1446 1447 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1448 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1449 else 1450 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1451 *(uint16_t *)wh->i_dur = htole16(dur + sc->sifs); 1452 } 1453 #ifndef IEEE80211_STA_ONLY 1454 /* ask MAC to insert timestamp into probe responses */ 1455 if ((wh->i_fc[0] & 1456 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1457 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1458 /* NOTE: beacons do not pass through tx_data() */ 1459 txwi->flags |= RT2860_TX_TS; 1460 #endif 1461 1462 #if NBPFILTER > 0 1463 if (__predict_false(sc->sc_drvbpf != NULL)) { 1464 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1465 struct mbuf mb; 1466 1467 tap->wt_flags = 0; 1468 tap->wt_rate = rt2860_rates[ridx].rate; 1469 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1470 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1471 tap->wt_hwqueue = qid; 1472 if (mcs & RT2860_PHY_SHPRE) 1473 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1474 1475 mb.m_data = (caddr_t)tap; 1476 mb.m_len = sc->sc_txtap_len; 1477 mb.m_next = m; 1478 mb.m_nextpkt = NULL; 1479 mb.m_type = 0; 1480 mb.m_flags = 0; 1481 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1482 } 1483 #endif 1484 1485 /* copy and trim 802.11 header */ 1486 memcpy(txwi + 1, wh, hdrlen); 1487 m_adj(m, hdrlen); 1488 1489 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1490 BUS_DMA_NOWAIT); 1491 if (__predict_false(error != 0 && error != EFBIG)) { 1492 printf("%s: can't map mbuf (error %d)\n", 1493 sc->sc_dev.dv_xname, error); 1494 m_freem(m); 1495 return error; 1496 } 1497 if (__predict_true(error == 0)) { 1498 /* determine how many TXDs are required */ 1499 ntxds = 1 + (data->map->dm_nsegs / 2); 1500 1501 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1502 /* not enough free TXDs, force mbuf defrag */ 1503 bus_dmamap_unload(sc->sc_dmat, data->map); 1504 error = EFBIG; 1505 } 1506 } 1507 if (__predict_false(error != 0)) { 1508 /* too many fragments, linearize */ 1509 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1510 if (m1 == NULL) { 1511 m_freem(m); 1512 return ENOBUFS; 1513 } 1514 if (m->m_pkthdr.len > MHLEN) { 1515 MCLGET(m1, M_DONTWAIT); 1516 if (!(m1->m_flags & M_EXT)) { 1517 m_freem(m); 1518 m_freem(m1); 1519 return ENOBUFS; 1520 } 1521 } 1522 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1523 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1524 m_freem(m); 1525 m = m1; 1526 1527 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1528 BUS_DMA_NOWAIT); 1529 if (__predict_false(error != 0)) { 1530 printf("%s: can't map mbuf (error %d)\n", 1531 sc->sc_dev.dv_xname, error); 1532 m_freem(m); 1533 return error; 1534 } 1535 1536 /* determine how many TXDs are now required */ 1537 ntxds = 1 + (data->map->dm_nsegs / 2); 1538 1539 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1540 /* this is a hopeless case, drop the mbuf! */ 1541 bus_dmamap_unload(sc->sc_dmat, data->map); 1542 m_freem(m); 1543 return ENOBUFS; 1544 } 1545 } 1546 1547 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1548 1549 /* first segment is TXWI + 802.11 header */ 1550 txd = &ring->txd[ring->cur]; 1551 txd->sdp0 = htole32(data->paddr); 1552 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1553 txd->flags = qsel; 1554 1555 /* setup payload segments */ 1556 seg = data->map->dm_segs; 1557 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1558 txd->sdp1 = htole32(seg->ds_addr); 1559 txd->sdl1 = htole16(seg->ds_len); 1560 seg++; 1561 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1562 /* grab a new Tx descriptor */ 1563 txd = &ring->txd[ring->cur]; 1564 txd->sdp0 = htole32(seg->ds_addr); 1565 txd->sdl0 = htole16(seg->ds_len); 1566 txd->flags = qsel; 1567 seg++; 1568 } 1569 /* finalize last segment */ 1570 if (nsegs > 0) { 1571 txd->sdp1 = htole32(seg->ds_addr); 1572 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1573 } else { 1574 txd->sdl0 |= htole16(RT2860_TX_LS0); 1575 txd->sdl1 = 0; 1576 } 1577 1578 /* remove from the free pool and link it into the SW Tx slot */ 1579 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1580 data->m = m; 1581 data->ni = ni; 1582 ring->data[ring->cur] = data; 1583 1584 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1585 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1586 BUS_DMASYNC_PREWRITE); 1587 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1588 BUS_DMASYNC_PREWRITE); 1589 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1590 BUS_DMASYNC_PREWRITE); 1591 1592 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1593 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1594 1595 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1596 ring->queued += ntxds; 1597 if (ring->queued >= RT2860_TX_RING_COUNT) 1598 sc->qfullmsk |= 1 << qid; 1599 1600 /* kick Tx */ 1601 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1602 1603 return 0; 1604 } 1605 1606 void 1607 rt2860_start(struct ifnet *ifp) 1608 { 1609 struct rt2860_softc *sc = ifp->if_softc; 1610 struct ieee80211com *ic = &sc->sc_ic; 1611 struct ieee80211_node *ni; 1612 struct mbuf *m; 1613 1614 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1615 return; 1616 1617 for (;;) { 1618 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1619 ifp->if_flags |= IFF_OACTIVE; 1620 break; 1621 } 1622 /* send pending management frames first */ 1623 IF_DEQUEUE(&ic->ic_mgtq, m); 1624 if (m != NULL) { 1625 ni = (void *)m->m_pkthdr.rcvif; 1626 goto sendit; 1627 } 1628 if (ic->ic_state != IEEE80211_S_RUN) 1629 break; 1630 1631 /* send buffered frames for power-save mode */ 1632 IF_DEQUEUE(&ic->ic_pwrsaveq, m); 1633 if (m != NULL) { 1634 ni = (void *)m->m_pkthdr.rcvif; 1635 goto sendit; 1636 } 1637 1638 /* encapsulate and send data frames */ 1639 IFQ_DEQUEUE(&ifp->if_snd, m); 1640 if (m == NULL) 1641 break; 1642 #if NBPFILTER > 0 1643 if (ifp->if_bpf != NULL) 1644 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1645 #endif 1646 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1647 continue; 1648 sendit: 1649 #if NBPFILTER > 0 1650 if (ic->ic_rawbpf != NULL) 1651 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1652 #endif 1653 if (rt2860_tx(sc, m, ni) != 0) { 1654 ieee80211_release_node(ic, ni); 1655 ifp->if_oerrors++; 1656 continue; 1657 } 1658 1659 sc->sc_tx_timer = 5; 1660 ifp->if_timer = 1; 1661 } 1662 } 1663 1664 void 1665 rt2860_watchdog(struct ifnet *ifp) 1666 { 1667 struct rt2860_softc *sc = ifp->if_softc; 1668 1669 ifp->if_timer = 0; 1670 1671 if (sc->sc_tx_timer > 0) { 1672 if (--sc->sc_tx_timer == 0) { 1673 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1674 rt2860_init(ifp); 1675 ifp->if_oerrors++; 1676 return; 1677 } 1678 ifp->if_timer = 1; 1679 } 1680 1681 ieee80211_watchdog(ifp); 1682 } 1683 1684 int 1685 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1686 { 1687 struct rt2860_softc *sc = ifp->if_softc; 1688 struct ieee80211com *ic = &sc->sc_ic; 1689 struct ifaddr *ifa; 1690 struct ifreq *ifr; 1691 int s, error = 0; 1692 1693 s = splnet(); 1694 1695 switch (cmd) { 1696 case SIOCSIFADDR: 1697 ifa = (struct ifaddr *)data; 1698 ifp->if_flags |= IFF_UP; 1699 #ifdef INET 1700 if (ifa->ifa_addr->sa_family == AF_INET) 1701 arp_ifinit(&ic->ic_ac, ifa); 1702 #endif 1703 /* FALLTHROUGH */ 1704 case SIOCSIFFLAGS: 1705 if (ifp->if_flags & IFF_UP) { 1706 if (!(ifp->if_flags & IFF_RUNNING)) 1707 rt2860_init(ifp); 1708 } else { 1709 if (ifp->if_flags & IFF_RUNNING) 1710 rt2860_stop(ifp, 1); 1711 } 1712 break; 1713 1714 case SIOCADDMULTI: 1715 case SIOCDELMULTI: 1716 ifr = (struct ifreq *)data; 1717 error = (cmd == SIOCADDMULTI) ? 1718 ether_addmulti(ifr, &ic->ic_ac) : 1719 ether_delmulti(ifr, &ic->ic_ac); 1720 1721 if (error == ENETRESET) 1722 error = 0; 1723 break; 1724 1725 case SIOCS80211CHANNEL: 1726 /* 1727 * This allows for fast channel switching in monitor mode 1728 * (used by kismet). In IBSS mode, we must explicitly reset 1729 * the interface to generate a new beacon frame. 1730 */ 1731 error = ieee80211_ioctl(ifp, cmd, data); 1732 if (error == ENETRESET && 1733 ic->ic_opmode == IEEE80211_M_MONITOR) { 1734 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1735 (IFF_UP | IFF_RUNNING)) 1736 rt2860_set_chan(sc, ic->ic_ibss_chan); 1737 error = 0; 1738 } 1739 break; 1740 1741 default: 1742 error = ieee80211_ioctl(ifp, cmd, data); 1743 } 1744 1745 if (error == ENETRESET) { 1746 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1747 (IFF_UP | IFF_RUNNING)) 1748 rt2860_init(ifp); 1749 error = 0; 1750 } 1751 1752 splx(s); 1753 1754 return error; 1755 } 1756 1757 /* 1758 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1759 * We access the BBP through the 8051 microcontroller unit which means that 1760 * the microcode must be loaded first. 1761 */ 1762 void 1763 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1764 { 1765 int ntries; 1766 1767 for (ntries = 0; ntries < 100; ntries++) { 1768 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1769 break; 1770 DELAY(1); 1771 } 1772 if (ntries == 100) { 1773 printf("%s: could not write to BBP through MCU\n", 1774 sc->sc_dev.dv_xname); 1775 return; 1776 } 1777 1778 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1779 RT2860_BBP_CSR_KICK | reg << 8 | val); 1780 RAL_BARRIER_WRITE(sc); 1781 1782 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0); 1783 DELAY(1000); 1784 } 1785 1786 uint8_t 1787 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1788 { 1789 uint32_t val; 1790 int ntries; 1791 1792 for (ntries = 0; ntries < 100; ntries++) { 1793 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1794 break; 1795 DELAY(1); 1796 } 1797 if (ntries == 100) { 1798 printf("%s: could not read from BBP through MCU\n", 1799 sc->sc_dev.dv_xname); 1800 return 0; 1801 } 1802 1803 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1804 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1805 RAL_BARRIER_WRITE(sc); 1806 1807 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0); 1808 DELAY(1000); 1809 1810 for (ntries = 0; ntries < 100; ntries++) { 1811 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1812 if (!(val & RT2860_BBP_CSR_KICK)) 1813 return val & 0xff; 1814 DELAY(1); 1815 } 1816 printf("%s: could not read from BBP through MCU\n", 1817 sc->sc_dev.dv_xname); 1818 1819 return 0; 1820 } 1821 1822 /* 1823 * Write to one of the 4 programmable 24-bit RF registers. 1824 */ 1825 void 1826 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 1827 { 1828 uint32_t tmp; 1829 int ntries; 1830 1831 for (ntries = 0; ntries < 100; ntries++) { 1832 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 1833 break; 1834 DELAY(1); 1835 } 1836 if (ntries == 100) { 1837 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1838 return; 1839 } 1840 1841 /* RF registers are 24-bit on the RT2860 */ 1842 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1843 (val & 0x3fffff) << 2 | (reg & 3); 1844 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 1845 } 1846 1847 /* 1848 * Send a command to the 8051 microcontroller unit. 1849 */ 1850 int 1851 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg) 1852 { 1853 int ntries; 1854 1855 for (ntries = 0; ntries < 100; ntries++) { 1856 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 1857 break; 1858 DELAY(2); 1859 } 1860 if (ntries == 100) 1861 return EIO; 1862 1863 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 1864 RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg); 1865 RAL_BARRIER_WRITE(sc); 1866 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 1867 1868 return 0; 1869 } 1870 1871 void 1872 rt2860_enable_mrr(struct rt2860_softc *sc) 1873 { 1874 #define CCK(mcs) (mcs) 1875 #define OFDM(mcs) (1 << 3 | (mcs)) 1876 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 1877 OFDM(6) << 28 | /* 54->48 */ 1878 OFDM(5) << 24 | /* 48->36 */ 1879 OFDM(4) << 20 | /* 36->24 */ 1880 OFDM(3) << 16 | /* 24->18 */ 1881 OFDM(2) << 12 | /* 18->12 */ 1882 OFDM(1) << 8 | /* 12-> 9 */ 1883 OFDM(0) << 4 | /* 9-> 6 */ 1884 OFDM(0)); /* 6-> 6 */ 1885 1886 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 1887 CCK(2) << 12 | /* 11->5.5 */ 1888 CCK(1) << 8 | /* 5.5-> 2 */ 1889 CCK(0) << 4 | /* 2-> 1 */ 1890 CCK(0)); /* 1-> 1 */ 1891 #undef OFDM 1892 #undef CCK 1893 } 1894 1895 void 1896 rt2860_set_txpreamble(struct rt2860_softc *sc) 1897 { 1898 uint32_t tmp; 1899 1900 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 1901 tmp &= ~RT2860_CCK_SHORT_EN; 1902 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1903 tmp |= RT2860_CCK_SHORT_EN; 1904 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 1905 } 1906 1907 void 1908 rt2860_set_basicrates(struct rt2860_softc *sc) 1909 { 1910 struct ieee80211com *ic = &sc->sc_ic; 1911 1912 /* set basic rates mask */ 1913 if (ic->ic_curmode == IEEE80211_MODE_11B) 1914 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 1915 else if (ic->ic_curmode == IEEE80211_MODE_11A) 1916 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 1917 else /* 11g */ 1918 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 1919 } 1920 1921 void 1922 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 1923 { 1924 uint32_t tmp; 1925 1926 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 1927 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 1928 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 1929 rt2860_mcu_bbp_write(sc, 86, 0x00); 1930 1931 if (group == 0) { 1932 if (sc->ext_2ghz_lna) { 1933 rt2860_mcu_bbp_write(sc, 82, 0x62); 1934 rt2860_mcu_bbp_write(sc, 75, 0x46); 1935 } else { 1936 rt2860_mcu_bbp_write(sc, 82, 0x84); 1937 rt2860_mcu_bbp_write(sc, 75, 0x50); 1938 } 1939 } else { 1940 if (sc->ext_5ghz_lna) { 1941 rt2860_mcu_bbp_write(sc, 82, 0xf2); 1942 rt2860_mcu_bbp_write(sc, 75, 0x46); 1943 } else { 1944 rt2860_mcu_bbp_write(sc, 82, 0xf2); 1945 rt2860_mcu_bbp_write(sc, 75, 0x50); 1946 } 1947 } 1948 1949 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 1950 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 1951 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 1952 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 1953 1954 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 1955 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN; 1956 if (group == 0) { /* 2GHz */ 1957 tmp |= RT2860_PA_PE_G0_EN | RT2860_LNA_PE_G0_EN; 1958 if (sc->ntxchains > 1) 1959 tmp |= RT2860_PA_PE_G1_EN; 1960 if (sc->nrxchains > 1) 1961 tmp |= RT2860_LNA_PE_G1_EN; 1962 } else { /* 5GHz */ 1963 tmp |= RT2860_PA_PE_A0_EN | RT2860_LNA_PE_A0_EN; 1964 if (sc->ntxchains > 1) 1965 tmp |= RT2860_PA_PE_A1_EN; 1966 if (sc->nrxchains > 1) 1967 tmp |= RT2860_LNA_PE_A1_EN; 1968 } 1969 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 1970 1971 /* set initial AGC value */ 1972 if (group == 0) 1973 rt2860_mcu_bbp_write(sc, 66, 0x2e + sc->lna[0]); 1974 else 1975 rt2860_mcu_bbp_write(sc, 66, 0x32 + (sc->lna[group] * 5) / 3); 1976 } 1977 1978 void 1979 rt2860_set_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 1980 { 1981 struct ieee80211com *ic = &sc->sc_ic; 1982 const struct rfprog *rfprog = rt2860_rf2850; 1983 uint32_t r2, r3, r4; 1984 int8_t txpow1, txpow2; 1985 u_int i, chan, group; 1986 1987 chan = ieee80211_chan2ieee(ic, c); 1988 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1989 return; 1990 1991 /* find the settings for this channel (we know it exists) */ 1992 for (i = 0; rfprog[i].chan != chan; i++); 1993 1994 r2 = rfprog[i].r2; 1995 if (sc->ntxchains == 1) 1996 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 1997 if (sc->nrxchains == 1) 1998 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 1999 else if (sc->nrxchains == 2) 2000 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2001 2002 /* use Tx power values from EEPROM */ 2003 txpow1 = sc->txpow1[i]; 2004 txpow2 = sc->txpow2[i]; 2005 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2006 if (txpow1 >= 0) 2007 txpow1 = txpow1 << 1; 2008 else 2009 txpow1 = (7 + txpow1) << 1 | 1; 2010 if (txpow2 >= 0) 2011 txpow2 = txpow2 << 1; 2012 else 2013 txpow2 = (7 + txpow2) << 1 | 1; 2014 } 2015 r3 = rfprog[i].r3 | txpow1 << 7; 2016 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2017 2018 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2019 rt2860_rf_write(sc, RT2860_RF2, r2); 2020 rt2860_rf_write(sc, RT2860_RF3, r3); 2021 rt2860_rf_write(sc, RT2860_RF4, r4); 2022 2023 DELAY(200); 2024 2025 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2026 rt2860_rf_write(sc, RT2860_RF2, r2); 2027 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2028 rt2860_rf_write(sc, RT2860_RF4, r4); 2029 2030 DELAY(200); 2031 2032 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2033 rt2860_rf_write(sc, RT2860_RF2, r2); 2034 rt2860_rf_write(sc, RT2860_RF3, r3); 2035 rt2860_rf_write(sc, RT2860_RF4, r4); 2036 2037 /* 802.11a uses a 16 microseconds short interframe space */ 2038 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2039 2040 /* determine channel group */ 2041 if (chan <= 14) 2042 group = 0; 2043 else if (chan <= 64) 2044 group = 1; 2045 else if (chan <= 128) 2046 group = 2; 2047 else 2048 group = 3; 2049 2050 /* XXX necessary only when group has changed! */ 2051 rt2860_select_chan_group(sc, group); 2052 2053 DELAY(1000); 2054 } 2055 2056 void 2057 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2058 { 2059 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2060 which | (sc->leds & 0x7f)); 2061 } 2062 2063 /* 2064 * Hardware has a general-purpose programmable timer interrupt that can 2065 * periodically raise MAC_INT_4. 2066 */ 2067 void 2068 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2069 { 2070 uint32_t tmp; 2071 2072 /* disable GP timer before reprogramming it */ 2073 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2074 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2075 2076 if (ms == 0) 2077 return; 2078 2079 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2080 ms *= 16; /* Unit: 64us */ 2081 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2082 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2083 2084 /* enable GP timer */ 2085 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2086 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2087 } 2088 2089 void 2090 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2091 { 2092 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2093 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2094 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2095 bssid[4] | bssid[5] << 8); 2096 } 2097 2098 void 2099 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2100 { 2101 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2102 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2103 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2104 addr[4] | addr[5] << 8); 2105 } 2106 2107 void 2108 rt2860_updateslot(struct ieee80211com *ic) 2109 { 2110 struct rt2860_softc *sc = ic->ic_softc; 2111 uint32_t tmp; 2112 2113 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2114 tmp &= ~0xff; 2115 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2116 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2117 } 2118 2119 void 2120 rt2860_updateprot(struct ieee80211com *ic) 2121 { 2122 struct rt2860_softc *sc = ic->ic_softc; 2123 uint32_t tmp; 2124 2125 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2126 /* setup protection frame rate (MCS code) */ 2127 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2128 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2129 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2130 2131 /* CCK frames don't require protection */ 2132 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2133 2134 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2135 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2136 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2137 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2138 tmp |= RT2860_PROT_CTRL_CTS; 2139 } 2140 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2141 } 2142 2143 void 2144 rt2860_updateedca(struct ieee80211com *ic) 2145 { 2146 struct rt2860_softc *sc = ic->ic_softc; 2147 int aci; 2148 2149 /* update MAC TX configuration registers */ 2150 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2151 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2152 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 2153 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 2154 ic->ic_edca_ac[aci].ac_aifsn << 8 | 2155 ic->ic_edca_ac[aci].ac_txoplimit); 2156 } 2157 2158 /* update SCH/DMA registers too */ 2159 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2160 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 2161 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 2162 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 2163 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 2164 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2165 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 2166 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 2167 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 2168 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 2169 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2170 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 2171 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 2172 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 2173 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 2174 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2175 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 2176 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 2177 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2178 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 2179 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 2180 } 2181 2182 int 2183 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2184 struct ieee80211_key *k) 2185 { 2186 struct rt2860_softc *sc = ic->ic_softc; 2187 bus_size_t base; 2188 uint32_t attr; 2189 uint8_t mode, wcid, iv[8]; 2190 2191 /* map net80211 cipher to RT2860 security mode */ 2192 switch (k->k_cipher) { 2193 case IEEE80211_CIPHER_WEP40: 2194 mode = RT2860_MODE_WEP40; 2195 break; 2196 case IEEE80211_CIPHER_WEP104: 2197 mode = RT2860_MODE_WEP104; 2198 break; 2199 case IEEE80211_CIPHER_TKIP: 2200 mode = RT2860_MODE_TKIP; 2201 break; 2202 case IEEE80211_CIPHER_CCMP: 2203 mode = RT2860_MODE_AES_CCMP; 2204 break; 2205 default: 2206 return EINVAL; 2207 } 2208 2209 if (k->k_flags & IEEE80211_KEY_GROUP) { 2210 wcid = 0; /* NB: update WCID0 for group keys */ 2211 base = RT2860_SKEY(0, k->k_id); 2212 } else { 2213 wcid = RT2860_AID2WCID(ni->ni_associd); 2214 base = RT2860_PKEY(wcid); 2215 } 2216 2217 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2218 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 2219 #ifndef IEEE80211_STA_ONLY 2220 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2221 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 2222 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 2223 } else 2224 #endif 2225 { 2226 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 2227 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 2228 } 2229 } else 2230 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 2231 2232 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 2233 (k->k_flags & IEEE80211_KEY_TX)) { 2234 /* set initial packet number in IV+EIV */ 2235 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 2236 k->k_cipher == IEEE80211_CIPHER_WEP104) { 2237 uint32_t val = arc4random(); 2238 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 2239 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 2240 val += 0x000100; 2241 iv[0] = val; 2242 iv[1] = val >> 8; 2243 iv[2] = val >> 16; 2244 iv[3] = k->k_id << 6; 2245 iv[4] = iv[5] = iv[6] = iv[7] = 0; 2246 } else { 2247 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2248 iv[0] = k->k_tsc >> 8; 2249 iv[1] = (iv[0] | 0x20) & 0x7f; 2250 iv[2] = k->k_tsc; 2251 } else /* CCMP */ { 2252 iv[0] = k->k_tsc; 2253 iv[1] = k->k_tsc >> 8; 2254 iv[2] = 0; 2255 } 2256 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 2257 iv[4] = k->k_tsc >> 16; 2258 iv[5] = k->k_tsc >> 24; 2259 iv[6] = k->k_tsc >> 32; 2260 iv[7] = k->k_tsc >> 40; 2261 } 2262 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 2263 } 2264 2265 if (k->k_flags & IEEE80211_KEY_GROUP) { 2266 /* install group key */ 2267 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 2268 attr &= ~(0xf << (k->k_id * 4)); 2269 attr |= mode << (k->k_id * 4); 2270 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 2271 } else { 2272 /* install pairwise key */ 2273 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 2274 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2275 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 2276 } 2277 return 0; 2278 } 2279 2280 void 2281 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2282 struct ieee80211_key *k) 2283 { 2284 struct rt2860_softc *sc = ic->ic_softc; 2285 uint32_t attr; 2286 uint8_t wcid; 2287 2288 if (k->k_flags & IEEE80211_KEY_GROUP) { 2289 /* remove group key */ 2290 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 2291 attr &= ~(0xf << (k->k_id * 4)); 2292 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 2293 2294 } else { 2295 /* remove pairwise key */ 2296 wcid = RT2860_AID2WCID(ni->ni_associd); 2297 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 2298 attr &= ~0xf; 2299 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 2300 } 2301 } 2302 2303 #if NBPFILTER > 0 2304 int8_t 2305 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 2306 { 2307 struct ieee80211com *ic = &sc->sc_ic; 2308 struct ieee80211_channel *c = ic->ic_ibss_chan; 2309 int delta; 2310 2311 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2312 u_int chan = ieee80211_chan2ieee(ic, c); 2313 delta = sc->rssi_5ghz[rxchain]; 2314 2315 /* determine channel group */ 2316 if (chan <= 64) 2317 delta -= sc->lna[1]; 2318 else if (chan <= 128) 2319 delta -= sc->lna[2]; 2320 else 2321 delta -= sc->lna[3]; 2322 } else 2323 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 2324 2325 return -12 - delta - rssi; 2326 } 2327 #endif 2328 2329 /* 2330 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 2331 * Used to adjust per-rate Tx power registers. 2332 */ 2333 static __inline uint32_t 2334 b4inc(uint32_t b32, int8_t delta) 2335 { 2336 int8_t i, b4; 2337 2338 for (i = 0; i < 8; i++) { 2339 b4 = b32 & 0xf; 2340 b4 += delta; 2341 if (b4 < 0) 2342 b4 = 0; 2343 else if (b4 > 0xf) 2344 b4 = 0xf; 2345 b32 = b32 >> 4 | b4 << 28; 2346 } 2347 return b32; 2348 } 2349 2350 const char * 2351 rt2860_get_rf(uint8_t rev) 2352 { 2353 switch (rev) { 2354 case RT2860_RF_2820: return "RT2820"; 2355 case RT2860_RF_2850: return "RT2850"; 2356 case RT2860_RF_2720: return "RT2720"; 2357 case RT2860_RF_2750: return "RT2750"; 2358 default: return "unknown"; 2359 } 2360 } 2361 2362 int 2363 rt2860_read_eeprom(struct rt2860_softc *sc) 2364 { 2365 struct ieee80211com *ic = &sc->sc_ic; 2366 uint16_t val; 2367 int8_t delta_2ghz, delta_5ghz; 2368 int ridx, ant, i; 2369 2370 /* read EEPROM version */ 2371 val = rt2860_eeprom_read(sc, RT2860_EEPROM_VERSION); 2372 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 2373 2374 /* read MAC address */ 2375 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC01); 2376 ic->ic_myaddr[0] = val & 0xff; 2377 ic->ic_myaddr[1] = val >> 8; 2378 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC23); 2379 ic->ic_myaddr[2] = val & 0xff; 2380 ic->ic_myaddr[3] = val >> 8; 2381 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC45); 2382 ic->ic_myaddr[4] = val & 0xff; 2383 ic->ic_myaddr[5] = val >> 8; 2384 2385 /* read country code */ 2386 val = rt2860_eeprom_read(sc, RT2860_EEPROM_COUNTRY); 2387 DPRINTF(("EEPROM region code=0x%04x\n", val)); 2388 2389 /* read default BBP settings */ 2390 for (i = 0; i < 8; i++) { 2391 val = rt2860_eeprom_read(sc, RT2860_EEPROM_BBP_BASE + i); 2392 sc->bbp[i].val = val & 0xff; 2393 sc->bbp[i].reg = val >> 8; 2394 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 2395 } 2396 2397 /* read RF frequency offset from EEPROM */ 2398 val = rt2860_eeprom_read(sc, RT2860_EEPROM_FREQ_LEDS); 2399 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 2400 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 2401 2402 if ((sc->leds = val >> 8) != 0xff) { 2403 /* read LEDs operating mode */ 2404 sc->led[0] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED1); 2405 sc->led[1] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED2); 2406 sc->led[2] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED3); 2407 } else { 2408 /* broken EEPROM, use default settings */ 2409 sc->leds = 0x01; 2410 sc->led[0] = 0x5555; 2411 sc->led[1] = 0x2221; 2412 sc->led[2] = 0xa9f8; 2413 } 2414 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 2415 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 2416 2417 /* read RF information */ 2418 val = rt2860_eeprom_read(sc, RT2860_EEPROM_ANTENNA); 2419 if (val == 0xffff) { 2420 /* broken EEPROM, default to RF2820 1T2R */ 2421 DPRINTF(("invalid EEPROM antenna info, using default\n")); 2422 sc->rf_rev = RT2860_RF_2820; 2423 sc->ntxchains = 1; 2424 sc->nrxchains = 2; 2425 } else { 2426 sc->rf_rev = (val >> 8) & 0xf; 2427 sc->ntxchains = (val >> 4) & 0xf; 2428 sc->nrxchains = val & 0xf; 2429 } 2430 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 2431 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 2432 2433 /* check if RF supports automatic Tx access gain control */ 2434 val = rt2860_eeprom_read(sc, RT2860_EEPROM_CONFIG); 2435 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 2436 if ((val & 0xff) != 0xff) { 2437 sc->ext_5ghz_lna = (val >> 3) & 1; 2438 sc->ext_2ghz_lna = (val >> 2) & 1; 2439 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 2440 } 2441 2442 if (sc->sc_flags & RT2860_ADVANCED_PS) { 2443 /* read PCIe power save level */ 2444 val = rt2860_eeprom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 2445 if ((val & 0xff) != 0xff) { 2446 sc->pslevel = val & 0x3; 2447 val = rt2860_eeprom_read(sc, RT2860_EEPROM_REV); 2448 if (val >> 8 != 0x92 || !(val & 0x80)) 2449 sc->pslevel = MIN(sc->pslevel, 1); 2450 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 2451 } 2452 } 2453 /* read power settings for 2GHz channels */ 2454 for (i = 0; i < 14; i += 2) { 2455 val = rt2860_eeprom_read(sc, 2456 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 2457 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 2458 sc->txpow1[i + 1] = (int8_t)(val >> 8); 2459 2460 val = rt2860_eeprom_read(sc, 2461 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 2462 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 2463 sc->txpow2[i + 1] = (int8_t)(val >> 8); 2464 } 2465 /* fix broken Tx power entries */ 2466 for (i = 0; i < 14; i++) { 2467 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 2468 sc->txpow1[i] = 5; 2469 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 2470 sc->txpow2[i] = 5; 2471 DPRINTF(("chan %d: power1=%d, power2=%d\n", 2472 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 2473 } 2474 /* read power settings for 5GHz channels */ 2475 for (i = 0; i < 36; i += 2) { 2476 val = rt2860_eeprom_read(sc, 2477 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 2478 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 2479 sc->txpow1[i + 15] = (int8_t)(val >> 8); 2480 2481 val = rt2860_eeprom_read(sc, 2482 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 2483 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 2484 sc->txpow2[i + 15] = (int8_t)(val >> 8); 2485 } 2486 /* fix broken Tx power entries */ 2487 for (i = 0; i < 36; i++) { 2488 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 2489 sc->txpow1[14 + i] = 5; 2490 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 2491 sc->txpow2[14 + i] = 5; 2492 DPRINTF(("chan %d: power1=%d, power2=%d\n", 2493 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 2494 sc->txpow2[14 + i])); 2495 } 2496 2497 /* read Tx power compensation for each Tx rate */ 2498 val = rt2860_eeprom_read(sc, RT2860_EEPROM_DELTAPWR); 2499 delta_2ghz = delta_5ghz = 0; 2500 if ((val & 0xff) != 0xff && (val & 0x80)) { 2501 delta_2ghz = val & 0xf; 2502 if (!(val & 0x40)) /* negative number */ 2503 delta_2ghz = -delta_2ghz; 2504 } 2505 val >>= 8; 2506 if ((val & 0xff) != 0xff && (val & 0x80)) { 2507 delta_5ghz = val & 0xf; 2508 if (!(val & 0x40)) /* negative number */ 2509 delta_5ghz = -delta_5ghz; 2510 } 2511 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 2512 delta_2ghz, delta_5ghz)); 2513 2514 for (ridx = 0; ridx < 5; ridx++) { 2515 uint32_t reg; 2516 2517 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx); 2518 reg = (uint32_t)val << 16; 2519 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx + 1); 2520 reg |= val; 2521 2522 sc->txpow20mhz[ridx] = reg; 2523 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 2524 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 2525 2526 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 2527 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 2528 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 2529 } 2530 2531 /* read factory-calibrated samples for temperature compensation */ 2532 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 2533 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 2534 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 2535 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 2536 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 2537 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 2538 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 2539 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 2540 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 2541 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 2542 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 2543 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 2544 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 2545 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 2546 sc->step_2ghz = val >> 8; 2547 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 2548 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 2549 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 2550 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 2551 sc->tssi_2ghz[8], sc->step_2ghz)); 2552 /* check that ref value is correct, otherwise disable calibration */ 2553 if (sc->tssi_2ghz[4] == 0xff) 2554 sc->calib_2ghz = 0; 2555 2556 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 2557 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 2558 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 2559 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 2560 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 2561 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 2562 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 2563 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 2564 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 2565 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 2566 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 2567 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 2568 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 2569 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 2570 sc->step_5ghz = val >> 8; 2571 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 2572 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 2573 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 2574 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 2575 sc->tssi_5ghz[8], sc->step_5ghz)); 2576 /* check that ref value is correct, otherwise disable calibration */ 2577 if (sc->tssi_5ghz[4] == 0xff) 2578 sc->calib_5ghz = 0; 2579 2580 /* read RSSI offsets and LNA gains from EEPROM */ 2581 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 2582 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 2583 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 2584 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 2585 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 2586 sc->lna[2] = val >> 8; /* channel group 2 */ 2587 2588 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 2589 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 2590 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 2591 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 2592 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 2593 sc->lna[3] = val >> 8; /* channel group 3 */ 2594 2595 val = rt2860_eeprom_read(sc, RT2860_EEPROM_LNA); 2596 sc->lna[0] = val & 0xff; /* channel group 0 */ 2597 sc->lna[1] = val >> 8; /* channel group 1 */ 2598 2599 /* fix broken 5GHz LNA entries */ 2600 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 2601 DPRINTF(("invalid LNA for channel group %d\n", 2)); 2602 sc->lna[2] = sc->lna[1]; 2603 } 2604 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 2605 DPRINTF(("invalid LNA for channel group %d\n", 3)); 2606 sc->lna[3] = sc->lna[1]; 2607 } 2608 2609 /* fix broken RSSI offset entries */ 2610 for (ant = 0; ant < 3; ant++) { 2611 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 2612 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 2613 ant + 1, sc->rssi_2ghz[ant])); 2614 sc->rssi_2ghz[ant] = 0; 2615 } 2616 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 2617 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 2618 ant + 1, sc->rssi_5ghz[ant])); 2619 sc->rssi_5ghz[ant] = 0; 2620 } 2621 } 2622 2623 return 0; 2624 } 2625 2626 int 2627 rt2860_bbp_init(struct rt2860_softc *sc) 2628 { 2629 int i, ntries; 2630 2631 /* wait for BBP to wake up */ 2632 for (ntries = 0; ntries < 20; ntries++) { 2633 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 2634 if (bbp0 != 0 && bbp0 != 0xff) 2635 break; 2636 } 2637 if (ntries == 20) { 2638 printf("%s: timeout waiting for BBP to wake up\n", 2639 sc->sc_dev.dv_xname); 2640 return ETIMEDOUT; 2641 } 2642 2643 /* initialize BBP registers to default values */ 2644 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 2645 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 2646 rt2860_def_bbp[i].val); 2647 } 2648 2649 /* fix BBP84 for RT2860E */ 2650 if ((sc->mac_rev & 0xffff) != 0x0101) 2651 rt2860_mcu_bbp_write(sc, 84, 0x19); 2652 2653 /* fix BBP69 and BBP73 for RT2860C */ 2654 if (sc->mac_rev == 0x28600100) { 2655 rt2860_mcu_bbp_write(sc, 69, 0x16); 2656 rt2860_mcu_bbp_write(sc, 73, 0x12); 2657 } 2658 2659 return 0; 2660 } 2661 2662 int 2663 rt2860_txrx_enable(struct rt2860_softc *sc) 2664 { 2665 uint32_t tmp; 2666 int ntries; 2667 2668 /* enable Tx/Rx DMA engine */ 2669 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 2670 RAL_BARRIER_READ_WRITE(sc); 2671 for (ntries = 0; ntries < 200; ntries++) { 2672 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 2673 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 2674 break; 2675 DELAY(1000); 2676 } 2677 if (ntries == 200) { 2678 printf("%s: timeout waiting for DMA engine\n", 2679 sc->sc_dev.dv_xname); 2680 return ETIMEDOUT; 2681 } 2682 2683 DELAY(50); 2684 2685 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 2686 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 2687 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 2688 2689 /* set Rx filter */ 2690 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 2691 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 2692 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 2693 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 2694 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 2695 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 2696 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 2697 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 2698 } 2699 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 2700 2701 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 2702 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 2703 2704 return 0; 2705 } 2706 2707 int 2708 rt2860_init(struct ifnet *ifp) 2709 { 2710 struct rt2860_softc *sc = ifp->if_softc; 2711 struct ieee80211com *ic = &sc->sc_ic; 2712 uint32_t tmp; 2713 uint8_t bbp1, bbp3; 2714 int i, qid, ridx, ntries, error; 2715 2716 /* for CardBus, power on the socket */ 2717 if (!(sc->sc_flags & RT2860_ENABLED)) { 2718 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2719 printf("%s: could not enable device\n", 2720 sc->sc_dev.dv_xname); 2721 return EIO; 2722 } 2723 sc->sc_flags |= RT2860_ENABLED; 2724 } 2725 2726 rt2860_stop(ifp, 0); 2727 2728 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 2729 tmp &= 0xff0; 2730 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 2731 2732 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0xffffffff); 2733 2734 /* PBF hardware reset */ 2735 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 2736 RAL_BARRIER_WRITE(sc); 2737 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 2738 2739 if (!(sc->sc_flags & RT2860_FWLOADED)) { 2740 if ((error = rt2860_load_microcode(sc)) != 0) { 2741 printf("%s: could not load 8051 microcode\n", 2742 sc->sc_dev.dv_xname); 2743 rt2860_stop(ifp, 1); 2744 return error; 2745 } 2746 sc->sc_flags |= RT2860_FWLOADED; 2747 } 2748 2749 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2750 rt2860_set_macaddr(sc, ic->ic_myaddr); 2751 2752 /* init Tx power for all Tx rates (from EEPROM) */ 2753 for (ridx = 0; ridx < 5; ridx++) { 2754 if (sc->txpow20mhz[ridx] == 0xffffffff) 2755 continue; 2756 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 2757 } 2758 2759 for (ntries = 0; ntries < 100; ntries++) { 2760 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 2761 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 2762 break; 2763 DELAY(1000); 2764 } 2765 if (ntries == 100) { 2766 printf("%s: timeout waiting for DMA engine\n", 2767 sc->sc_dev.dv_xname); 2768 rt2860_stop(ifp, 1); 2769 return ETIMEDOUT; 2770 } 2771 tmp &= 0xff0; 2772 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 2773 2774 /* reset Rx ring and all 6 Tx rings */ 2775 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 2776 2777 /* PBF hardware reset */ 2778 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 2779 RAL_BARRIER_WRITE(sc); 2780 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 2781 2782 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 2783 RAL_BARRIER_WRITE(sc); 2784 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 2785 2786 for (i = 0; i < nitems(rt2860_def_mac); i++) 2787 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 2788 2789 /* wait while MAC is busy */ 2790 for (ntries = 0; ntries < 100; ntries++) { 2791 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 2792 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 2793 break; 2794 DELAY(1000); 2795 } 2796 if (ntries == 100) { 2797 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname); 2798 rt2860_stop(ifp, 1); 2799 return ETIMEDOUT; 2800 } 2801 2802 /* clear Host to MCU mailbox */ 2803 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 2804 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 2805 2806 if ((error = rt2860_bbp_init(sc)) != 0) { 2807 rt2860_stop(ifp, 1); 2808 return error; 2809 } 2810 2811 /* clear RX WCID search table */ 2812 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 2813 /* clear pairwise key table */ 2814 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 2815 /* clear IV/EIV table */ 2816 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 2817 /* clear WCID attribute table */ 2818 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 2819 /* clear shared key table */ 2820 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 2821 /* clear shared key mode */ 2822 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 2823 2824 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 2825 for (qid = 0; qid < 6; qid++) { 2826 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 2827 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 2828 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 2829 } 2830 2831 /* init Rx ring */ 2832 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 2833 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 2834 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 2835 2836 /* setup maximum buffer sizes */ 2837 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 2838 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 2839 2840 for (ntries = 0; ntries < 100; ntries++) { 2841 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 2842 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 2843 break; 2844 DELAY(1000); 2845 } 2846 if (ntries == 100) { 2847 printf("%s: timeout waiting for DMA engine\n", 2848 sc->sc_dev.dv_xname); 2849 rt2860_stop(ifp, 1); 2850 return ETIMEDOUT; 2851 } 2852 tmp &= 0xff0; 2853 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 2854 2855 /* disable interrupts mitigation */ 2856 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 2857 2858 /* write vendor-specific BBP values (from EEPROM) */ 2859 for (i = 0; i < 8; i++) { 2860 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 2861 continue; 2862 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 2863 } 2864 2865 /* send LEDs operating mode to microcontroller */ 2866 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 2867 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 2868 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 2869 2870 /* disable non-existing Rx chains */ 2871 bbp3 = rt2860_mcu_bbp_read(sc, 3); 2872 bbp3 &= ~(1 << 3 | 1 << 4); 2873 if (sc->nrxchains == 2) 2874 bbp3 |= 1 << 3; 2875 else if (sc->nrxchains == 3) 2876 bbp3 |= 1 << 4; 2877 rt2860_mcu_bbp_write(sc, 3, bbp3); 2878 2879 /* disable non-existing Tx chains */ 2880 bbp1 = rt2860_mcu_bbp_read(sc, 1); 2881 if (sc->ntxchains == 1) 2882 bbp1 &= ~(1 << 3 | 1 << 4); 2883 rt2860_mcu_bbp_write(sc, 1, bbp1); 2884 2885 /* select default channel */ 2886 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2887 rt2860_set_chan(sc, ic->ic_ibss_chan); 2888 2889 /* XXX not clear what the following 8051 command does.. */ 2890 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BOOT, 0); 2891 2892 /* set RTS threshold */ 2893 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 2894 tmp &= ~0xffff00; 2895 tmp |= ic->ic_rtsthreshold << 8; 2896 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 2897 2898 /* setup initial protection mode */ 2899 sc->sc_ic_flags = ic->ic_flags; 2900 rt2860_updateprot(ic); 2901 2902 /* turn radio LED on */ 2903 rt2860_set_leds(sc, RT2860_LED_RADIO); 2904 2905 if (ic->ic_flags & IEEE80211_F_WEPON) { 2906 /* install WEP keys */ 2907 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2908 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2909 } 2910 2911 /* enable Tx/Rx DMA engine */ 2912 if ((error = rt2860_txrx_enable(sc)) != 0) { 2913 rt2860_stop(ifp, 1); 2914 return error; 2915 } 2916 2917 /* clear pending interrupts */ 2918 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 2919 /* enable interrupts */ 2920 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 2921 2922 if (sc->sc_flags & RT2860_ADVANCED_PS) 2923 (void)rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel); 2924 2925 ifp->if_flags &= ~IFF_OACTIVE; 2926 ifp->if_flags |= IFF_RUNNING; 2927 2928 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2929 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2930 else 2931 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2932 2933 return 0; 2934 } 2935 2936 void 2937 rt2860_stop(struct ifnet *ifp, int disable) 2938 { 2939 struct rt2860_softc *sc = ifp->if_softc; 2940 struct ieee80211com *ic = &sc->sc_ic; 2941 uint32_t tmp; 2942 int qid; 2943 2944 if (ifp->if_flags & IFF_RUNNING) 2945 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 2946 2947 sc->sc_tx_timer = 0; 2948 ifp->if_timer = 0; 2949 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2950 2951 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2952 2953 /* disable interrupts */ 2954 RAL_WRITE(sc, RT2860_INT_MASK, 0); 2955 2956 /* disable GP timer */ 2957 rt2860_set_gp_timer(sc, 0); 2958 2959 /* disable Rx */ 2960 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 2961 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 2962 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 2963 2964 /* reset adapter */ 2965 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 2966 RAL_BARRIER_WRITE(sc); 2967 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 2968 2969 /* reset Tx and Rx rings (and reclaim TXWIs) */ 2970 sc->qfullmsk = 0; 2971 for (qid = 0; qid < 6; qid++) 2972 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 2973 rt2860_reset_rx_ring(sc, &sc->rxq); 2974 2975 /* for CardBus, power down the socket */ 2976 if (disable && sc->sc_disable != NULL) { 2977 if (sc->sc_flags & RT2860_ENABLED) { 2978 (*sc->sc_disable)(sc); 2979 sc->sc_flags &= ~(RT2860_ENABLED | RT2860_FWLOADED); 2980 } 2981 } 2982 } 2983 2984 int 2985 rt2860_load_microcode(struct rt2860_softc *sc) 2986 { 2987 u_char *ucode; 2988 size_t size; 2989 int error, ntries; 2990 2991 if ((error = loadfirmware("ral-rt2860", &ucode, &size)) != 0) { 2992 printf("%s: error %d, could not read firmware file %s\n", 2993 sc->sc_dev.dv_xname, error, "ral-rt2860"); 2994 return error; 2995 } 2996 2997 /* set "host program ram write selection" bit */ 2998 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 2999 /* write microcode image */ 3000 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, ucode, size); 3001 /* kick microcontroller unit */ 3002 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 3003 RAL_BARRIER_WRITE(sc); 3004 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 3005 3006 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3007 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3008 3009 free(ucode, M_DEVBUF); 3010 3011 /* wait until microcontroller is ready */ 3012 RAL_BARRIER_READ_WRITE(sc); 3013 for (ntries = 0; ntries < 1000; ntries++) { 3014 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 3015 break; 3016 DELAY(1000); 3017 } 3018 if (ntries == 1000) { 3019 printf("%s: timeout waiting for MCU to initialize\n", 3020 sc->sc_dev.dv_xname); 3021 return ETIMEDOUT; 3022 } 3023 return 0; 3024 } 3025 3026 /* 3027 * This function is called periodically to adjust Tx power based on 3028 * temperature variation. 3029 */ 3030 void 3031 rt2860_calib(struct rt2860_softc *sc) 3032 { 3033 struct ieee80211com *ic = &sc->sc_ic; 3034 const uint8_t *tssi; 3035 uint8_t step, bbp49; 3036 int8_t ridx, d; 3037 3038 /* read current temperature */ 3039 bbp49 = rt2860_mcu_bbp_read(sc, 49); 3040 3041 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 3042 tssi = &sc->tssi_2ghz[4]; 3043 step = sc->step_2ghz; 3044 } else { 3045 tssi = &sc->tssi_5ghz[4]; 3046 step = sc->step_5ghz; 3047 } 3048 3049 if (bbp49 < tssi[0]) { /* lower than reference */ 3050 /* use higher Tx power than default */ 3051 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 3052 } else if (bbp49 > tssi[0]) { /* greater than reference */ 3053 /* use lower Tx power than default */ 3054 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 3055 } else { 3056 /* use default Tx power */ 3057 d = 0; 3058 } 3059 d *= step; 3060 3061 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 3062 3063 /* write adjusted Tx power values for each Tx rate */ 3064 for (ridx = 0; ridx < 5; ridx++) { 3065 if (sc->txpow20mhz[ridx] == 0xffffffff) 3066 continue; 3067 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 3068 b4inc(sc->txpow20mhz[ridx], d)); 3069 } 3070 } 3071 3072 #ifndef IEEE80211_STA_ONLY 3073 int 3074 rt2860_setup_beacon(struct rt2860_softc *sc) 3075 { 3076 struct ieee80211com *ic = &sc->sc_ic; 3077 struct rt2860_txwi txwi; 3078 struct mbuf *m; 3079 int ridx; 3080 3081 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL) 3082 return ENOBUFS; 3083 3084 memset(&txwi, 0, sizeof txwi); 3085 txwi.wcid = 0xff; 3086 txwi.len = htole16(m->m_pkthdr.len); 3087 /* send beacons at the lowest available rate */ 3088 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 3089 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 3090 txwi.phy = htole16(rt2860_rates[ridx].mcs); 3091 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 3092 txwi.phy |= htole16(RT2860_PHY_OFDM); 3093 txwi.txop = RT2860_TX_TXOP_HT; 3094 txwi.flags = RT2860_TX_TS; 3095 3096 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 3097 (uint8_t *)&txwi, sizeof txwi); 3098 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 3099 mtod(m, uint8_t *), m->m_pkthdr.len); 3100 3101 m_freem(m); 3102 3103 return 0; 3104 } 3105 #endif 3106 3107 void 3108 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 3109 { 3110 struct ieee80211com *ic = &sc->sc_ic; 3111 uint32_t tmp; 3112 3113 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 3114 3115 tmp &= ~0x1fffff; 3116 tmp |= ic->ic_bss->ni_intval * 16; 3117 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3118 if (ic->ic_opmode == IEEE80211_M_STA) { 3119 /* 3120 * Local TSF is always updated with remote TSF on beacon 3121 * reception. 3122 */ 3123 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3124 } 3125 #ifndef IEEE80211_STA_ONLY 3126 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3127 tmp |= RT2860_BCN_TX_EN; 3128 /* 3129 * Local TSF is updated with remote TSF on beacon reception 3130 * only if the remote TSF is greater than local TSF. 3131 */ 3132 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3133 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3134 tmp |= RT2860_BCN_TX_EN; 3135 /* SYNC with nobody */ 3136 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3137 } 3138 #endif 3139 3140 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 3141 } 3142 3143 void 3144 rt2860_power(int why, void *arg) 3145 { 3146 struct rt2860_softc *sc = arg; 3147 struct ifnet *ifp = &sc->sc_ic.ic_if; 3148 int s; 3149 3150 DPRINTF(("%s: rt2860_power(%d)\n", sc->sc_dev.dv_xname, why)); 3151 3152 s = splnet(); 3153 switch (why) { 3154 case PWR_SUSPEND: 3155 case PWR_STANDBY: 3156 rt2860_stop(ifp, 1); 3157 sc->sc_flags &= ~RT2860_FWLOADED; 3158 if (sc->sc_power != NULL) 3159 (*sc->sc_power)(sc, why); 3160 break; 3161 case PWR_RESUME: 3162 if (ifp->if_flags & IFF_UP) { 3163 rt2860_init(ifp); 3164 if (sc->sc_power != NULL) 3165 (*sc->sc_power)(sc, why); 3166 if (ifp->if_flags & IFF_RUNNING) 3167 rt2860_start(ifp); 3168 } 3169 break; 3170 } 3171 splx(s); 3172 } 3173 3174 void 3175 rt2860_shutdown(void *arg) 3176 { 3177 struct rt2860_softc *sc = arg; 3178 struct ifnet *ifp = &sc->sc_ic.ic_if; 3179 3180 rt2860_stop(ifp, 1); 3181 } 3182