1 /* $OpenBSD: rt2860.c,v 1.98 2020/02/19 11:05:04 claudio Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Ralink Technology RT2860/RT3090/RT3290/RT3390/RT3562/RT5390/ 21 * RT5392 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_amrr.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/ic/rt2860var.h> 58 #include <dev/ic/rt2860reg.h> 59 60 #include <dev/pci/pcidevs.h> 61 62 #ifdef RAL_DEBUG 63 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 65 int rt2860_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 void rt2860_attachhook(struct device *); 72 int rt2860_alloc_tx_ring(struct rt2860_softc *, 73 struct rt2860_tx_ring *); 74 void rt2860_reset_tx_ring(struct rt2860_softc *, 75 struct rt2860_tx_ring *); 76 void rt2860_free_tx_ring(struct rt2860_softc *, 77 struct rt2860_tx_ring *); 78 int rt2860_alloc_tx_pool(struct rt2860_softc *); 79 void rt2860_free_tx_pool(struct rt2860_softc *); 80 int rt2860_alloc_rx_ring(struct rt2860_softc *, 81 struct rt2860_rx_ring *); 82 void rt2860_reset_rx_ring(struct rt2860_softc *, 83 struct rt2860_rx_ring *); 84 void rt2860_free_rx_ring(struct rt2860_softc *, 85 struct rt2860_rx_ring *); 86 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *); 87 int rt2860_media_change(struct ifnet *); 88 void rt2860_iter_func(void *, struct ieee80211_node *); 89 void rt2860_updatestats(struct rt2860_softc *); 90 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *, 91 int); 92 void rt2860_node_leave(struct ieee80211com *, 93 struct ieee80211_node *); 94 int rt2860_ampdu_rx_start(struct ieee80211com *, 95 struct ieee80211_node *, uint8_t); 96 void rt2860_ampdu_rx_stop(struct ieee80211com *, 97 struct ieee80211_node *, uint8_t); 98 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 99 int); 100 uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 101 uint16_t rt3290_efuse_read_2(struct rt2860_softc *, uint16_t); 102 uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 103 void rt2860_intr_coherent(struct rt2860_softc *); 104 void rt2860_drain_stats_fifo(struct rt2860_softc *); 105 void rt2860_tx_intr(struct rt2860_softc *, int); 106 void rt2860_rx_intr(struct rt2860_softc *); 107 void rt2860_tbtt_intr(struct rt2860_softc *); 108 void rt2860_gp_intr(struct rt2860_softc *); 109 int rt2860_tx(struct rt2860_softc *, struct mbuf *, 110 struct ieee80211_node *); 111 void rt2860_start(struct ifnet *); 112 void rt2860_watchdog(struct ifnet *); 113 int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 114 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 115 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 116 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 117 uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 118 void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 119 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 120 void rt2860_enable_mrr(struct rt2860_softc *); 121 void rt2860_set_txpreamble(struct rt2860_softc *); 122 void rt2860_set_basicrates(struct rt2860_softc *); 123 void rt2860_select_chan_group(struct rt2860_softc *, int); 124 void rt2860_set_chan(struct rt2860_softc *, u_int); 125 void rt3090_set_chan(struct rt2860_softc *, u_int); 126 void rt5390_set_chan(struct rt2860_softc *, u_int); 127 int rt3090_rf_init(struct rt2860_softc *); 128 void rt5390_rf_init(struct rt2860_softc *); 129 void rt3090_rf_wakeup(struct rt2860_softc *); 130 void rt5390_rf_wakeup(struct rt2860_softc *); 131 int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 132 uint8_t *); 133 void rt3090_rf_setup(struct rt2860_softc *); 134 void rt2860_set_leds(struct rt2860_softc *, uint16_t); 135 void rt2860_set_gp_timer(struct rt2860_softc *, int); 136 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 137 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 138 void rt2860_updateslot(struct ieee80211com *); 139 void rt2860_updateprot(struct ieee80211com *); 140 void rt2860_updateedca(struct ieee80211com *); 141 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 142 struct ieee80211_key *); 143 void rt2860_delete_key(struct ieee80211com *, 144 struct ieee80211_node *, struct ieee80211_key *); 145 #if NBPFILTER > 0 146 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 147 #endif 148 const char * rt2860_get_rf(uint16_t); 149 int rt2860_read_eeprom(struct rt2860_softc *); 150 int rt2860_bbp_init(struct rt2860_softc *); 151 void rt5390_bbp_init(struct rt2860_softc *); 152 int rt3290_wlan_enable(struct rt2860_softc *); 153 int rt2860_txrx_enable(struct rt2860_softc *); 154 int rt2860_init(struct ifnet *); 155 void rt2860_stop(struct ifnet *, int); 156 int rt2860_load_microcode(struct rt2860_softc *); 157 void rt2860_calib(struct rt2860_softc *); 158 void rt3090_set_rx_antenna(struct rt2860_softc *, int); 159 void rt2860_switch_chan(struct rt2860_softc *, 160 struct ieee80211_channel *); 161 #ifndef IEEE80211_STA_ONLY 162 int rt2860_setup_beacon(struct rt2860_softc *); 163 #endif 164 void rt2860_enable_tsf_sync(struct rt2860_softc *); 165 166 static const struct { 167 uint32_t reg; 168 uint32_t val; 169 } rt2860_def_mac[] = { 170 RT2860_DEF_MAC 171 }; 172 173 static const struct { 174 uint8_t reg; 175 uint8_t val; 176 } rt2860_def_bbp[] = { 177 RT2860_DEF_BBP 178 },rt3290_def_bbp[] = { 179 RT3290_DEF_BBP 180 },rt5390_def_bbp[] = { 181 RT5390_DEF_BBP 182 }; 183 184 static const struct rfprog { 185 uint8_t chan; 186 uint32_t r1, r2, r3, r4; 187 } rt2860_rf2850[] = { 188 RT2860_RF2850 189 }; 190 191 struct { 192 uint8_t n, r, k; 193 } rt3090_freqs[] = { 194 RT3070_RF3052 195 }; 196 197 static const struct { 198 uint8_t reg; 199 uint8_t val; 200 } rt3090_def_rf[] = { 201 RT3070_DEF_RF 202 }, rt3290_def_rf[] = { 203 RT3290_DEF_RF 204 }, rt3572_def_rf[] = { 205 RT3572_DEF_RF 206 }, rt5390_def_rf[] = { 207 RT5390_DEF_RF 208 }, rt5392_def_rf[] = { 209 RT5392_DEF_RF 210 }; 211 212 int 213 rt2860_attach(void *xsc, int id) 214 { 215 struct rt2860_softc *sc = xsc; 216 struct ieee80211com *ic = &sc->sc_ic; 217 int qid, ntries, error; 218 uint32_t tmp, reg; 219 220 sc->amrr.amrr_min_success_threshold = 1; 221 sc->amrr.amrr_max_success_threshold = 15; 222 223 if (id == PCI_PRODUCT_RALINK_RT3290) 224 reg = RT2860_PCI_CFG; 225 else 226 reg = RT2860_ASIC_VER_ID; 227 228 /* wait for NIC to initialize */ 229 for (ntries = 0; ntries < 100; ntries++) { 230 tmp = RAL_READ(sc, reg); 231 if (tmp != 0 && tmp != 0xffffffff) 232 break; 233 DELAY(10); 234 } 235 if (ntries == 100) { 236 printf("%s: timeout waiting for NIC to initialize\n", 237 sc->sc_dev.dv_xname); 238 return ETIMEDOUT; 239 } 240 sc->mac_ver = tmp >> 16; 241 sc->mac_rev = tmp & 0xffff; 242 243 if (sc->mac_ver != 0x2860 && 244 (id == PCI_PRODUCT_RALINK_RT2890 || 245 id == PCI_PRODUCT_RALINK_RT2790 || 246 id == PCI_PRODUCT_AWT_RT2890)) 247 sc->sc_flags |= RT2860_ADVANCED_PS; 248 249 /* retrieve RF rev. no and various other things from EEPROM */ 250 rt2860_read_eeprom(sc); 251 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 252 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n", 253 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev, 254 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains); 255 256 /* 257 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 258 */ 259 for (qid = 0; qid < 6; qid++) { 260 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 261 printf("%s: could not allocate Tx ring %d\n", 262 sc->sc_dev.dv_xname, qid); 263 goto fail1; 264 } 265 } 266 267 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 268 printf("%s: could not allocate Rx ring\n", 269 sc->sc_dev.dv_xname); 270 goto fail1; 271 } 272 273 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 274 printf("%s: could not allocate Tx pool\n", 275 sc->sc_dev.dv_xname); 276 goto fail2; 277 } 278 279 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 280 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 281 EDCA_AC_VO : 5; 282 283 config_mountroot(xsc, rt2860_attachhook); 284 285 return 0; 286 287 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 288 fail1: while (--qid >= 0) 289 rt2860_free_tx_ring(sc, &sc->txq[qid]); 290 return error; 291 } 292 293 void 294 rt2860_attachhook(struct device *self) 295 { 296 struct rt2860_softc *sc = (struct rt2860_softc *)self; 297 struct ieee80211com *ic = &sc->sc_ic; 298 struct ifnet *ifp = &ic->ic_if; 299 int i, error; 300 301 if (sc->mac_ver == 0x3290) { 302 error = loadfirmware("ral-rt3290", &sc->ucode, &sc->ucsize); 303 } else { 304 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize); 305 } 306 if (error != 0) { 307 printf("%s: error %d, could not read firmware file %s\n", 308 sc->sc_dev.dv_xname, error, "ral-rt2860"); 309 return; 310 } 311 312 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 313 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 314 ic->ic_state = IEEE80211_S_INIT; 315 316 /* set device capabilities */ 317 ic->ic_caps = 318 IEEE80211_C_MONITOR | /* monitor mode supported */ 319 #ifndef IEEE80211_STA_ONLY 320 IEEE80211_C_IBSS | /* IBSS mode supported */ 321 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 322 IEEE80211_C_APPMGT | /* HostAP power management */ 323 #endif 324 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 325 IEEE80211_C_SHSLOT | /* short slot time supported */ 326 IEEE80211_C_WEP | /* s/w WEP */ 327 IEEE80211_C_RSN; /* WPA/RSN */ 328 329 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 330 /* set supported .11a rates */ 331 ic->ic_sup_rates[IEEE80211_MODE_11A] = 332 ieee80211_std_rateset_11a; 333 334 /* set supported .11a channels */ 335 for (i = 14; i < nitems(rt2860_rf2850); i++) { 336 uint8_t chan = rt2860_rf2850[i].chan; 337 ic->ic_channels[chan].ic_freq = 338 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 339 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 340 } 341 } 342 343 /* set supported .11b and .11g rates */ 344 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 345 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 346 347 /* set supported .11b and .11g channels (1 through 14) */ 348 for (i = 1; i <= 14; i++) { 349 ic->ic_channels[i].ic_freq = 350 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 351 ic->ic_channels[i].ic_flags = 352 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 353 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 354 } 355 356 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 357 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 358 359 ifp->if_softc = sc; 360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 361 ifp->if_ioctl = rt2860_ioctl; 362 ifp->if_start = rt2860_start; 363 ifp->if_watchdog = rt2860_watchdog; 364 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 365 366 if_attach(ifp); 367 ieee80211_ifattach(ifp); 368 ic->ic_node_alloc = rt2860_node_alloc; 369 ic->ic_newassoc = rt2860_newassoc; 370 #ifndef IEEE80211_STA_ONLY 371 ic->ic_node_leave = rt2860_node_leave; 372 #endif 373 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 374 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 375 ic->ic_updateslot = rt2860_updateslot; 376 ic->ic_updateedca = rt2860_updateedca; 377 ic->ic_set_key = rt2860_set_key; 378 ic->ic_delete_key = rt2860_delete_key; 379 /* override state transition machine */ 380 sc->sc_newstate = ic->ic_newstate; 381 ic->ic_newstate = rt2860_newstate; 382 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status); 383 384 #if NBPFILTER > 0 385 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 386 sizeof (struct ieee80211_frame) + 64); 387 388 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 389 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 390 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 391 392 sc->sc_txtap_len = sizeof sc->sc_txtapu; 393 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 394 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 395 #endif 396 } 397 398 int 399 rt2860_detach(void *xsc) 400 { 401 struct rt2860_softc *sc = xsc; 402 struct ifnet *ifp = &sc->sc_ic.ic_if; 403 int qid; 404 405 ieee80211_ifdetach(ifp); /* free all nodes */ 406 if_detach(ifp); 407 408 for (qid = 0; qid < 6; qid++) 409 rt2860_free_tx_ring(sc, &sc->txq[qid]); 410 rt2860_free_rx_ring(sc, &sc->rxq); 411 rt2860_free_tx_pool(sc); 412 413 if (sc->ucode != NULL) 414 free(sc->ucode, M_DEVBUF, sc->ucsize); 415 416 return 0; 417 } 418 419 void 420 rt2860_suspend(void *xsc) 421 { 422 struct rt2860_softc *sc = xsc; 423 struct ifnet *ifp = &sc->sc_ic.ic_if; 424 425 if (ifp->if_flags & IFF_RUNNING) 426 rt2860_stop(ifp, 1); 427 } 428 429 void 430 rt2860_wakeup(void *xsc) 431 { 432 struct rt2860_softc *sc = xsc; 433 struct ifnet *ifp = &sc->sc_ic.ic_if; 434 435 if (ifp->if_flags & IFF_UP) 436 rt2860_init(ifp); 437 } 438 439 int 440 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 441 { 442 int nsegs, size, error; 443 444 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 445 446 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 447 BUS_DMA_NOWAIT, &ring->map); 448 if (error != 0) { 449 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 450 goto fail; 451 } 452 453 /* Tx rings must be 4-DWORD aligned */ 454 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 455 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 456 if (error != 0) { 457 printf("%s: could not allocate DMA memory\n", 458 sc->sc_dev.dv_xname); 459 goto fail; 460 } 461 462 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 463 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT); 464 if (error != 0) { 465 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 466 goto fail; 467 } 468 469 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 470 BUS_DMA_NOWAIT); 471 if (error != 0) { 472 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 473 goto fail; 474 } 475 476 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 477 478 ring->paddr = ring->map->dm_segs[0].ds_addr; 479 480 return 0; 481 482 fail: rt2860_free_tx_ring(sc, ring); 483 return error; 484 } 485 486 void 487 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 488 { 489 struct rt2860_tx_data *data; 490 int i; 491 492 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 493 if ((data = ring->data[i]) == NULL) 494 continue; /* nothing mapped in this slot */ 495 496 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 497 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 498 bus_dmamap_unload(sc->sc_dmat, data->map); 499 m_freem(data->m); 500 data->m= NULL; 501 data->ni = NULL; /* node already freed */ 502 503 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 504 ring->data[i] = NULL; 505 } 506 507 ring->queued = 0; 508 ring->cur = ring->next = 0; 509 } 510 511 void 512 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 513 { 514 struct rt2860_tx_data *data; 515 int i; 516 517 if (ring->txd != NULL) { 518 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 519 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 520 bus_dmamap_unload(sc->sc_dmat, ring->map); 521 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd, 522 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 523 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 524 } 525 if (ring->map != NULL) 526 bus_dmamap_destroy(sc->sc_dmat, ring->map); 527 528 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 529 if ((data = ring->data[i]) == NULL) 530 continue; /* nothing mapped in this slot */ 531 532 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 533 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 534 bus_dmamap_unload(sc->sc_dmat, data->map); 535 m_freem(data->m); 536 537 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 538 } 539 } 540 541 /* 542 * Allocate a pool of TX Wireless Information blocks. 543 */ 544 int 545 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 546 { 547 caddr_t vaddr; 548 bus_addr_t paddr; 549 int i, nsegs, size, error; 550 551 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 552 553 /* init data_pool early in case of failure.. */ 554 SLIST_INIT(&sc->data_pool); 555 556 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 557 BUS_DMA_NOWAIT, &sc->txwi_map); 558 if (error != 0) { 559 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 560 goto fail; 561 } 562 563 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 564 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 565 if (error != 0) { 566 printf("%s: could not allocate DMA memory\n", 567 sc->sc_dev.dv_xname); 568 goto fail; 569 } 570 571 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 572 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 573 if (error != 0) { 574 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 575 goto fail; 576 } 577 578 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 579 size, NULL, BUS_DMA_NOWAIT); 580 if (error != 0) { 581 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 582 goto fail; 583 } 584 585 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 586 BUS_DMASYNC_PREWRITE); 587 588 vaddr = sc->txwi_vaddr; 589 paddr = sc->txwi_map->dm_segs[0].ds_addr; 590 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 591 struct rt2860_tx_data *data = &sc->data[i]; 592 593 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 594 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 595 &data->map); /* <0> */ 596 if (error != 0) { 597 printf("%s: could not create DMA map\n", 598 sc->sc_dev.dv_xname); 599 goto fail; 600 } 601 data->txwi = (struct rt2860_txwi *)vaddr; 602 data->paddr = paddr; 603 vaddr += RT2860_TXWI_DMASZ; 604 paddr += RT2860_TXWI_DMASZ; 605 606 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 607 } 608 609 return 0; 610 611 fail: rt2860_free_tx_pool(sc); 612 return error; 613 } 614 615 void 616 rt2860_free_tx_pool(struct rt2860_softc *sc) 617 { 618 if (sc->txwi_vaddr != NULL) { 619 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 620 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 621 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 622 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 623 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 624 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 625 } 626 if (sc->txwi_map != NULL) 627 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 628 629 while (!SLIST_EMPTY(&sc->data_pool)) { 630 struct rt2860_tx_data *data; 631 data = SLIST_FIRST(&sc->data_pool); 632 bus_dmamap_destroy(sc->sc_dmat, data->map); 633 SLIST_REMOVE_HEAD(&sc->data_pool, next); 634 } 635 } 636 637 int 638 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 639 { 640 int i, nsegs, size, error; 641 642 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 643 644 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 645 BUS_DMA_NOWAIT, &ring->map); 646 if (error != 0) { 647 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 648 goto fail; 649 } 650 651 /* Rx ring must be 4-DWORD aligned */ 652 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 653 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 654 if (error != 0) { 655 printf("%s: could not allocate DMA memory\n", 656 sc->sc_dev.dv_xname); 657 goto fail; 658 } 659 660 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 661 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT); 662 if (error != 0) { 663 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 664 goto fail; 665 } 666 667 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 668 BUS_DMA_NOWAIT); 669 if (error != 0) { 670 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 671 goto fail; 672 } 673 674 ring->paddr = ring->map->dm_segs[0].ds_addr; 675 676 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 677 struct rt2860_rx_data *data = &ring->data[i]; 678 struct rt2860_rxd *rxd = &ring->rxd[i]; 679 680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 681 0, BUS_DMA_NOWAIT, &data->map); 682 if (error != 0) { 683 printf("%s: could not create DMA map\n", 684 sc->sc_dev.dv_xname); 685 goto fail; 686 } 687 688 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 689 if (data->m == NULL) { 690 printf("%s: could not allocate Rx mbuf\n", 691 sc->sc_dev.dv_xname); 692 error = ENOBUFS; 693 goto fail; 694 } 695 696 error = bus_dmamap_load(sc->sc_dmat, data->map, 697 mtod(data->m, void *), MCLBYTES, NULL, 698 BUS_DMA_READ | BUS_DMA_NOWAIT); 699 if (error != 0) { 700 printf("%s: could not load DMA map\n", 701 sc->sc_dev.dv_xname); 702 goto fail; 703 } 704 705 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 706 rxd->sdl0 = htole16(MCLBYTES); 707 } 708 709 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 710 711 return 0; 712 713 fail: rt2860_free_rx_ring(sc, ring); 714 return error; 715 } 716 717 void 718 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 719 { 720 int i; 721 722 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 723 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 724 725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 726 BUS_DMASYNC_PREWRITE); 727 728 ring->cur = 0; 729 } 730 731 void 732 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 733 { 734 int i; 735 736 if (ring->rxd != NULL) { 737 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 738 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 739 bus_dmamap_unload(sc->sc_dmat, ring->map); 740 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd, 741 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 742 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 743 } 744 if (ring->map != NULL) 745 bus_dmamap_destroy(sc->sc_dmat, ring->map); 746 747 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 748 struct rt2860_rx_data *data = &ring->data[i]; 749 750 if (data->m != NULL) { 751 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 752 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 753 bus_dmamap_unload(sc->sc_dmat, data->map); 754 m_freem(data->m); 755 } 756 if (data->map != NULL) 757 bus_dmamap_destroy(sc->sc_dmat, data->map); 758 } 759 } 760 761 struct ieee80211_node * 762 rt2860_node_alloc(struct ieee80211com *ic) 763 { 764 return malloc(sizeof (struct rt2860_node), M_DEVBUF, 765 M_NOWAIT | M_ZERO); 766 } 767 768 int 769 rt2860_media_change(struct ifnet *ifp) 770 { 771 struct rt2860_softc *sc = ifp->if_softc; 772 struct ieee80211com *ic = &sc->sc_ic; 773 uint8_t rate, ridx; 774 int error; 775 776 error = ieee80211_media_change(ifp); 777 if (error != ENETRESET) 778 return error; 779 780 if (ic->ic_fixed_rate != -1) { 781 rate = ic->ic_sup_rates[ic->ic_curmode]. 782 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 783 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 784 if (rt2860_rates[ridx].rate == rate) 785 break; 786 sc->fixed_ridx = ridx; 787 } 788 789 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 790 (IFF_UP | IFF_RUNNING)) { 791 rt2860_stop(ifp, 0); 792 rt2860_init(ifp); 793 } 794 return 0; 795 } 796 797 void 798 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 799 { 800 struct rt2860_softc *sc = arg; 801 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 802 803 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 804 } 805 806 void 807 rt2860_updatestats(struct rt2860_softc *sc) 808 { 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 #ifndef IEEE80211_STA_ONLY 812 /* 813 * In IBSS or HostAP modes (when the hardware sends beacons), the 814 * MAC can run into a livelock and start sending CTS-to-self frames 815 * like crazy if protection is enabled. Fortunately, we can detect 816 * when such a situation occurs and reset the MAC. 817 */ 818 if (ic->ic_curmode != IEEE80211_M_STA) { 819 /* check if we're in a livelock situation.. */ 820 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 821 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 822 /* ..and reset MAC/BBP for a while.. */ 823 DPRINTF(("CTS-to-self livelock detected\n")); 824 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 825 RAL_BARRIER_WRITE(sc); 826 DELAY(1); 827 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 828 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 829 } 830 } 831 #endif 832 if (ic->ic_opmode == IEEE80211_M_STA) 833 rt2860_iter_func(sc, ic->ic_bss); 834 #ifndef IEEE80211_STA_ONLY 835 else 836 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc); 837 #endif 838 } 839 840 void 841 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 842 { 843 struct rt2860_softc *sc = ic->ic_softc; 844 struct rt2860_node *rn = (void *)ni; 845 struct ieee80211_rateset *rs = &ni->ni_rates; 846 uint8_t rate, wcid = 0; 847 int ridx, i, j; 848 849 if (isnew && ni->ni_associd != 0) { 850 /* only interested in true associations */ 851 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 852 853 /* init WCID table entry */ 854 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 855 ni->ni_macaddr, IEEE80211_ADDR_LEN); 856 } 857 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 858 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 859 860 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 861 /* start at lowest available bit-rate, AMRR will raise */ 862 ni->ni_txrate = 0; 863 864 for (i = 0; i < rs->rs_nrates; i++) { 865 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 866 /* convert 802.11 rate to hardware rate index */ 867 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 868 if (rt2860_rates[ridx].rate == rate) 869 break; 870 rn->ridx[i] = ridx; 871 /* determine rate of control response frames */ 872 for (j = i; j >= 0; j--) { 873 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 874 rt2860_rates[rn->ridx[i]].phy == 875 rt2860_rates[rn->ridx[j]].phy) 876 break; 877 } 878 if (j >= 0) { 879 rn->ctl_ridx[i] = rn->ridx[j]; 880 } else { 881 /* no basic rate found, use mandatory one */ 882 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 883 } 884 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 885 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 886 } 887 } 888 889 #ifndef IEEE80211_STA_ONLY 890 void 891 rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni) 892 { 893 struct rt2860_softc *sc = ic->ic_softc; 894 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 895 896 /* clear Rx WCID search table entry */ 897 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 898 } 899 #endif 900 901 int 902 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 903 uint8_t tid) 904 { 905 struct rt2860_softc *sc = ic->ic_softc; 906 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 907 uint32_t tmp; 908 909 /* update BA session mask */ 910 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 911 tmp |= (1 << tid) << 16; 912 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 913 return 0; 914 } 915 916 void 917 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 918 uint8_t tid) 919 { 920 struct rt2860_softc *sc = ic->ic_softc; 921 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 922 uint32_t tmp; 923 924 /* update BA session mask */ 925 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 926 tmp &= ~((1 << tid) << 16); 927 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 928 } 929 930 int 931 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 932 { 933 struct rt2860_softc *sc = ic->ic_if.if_softc; 934 enum ieee80211_state ostate; 935 uint32_t tmp; 936 937 ostate = ic->ic_state; 938 939 if (ostate == IEEE80211_S_RUN) { 940 /* turn link LED off */ 941 rt2860_set_leds(sc, RT2860_LED_RADIO); 942 } 943 944 switch (nstate) { 945 case IEEE80211_S_INIT: 946 if (ostate == IEEE80211_S_RUN) { 947 /* abort TSF synchronization */ 948 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 949 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 950 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 951 RT2860_TBTT_TIMER_EN)); 952 } 953 rt2860_set_gp_timer(sc, 0); 954 break; 955 956 case IEEE80211_S_SCAN: 957 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 958 if (ostate != IEEE80211_S_SCAN) 959 rt2860_set_gp_timer(sc, 150); 960 break; 961 962 case IEEE80211_S_AUTH: 963 case IEEE80211_S_ASSOC: 964 rt2860_set_gp_timer(sc, 0); 965 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 966 break; 967 968 case IEEE80211_S_RUN: 969 rt2860_set_gp_timer(sc, 0); 970 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 971 972 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 973 rt2860_updateslot(ic); 974 rt2860_enable_mrr(sc); 975 rt2860_set_txpreamble(sc); 976 rt2860_set_basicrates(sc); 977 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 978 } 979 980 #ifndef IEEE80211_STA_ONLY 981 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 982 ic->ic_opmode == IEEE80211_M_IBSS) 983 (void)rt2860_setup_beacon(sc); 984 #endif 985 986 if (ic->ic_opmode == IEEE80211_M_STA) { 987 /* fake a join to init the tx rate */ 988 rt2860_newassoc(ic, ic->ic_bss, 1); 989 } 990 991 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 992 rt2860_enable_tsf_sync(sc); 993 rt2860_set_gp_timer(sc, 500); 994 } 995 996 /* turn link LED on */ 997 rt2860_set_leds(sc, RT2860_LED_RADIO | 998 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 999 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1000 break; 1001 } 1002 1003 return sc->sc_newstate(ic, nstate, arg); 1004 } 1005 1006 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 1007 uint16_t 1008 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1009 { 1010 uint32_t tmp; 1011 uint16_t reg; 1012 int ntries; 1013 1014 addr *= 2; 1015 /*- 1016 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1017 * DATA0: F E D C 1018 * DATA1: B A 9 8 1019 * DATA2: 7 6 5 4 1020 * DATA3: 3 2 1 0 1021 */ 1022 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1023 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1024 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1025 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1026 for (ntries = 0; ntries < 500; ntries++) { 1027 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1028 if (!(tmp & RT3070_EFSROM_KICK)) 1029 break; 1030 DELAY(2); 1031 } 1032 if (ntries == 500) 1033 return 0xffff; 1034 1035 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1036 return 0xffff; /* address not found */ 1037 1038 /* determine to which 32-bit register our 16-bit word belongs */ 1039 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1040 tmp = RAL_READ(sc, reg); 1041 1042 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1043 } 1044 1045 /* Read 16 bits from eFUSE ROM (RT3290 only) */ 1046 uint16_t 1047 rt3290_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1048 { 1049 uint32_t tmp; 1050 uint16_t reg; 1051 int ntries; 1052 1053 addr *= 2; 1054 /*- 1055 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1056 * DATA3: 3 2 1 0 1057 * DATA2: 7 6 5 4 1058 * DATA1: B A 9 8 1059 * DATA0: F E D C 1060 */ 1061 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL); 1062 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1063 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1064 RAL_WRITE(sc, RT3290_EFUSE_CTRL, tmp); 1065 for (ntries = 0; ntries < 500; ntries++) { 1066 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL); 1067 if (!(tmp & RT3070_EFSROM_KICK)) 1068 break; 1069 DELAY(2); 1070 } 1071 if (ntries == 500) 1072 return 0xffff; 1073 1074 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1075 return 0xffff; /* address not found */ 1076 1077 /* determine to which 32-bit register our 16-bit word belongs */ 1078 reg = RT3290_EFUSE_DATA3 + (addr & 0xc); 1079 tmp = RAL_READ(sc, reg); 1080 1081 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1082 } 1083 1084 /* 1085 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1086 * 93C66 or 93C86). 1087 */ 1088 uint16_t 1089 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1090 { 1091 uint32_t tmp; 1092 uint16_t val; 1093 int n; 1094 1095 /* clock C once before the first command */ 1096 RT2860_EEPROM_CTL(sc, 0); 1097 1098 RT2860_EEPROM_CTL(sc, RT2860_S); 1099 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1100 RT2860_EEPROM_CTL(sc, RT2860_S); 1101 1102 /* write start bit (1) */ 1103 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1104 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1105 1106 /* write READ opcode (10) */ 1107 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1108 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1109 RT2860_EEPROM_CTL(sc, RT2860_S); 1110 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1111 1112 /* write address (A5-A0 or A7-A0) */ 1113 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1114 for (; n >= 0; n--) { 1115 RT2860_EEPROM_CTL(sc, RT2860_S | 1116 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1117 RT2860_EEPROM_CTL(sc, RT2860_S | 1118 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1119 } 1120 1121 RT2860_EEPROM_CTL(sc, RT2860_S); 1122 1123 /* read data Q15-Q0 */ 1124 val = 0; 1125 for (n = 15; n >= 0; n--) { 1126 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1127 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1128 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1129 RT2860_EEPROM_CTL(sc, RT2860_S); 1130 } 1131 1132 RT2860_EEPROM_CTL(sc, 0); 1133 1134 /* clear Chip Select and clock C */ 1135 RT2860_EEPROM_CTL(sc, RT2860_S); 1136 RT2860_EEPROM_CTL(sc, 0); 1137 RT2860_EEPROM_CTL(sc, RT2860_C); 1138 1139 return val; 1140 } 1141 1142 static __inline uint16_t 1143 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1144 { 1145 /* either eFUSE ROM or EEPROM */ 1146 return sc->sc_srom_read(sc, addr); 1147 } 1148 1149 void 1150 rt2860_intr_coherent(struct rt2860_softc *sc) 1151 { 1152 uint32_t tmp; 1153 1154 /* DMA finds data coherent event when checking the DDONE bit */ 1155 1156 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1157 1158 /* restart DMA engine */ 1159 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1160 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1161 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1162 1163 (void)rt2860_txrx_enable(sc); 1164 } 1165 1166 void 1167 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1168 { 1169 struct ifnet *ifp = &sc->sc_ic.ic_if; 1170 struct ieee80211_amrr_node *amn; 1171 uint32_t stat; 1172 uint8_t wcid, mcs, pid; 1173 1174 /* drain Tx status FIFO (maxsize = 16) */ 1175 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1176 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1177 1178 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1179 1180 /* if no ACK was requested, no feedback is available */ 1181 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1182 continue; 1183 1184 /* update per-STA AMRR stats */ 1185 amn = &sc->amn[wcid]; 1186 amn->amn_txcnt++; 1187 if (stat & RT2860_TXQ_OK) { 1188 /* 1189 * Check if there were retries, ie if the Tx success 1190 * rate is different from the requested rate. Note 1191 * that it works only because we do not allow rate 1192 * fallback from OFDM to CCK. 1193 */ 1194 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1195 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1196 if (mcs + 1 != pid) 1197 amn->amn_retrycnt++; 1198 } else { 1199 amn->amn_retrycnt++; 1200 ifp->if_oerrors++; 1201 } 1202 } 1203 } 1204 1205 void 1206 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1207 { 1208 struct ieee80211com *ic = &sc->sc_ic; 1209 struct ifnet *ifp = &ic->ic_if; 1210 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1211 uint32_t hw; 1212 1213 rt2860_drain_stats_fifo(sc); 1214 1215 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1216 while (ring->next != hw) { 1217 struct rt2860_tx_data *data = ring->data[ring->next]; 1218 1219 if (data != NULL) { 1220 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1221 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1222 bus_dmamap_unload(sc->sc_dmat, data->map); 1223 m_freem(data->m); 1224 data->m= NULL; 1225 ieee80211_release_node(ic, data->ni); 1226 data->ni = NULL; 1227 1228 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1229 ring->data[ring->next] = NULL; 1230 } 1231 ring->queued--; 1232 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1233 } 1234 1235 sc->sc_tx_timer = 0; 1236 if (ring->queued <= RT2860_TX_RING_ONEMORE) 1237 sc->qfullmsk &= ~(1 << qid); 1238 ifq_clr_oactive(&ifp->if_snd); 1239 rt2860_start(ifp); 1240 } 1241 1242 /* 1243 * Return the Rx chain with the highest RSSI for a given frame. 1244 */ 1245 static __inline uint8_t 1246 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1247 { 1248 uint8_t rxchain = 0; 1249 1250 if (sc->nrxchains > 1) { 1251 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1252 rxchain = 1; 1253 if (sc->nrxchains > 2) 1254 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1255 rxchain = 2; 1256 } 1257 return rxchain; 1258 } 1259 1260 void 1261 rt2860_rx_intr(struct rt2860_softc *sc) 1262 { 1263 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1264 struct ieee80211com *ic = &sc->sc_ic; 1265 struct ifnet *ifp = &ic->ic_if; 1266 struct ieee80211_frame *wh; 1267 struct ieee80211_rxinfo rxi; 1268 struct ieee80211_node *ni; 1269 struct mbuf *m, *m1; 1270 uint32_t hw; 1271 uint8_t ant, rssi; 1272 int error; 1273 #if NBPFILTER > 0 1274 struct rt2860_rx_radiotap_header *tap; 1275 uint16_t phy; 1276 #endif 1277 1278 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1279 while (sc->rxq.cur != hw) { 1280 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1281 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1282 struct rt2860_rxwi *rxwi; 1283 1284 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1285 sc->rxq.cur * sizeof (struct rt2860_rxd), 1286 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1287 1288 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1289 DPRINTF(("RXD DDONE bit not set!\n")); 1290 break; /* should not happen */ 1291 } 1292 1293 if (__predict_false(rxd->flags & 1294 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1295 ifp->if_ierrors++; 1296 goto skip; 1297 } 1298 1299 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1300 /* report MIC failures to net80211 for TKIP */ 1301 ic->ic_stats.is_rx_locmicfail++; 1302 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1303 ifp->if_ierrors++; 1304 goto skip; 1305 } 1306 1307 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1308 if (__predict_false(m1 == NULL)) { 1309 ifp->if_ierrors++; 1310 goto skip; 1311 } 1312 1313 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1314 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1315 bus_dmamap_unload(sc->sc_dmat, data->map); 1316 1317 error = bus_dmamap_load(sc->sc_dmat, data->map, 1318 mtod(m1, void *), MCLBYTES, NULL, 1319 BUS_DMA_READ | BUS_DMA_NOWAIT); 1320 if (__predict_false(error != 0)) { 1321 m_freem(m1); 1322 1323 /* try to reload the old mbuf */ 1324 error = bus_dmamap_load(sc->sc_dmat, data->map, 1325 mtod(data->m, void *), MCLBYTES, NULL, 1326 BUS_DMA_READ | BUS_DMA_NOWAIT); 1327 if (__predict_false(error != 0)) { 1328 panic("%s: could not load old rx mbuf", 1329 sc->sc_dev.dv_xname); 1330 } 1331 /* physical address may have changed */ 1332 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1333 ifp->if_ierrors++; 1334 goto skip; 1335 } 1336 1337 /* 1338 * New mbuf successfully loaded, update Rx ring and continue 1339 * processing. 1340 */ 1341 m = data->m; 1342 data->m = m1; 1343 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1344 1345 rxwi = mtod(m, struct rt2860_rxwi *); 1346 1347 /* finalize mbuf */ 1348 m->m_data = (caddr_t)(rxwi + 1); 1349 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff; 1350 1351 wh = mtod(m, struct ieee80211_frame *); 1352 rxi.rxi_flags = 0; 1353 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1354 /* frame is decrypted by hardware */ 1355 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1356 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1357 } 1358 1359 /* HW may insert 2 padding bytes after 802.11 header */ 1360 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1361 u_int hdrlen = ieee80211_get_hdrlen(wh); 1362 memmove((caddr_t)wh + 2, wh, hdrlen); 1363 m->m_data += 2; 1364 wh = mtod(m, struct ieee80211_frame *); 1365 } 1366 1367 ant = rt2860_maxrssi_chain(sc, rxwi); 1368 rssi = rxwi->rssi[ant]; 1369 1370 #if NBPFILTER > 0 1371 if (__predict_true(sc->sc_drvbpf == NULL)) 1372 goto skipbpf; 1373 1374 tap = &sc->sc_rxtap; 1375 tap->wr_flags = 0; 1376 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1377 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1378 tap->wr_antsignal = rssi; 1379 tap->wr_antenna = ant; 1380 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1381 tap->wr_rate = 2; /* in case it can't be found below */ 1382 phy = letoh16(rxwi->phy); 1383 switch (phy & RT2860_PHY_MODE) { 1384 case RT2860_PHY_CCK: 1385 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1386 case 0: tap->wr_rate = 2; break; 1387 case 1: tap->wr_rate = 4; break; 1388 case 2: tap->wr_rate = 11; break; 1389 case 3: tap->wr_rate = 22; break; 1390 } 1391 if (phy & RT2860_PHY_SHPRE) 1392 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1393 break; 1394 case RT2860_PHY_OFDM: 1395 switch (phy & RT2860_PHY_MCS) { 1396 case 0: tap->wr_rate = 12; break; 1397 case 1: tap->wr_rate = 18; break; 1398 case 2: tap->wr_rate = 24; break; 1399 case 3: tap->wr_rate = 36; break; 1400 case 4: tap->wr_rate = 48; break; 1401 case 5: tap->wr_rate = 72; break; 1402 case 6: tap->wr_rate = 96; break; 1403 case 7: tap->wr_rate = 108; break; 1404 } 1405 break; 1406 } 1407 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, 1408 BPF_DIRECTION_IN); 1409 skipbpf: 1410 #endif 1411 /* grab a reference to the source node */ 1412 ni = ieee80211_find_rxnode(ic, wh); 1413 1414 /* send the frame to the 802.11 layer */ 1415 rxi.rxi_rssi = rssi; 1416 rxi.rxi_tstamp = 0; /* unused */ 1417 ieee80211_inputm(ifp, m, ni, &rxi, &ml); 1418 1419 /* node is no longer needed */ 1420 ieee80211_release_node(ic, ni); 1421 1422 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1423 1424 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1425 sc->rxq.cur * sizeof (struct rt2860_rxd), 1426 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1427 1428 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1429 } 1430 if_input(ifp, &ml); 1431 1432 /* tell HW what we have processed */ 1433 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1434 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1435 } 1436 1437 void 1438 rt2860_tbtt_intr(struct rt2860_softc *sc) 1439 { 1440 struct ieee80211com *ic = &sc->sc_ic; 1441 1442 #ifndef IEEE80211_STA_ONLY 1443 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1444 /* one less beacon until next DTIM */ 1445 if (ic->ic_dtim_count == 0) 1446 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1447 else 1448 ic->ic_dtim_count--; 1449 1450 /* update dynamic parts of beacon */ 1451 rt2860_setup_beacon(sc); 1452 1453 /* flush buffered multicast frames */ 1454 if (ic->ic_dtim_count == 0) 1455 ieee80211_notify_dtim(ic); 1456 } 1457 #endif 1458 /* check if protection mode has changed */ 1459 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1460 rt2860_updateprot(ic); 1461 sc->sc_ic_flags = ic->ic_flags; 1462 } 1463 } 1464 1465 void 1466 rt2860_gp_intr(struct rt2860_softc *sc) 1467 { 1468 struct ieee80211com *ic = &sc->sc_ic; 1469 1470 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1471 1472 if (ic->ic_state == IEEE80211_S_SCAN) 1473 ieee80211_next_scan(&ic->ic_if); 1474 else if (ic->ic_state == IEEE80211_S_RUN) 1475 rt2860_updatestats(sc); 1476 } 1477 1478 int 1479 rt2860_intr(void *arg) 1480 { 1481 struct rt2860_softc *sc = arg; 1482 uint32_t r; 1483 1484 r = RAL_READ(sc, RT2860_INT_STATUS); 1485 if (__predict_false(r == 0xffffffff)) 1486 return 0; /* device likely went away */ 1487 if (r == 0) 1488 return 0; /* not for us */ 1489 1490 /* acknowledge interrupts */ 1491 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1492 1493 if (r & RT2860_TX_RX_COHERENT) 1494 rt2860_intr_coherent(sc); 1495 1496 if (r & RT2860_MAC_INT_2) /* TX status */ 1497 rt2860_drain_stats_fifo(sc); 1498 1499 if (r & RT2860_TX_DONE_INT5) 1500 rt2860_tx_intr(sc, 5); 1501 1502 if (r & RT2860_RX_DONE_INT) 1503 rt2860_rx_intr(sc); 1504 1505 if (r & RT2860_TX_DONE_INT4) 1506 rt2860_tx_intr(sc, 4); 1507 1508 if (r & RT2860_TX_DONE_INT3) 1509 rt2860_tx_intr(sc, 3); 1510 1511 if (r & RT2860_TX_DONE_INT2) 1512 rt2860_tx_intr(sc, 2); 1513 1514 if (r & RT2860_TX_DONE_INT1) 1515 rt2860_tx_intr(sc, 1); 1516 1517 if (r & RT2860_TX_DONE_INT0) 1518 rt2860_tx_intr(sc, 0); 1519 1520 if (r & RT2860_MAC_INT_0) /* TBTT */ 1521 rt2860_tbtt_intr(sc); 1522 1523 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1524 /* TBD wakeup */; 1525 1526 if (r & RT2860_MAC_INT_4) /* GP timer */ 1527 rt2860_gp_intr(sc); 1528 1529 return 1; 1530 } 1531 1532 int 1533 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1534 { 1535 struct ieee80211com *ic = &sc->sc_ic; 1536 struct rt2860_node *rn = (void *)ni; 1537 struct rt2860_tx_ring *ring; 1538 struct rt2860_tx_data *data; 1539 struct rt2860_txd *txd; 1540 struct rt2860_txwi *txwi; 1541 struct ieee80211_frame *wh; 1542 bus_dma_segment_t *seg; 1543 u_int hdrlen; 1544 uint16_t qos, dur; 1545 uint8_t type, qsel, mcs, pid, tid, qid; 1546 int nsegs, hasqos, ridx, ctl_ridx; 1547 1548 /* the data pool contains at least one element, pick the first */ 1549 data = SLIST_FIRST(&sc->data_pool); 1550 1551 wh = mtod(m, struct ieee80211_frame *); 1552 hdrlen = ieee80211_get_hdrlen(wh); 1553 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1554 1555 if ((hasqos = ieee80211_has_qos(wh))) { 1556 qos = ieee80211_get_qos(wh); 1557 tid = qos & IEEE80211_QOS_TID; 1558 qid = ieee80211_up_to_ac(ic, tid); 1559 } else { 1560 qos = 0; 1561 tid = 0; 1562 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1563 sc->mgtqid : EDCA_AC_BE; 1564 } 1565 ring = &sc->txq[qid]; 1566 1567 /* pickup a rate index */ 1568 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1569 type != IEEE80211_FC0_TYPE_DATA) { 1570 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1571 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1572 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1573 } else if (ic->ic_fixed_rate != -1) { 1574 ridx = sc->fixed_ridx; 1575 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1576 } else { 1577 ridx = rn->ridx[ni->ni_txrate]; 1578 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1579 } 1580 1581 /* get MCS code from rate index */ 1582 mcs = rt2860_rates[ridx].mcs; 1583 1584 /* setup TX Wireless Information */ 1585 txwi = data->txwi; 1586 txwi->flags = 0; 1587 /* let HW generate seq numbers for non-QoS frames */ 1588 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1589 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1590 txwi->len = htole16(m->m_pkthdr.len); 1591 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1592 txwi->phy = htole16(RT2860_PHY_CCK); 1593 if (ridx != RT2860_RIDX_CCK1 && 1594 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1595 mcs |= RT2860_PHY_SHPRE; 1596 } else 1597 txwi->phy = htole16(RT2860_PHY_OFDM); 1598 txwi->phy |= htole16(mcs); 1599 1600 /* 1601 * We store the MCS code into the driver-private PacketID field. 1602 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1603 * that we know at which initial rate the frame was transmitted. 1604 * We add 1 to the MCS code because setting the PacketID field to 1605 * 0 means that we don't want feedback in TX_STAT_FIFO. 1606 */ 1607 pid = (mcs + 1) & 0xf; 1608 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1609 1610 /* check if RTS/CTS or CTS-to-self protection is required */ 1611 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1612 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1613 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1614 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1615 txwi->txop = RT2860_TX_TXOP_HT; 1616 else 1617 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1618 1619 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1620 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 1621 IEEE80211_QOS_ACK_POLICY_NOACK)) { 1622 txwi->xflags |= RT2860_TX_ACK; 1623 1624 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1625 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1626 else 1627 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1628 *(uint16_t *)wh->i_dur = htole16(dur); 1629 } 1630 #ifndef IEEE80211_STA_ONLY 1631 /* ask MAC to insert timestamp into probe responses */ 1632 if ((wh->i_fc[0] & 1633 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1634 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1635 /* NOTE: beacons do not pass through tx_data() */ 1636 txwi->flags |= RT2860_TX_TS; 1637 #endif 1638 1639 #if NBPFILTER > 0 1640 if (__predict_false(sc->sc_drvbpf != NULL)) { 1641 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1642 1643 tap->wt_flags = 0; 1644 tap->wt_rate = rt2860_rates[ridx].rate; 1645 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1646 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1647 tap->wt_hwqueue = qid; 1648 if (mcs & RT2860_PHY_SHPRE) 1649 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1650 1651 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, 1652 BPF_DIRECTION_OUT); 1653 } 1654 #endif 1655 1656 /* copy and trim 802.11 header */ 1657 memcpy(txwi + 1, wh, hdrlen); 1658 m_adj(m, hdrlen); 1659 1660 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */ 1661 1662 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) { 1663 if (m_defrag(m, M_DONTWAIT)) 1664 return (ENOBUFS); 1665 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1666 data->map, m, BUS_DMA_NOWAIT)) 1667 return (EFBIG); 1668 } 1669 1670 /* The map will fit into the tx ring: (a "full" ring may have a few 1671 * unused descriptors, at most (txds(MAX_SCATTER) - 1)) 1672 * 1673 * ring->queued + txds(data->map->nsegs) 1674 * <= { <0> data->map->nsegs <= MAX_SCATTER } 1675 * ring->queued + txds(MAX_SCATTER) 1676 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) } 1677 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER) 1678 * <= { arithmetic } 1679 * TX_RING_MAX 1680 */ 1681 1682 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1683 1684 /* first segment is TXWI + 802.11 header */ 1685 txd = &ring->txd[ring->cur]; 1686 txd->sdp0 = htole32(data->paddr); 1687 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1688 txd->flags = qsel; 1689 1690 /* setup payload segments */ 1691 seg = data->map->dm_segs; 1692 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1693 txd->sdp1 = htole32(seg->ds_addr); 1694 txd->sdl1 = htole16(seg->ds_len); 1695 seg++; 1696 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1697 /* grab a new Tx descriptor */ 1698 txd = &ring->txd[ring->cur]; 1699 txd->sdp0 = htole32(seg->ds_addr); 1700 txd->sdl0 = htole16(seg->ds_len); 1701 txd->flags = qsel; 1702 seg++; 1703 } 1704 /* finalize last segment */ 1705 if (nsegs > 0) { 1706 txd->sdp1 = htole32(seg->ds_addr); 1707 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1708 } else { 1709 txd->sdl0 |= htole16(RT2860_TX_LS0); 1710 txd->sdl1 = 0; 1711 } 1712 1713 /* remove from the free pool and link it into the SW Tx slot */ 1714 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1715 data->m = m; 1716 data->ni = ni; 1717 ring->data[ring->cur] = data; 1718 1719 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1720 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1721 BUS_DMASYNC_PREWRITE); 1722 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1723 BUS_DMASYNC_PREWRITE); 1724 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1725 BUS_DMASYNC_PREWRITE); 1726 1727 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1728 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1729 1730 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1731 ring->queued += 1 + (data->map->dm_nsegs / 2); 1732 if (ring->queued > RT2860_TX_RING_ONEMORE) 1733 sc->qfullmsk |= 1 << qid; 1734 1735 /* kick Tx */ 1736 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1737 1738 return 0; 1739 } 1740 1741 void 1742 rt2860_start(struct ifnet *ifp) 1743 { 1744 struct rt2860_softc *sc = ifp->if_softc; 1745 struct ieee80211com *ic = &sc->sc_ic; 1746 struct ieee80211_node *ni; 1747 struct mbuf *m; 1748 1749 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1750 return; 1751 1752 for (;;) { 1753 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1754 ifq_set_oactive(&ifp->if_snd); 1755 break; 1756 } 1757 /* send pending management frames first */ 1758 m = mq_dequeue(&ic->ic_mgtq); 1759 if (m != NULL) { 1760 ni = m->m_pkthdr.ph_cookie; 1761 goto sendit; 1762 } 1763 if (ic->ic_state != IEEE80211_S_RUN) 1764 break; 1765 1766 /* send buffered frames for power-save mode */ 1767 m = mq_dequeue(&ic->ic_pwrsaveq); 1768 if (m != NULL) { 1769 ni = m->m_pkthdr.ph_cookie; 1770 goto sendit; 1771 } 1772 1773 /* encapsulate and send data frames */ 1774 IFQ_DEQUEUE(&ifp->if_snd, m); 1775 if (m == NULL) 1776 break; 1777 #if NBPFILTER > 0 1778 if (ifp->if_bpf != NULL) 1779 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1780 #endif 1781 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1782 continue; 1783 sendit: 1784 #if NBPFILTER > 0 1785 if (ic->ic_rawbpf != NULL) 1786 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1787 #endif 1788 if (rt2860_tx(sc, m, ni) != 0) { 1789 m_freem(m); 1790 ieee80211_release_node(ic, ni); 1791 ifp->if_oerrors++; 1792 continue; 1793 } 1794 1795 sc->sc_tx_timer = 5; 1796 ifp->if_timer = 1; 1797 } 1798 } 1799 1800 void 1801 rt2860_watchdog(struct ifnet *ifp) 1802 { 1803 struct rt2860_softc *sc = ifp->if_softc; 1804 1805 ifp->if_timer = 0; 1806 1807 if (sc->sc_tx_timer > 0) { 1808 if (--sc->sc_tx_timer == 0) { 1809 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1810 rt2860_stop(ifp, 0); 1811 rt2860_init(ifp); 1812 ifp->if_oerrors++; 1813 return; 1814 } 1815 ifp->if_timer = 1; 1816 } 1817 1818 ieee80211_watchdog(ifp); 1819 } 1820 1821 int 1822 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1823 { 1824 struct rt2860_softc *sc = ifp->if_softc; 1825 struct ieee80211com *ic = &sc->sc_ic; 1826 int s, error = 0; 1827 1828 s = splnet(); 1829 1830 switch (cmd) { 1831 case SIOCSIFADDR: 1832 ifp->if_flags |= IFF_UP; 1833 /* FALLTHROUGH */ 1834 case SIOCSIFFLAGS: 1835 if (ifp->if_flags & IFF_UP) { 1836 if (!(ifp->if_flags & IFF_RUNNING)) 1837 rt2860_init(ifp); 1838 } else { 1839 if (ifp->if_flags & IFF_RUNNING) 1840 rt2860_stop(ifp, 1); 1841 } 1842 break; 1843 1844 case SIOCS80211CHANNEL: 1845 /* 1846 * This allows for fast channel switching in monitor mode 1847 * (used by kismet). In IBSS mode, we must explicitly reset 1848 * the interface to generate a new beacon frame. 1849 */ 1850 error = ieee80211_ioctl(ifp, cmd, data); 1851 if (error == ENETRESET && 1852 ic->ic_opmode == IEEE80211_M_MONITOR) { 1853 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1854 (IFF_UP | IFF_RUNNING)) 1855 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1856 error = 0; 1857 } 1858 break; 1859 1860 default: 1861 error = ieee80211_ioctl(ifp, cmd, data); 1862 } 1863 1864 if (error == ENETRESET) { 1865 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1866 (IFF_UP | IFF_RUNNING)) { 1867 rt2860_stop(ifp, 0); 1868 rt2860_init(ifp); 1869 } 1870 error = 0; 1871 } 1872 1873 splx(s); 1874 1875 return error; 1876 } 1877 1878 /* 1879 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1880 * We access the BBP through the 8051 microcontroller unit which means that 1881 * the microcode must be loaded first. 1882 */ 1883 void 1884 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1885 { 1886 int ntries; 1887 1888 for (ntries = 0; ntries < 100; ntries++) { 1889 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1890 break; 1891 DELAY(1); 1892 } 1893 if (ntries == 100) { 1894 printf("%s: could not write to BBP through MCU\n", 1895 sc->sc_dev.dv_xname); 1896 return; 1897 } 1898 1899 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1900 RT2860_BBP_CSR_KICK | reg << 8 | val); 1901 RAL_BARRIER_WRITE(sc); 1902 1903 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1904 DELAY(1000); 1905 } 1906 1907 uint8_t 1908 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1909 { 1910 uint32_t val; 1911 int ntries; 1912 1913 for (ntries = 0; ntries < 100; ntries++) { 1914 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1915 break; 1916 DELAY(1); 1917 } 1918 if (ntries == 100) { 1919 printf("%s: could not read from BBP through MCU\n", 1920 sc->sc_dev.dv_xname); 1921 return 0; 1922 } 1923 1924 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1925 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1926 RAL_BARRIER_WRITE(sc); 1927 1928 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1929 DELAY(1000); 1930 1931 for (ntries = 0; ntries < 100; ntries++) { 1932 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1933 if (!(val & RT2860_BBP_CSR_KICK)) 1934 return val & 0xff; 1935 DELAY(1); 1936 } 1937 printf("%s: could not read from BBP through MCU\n", 1938 sc->sc_dev.dv_xname); 1939 1940 return 0; 1941 } 1942 1943 /* 1944 * Write to one of the 4 programmable 24-bit RF registers. 1945 */ 1946 void 1947 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 1948 { 1949 uint32_t tmp; 1950 int ntries; 1951 1952 for (ntries = 0; ntries < 100; ntries++) { 1953 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 1954 break; 1955 DELAY(1); 1956 } 1957 if (ntries == 100) { 1958 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1959 return; 1960 } 1961 1962 /* RF registers are 24-bit on the RT2860 */ 1963 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1964 (val & 0x3fffff) << 2 | (reg & 3); 1965 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 1966 } 1967 1968 uint8_t 1969 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 1970 { 1971 uint32_t tmp; 1972 int ntries; 1973 1974 for (ntries = 0; ntries < 100; ntries++) { 1975 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 1976 break; 1977 DELAY(1); 1978 } 1979 if (ntries == 100) { 1980 printf("%s: could not read RF register\n", 1981 sc->sc_dev.dv_xname); 1982 return 0xff; 1983 } 1984 tmp = RT3070_RF_KICK | reg << 8; 1985 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 1986 1987 for (ntries = 0; ntries < 100; ntries++) { 1988 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 1989 if (!(tmp & RT3070_RF_KICK)) 1990 break; 1991 DELAY(1); 1992 } 1993 if (ntries == 100) { 1994 printf("%s: could not read RF register\n", 1995 sc->sc_dev.dv_xname); 1996 return 0xff; 1997 } 1998 return tmp & 0xff; 1999 } 2000 2001 void 2002 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2003 { 2004 uint32_t tmp; 2005 int ntries; 2006 2007 for (ntries = 0; ntries < 10; ntries++) { 2008 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2009 break; 2010 DELAY(10); 2011 } 2012 if (ntries == 10) { 2013 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2014 return; 2015 } 2016 2017 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2018 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2019 } 2020 2021 /* 2022 * Send a command to the 8051 microcontroller unit. 2023 */ 2024 int 2025 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2026 { 2027 int slot, ntries; 2028 uint32_t tmp; 2029 uint8_t cid; 2030 2031 for (ntries = 0; ntries < 100; ntries++) { 2032 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2033 break; 2034 DELAY(2); 2035 } 2036 if (ntries == 100) 2037 return EIO; 2038 2039 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2040 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2041 RAL_BARRIER_WRITE(sc); 2042 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2043 2044 if (!wait) 2045 return 0; 2046 /* wait for the command to complete */ 2047 for (ntries = 0; ntries < 200; ntries++) { 2048 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2049 /* find the command slot */ 2050 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2051 if ((tmp & 0xff) == cid) 2052 break; 2053 if (slot < 4) 2054 break; 2055 DELAY(100); 2056 } 2057 if (ntries == 200) { 2058 /* clear command and status */ 2059 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2060 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2061 return ETIMEDOUT; 2062 } 2063 /* get command status (1 means success) */ 2064 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2065 tmp = (tmp >> (slot * 8)) & 0xff; 2066 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2067 cmd, slot, tmp)); 2068 /* clear command and status */ 2069 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2070 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2071 return (tmp == 1) ? 0 : EIO; 2072 } 2073 2074 void 2075 rt2860_enable_mrr(struct rt2860_softc *sc) 2076 { 2077 #define CCK(mcs) (mcs) 2078 #define OFDM(mcs) (1 << 3 | (mcs)) 2079 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2080 OFDM(6) << 28 | /* 54->48 */ 2081 OFDM(5) << 24 | /* 48->36 */ 2082 OFDM(4) << 20 | /* 36->24 */ 2083 OFDM(3) << 16 | /* 24->18 */ 2084 OFDM(2) << 12 | /* 18->12 */ 2085 OFDM(1) << 8 | /* 12-> 9 */ 2086 OFDM(0) << 4 | /* 9-> 6 */ 2087 OFDM(0)); /* 6-> 6 */ 2088 2089 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2090 CCK(2) << 12 | /* 11->5.5 */ 2091 CCK(1) << 8 | /* 5.5-> 2 */ 2092 CCK(0) << 4 | /* 2-> 1 */ 2093 CCK(0)); /* 1-> 1 */ 2094 #undef OFDM 2095 #undef CCK 2096 } 2097 2098 void 2099 rt2860_set_txpreamble(struct rt2860_softc *sc) 2100 { 2101 uint32_t tmp; 2102 2103 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2104 tmp &= ~RT2860_CCK_SHORT_EN; 2105 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2106 tmp |= RT2860_CCK_SHORT_EN; 2107 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2108 } 2109 2110 void 2111 rt2860_set_basicrates(struct rt2860_softc *sc) 2112 { 2113 struct ieee80211com *ic = &sc->sc_ic; 2114 2115 /* set basic rates mask */ 2116 if (ic->ic_curmode == IEEE80211_MODE_11B) 2117 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2118 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2119 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2120 else /* 11g */ 2121 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2122 } 2123 2124 void 2125 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2126 { 2127 uint32_t tmp; 2128 uint8_t agc; 2129 2130 /* Wait for BBP to settle */ 2131 DELAY(1000); 2132 2133 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2134 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2135 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2136 rt2860_mcu_bbp_write(sc, 86, 0x00); 2137 2138 if (group == 0) { 2139 if (sc->ext_2ghz_lna) { 2140 rt2860_mcu_bbp_write(sc, 82, 0x62); 2141 rt2860_mcu_bbp_write(sc, 75, 0x46); 2142 } else { 2143 rt2860_mcu_bbp_write(sc, 82, 0x84); 2144 rt2860_mcu_bbp_write(sc, 75, 0x50); 2145 } 2146 } else { 2147 if (sc->mac_ver == 0x3572) 2148 rt2860_mcu_bbp_write(sc, 82, 0x94); 2149 else 2150 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2151 2152 if (sc->ext_5ghz_lna) 2153 rt2860_mcu_bbp_write(sc, 75, 0x46); 2154 else 2155 rt2860_mcu_bbp_write(sc, 75, 0x50); 2156 } 2157 2158 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2159 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2160 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2161 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2162 2163 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2164 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2165 if (sc->nrxchains > 1) 2166 tmp |= RT2860_LNA_PE1_EN; 2167 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2168 tmp |= RT3593_LNA_PE2_EN; 2169 if (group == 0) { /* 2GHz */ 2170 tmp |= RT2860_PA_PE_G0_EN; 2171 if (sc->ntxchains > 1) 2172 tmp |= RT2860_PA_PE_G1_EN; 2173 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2174 tmp |= RT3593_PA_PE_G2_EN; 2175 } else { /* 5GHz */ 2176 tmp |= RT2860_PA_PE_A0_EN; 2177 if (sc->ntxchains > 1) 2178 tmp |= RT2860_PA_PE_A1_EN; 2179 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2180 tmp |= RT3593_PA_PE_A2_EN; 2181 } 2182 if (sc->mac_ver == 0x3572) { 2183 rt3090_rf_write(sc, 8, 0x00); 2184 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2185 rt3090_rf_write(sc, 8, 0x80); 2186 } else 2187 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2188 2189 if (sc->mac_ver == 0x3593) { 2190 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2191 if (sc->sc_flags & RT2860_PCIE) { 2192 tmp &= ~0x01010000; 2193 if (group == 0) 2194 tmp |= 0x00010000; 2195 } else { 2196 tmp &= ~0x00008080; 2197 if (group == 0) 2198 tmp |= 0x00000080; 2199 } 2200 tmp = (tmp & ~0x00001000) | 0x00000010; 2201 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2202 } 2203 2204 /* set initial AGC value */ 2205 if (group == 0) { /* 2GHz band */ 2206 if (sc->mac_ver >= 0x3071) 2207 agc = 0x1c + sc->lna[0] * 2; 2208 else 2209 agc = 0x2e + sc->lna[0]; 2210 } else { /* 5GHz band */ 2211 if (sc->mac_ver == 0x3572) 2212 agc = 0x22 + (sc->lna[group] * 5) / 3; 2213 else 2214 agc = 0x32 + (sc->lna[group] * 5) / 3; 2215 } 2216 rt2860_mcu_bbp_write(sc, 66, agc); 2217 2218 DELAY(1000); 2219 } 2220 2221 void 2222 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2223 { 2224 const struct rfprog *rfprog = rt2860_rf2850; 2225 uint32_t r2, r3, r4; 2226 int8_t txpow1, txpow2; 2227 u_int i; 2228 2229 /* find the settings for this channel (we know it exists) */ 2230 for (i = 0; rfprog[i].chan != chan; i++); 2231 2232 r2 = rfprog[i].r2; 2233 if (sc->ntxchains == 1) 2234 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2235 if (sc->nrxchains == 1) 2236 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2237 else if (sc->nrxchains == 2) 2238 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2239 2240 /* use Tx power values from EEPROM */ 2241 txpow1 = sc->txpow1[i]; 2242 txpow2 = sc->txpow2[i]; 2243 if (chan > 14) { 2244 if (txpow1 >= 0) 2245 txpow1 = txpow1 << 1 | 1; 2246 else 2247 txpow1 = (7 + txpow1) << 1; 2248 if (txpow2 >= 0) 2249 txpow2 = txpow2 << 1 | 1; 2250 else 2251 txpow2 = (7 + txpow2) << 1; 2252 } 2253 r3 = rfprog[i].r3 | txpow1 << 7; 2254 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2255 2256 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2257 rt2860_rf_write(sc, RT2860_RF2, r2); 2258 rt2860_rf_write(sc, RT2860_RF3, r3); 2259 rt2860_rf_write(sc, RT2860_RF4, r4); 2260 2261 DELAY(200); 2262 2263 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2264 rt2860_rf_write(sc, RT2860_RF2, r2); 2265 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2266 rt2860_rf_write(sc, RT2860_RF4, r4); 2267 2268 DELAY(200); 2269 2270 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2271 rt2860_rf_write(sc, RT2860_RF2, r2); 2272 rt2860_rf_write(sc, RT2860_RF3, r3); 2273 rt2860_rf_write(sc, RT2860_RF4, r4); 2274 } 2275 2276 void 2277 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2278 { 2279 int8_t txpow1, txpow2; 2280 uint8_t rf; 2281 int i; 2282 2283 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2284 2285 /* find the settings for this channel (we know it exists) */ 2286 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2287 2288 /* use Tx power values from EEPROM */ 2289 txpow1 = sc->txpow1[i]; 2290 txpow2 = sc->txpow2[i]; 2291 2292 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2293 rf = rt3090_rf_read(sc, 3); 2294 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2295 rt3090_rf_write(sc, 3, rf); 2296 rf = rt3090_rf_read(sc, 6); 2297 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2298 rt3090_rf_write(sc, 6, rf); 2299 2300 /* set Tx0 power */ 2301 rf = rt3090_rf_read(sc, 12); 2302 rf = (rf & ~0x1f) | txpow1; 2303 rt3090_rf_write(sc, 12, rf); 2304 2305 /* set Tx1 power */ 2306 rf = rt3090_rf_read(sc, 13); 2307 rf = (rf & ~0x1f) | txpow2; 2308 rt3090_rf_write(sc, 13, rf); 2309 2310 rf = rt3090_rf_read(sc, 1); 2311 rf &= ~0xfc; 2312 if (sc->ntxchains == 1) 2313 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2314 else if (sc->ntxchains == 2) 2315 rf |= RT3070_TX2_PD; 2316 if (sc->nrxchains == 1) 2317 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2318 else if (sc->nrxchains == 2) 2319 rf |= RT3070_RX2_PD; 2320 rt3090_rf_write(sc, 1, rf); 2321 2322 /* set RF offset */ 2323 rf = rt3090_rf_read(sc, 23); 2324 rf = (rf & ~0x7f) | sc->freq; 2325 rt3090_rf_write(sc, 23, rf); 2326 2327 /* program RF filter */ 2328 rf = rt3090_rf_read(sc, 24); /* Tx */ 2329 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2330 rt3090_rf_write(sc, 24, rf); 2331 rf = rt3090_rf_read(sc, 31); /* Rx */ 2332 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2333 rt3090_rf_write(sc, 31, rf); 2334 2335 /* enable RF tuning */ 2336 rf = rt3090_rf_read(sc, 7); 2337 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2338 } 2339 2340 void 2341 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2342 { 2343 uint8_t h20mhz, rf, tmp; 2344 int8_t txpow1, txpow2; 2345 int i; 2346 2347 /* RT5390 is 2GHz only */ 2348 KASSERT(chan >= 1 && chan <= 14); 2349 2350 /* find the settings for this channel (we know it exists) */ 2351 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2352 2353 /* use Tx power values from EEPROM */ 2354 txpow1 = sc->txpow1[i]; 2355 txpow2 = sc->txpow2[i]; 2356 2357 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2358 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2359 rf = rt3090_rf_read(sc, 11); 2360 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2361 rt3090_rf_write(sc, 11, rf); 2362 2363 rf = rt3090_rf_read(sc, 49); 2364 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2365 /* the valid range of the RF R49 is 0x00~0x27 */ 2366 if ((rf & 0x3f) > 0x27) 2367 rf = (rf & ~0x3f) | 0x27; 2368 rt3090_rf_write(sc, 49, rf); 2369 if (sc->mac_ver == 0x5392) { 2370 rf = rt3090_rf_read(sc, 50); 2371 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2372 /* the valid range of the RF R50 is 0x00~0x27 */ 2373 if ((rf & 0x3f) > 0x27) 2374 rf = (rf & ~0x3f) | 0x27; 2375 rt3090_rf_write(sc, 50, rf); 2376 } 2377 2378 rf = rt3090_rf_read(sc, 1); 2379 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2380 if (sc->mac_ver == 0x5392) 2381 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2382 rt3090_rf_write(sc, 1, rf); 2383 2384 rf = rt3090_rf_read(sc, 2); 2385 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2386 DELAY(1000); 2387 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2388 2389 rf = rt3090_rf_read(sc, 17); 2390 tmp = rf; 2391 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2392 rf = MIN(rf, 0x5f); 2393 if (tmp != rf) 2394 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2395 2396 if (sc->mac_ver == 0x5390) { 2397 if (chan <= 4) 2398 rf = 0x73; 2399 else if (chan >= 5 && chan <= 6) 2400 rf = 0x63; 2401 else if (chan >= 7 && chan <= 10) 2402 rf = 0x53; 2403 else 2404 rf = 43; 2405 rt3090_rf_write(sc, 55, rf); 2406 2407 if (chan == 1) 2408 rf = 0x0c; 2409 else if (chan == 2) 2410 rf = 0x0b; 2411 else if (chan == 3) 2412 rf = 0x0a; 2413 else if (chan >= 4 && chan <= 6) 2414 rf = 0x09; 2415 else if (chan >= 7 && chan <= 12) 2416 rf = 0x08; 2417 else if (chan == 13) 2418 rf = 0x07; 2419 else 2420 rf = 0x06; 2421 rt3090_rf_write(sc, 59, rf); 2422 } else if (sc->mac_ver == 0x3290) { 2423 if (chan == 6) 2424 rt2860_mcu_bbp_write(sc, 68, 0x0c); 2425 else 2426 rt2860_mcu_bbp_write(sc, 68, 0x0b); 2427 2428 if (chan >= 1 && chan < 6) 2429 rf = 0x0f; 2430 else if (chan >= 7 && chan <= 11) 2431 rf = 0x0e; 2432 else if (chan >= 12 && chan <= 14) 2433 rf = 0x0d; 2434 rt3090_rf_write(sc, 59, rf); 2435 } 2436 2437 /* Tx/Rx h20M */ 2438 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2439 rf = rt3090_rf_read(sc, 30); 2440 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2441 rt3090_rf_write(sc, 30, rf); 2442 2443 /* Rx BB filter VCM */ 2444 rf = rt3090_rf_read(sc, 30); 2445 rf = (rf & ~0x18) | 0x10; 2446 rt3090_rf_write(sc, 30, rf); 2447 2448 /* Initiate VCO calibration. */ 2449 rf = rt3090_rf_read(sc, 3); 2450 rf |= RT3593_VCOCAL; 2451 rt3090_rf_write(sc, 3, rf); 2452 } 2453 2454 int 2455 rt3090_rf_init(struct rt2860_softc *sc) 2456 { 2457 uint32_t tmp; 2458 uint8_t rf, bbp; 2459 int i; 2460 2461 rf = rt3090_rf_read(sc, 30); 2462 /* toggle RF R30 bit 7 */ 2463 rt3090_rf_write(sc, 30, rf | 0x80); 2464 DELAY(1000); 2465 rt3090_rf_write(sc, 30, rf & ~0x80); 2466 2467 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2468 tmp &= ~0x1f000000; 2469 if (sc->patch_dac && sc->mac_rev < 0x0211) 2470 tmp |= 0x0d000000; /* 1.35V */ 2471 else 2472 tmp |= 0x01000000; /* 1.2V */ 2473 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2474 2475 /* patch LNA_PE_G1 */ 2476 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2477 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2478 2479 /* initialize RF registers to default value */ 2480 if (sc->mac_ver == 0x3572) { 2481 for (i = 0; i < nitems(rt3572_def_rf); i++) { 2482 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2483 rt3572_def_rf[i].val); 2484 } 2485 } else { 2486 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2487 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2488 rt3090_def_rf[i].val); 2489 } 2490 } 2491 2492 /* select 20MHz bandwidth */ 2493 rt3090_rf_write(sc, 31, 0x14); 2494 2495 rf = rt3090_rf_read(sc, 6); 2496 rt3090_rf_write(sc, 6, rf | 0x40); 2497 2498 if (sc->mac_ver != 0x3593) { 2499 /* calibrate filter for 20MHz bandwidth */ 2500 sc->rf24_20mhz = 0x1f; /* default value */ 2501 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2502 2503 /* select 40MHz bandwidth */ 2504 bbp = rt2860_mcu_bbp_read(sc, 4); 2505 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2506 rf = rt3090_rf_read(sc, 31); 2507 rt3090_rf_write(sc, 31, rf | 0x20); 2508 2509 /* calibrate filter for 40MHz bandwidth */ 2510 sc->rf24_40mhz = 0x2f; /* default value */ 2511 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2512 2513 /* go back to 20MHz bandwidth */ 2514 bbp = rt2860_mcu_bbp_read(sc, 4); 2515 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2516 } 2517 if (sc->mac_rev < 0x0211) 2518 rt3090_rf_write(sc, 27, 0x03); 2519 2520 tmp = RAL_READ(sc, RT3070_OPT_14); 2521 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2522 2523 if (sc->rf_rev == RT3070_RF_3020) 2524 rt3090_set_rx_antenna(sc, 0); 2525 2526 bbp = rt2860_mcu_bbp_read(sc, 138); 2527 if (sc->mac_ver == 0x3593) { 2528 if (sc->ntxchains == 1) 2529 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2530 else if (sc->ntxchains == 2) 2531 bbp |= 0x40; /* turn off DAC2 */ 2532 if (sc->nrxchains == 1) 2533 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2534 else if (sc->nrxchains == 2) 2535 bbp &= ~0x04; /* turn off ADC2 */ 2536 } else { 2537 if (sc->ntxchains == 1) 2538 bbp |= 0x20; /* turn off DAC1 */ 2539 if (sc->nrxchains == 1) 2540 bbp &= ~0x02; /* turn off ADC1 */ 2541 } 2542 rt2860_mcu_bbp_write(sc, 138, bbp); 2543 2544 rf = rt3090_rf_read(sc, 1); 2545 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2546 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2547 rt3090_rf_write(sc, 1, rf); 2548 2549 rf = rt3090_rf_read(sc, 15); 2550 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2551 2552 rf = rt3090_rf_read(sc, 17); 2553 rf &= ~RT3070_TX_LO1; 2554 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2555 rf |= 0x20; /* fix for long range Rx issue */ 2556 if (sc->txmixgain_2ghz >= 2) 2557 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2558 rt3090_rf_write(sc, 17, rf); 2559 2560 rf = rt3090_rf_read(sc, 20); 2561 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2562 2563 rf = rt3090_rf_read(sc, 21); 2564 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2565 2566 return 0; 2567 } 2568 2569 void 2570 rt5390_rf_init(struct rt2860_softc *sc) 2571 { 2572 uint8_t rf, bbp; 2573 int i; 2574 2575 rf = rt3090_rf_read(sc, 2); 2576 /* Toggle RF R2 bit 7. */ 2577 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2578 DELAY(1000); 2579 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2580 2581 /* Initialize RF registers to default value. */ 2582 if (sc->mac_ver == 0x5392) { 2583 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2584 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2585 rt5392_def_rf[i].val); 2586 } 2587 } else if (sc->mac_ver == 0x3290) { 2588 for (i = 0; i < nitems(rt3290_def_rf); i++) { 2589 rt3090_rf_write(sc, rt3290_def_rf[i].reg, 2590 rt3290_def_rf[i].val); 2591 } 2592 } else { 2593 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2594 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2595 rt5390_def_rf[i].val); 2596 } 2597 } 2598 2599 sc->rf24_20mhz = 0x1f; 2600 sc->rf24_40mhz = 0x2f; 2601 2602 if (sc->mac_rev < 0x0211) 2603 rt3090_rf_write(sc, 27, 0x03); 2604 2605 /* Set led open drain enable. */ 2606 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2607 2608 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2609 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2610 2611 if (sc->mac_ver == 0x3290 || 2612 sc->mac_ver == 0x5390) 2613 rt3090_set_rx_antenna(sc, 0); 2614 2615 /* Patch RSSI inaccurate issue. */ 2616 rt2860_mcu_bbp_write(sc, 79, 0x13); 2617 rt2860_mcu_bbp_write(sc, 80, 0x05); 2618 rt2860_mcu_bbp_write(sc, 81, 0x33); 2619 2620 /* Enable DC filter. */ 2621 if (sc->mac_rev >= 0x0211 || 2622 sc->mac_ver == 0x3290) 2623 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2624 2625 bbp = rt2860_mcu_bbp_read(sc, 138); 2626 if (sc->ntxchains == 1) 2627 bbp |= 0x20; /* Turn off DAC1. */ 2628 if (sc->nrxchains == 1) 2629 bbp &= ~0x02; /* Turn off ADC1. */ 2630 rt2860_mcu_bbp_write(sc, 138, bbp); 2631 2632 /* Enable RX LO1 and LO2. */ 2633 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2634 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2635 2636 /* Avoid data lost and CRC error. */ 2637 rt2860_mcu_bbp_write(sc, 4, 2638 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2639 2640 rf = rt3090_rf_read(sc, 30); 2641 rf = (rf & ~0x18) | 0x10; 2642 rt3090_rf_write(sc, 30, rf); 2643 2644 /* Disable hardware antenna diversity. */ 2645 if (sc->mac_ver == 0x5390) 2646 rt2860_mcu_bbp_write(sc, 154, 0); 2647 } 2648 2649 void 2650 rt3090_rf_wakeup(struct rt2860_softc *sc) 2651 { 2652 uint32_t tmp; 2653 uint8_t rf; 2654 2655 if (sc->mac_ver == 0x3593) { 2656 /* enable VCO */ 2657 rf = rt3090_rf_read(sc, 1); 2658 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2659 2660 /* initiate VCO calibration */ 2661 rf = rt3090_rf_read(sc, 3); 2662 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2663 2664 /* enable VCO bias current control */ 2665 rf = rt3090_rf_read(sc, 6); 2666 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2667 2668 /* initiate res calibration */ 2669 rf = rt3090_rf_read(sc, 2); 2670 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2671 2672 /* set reference current control to 0.33 mA */ 2673 rf = rt3090_rf_read(sc, 22); 2674 rf &= ~RT3593_CP_IC_MASK; 2675 rf |= 1 << RT3593_CP_IC_SHIFT; 2676 rt3090_rf_write(sc, 22, rf); 2677 2678 /* enable RX CTB */ 2679 rf = rt3090_rf_read(sc, 46); 2680 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2681 2682 rf = rt3090_rf_read(sc, 20); 2683 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2684 rt3090_rf_write(sc, 20, rf); 2685 } else { 2686 /* enable RF block */ 2687 rf = rt3090_rf_read(sc, 1); 2688 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2689 2690 /* enable VCO bias current control */ 2691 rf = rt3090_rf_read(sc, 7); 2692 rt3090_rf_write(sc, 7, rf | 0x30); 2693 2694 rf = rt3090_rf_read(sc, 9); 2695 rt3090_rf_write(sc, 9, rf | 0x0e); 2696 2697 /* enable RX CTB */ 2698 rf = rt3090_rf_read(sc, 21); 2699 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2700 2701 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2702 rf = rt3090_rf_read(sc, 27); 2703 rf &= ~0x77; 2704 if (sc->mac_rev < 0x0211) 2705 rf |= 0x03; 2706 rt3090_rf_write(sc, 27, rf); 2707 } 2708 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2709 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2710 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2711 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2712 } 2713 } 2714 2715 void 2716 rt5390_rf_wakeup(struct rt2860_softc *sc) 2717 { 2718 uint32_t tmp; 2719 uint8_t rf; 2720 2721 rf = rt3090_rf_read(sc, 1); 2722 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2723 RT3070_TX0_PD; 2724 if (sc->mac_ver == 0x5392) 2725 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2726 rt3090_rf_write(sc, 1, rf); 2727 2728 rf = rt3090_rf_read(sc, 6); 2729 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2730 if (sc->mac_ver == 0x5390) 2731 rf &= ~RT3593_VCO_IC; 2732 rt3090_rf_write(sc, 6, rf); 2733 2734 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2735 2736 rf = rt3090_rf_read(sc, 22); 2737 rf = (rf & ~0xe0) | 0x20; 2738 rt3090_rf_write(sc, 22, rf); 2739 2740 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2741 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2742 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2743 2744 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2745 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2746 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2747 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2748 } 2749 } 2750 2751 int 2752 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2753 uint8_t *val) 2754 { 2755 uint8_t rf22, rf24; 2756 uint8_t bbp55_pb, bbp55_sb, delta; 2757 int ntries; 2758 2759 /* program filter */ 2760 rf24 = rt3090_rf_read(sc, 24); 2761 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2762 rt3090_rf_write(sc, 24, rf24); 2763 2764 /* enable baseband loopback mode */ 2765 rf22 = rt3090_rf_read(sc, 22); 2766 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2767 2768 /* set power and frequency of passband test tone */ 2769 rt2860_mcu_bbp_write(sc, 24, 0x00); 2770 for (ntries = 0; ntries < 100; ntries++) { 2771 /* transmit test tone */ 2772 rt2860_mcu_bbp_write(sc, 25, 0x90); 2773 DELAY(1000); 2774 /* read received power */ 2775 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2776 if (bbp55_pb != 0) 2777 break; 2778 } 2779 if (ntries == 100) 2780 return ETIMEDOUT; 2781 2782 /* set power and frequency of stopband test tone */ 2783 rt2860_mcu_bbp_write(sc, 24, 0x06); 2784 for (ntries = 0; ntries < 100; ntries++) { 2785 /* transmit test tone */ 2786 rt2860_mcu_bbp_write(sc, 25, 0x90); 2787 DELAY(1000); 2788 /* read received power */ 2789 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2790 2791 delta = bbp55_pb - bbp55_sb; 2792 if (delta > target) 2793 break; 2794 2795 /* reprogram filter */ 2796 rf24++; 2797 rt3090_rf_write(sc, 24, rf24); 2798 } 2799 if (ntries < 100) { 2800 if (rf24 != init) 2801 rf24--; /* backtrack */ 2802 *val = rf24; 2803 rt3090_rf_write(sc, 24, rf24); 2804 } 2805 2806 /* restore initial state */ 2807 rt2860_mcu_bbp_write(sc, 24, 0x00); 2808 2809 /* disable baseband loopback mode */ 2810 rf22 = rt3090_rf_read(sc, 22); 2811 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2812 2813 return 0; 2814 } 2815 2816 void 2817 rt3090_rf_setup(struct rt2860_softc *sc) 2818 { 2819 uint8_t bbp; 2820 int i; 2821 2822 if (sc->mac_rev >= 0x0211) { 2823 /* enable DC filter */ 2824 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2825 2826 /* improve power consumption */ 2827 bbp = rt2860_mcu_bbp_read(sc, 31); 2828 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2829 } 2830 2831 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2832 if (sc->mac_rev < 0x0211) { 2833 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2834 sc->patch_dac ? 0x2c : 0x0f); 2835 } else 2836 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2837 2838 /* initialize RF registers from ROM */ 2839 if (sc->mac_ver < 0x5390) { 2840 for (i = 0; i < 10; i++) { 2841 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2842 continue; 2843 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2844 } 2845 } 2846 } 2847 2848 void 2849 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2850 { 2851 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2852 which | (sc->leds & 0x7f), 0); 2853 } 2854 2855 /* 2856 * Hardware has a general-purpose programmable timer interrupt that can 2857 * periodically raise MAC_INT_4. 2858 */ 2859 void 2860 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2861 { 2862 uint32_t tmp; 2863 2864 /* disable GP timer before reprogramming it */ 2865 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2866 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2867 2868 if (ms == 0) 2869 return; 2870 2871 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2872 ms *= 16; /* Unit: 64us */ 2873 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2874 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2875 2876 /* enable GP timer */ 2877 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2878 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2879 } 2880 2881 void 2882 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2883 { 2884 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2885 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2886 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2887 bssid[4] | bssid[5] << 8); 2888 } 2889 2890 void 2891 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2892 { 2893 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2894 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2895 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2896 addr[4] | addr[5] << 8 | 0xff << 16); 2897 } 2898 2899 void 2900 rt2860_updateslot(struct ieee80211com *ic) 2901 { 2902 struct rt2860_softc *sc = ic->ic_softc; 2903 uint32_t tmp; 2904 2905 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2906 tmp &= ~0xff; 2907 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 2908 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT; 2909 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2910 } 2911 2912 void 2913 rt2860_updateprot(struct ieee80211com *ic) 2914 { 2915 struct rt2860_softc *sc = ic->ic_softc; 2916 uint32_t tmp; 2917 2918 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2919 /* setup protection frame rate (MCS code) */ 2920 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2921 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2922 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2923 2924 /* CCK frames don't require protection */ 2925 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2926 2927 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2928 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2929 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2930 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2931 tmp |= RT2860_PROT_CTRL_CTS; 2932 } 2933 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2934 } 2935 2936 void 2937 rt2860_updateedca(struct ieee80211com *ic) 2938 { 2939 struct rt2860_softc *sc = ic->ic_softc; 2940 int aci; 2941 2942 /* update MAC TX configuration registers */ 2943 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2944 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2945 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 2946 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 2947 ic->ic_edca_ac[aci].ac_aifsn << 8 | 2948 ic->ic_edca_ac[aci].ac_txoplimit); 2949 } 2950 2951 /* update SCH/DMA registers too */ 2952 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2953 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 2954 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 2955 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 2956 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 2957 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2958 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 2959 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 2960 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 2961 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 2962 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2963 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 2964 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 2965 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 2966 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 2967 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2968 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 2969 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 2970 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2971 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 2972 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 2973 } 2974 2975 int 2976 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2977 struct ieee80211_key *k) 2978 { 2979 struct rt2860_softc *sc = ic->ic_softc; 2980 bus_size_t base; 2981 uint32_t attr; 2982 uint8_t mode, wcid, iv[8]; 2983 2984 /* defer setting of WEP keys until interface is brought up */ 2985 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2986 (IFF_UP | IFF_RUNNING)) 2987 return 0; 2988 2989 /* map net80211 cipher to RT2860 security mode */ 2990 switch (k->k_cipher) { 2991 case IEEE80211_CIPHER_WEP40: 2992 mode = RT2860_MODE_WEP40; 2993 break; 2994 case IEEE80211_CIPHER_WEP104: 2995 mode = RT2860_MODE_WEP104; 2996 break; 2997 case IEEE80211_CIPHER_TKIP: 2998 mode = RT2860_MODE_TKIP; 2999 break; 3000 case IEEE80211_CIPHER_CCMP: 3001 mode = RT2860_MODE_AES_CCMP; 3002 break; 3003 default: 3004 return EINVAL; 3005 } 3006 3007 if (k->k_flags & IEEE80211_KEY_GROUP) { 3008 wcid = 0; /* NB: update WCID0 for group keys */ 3009 base = RT2860_SKEY(0, k->k_id); 3010 } else { 3011 wcid = ((struct rt2860_node *)ni)->wcid; 3012 base = RT2860_PKEY(wcid); 3013 } 3014 3015 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3016 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3017 #ifndef IEEE80211_STA_ONLY 3018 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3019 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3020 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3021 } else 3022 #endif 3023 { 3024 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3025 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3026 } 3027 } else 3028 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3029 3030 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3031 (k->k_flags & IEEE80211_KEY_TX)) { 3032 /* set initial packet number in IV+EIV */ 3033 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3034 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3035 uint32_t val = arc4random(); 3036 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3037 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3038 val += 0x000100; 3039 iv[0] = val; 3040 iv[1] = val >> 8; 3041 iv[2] = val >> 16; 3042 iv[3] = k->k_id << 6; 3043 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3044 } else { 3045 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3046 iv[0] = k->k_tsc >> 8; 3047 iv[1] = (iv[0] | 0x20) & 0x7f; 3048 iv[2] = k->k_tsc; 3049 } else /* CCMP */ { 3050 iv[0] = k->k_tsc; 3051 iv[1] = k->k_tsc >> 8; 3052 iv[2] = 0; 3053 } 3054 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3055 iv[4] = k->k_tsc >> 16; 3056 iv[5] = k->k_tsc >> 24; 3057 iv[6] = k->k_tsc >> 32; 3058 iv[7] = k->k_tsc >> 40; 3059 } 3060 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3061 } 3062 3063 if (k->k_flags & IEEE80211_KEY_GROUP) { 3064 /* install group key */ 3065 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3066 attr &= ~(0xf << (k->k_id * 4)); 3067 attr |= mode << (k->k_id * 4); 3068 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3069 } else { 3070 /* install pairwise key */ 3071 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3072 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3073 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3074 } 3075 return 0; 3076 } 3077 3078 void 3079 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3080 struct ieee80211_key *k) 3081 { 3082 struct rt2860_softc *sc = ic->ic_softc; 3083 uint32_t attr; 3084 uint8_t wcid; 3085 3086 if (k->k_flags & IEEE80211_KEY_GROUP) { 3087 /* remove group key */ 3088 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3089 attr &= ~(0xf << (k->k_id * 4)); 3090 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3091 3092 } else { 3093 /* remove pairwise key */ 3094 wcid = ((struct rt2860_node *)ni)->wcid; 3095 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3096 attr &= ~0xf; 3097 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3098 } 3099 } 3100 3101 #if NBPFILTER > 0 3102 int8_t 3103 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3104 { 3105 struct ieee80211com *ic = &sc->sc_ic; 3106 struct ieee80211_channel *c = ic->ic_ibss_chan; 3107 int delta; 3108 3109 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3110 u_int chan = ieee80211_chan2ieee(ic, c); 3111 delta = sc->rssi_5ghz[rxchain]; 3112 3113 /* determine channel group */ 3114 if (chan <= 64) 3115 delta -= sc->lna[1]; 3116 else if (chan <= 128) 3117 delta -= sc->lna[2]; 3118 else 3119 delta -= sc->lna[3]; 3120 } else 3121 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3122 3123 return -12 - delta - rssi; 3124 } 3125 #endif 3126 3127 /* 3128 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3129 * Used to adjust per-rate Tx power registers. 3130 */ 3131 static __inline uint32_t 3132 b4inc(uint32_t b32, int8_t delta) 3133 { 3134 int8_t i, b4; 3135 3136 for (i = 0; i < 8; i++) { 3137 b4 = b32 & 0xf; 3138 b4 += delta; 3139 if (b4 < 0) 3140 b4 = 0; 3141 else if (b4 > 0xf) 3142 b4 = 0xf; 3143 b32 = b32 >> 4 | b4 << 28; 3144 } 3145 return b32; 3146 } 3147 3148 const char * 3149 rt2860_get_rf(uint16_t rev) 3150 { 3151 switch (rev) { 3152 case RT2860_RF_2820: return "RT2820"; 3153 case RT2860_RF_2850: return "RT2850"; 3154 case RT2860_RF_2720: return "RT2720"; 3155 case RT2860_RF_2750: return "RT2750"; 3156 case RT3070_RF_3020: return "RT3020"; 3157 case RT3070_RF_2020: return "RT2020"; 3158 case RT3070_RF_3021: return "RT3021"; 3159 case RT3070_RF_3022: return "RT3022"; 3160 case RT3070_RF_3052: return "RT3052"; 3161 case RT3070_RF_3320: return "RT3320"; 3162 case RT3070_RF_3053: return "RT3053"; 3163 case RT3290_RF_3290: return "RT3290"; 3164 case RT5390_RF_5360: return "RT5360"; 3165 case RT5390_RF_5390: return "RT5390"; 3166 case RT5390_RF_5392: return "RT5392"; 3167 default: return "unknown"; 3168 } 3169 } 3170 3171 int 3172 rt2860_read_eeprom(struct rt2860_softc *sc) 3173 { 3174 struct ieee80211com *ic = &sc->sc_ic; 3175 int8_t delta_2ghz, delta_5ghz; 3176 uint32_t tmp; 3177 uint16_t val; 3178 int ridx, ant, i; 3179 3180 /* check whether the ROM is eFUSE ROM or EEPROM */ 3181 sc->sc_srom_read = rt2860_eeprom_read_2; 3182 if (sc->mac_ver == 0x3290) { 3183 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL); 3184 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3185 if (tmp & RT3070_SEL_EFUSE) 3186 sc->sc_srom_read = rt3290_efuse_read_2; 3187 } else if (sc->mac_ver >= 0x3071) { 3188 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3189 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3190 if (tmp & RT3070_SEL_EFUSE) 3191 sc->sc_srom_read = rt3090_efuse_read_2; 3192 } 3193 3194 /* read EEPROM version */ 3195 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3196 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3197 3198 /* read MAC address */ 3199 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3200 ic->ic_myaddr[0] = val & 0xff; 3201 ic->ic_myaddr[1] = val >> 8; 3202 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3203 ic->ic_myaddr[2] = val & 0xff; 3204 ic->ic_myaddr[3] = val >> 8; 3205 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3206 ic->ic_myaddr[4] = val & 0xff; 3207 ic->ic_myaddr[5] = val >> 8; 3208 3209 /* read country code */ 3210 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3211 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3212 3213 /* read vendor BBP settings */ 3214 for (i = 0; i < 8; i++) { 3215 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3216 sc->bbp[i].val = val & 0xff; 3217 sc->bbp[i].reg = val >> 8; 3218 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3219 } 3220 if (sc->mac_ver >= 0x3071) { 3221 /* read vendor RF settings */ 3222 for (i = 0; i < 10; i++) { 3223 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3224 sc->rf[i].val = val & 0xff; 3225 sc->rf[i].reg = val >> 8; 3226 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3227 sc->rf[i].val)); 3228 } 3229 } 3230 3231 /* read RF frequency offset from EEPROM */ 3232 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3233 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3234 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3235 if ((val >> 8) != 0xff) { 3236 /* read LEDs operating mode */ 3237 sc->leds = val >> 8; 3238 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3239 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3240 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3241 } else { 3242 /* broken EEPROM, use default settings */ 3243 sc->leds = 0x01; 3244 sc->led[0] = 0x5555; 3245 sc->led[1] = 0x2221; 3246 sc->led[2] = 0xa9f8; 3247 } 3248 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3249 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3250 3251 /* read RF information */ 3252 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3253 DPRINTF(("EEPROM ANT 0x%04x\n", val)); 3254 if (sc->mac_ver >= 0x5390 || sc->mac_ver == 0x3290) 3255 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3256 else 3257 sc->rf_rev = (val >> 8) & 0xf; 3258 sc->ntxchains = (val >> 4) & 0xf; 3259 sc->nrxchains = val & 0xf; 3260 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3261 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3262 3263 /* check if RF supports automatic Tx access gain control */ 3264 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3265 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3266 /* check if driver should patch the DAC issue */ 3267 if ((val >> 8) != 0xff) 3268 sc->patch_dac = (val >> 15) & 1; 3269 if ((val & 0xff) != 0xff) { 3270 sc->ext_5ghz_lna = (val >> 3) & 1; 3271 sc->ext_2ghz_lna = (val >> 2) & 1; 3272 /* check if RF supports automatic Tx access gain control */ 3273 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3274 /* check if we have a hardware radio switch */ 3275 sc->rfswitch = val & 1; 3276 } 3277 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3278 /* read PCIe power save level */ 3279 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3280 if ((val & 0xff) != 0xff) { 3281 sc->pslevel = val & 0x3; 3282 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3283 if ((val & 0xff80) != 0x9280) 3284 sc->pslevel = MIN(sc->pslevel, 1); 3285 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3286 } 3287 } 3288 3289 /* read power settings for 2GHz channels */ 3290 for (i = 0; i < 14; i += 2) { 3291 val = rt2860_srom_read(sc, 3292 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3293 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3294 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3295 3296 if (sc->mac_ver != 0x5390) { 3297 val = rt2860_srom_read(sc, 3298 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3299 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3300 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3301 } 3302 } 3303 /* fix broken Tx power entries */ 3304 for (i = 0; i < 14; i++) { 3305 if (sc->txpow1[i] < 0 || 3306 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3307 sc->txpow1[i] = 5; 3308 if (sc->mac_ver != 0x5390) { 3309 if (sc->txpow2[i] < 0 || 3310 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3311 sc->txpow2[i] = 5; 3312 } 3313 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3314 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3315 } 3316 /* read power settings for 5GHz channels */ 3317 for (i = 0; i < 40; i += 2) { 3318 val = rt2860_srom_read(sc, 3319 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3320 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3321 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3322 3323 val = rt2860_srom_read(sc, 3324 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3325 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3326 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3327 } 3328 /* fix broken Tx power entries */ 3329 for (i = 0; i < 40; i++) { 3330 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3331 sc->txpow1[14 + i] = 5; 3332 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3333 sc->txpow2[14 + i] = 5; 3334 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3335 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3336 sc->txpow2[14 + i])); 3337 } 3338 3339 /* read Tx power compensation for each Tx rate */ 3340 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3341 delta_2ghz = delta_5ghz = 0; 3342 if ((val & 0xff) != 0xff && (val & 0x80)) { 3343 delta_2ghz = val & 0xf; 3344 if (!(val & 0x40)) /* negative number */ 3345 delta_2ghz = -delta_2ghz; 3346 } 3347 val >>= 8; 3348 if ((val & 0xff) != 0xff && (val & 0x80)) { 3349 delta_5ghz = val & 0xf; 3350 if (!(val & 0x40)) /* negative number */ 3351 delta_5ghz = -delta_5ghz; 3352 } 3353 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3354 delta_2ghz, delta_5ghz)); 3355 3356 for (ridx = 0; ridx < 5; ridx++) { 3357 uint32_t reg; 3358 3359 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3360 reg = val; 3361 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3362 reg |= (uint32_t)val << 16; 3363 3364 sc->txpow20mhz[ridx] = reg; 3365 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3366 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3367 3368 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3369 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3370 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3371 } 3372 3373 /* read factory-calibrated samples for temperature compensation */ 3374 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3375 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3376 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3377 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3378 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3379 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3380 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3381 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3382 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3383 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3384 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3385 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3386 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3387 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3388 sc->step_2ghz = val >> 8; 3389 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3390 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3391 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3392 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3393 sc->tssi_2ghz[8], sc->step_2ghz)); 3394 /* check that ref value is correct, otherwise disable calibration */ 3395 if (sc->tssi_2ghz[4] == 0xff) 3396 sc->calib_2ghz = 0; 3397 3398 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3399 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3400 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3401 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3402 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3403 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3404 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3405 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3406 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3407 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3408 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3409 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3410 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3411 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3412 sc->step_5ghz = val >> 8; 3413 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3414 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3415 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3416 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3417 sc->tssi_5ghz[8], sc->step_5ghz)); 3418 /* check that ref value is correct, otherwise disable calibration */ 3419 if (sc->tssi_5ghz[4] == 0xff) 3420 sc->calib_5ghz = 0; 3421 3422 /* read RSSI offsets and LNA gains from EEPROM */ 3423 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3424 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3425 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3426 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3427 if (sc->mac_ver >= 0x3071) { 3428 /* 3429 * On RT3090 chips (limited to 2 Rx chains), this ROM 3430 * field contains the Tx mixer gain for the 2GHz band. 3431 */ 3432 if ((val & 0xff) != 0xff) 3433 sc->txmixgain_2ghz = val & 0x7; 3434 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3435 } else 3436 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3437 sc->lna[2] = val >> 8; /* channel group 2 */ 3438 3439 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3440 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3441 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3442 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3443 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3444 sc->lna[3] = val >> 8; /* channel group 3 */ 3445 3446 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3447 if (sc->mac_ver >= 0x3071) 3448 sc->lna[0] = RT3090_DEF_LNA; 3449 else /* channel group 0 */ 3450 sc->lna[0] = val & 0xff; 3451 sc->lna[1] = val >> 8; /* channel group 1 */ 3452 3453 /* fix broken 5GHz LNA entries */ 3454 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3455 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3456 sc->lna[2] = sc->lna[1]; 3457 } 3458 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3459 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3460 sc->lna[3] = sc->lna[1]; 3461 } 3462 3463 /* fix broken RSSI offset entries */ 3464 for (ant = 0; ant < 3; ant++) { 3465 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3466 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3467 ant + 1, sc->rssi_2ghz[ant])); 3468 sc->rssi_2ghz[ant] = 0; 3469 } 3470 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3471 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3472 ant + 1, sc->rssi_5ghz[ant])); 3473 sc->rssi_5ghz[ant] = 0; 3474 } 3475 } 3476 3477 return 0; 3478 } 3479 3480 int 3481 rt2860_bbp_init(struct rt2860_softc *sc) 3482 { 3483 int i, ntries; 3484 3485 /* wait for BBP to wake up */ 3486 for (ntries = 0; ntries < 20; ntries++) { 3487 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3488 if (bbp0 != 0 && bbp0 != 0xff) 3489 break; 3490 } 3491 if (ntries == 20) { 3492 printf("%s: timeout waiting for BBP to wake up\n", 3493 sc->sc_dev.dv_xname); 3494 return ETIMEDOUT; 3495 } 3496 3497 /* initialize BBP registers to default values */ 3498 if (sc->mac_ver >= 0x5390 || 3499 sc->mac_ver == 0x3290) 3500 rt5390_bbp_init(sc); 3501 else { 3502 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3503 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3504 rt2860_def_bbp[i].val); 3505 } 3506 } 3507 3508 /* fix BBP84 for RT2860E */ 3509 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3510 rt2860_mcu_bbp_write(sc, 84, 0x19); 3511 3512 if (sc->mac_ver >= 0x3071) { 3513 rt2860_mcu_bbp_write(sc, 79, 0x13); 3514 rt2860_mcu_bbp_write(sc, 80, 0x05); 3515 rt2860_mcu_bbp_write(sc, 81, 0x33); 3516 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3517 rt2860_mcu_bbp_write(sc, 69, 0x16); 3518 rt2860_mcu_bbp_write(sc, 73, 0x12); 3519 } 3520 3521 return 0; 3522 } 3523 3524 void 3525 rt5390_bbp_init(struct rt2860_softc *sc) 3526 { 3527 uint8_t bbp; 3528 int i; 3529 3530 /* Apply maximum likelihood detection for 2 stream case. */ 3531 if (sc->nrxchains > 1) { 3532 bbp = rt2860_mcu_bbp_read(sc, 105); 3533 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3534 } 3535 3536 /* Avoid data lost and CRC error. */ 3537 bbp = rt2860_mcu_bbp_read(sc, 4); 3538 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3539 if (sc->mac_ver == 0x3290) { 3540 for (i = 0; i < nitems(rt3290_def_bbp); i++) { 3541 rt2860_mcu_bbp_write(sc, rt3290_def_bbp[i].reg, 3542 rt3290_def_bbp[i].val); 3543 } 3544 } else { 3545 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3546 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3547 rt5390_def_bbp[i].val); 3548 } 3549 } 3550 3551 if (sc->mac_ver == 0x5392) { 3552 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3553 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3554 rt2860_mcu_bbp_write(sc, 98, 0x12); 3555 rt2860_mcu_bbp_write(sc, 106, 0x05); 3556 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3557 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3558 } 3559 3560 bbp = rt2860_mcu_bbp_read(sc, 152); 3561 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3562 3563 /* Disable hardware antenna diversity. */ 3564 if (sc->mac_ver == 0x5390) 3565 rt2860_mcu_bbp_write(sc, 154, 0); 3566 } 3567 3568 int 3569 rt3290_wlan_enable(struct rt2860_softc *sc) 3570 { 3571 uint32_t tmp; 3572 int ntries; 3573 3574 /* enable chip and check readiness */ 3575 tmp = RAL_READ(sc, RT3290_WLAN_CTRL); 3576 tmp |= RT3290_WLAN_EN | RT3290_FRC_WL_ANT_SET | 3577 RT3290_GPIO_OUT_OE_ALL; 3578 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp); 3579 3580 for (ntries = 0; ntries < 200; ntries++) { 3581 tmp = RAL_READ(sc, RT3290_CMB_CTRL); 3582 if ((tmp & RT3290_PLL_LD) && 3583 (tmp & RT3290_XTAL_RDY)) 3584 break; 3585 DELAY(20); 3586 } 3587 if (ntries == 200) 3588 return EIO; 3589 3590 /* toggle reset */ 3591 tmp = RAL_READ(sc, RT3290_WLAN_CTRL); 3592 tmp |= RT3290_WLAN_RESET | RT3290_WLAN_CLK_EN; 3593 tmp &= ~RT3290_PCIE_APP0_CLK_REQ; 3594 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp); 3595 DELAY(20); 3596 tmp &= ~RT3290_WLAN_RESET; 3597 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp); 3598 DELAY(1000); 3599 3600 /* clear garbage interrupts */ 3601 RAL_WRITE(sc, RT2860_INT_STATUS, 0x7fffffff); 3602 3603 return 0; 3604 } 3605 3606 int 3607 rt2860_txrx_enable(struct rt2860_softc *sc) 3608 { 3609 uint32_t tmp; 3610 int ntries; 3611 3612 /* enable Tx/Rx DMA engine */ 3613 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3614 RAL_BARRIER_READ_WRITE(sc); 3615 for (ntries = 0; ntries < 200; ntries++) { 3616 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3617 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3618 break; 3619 DELAY(1000); 3620 } 3621 if (ntries == 200) { 3622 printf("%s: timeout waiting for DMA engine\n", 3623 sc->sc_dev.dv_xname); 3624 return ETIMEDOUT; 3625 } 3626 3627 DELAY(50); 3628 3629 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3630 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3631 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3632 3633 /* set Rx filter */ 3634 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3635 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3636 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3637 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3638 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3639 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3640 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3641 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3642 } 3643 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3644 3645 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3646 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3647 3648 return 0; 3649 } 3650 3651 int 3652 rt2860_init(struct ifnet *ifp) 3653 { 3654 struct rt2860_softc *sc = ifp->if_softc; 3655 struct ieee80211com *ic = &sc->sc_ic; 3656 uint32_t tmp; 3657 uint8_t bbp1, bbp3; 3658 int i, qid, ridx, ntries, error; 3659 3660 /* for CardBus, power on the socket */ 3661 if (!(sc->sc_flags & RT2860_ENABLED)) { 3662 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3663 printf("%s: could not enable device\n", 3664 sc->sc_dev.dv_xname); 3665 return EIO; 3666 } 3667 sc->sc_flags |= RT2860_ENABLED; 3668 } 3669 3670 if (sc->mac_ver == 0x3290) { 3671 if ((error = rt3290_wlan_enable(sc)) != 0) { 3672 printf("%s: could not enable wlan\n", 3673 sc->sc_dev.dv_xname); 3674 rt2860_stop(ifp, 1); 3675 return error; 3676 } 3677 } 3678 3679 if (sc->mac_ver == 0x3290 && sc->rfswitch){ 3680 /* hardware has a radio switch on GPIO pin 0 */ 3681 if (!(RAL_READ(sc, RT3290_WLAN_CTRL) & RT3290_RADIO_EN)) { 3682 printf("%s: radio is disabled by hardware switch\n", 3683 sc->sc_dev.dv_xname); 3684 } 3685 } else if (sc->rfswitch) { 3686 /* hardware has a radio switch on GPIO pin 2 */ 3687 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3688 printf("%s: radio is disabled by hardware switch\n", 3689 sc->sc_dev.dv_xname); 3690 #ifdef notyet 3691 rt2860_stop(ifp, 1); 3692 return EPERM; 3693 #endif 3694 } 3695 } 3696 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3697 3698 /* disable DMA */ 3699 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3700 tmp &= 0xff0; 3701 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3702 3703 /* PBF hardware reset */ 3704 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3705 RAL_BARRIER_WRITE(sc); 3706 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3707 3708 if ((error = rt2860_load_microcode(sc)) != 0) { 3709 printf("%s: could not load 8051 microcode\n", 3710 sc->sc_dev.dv_xname); 3711 rt2860_stop(ifp, 1); 3712 return error; 3713 } 3714 3715 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3716 rt2860_set_macaddr(sc, ic->ic_myaddr); 3717 3718 /* init Tx power for all Tx rates (from EEPROM) */ 3719 for (ridx = 0; ridx < 5; ridx++) { 3720 if (sc->txpow20mhz[ridx] == 0xffffffff) 3721 continue; 3722 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3723 } 3724 3725 for (ntries = 0; ntries < 100; ntries++) { 3726 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3727 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3728 break; 3729 DELAY(1000); 3730 } 3731 if (ntries == 100) { 3732 printf("%s: timeout waiting for DMA engine\n", 3733 sc->sc_dev.dv_xname); 3734 rt2860_stop(ifp, 1); 3735 return ETIMEDOUT; 3736 } 3737 tmp &= 0xff0; 3738 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3739 3740 /* reset Rx ring and all 6 Tx rings */ 3741 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3742 3743 /* PBF hardware reset */ 3744 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3745 RAL_BARRIER_WRITE(sc); 3746 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3747 3748 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3749 3750 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3751 RAL_BARRIER_WRITE(sc); 3752 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3753 3754 for (i = 0; i < nitems(rt2860_def_mac); i++) 3755 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3756 if (sc->mac_ver == 0x3290 || 3757 sc->mac_ver >= 0x5390) 3758 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3759 else if (sc->mac_ver >= 0x3071) { 3760 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3761 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3762 4 << RT2860_DLY_PAPE_EN_SHIFT); 3763 } 3764 3765 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3766 sc->sc_flags |= RT2860_PCIE; 3767 /* PCIe has different clock cycle count than PCI */ 3768 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3769 tmp = (tmp & ~0xff) | 0x7d; 3770 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3771 } 3772 3773 /* wait while MAC is busy */ 3774 for (ntries = 0; ntries < 100; ntries++) { 3775 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3776 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3777 break; 3778 DELAY(1000); 3779 } 3780 if (ntries == 100) { 3781 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname); 3782 rt2860_stop(ifp, 1); 3783 return ETIMEDOUT; 3784 } 3785 3786 /* clear Host to MCU mailbox */ 3787 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3788 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3789 3790 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3791 DELAY(1000); 3792 3793 if ((error = rt2860_bbp_init(sc)) != 0) { 3794 rt2860_stop(ifp, 1); 3795 return error; 3796 } 3797 3798 /* clear RX WCID search table */ 3799 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3800 /* clear pairwise key table */ 3801 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3802 /* clear IV/EIV table */ 3803 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3804 /* clear WCID attribute table */ 3805 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3806 /* clear shared key table */ 3807 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3808 /* clear shared key mode */ 3809 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3810 3811 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3812 for (qid = 0; qid < 6; qid++) { 3813 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3814 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3815 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3816 } 3817 3818 /* init Rx ring */ 3819 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3820 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3821 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3822 3823 /* setup maximum buffer sizes */ 3824 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3825 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3826 3827 for (ntries = 0; ntries < 100; ntries++) { 3828 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3829 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3830 break; 3831 DELAY(1000); 3832 } 3833 if (ntries == 100) { 3834 printf("%s: timeout waiting for DMA engine\n", 3835 sc->sc_dev.dv_xname); 3836 rt2860_stop(ifp, 1); 3837 return ETIMEDOUT; 3838 } 3839 tmp &= 0xff0; 3840 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3841 3842 /* disable interrupts mitigation */ 3843 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3844 3845 /* write vendor-specific BBP values (from EEPROM) */ 3846 for (i = 0; i < 8; i++) { 3847 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3848 continue; 3849 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3850 } 3851 3852 /* select Main antenna for 1T1R devices */ 3853 if (sc->rf_rev == RT3070_RF_2020 || 3854 sc->rf_rev == RT3070_RF_3020 || 3855 sc->rf_rev == RT3290_RF_3290 || 3856 sc->rf_rev == RT3070_RF_3320 || 3857 sc->rf_rev == RT5390_RF_5390) 3858 rt3090_set_rx_antenna(sc, 0); 3859 3860 /* send LEDs operating mode to microcontroller */ 3861 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3862 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3863 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3864 3865 if (sc->mac_ver == 0x3290 || 3866 sc->mac_ver >= 0x5390) 3867 rt5390_rf_init(sc); 3868 else if (sc->mac_ver >= 0x3071) 3869 rt3090_rf_init(sc); 3870 3871 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3872 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3873 3874 if (sc->mac_ver == 0x3290 || 3875 sc->mac_ver >= 0x5390) 3876 rt5390_rf_wakeup(sc); 3877 else if (sc->mac_ver >= 0x3071) 3878 rt3090_rf_wakeup(sc); 3879 3880 /* disable non-existing Rx chains */ 3881 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3882 bbp3 &= ~(1 << 3 | 1 << 4); 3883 if (sc->nrxchains == 2) 3884 bbp3 |= 1 << 3; 3885 else if (sc->nrxchains == 3) 3886 bbp3 |= 1 << 4; 3887 rt2860_mcu_bbp_write(sc, 3, bbp3); 3888 3889 /* disable non-existing Tx chains */ 3890 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3891 if (sc->ntxchains == 1) 3892 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3893 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3894 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3895 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3896 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3897 rt2860_mcu_bbp_write(sc, 1, bbp1); 3898 3899 if (sc->mac_ver >= 0x3071) 3900 rt3090_rf_setup(sc); 3901 3902 /* select default channel */ 3903 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3904 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3905 3906 /* reset RF from MCU */ 3907 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3908 3909 /* set RTS threshold */ 3910 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3911 tmp &= ~0xffff00; 3912 tmp |= ic->ic_rtsthreshold << 8; 3913 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3914 3915 /* setup initial protection mode */ 3916 sc->sc_ic_flags = ic->ic_flags; 3917 rt2860_updateprot(ic); 3918 3919 /* turn radio LED on */ 3920 rt2860_set_leds(sc, RT2860_LED_RADIO); 3921 3922 /* enable Tx/Rx DMA engine */ 3923 if ((error = rt2860_txrx_enable(sc)) != 0) { 3924 rt2860_stop(ifp, 1); 3925 return error; 3926 } 3927 3928 /* clear pending interrupts */ 3929 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3930 /* enable interrupts */ 3931 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3932 3933 if (sc->sc_flags & RT2860_ADVANCED_PS) 3934 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3935 3936 ifp->if_flags |= IFF_RUNNING; 3937 ifq_clr_oactive(&ifp->if_snd); 3938 3939 if (ic->ic_flags & IEEE80211_F_WEPON) { 3940 /* install WEP keys */ 3941 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3942 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3943 } 3944 3945 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3946 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3947 else 3948 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3949 3950 return 0; 3951 } 3952 3953 void 3954 rt2860_stop(struct ifnet *ifp, int disable) 3955 { 3956 struct rt2860_softc *sc = ifp->if_softc; 3957 struct ieee80211com *ic = &sc->sc_ic; 3958 uint32_t tmp; 3959 int qid; 3960 3961 if (ifp->if_flags & IFF_RUNNING) 3962 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3963 3964 sc->sc_tx_timer = 0; 3965 ifp->if_timer = 0; 3966 ifp->if_flags &= ~IFF_RUNNING; 3967 ifq_clr_oactive(&ifp->if_snd); 3968 3969 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 3970 3971 /* disable interrupts */ 3972 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3973 3974 /* disable GP timer */ 3975 rt2860_set_gp_timer(sc, 0); 3976 3977 /* disable Rx */ 3978 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3979 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3980 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3981 3982 /* reset adapter */ 3983 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3984 RAL_BARRIER_WRITE(sc); 3985 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3986 3987 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3988 sc->qfullmsk = 0; 3989 for (qid = 0; qid < 6; qid++) 3990 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3991 rt2860_reset_rx_ring(sc, &sc->rxq); 3992 3993 /* for CardBus, power down the socket */ 3994 if (disable && sc->sc_disable != NULL) { 3995 if (sc->sc_flags & RT2860_ENABLED) { 3996 (*sc->sc_disable)(sc); 3997 sc->sc_flags &= ~RT2860_ENABLED; 3998 } 3999 } 4000 } 4001 4002 int 4003 rt2860_load_microcode(struct rt2860_softc *sc) 4004 { 4005 int ntries; 4006 4007 /* set "host program ram write selection" bit */ 4008 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4009 /* write microcode image */ 4010 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 4011 /* kick microcontroller unit */ 4012 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4013 RAL_BARRIER_WRITE(sc); 4014 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4015 4016 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4017 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4018 4019 /* wait until microcontroller is ready */ 4020 RAL_BARRIER_READ_WRITE(sc); 4021 for (ntries = 0; ntries < 1000; ntries++) { 4022 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4023 break; 4024 DELAY(1000); 4025 } 4026 if (ntries == 1000) { 4027 printf("%s: timeout waiting for MCU to initialize\n", 4028 sc->sc_dev.dv_xname); 4029 return ETIMEDOUT; 4030 } 4031 return 0; 4032 } 4033 4034 /* 4035 * This function is called periodically to adjust Tx power based on 4036 * temperature variation. 4037 */ 4038 void 4039 rt2860_calib(struct rt2860_softc *sc) 4040 { 4041 struct ieee80211com *ic = &sc->sc_ic; 4042 const uint8_t *tssi; 4043 uint8_t step, bbp49; 4044 int8_t ridx, d; 4045 4046 /* read current temperature */ 4047 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4048 4049 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4050 tssi = &sc->tssi_2ghz[4]; 4051 step = sc->step_2ghz; 4052 } else { 4053 tssi = &sc->tssi_5ghz[4]; 4054 step = sc->step_5ghz; 4055 } 4056 4057 if (bbp49 < tssi[0]) { /* lower than reference */ 4058 /* use higher Tx power than default */ 4059 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4060 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4061 /* use lower Tx power than default */ 4062 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4063 } else { 4064 /* use default Tx power */ 4065 d = 0; 4066 } 4067 d *= step; 4068 4069 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4070 4071 /* write adjusted Tx power values for each Tx rate */ 4072 for (ridx = 0; ridx < 5; ridx++) { 4073 if (sc->txpow20mhz[ridx] == 0xffffffff) 4074 continue; 4075 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4076 b4inc(sc->txpow20mhz[ridx], d)); 4077 } 4078 } 4079 4080 void 4081 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4082 { 4083 uint32_t tmp; 4084 if (aux) { 4085 if (sc->mac_ver == 0x5390) { 4086 rt2860_mcu_bbp_write(sc, 152, 4087 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4088 } else { 4089 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4090 RAL_WRITE(sc, RT2860_PCI_EECTRL, 4091 tmp & ~RT2860_C); 4092 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4093 RAL_WRITE(sc, RT2860_GPIO_CTRL, 4094 (tmp & ~0x0808) | 0x08); 4095 } 4096 } else { 4097 if (sc->mac_ver == 0x5390) { 4098 rt2860_mcu_bbp_write(sc, 152, 4099 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4100 } else { 4101 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4102 RAL_WRITE(sc, RT2860_PCI_EECTRL, 4103 tmp | RT2860_C); 4104 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4105 RAL_WRITE(sc, RT2860_GPIO_CTRL, 4106 tmp & ~0x0808); 4107 } 4108 } 4109 } 4110 4111 void 4112 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4113 { 4114 struct ieee80211com *ic = &sc->sc_ic; 4115 u_int chan, group; 4116 4117 chan = ieee80211_chan2ieee(ic, c); 4118 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4119 return; 4120 4121 if (sc->mac_ver == 0x3290 || 4122 sc->mac_ver >= 0x5390) 4123 rt5390_set_chan(sc, chan); 4124 else if (sc->mac_ver >= 0x3071) 4125 rt3090_set_chan(sc, chan); 4126 else 4127 rt2860_set_chan(sc, chan); 4128 4129 /* determine channel group */ 4130 if (chan <= 14) 4131 group = 0; 4132 else if (chan <= 64) 4133 group = 1; 4134 else if (chan <= 128) 4135 group = 2; 4136 else 4137 group = 3; 4138 4139 /* XXX necessary only when group has changed! */ 4140 if (sc->mac_ver <= 0x5390) 4141 rt2860_select_chan_group(sc, group); 4142 4143 DELAY(1000); 4144 } 4145 4146 #ifndef IEEE80211_STA_ONLY 4147 int 4148 rt2860_setup_beacon(struct rt2860_softc *sc) 4149 { 4150 struct ieee80211com *ic = &sc->sc_ic; 4151 struct rt2860_txwi txwi; 4152 struct mbuf *m; 4153 int ridx; 4154 4155 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL) 4156 return ENOBUFS; 4157 4158 memset(&txwi, 0, sizeof txwi); 4159 txwi.wcid = 0xff; 4160 txwi.len = htole16(m->m_pkthdr.len); 4161 /* send beacons at the lowest available rate */ 4162 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4163 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4164 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4165 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4166 txwi.phy |= htole16(RT2860_PHY_OFDM); 4167 txwi.txop = RT2860_TX_TXOP_HT; 4168 txwi.flags = RT2860_TX_TS; 4169 txwi.xflags = RT2860_TX_NSEQ; 4170 4171 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4172 (uint8_t *)&txwi, sizeof txwi); 4173 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4174 mtod(m, uint8_t *), m->m_pkthdr.len); 4175 4176 m_freem(m); 4177 4178 return 0; 4179 } 4180 #endif 4181 4182 void 4183 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4184 { 4185 struct ieee80211com *ic = &sc->sc_ic; 4186 uint32_t tmp; 4187 4188 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4189 4190 tmp &= ~0x1fffff; 4191 tmp |= ic->ic_bss->ni_intval * 16; 4192 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4193 if (ic->ic_opmode == IEEE80211_M_STA) { 4194 /* 4195 * Local TSF is always updated with remote TSF on beacon 4196 * reception. 4197 */ 4198 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4199 } 4200 #ifndef IEEE80211_STA_ONLY 4201 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 4202 tmp |= RT2860_BCN_TX_EN; 4203 /* 4204 * Local TSF is updated with remote TSF on beacon reception 4205 * only if the remote TSF is greater than local TSF. 4206 */ 4207 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4208 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4209 tmp |= RT2860_BCN_TX_EN; 4210 /* SYNC with nobody */ 4211 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4212 } 4213 #endif 4214 4215 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4216 } 4217