1 /* $OpenBSD: rt2860.c,v 1.73 2014/07/12 18:48:17 tedu Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Ralink Technology RT2860/RT3090/RT3390/RT3562 chipset driver 21 * http://www.ralinktech.com/ 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/queue.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 38 #include <machine/bus.h> 39 #include <machine/endian.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/if_ether.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_amrr.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/ic/rt2860var.h> 61 #include <dev/ic/rt2860reg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/rndvar.h> 68 69 #ifdef RAL_DEBUG 70 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 71 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 72 int rt2860_debug = 0; 73 #else 74 #define DPRINTF(x) 75 #define DPRINTFN(n, x) 76 #endif 77 78 void rt2860_attachhook(void *); 79 int rt2860_alloc_tx_ring(struct rt2860_softc *, 80 struct rt2860_tx_ring *); 81 void rt2860_reset_tx_ring(struct rt2860_softc *, 82 struct rt2860_tx_ring *); 83 void rt2860_free_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 int rt2860_alloc_tx_pool(struct rt2860_softc *); 86 void rt2860_free_tx_pool(struct rt2860_softc *); 87 int rt2860_alloc_rx_ring(struct rt2860_softc *, 88 struct rt2860_rx_ring *); 89 void rt2860_reset_rx_ring(struct rt2860_softc *, 90 struct rt2860_rx_ring *); 91 void rt2860_free_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *); 94 int rt2860_media_change(struct ifnet *); 95 void rt2860_iter_func(void *, struct ieee80211_node *); 96 void rt2860_updatestats(struct rt2860_softc *); 97 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *, 98 int); 99 void rt2860_node_leave(struct ieee80211com *, 100 struct ieee80211_node *); 101 int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 106 int); 107 uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 108 uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 109 void rt2860_intr_coherent(struct rt2860_softc *); 110 void rt2860_drain_stats_fifo(struct rt2860_softc *); 111 void rt2860_tx_intr(struct rt2860_softc *, int); 112 void rt2860_rx_intr(struct rt2860_softc *); 113 void rt2860_tbtt_intr(struct rt2860_softc *); 114 void rt2860_gp_intr(struct rt2860_softc *); 115 int rt2860_tx(struct rt2860_softc *, struct mbuf *, 116 struct ieee80211_node *); 117 void rt2860_start(struct ifnet *); 118 void rt2860_watchdog(struct ifnet *); 119 int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 120 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 121 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 122 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 123 uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 124 void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 125 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 126 void rt2860_enable_mrr(struct rt2860_softc *); 127 void rt2860_set_txpreamble(struct rt2860_softc *); 128 void rt2860_set_basicrates(struct rt2860_softc *); 129 void rt2860_select_chan_group(struct rt2860_softc *, int); 130 void rt2860_set_chan(struct rt2860_softc *, u_int); 131 void rt3090_set_chan(struct rt2860_softc *, u_int); 132 int rt3090_rf_init(struct rt2860_softc *); 133 void rt3090_rf_wakeup(struct rt2860_softc *); 134 int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 135 uint8_t *); 136 void rt3090_rf_setup(struct rt2860_softc *); 137 void rt2860_set_leds(struct rt2860_softc *, uint16_t); 138 void rt2860_set_gp_timer(struct rt2860_softc *, int); 139 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 140 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 141 void rt2860_updateslot(struct ieee80211com *); 142 void rt2860_updateprot(struct ieee80211com *); 143 void rt2860_updateedca(struct ieee80211com *); 144 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 145 struct ieee80211_key *); 146 void rt2860_delete_key(struct ieee80211com *, 147 struct ieee80211_node *, struct ieee80211_key *); 148 #if NBPFILTER > 0 149 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 150 #endif 151 const char * rt2860_get_rf(uint8_t); 152 int rt2860_read_eeprom(struct rt2860_softc *); 153 int rt2860_bbp_init(struct rt2860_softc *); 154 int rt2860_txrx_enable(struct rt2860_softc *); 155 int rt2860_init(struct ifnet *); 156 void rt2860_stop(struct ifnet *, int); 157 int rt2860_load_microcode(struct rt2860_softc *); 158 void rt2860_calib(struct rt2860_softc *); 159 void rt3090_set_rx_antenna(struct rt2860_softc *, int); 160 void rt2860_switch_chan(struct rt2860_softc *, 161 struct ieee80211_channel *); 162 #ifndef IEEE80211_STA_ONLY 163 int rt2860_setup_beacon(struct rt2860_softc *); 164 #endif 165 void rt2860_enable_tsf_sync(struct rt2860_softc *); 166 167 static const struct { 168 uint32_t reg; 169 uint32_t val; 170 } rt2860_def_mac[] = { 171 RT2860_DEF_MAC 172 }; 173 174 static const struct { 175 uint8_t reg; 176 uint8_t val; 177 } rt2860_def_bbp[] = { 178 RT2860_DEF_BBP 179 }; 180 181 static const struct rfprog { 182 uint8_t chan; 183 uint32_t r1, r2, r3, r4; 184 } rt2860_rf2850[] = { 185 RT2860_RF2850 186 }; 187 188 struct { 189 uint8_t n, r, k; 190 } rt3090_freqs[] = { 191 RT3070_RF3052 192 }; 193 194 static const struct { 195 uint8_t reg; 196 uint8_t val; 197 } rt3090_def_rf[] = { 198 RT3070_DEF_RF 199 }, rt3572_def_rf[] = { 200 RT3572_DEF_RF 201 }; 202 203 int 204 rt2860_attach(void *xsc, int id) 205 { 206 struct rt2860_softc *sc = xsc; 207 struct ieee80211com *ic = &sc->sc_ic; 208 int qid, ntries, error; 209 uint32_t tmp; 210 211 sc->amrr.amrr_min_success_threshold = 1; 212 sc->amrr.amrr_max_success_threshold = 15; 213 214 /* wait for NIC to initialize */ 215 for (ntries = 0; ntries < 100; ntries++) { 216 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 217 if (tmp != 0 && tmp != 0xffffffff) 218 break; 219 DELAY(10); 220 } 221 if (ntries == 100) { 222 printf("%s: timeout waiting for NIC to initialize\n", 223 sc->sc_dev.dv_xname); 224 return ETIMEDOUT; 225 } 226 sc->mac_ver = tmp >> 16; 227 sc->mac_rev = tmp & 0xffff; 228 229 if (sc->mac_ver != 0x2860 && 230 (id == PCI_PRODUCT_RALINK_RT2890 || 231 id == PCI_PRODUCT_RALINK_RT2790 || 232 id == PCI_PRODUCT_AWT_RT2890)) 233 sc->sc_flags |= RT2860_ADVANCED_PS; 234 235 /* retrieve RF rev. no and various other things from EEPROM */ 236 rt2860_read_eeprom(sc); 237 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 238 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n", 239 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev, 240 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains); 241 242 /* 243 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 244 */ 245 for (qid = 0; qid < 6; qid++) { 246 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 247 printf("%s: could not allocate Tx ring %d\n", 248 sc->sc_dev.dv_xname, qid); 249 goto fail1; 250 } 251 } 252 253 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 254 printf("%s: could not allocate Rx ring\n", 255 sc->sc_dev.dv_xname); 256 goto fail1; 257 } 258 259 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 260 printf("%s: could not allocate Tx pool\n", 261 sc->sc_dev.dv_xname); 262 goto fail2; 263 } 264 265 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 266 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 267 EDCA_AC_VO : 5; 268 269 if (rootvp == NULL) 270 mountroothook_establish(rt2860_attachhook, sc); 271 else 272 rt2860_attachhook(sc); 273 274 return 0; 275 276 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 277 fail1: while (--qid >= 0) 278 rt2860_free_tx_ring(sc, &sc->txq[qid]); 279 return error; 280 } 281 282 void 283 rt2860_attachhook(void *xsc) 284 { 285 struct rt2860_softc *sc = xsc; 286 struct ieee80211com *ic = &sc->sc_ic; 287 struct ifnet *ifp = &ic->ic_if; 288 int i, error; 289 290 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize); 291 if (error != 0) { 292 printf("%s: error %d, could not read firmware file %s\n", 293 sc->sc_dev.dv_xname, error, "ral-rt2860"); 294 return; 295 } 296 297 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 298 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 299 ic->ic_state = IEEE80211_S_INIT; 300 301 /* set device capabilities */ 302 ic->ic_caps = 303 IEEE80211_C_MONITOR | /* monitor mode supported */ 304 #ifndef IEEE80211_STA_ONLY 305 IEEE80211_C_IBSS | /* IBSS mode supported */ 306 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 307 IEEE80211_C_APPMGT | /* HostAP power management */ 308 #endif 309 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 310 IEEE80211_C_SHSLOT | /* short slot time supported */ 311 IEEE80211_C_WEP | /* s/w WEP */ 312 IEEE80211_C_RSN; /* WPA/RSN */ 313 314 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 315 /* set supported .11a rates */ 316 ic->ic_sup_rates[IEEE80211_MODE_11A] = 317 ieee80211_std_rateset_11a; 318 319 /* set supported .11a channels */ 320 for (i = 14; i < nitems(rt2860_rf2850); i++) { 321 uint8_t chan = rt2860_rf2850[i].chan; 322 ic->ic_channels[chan].ic_freq = 323 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 324 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 325 } 326 } 327 328 /* set supported .11b and .11g rates */ 329 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 330 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 331 332 /* set supported .11b and .11g channels (1 through 14) */ 333 for (i = 1; i <= 14; i++) { 334 ic->ic_channels[i].ic_freq = 335 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 336 ic->ic_channels[i].ic_flags = 337 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 338 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 339 } 340 341 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 342 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 343 344 ifp->if_softc = sc; 345 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 346 ifp->if_ioctl = rt2860_ioctl; 347 ifp->if_start = rt2860_start; 348 ifp->if_watchdog = rt2860_watchdog; 349 IFQ_SET_READY(&ifp->if_snd); 350 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 351 352 if_attach(ifp); 353 ieee80211_ifattach(ifp); 354 ic->ic_node_alloc = rt2860_node_alloc; 355 ic->ic_newassoc = rt2860_newassoc; 356 #ifndef IEEE80211_STA_ONLY 357 ic->ic_node_leave = rt2860_node_leave; 358 #endif 359 #ifndef IEEE80211_NO_HT 360 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 361 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 362 #endif 363 ic->ic_updateslot = rt2860_updateslot; 364 ic->ic_updateedca = rt2860_updateedca; 365 ic->ic_set_key = rt2860_set_key; 366 ic->ic_delete_key = rt2860_delete_key; 367 /* override state transition machine */ 368 sc->sc_newstate = ic->ic_newstate; 369 ic->ic_newstate = rt2860_newstate; 370 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status); 371 372 #if NBPFILTER > 0 373 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 374 sizeof (struct ieee80211_frame) + 64); 375 376 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 377 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 378 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 379 380 sc->sc_txtap_len = sizeof sc->sc_txtapu; 381 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 382 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 383 #endif 384 } 385 386 int 387 rt2860_detach(void *xsc) 388 { 389 struct rt2860_softc *sc = xsc; 390 struct ifnet *ifp = &sc->sc_ic.ic_if; 391 int qid; 392 393 ieee80211_ifdetach(ifp); /* free all nodes */ 394 if_detach(ifp); 395 396 for (qid = 0; qid < 6; qid++) 397 rt2860_free_tx_ring(sc, &sc->txq[qid]); 398 rt2860_free_rx_ring(sc, &sc->rxq); 399 rt2860_free_tx_pool(sc); 400 401 if (sc->ucode != NULL) 402 free(sc->ucode, M_DEVBUF, 0); 403 404 return 0; 405 } 406 407 void 408 rt2860_suspend(void *xsc) 409 { 410 struct rt2860_softc *sc = xsc; 411 struct ifnet *ifp = &sc->sc_ic.ic_if; 412 413 if (ifp->if_flags & IFF_RUNNING) 414 rt2860_stop(ifp, 1); 415 } 416 417 void 418 rt2860_wakeup(void *xsc) 419 { 420 struct rt2860_softc *sc = xsc; 421 struct ifnet *ifp = &sc->sc_ic.ic_if; 422 423 if (ifp->if_flags & IFF_UP) 424 rt2860_init(ifp); 425 } 426 427 int 428 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 429 { 430 int nsegs, size, error; 431 432 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 433 434 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 435 BUS_DMA_NOWAIT, &ring->map); 436 if (error != 0) { 437 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 438 goto fail; 439 } 440 441 /* Tx rings must be 4-DWORD aligned */ 442 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 443 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 444 if (error != 0) { 445 printf("%s: could not allocate DMA memory\n", 446 sc->sc_dev.dv_xname); 447 goto fail; 448 } 449 450 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 451 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT); 452 if (error != 0) { 453 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 454 goto fail; 455 } 456 457 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 458 BUS_DMA_NOWAIT); 459 if (error != 0) { 460 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 461 goto fail; 462 } 463 464 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 465 466 ring->paddr = ring->map->dm_segs[0].ds_addr; 467 468 return 0; 469 470 fail: rt2860_free_tx_ring(sc, ring); 471 return error; 472 } 473 474 void 475 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 476 { 477 struct rt2860_tx_data *data; 478 int i; 479 480 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 481 if ((data = ring->data[i]) == NULL) 482 continue; /* nothing mapped in this slot */ 483 484 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 485 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 486 bus_dmamap_unload(sc->sc_dmat, data->map); 487 m_freem(data->m); 488 data->m= NULL; 489 data->ni = NULL; /* node already freed */ 490 491 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 492 ring->data[i] = NULL; 493 } 494 495 ring->queued = 0; 496 ring->cur = ring->next = 0; 497 } 498 499 void 500 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 501 { 502 struct rt2860_tx_data *data; 503 int i; 504 505 if (ring->txd != NULL) { 506 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 507 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 508 bus_dmamap_unload(sc->sc_dmat, ring->map); 509 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd, 510 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 511 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 512 } 513 if (ring->map != NULL) 514 bus_dmamap_destroy(sc->sc_dmat, ring->map); 515 516 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 517 if ((data = ring->data[i]) == NULL) 518 continue; /* nothing mapped in this slot */ 519 520 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 521 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 522 bus_dmamap_unload(sc->sc_dmat, data->map); 523 m_freem(data->m); 524 525 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 526 } 527 } 528 529 /* 530 * Allocate a pool of TX Wireless Information blocks. 531 */ 532 int 533 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 534 { 535 caddr_t vaddr; 536 bus_addr_t paddr; 537 int i, nsegs, size, error; 538 539 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 540 541 /* init data_pool early in case of failure.. */ 542 SLIST_INIT(&sc->data_pool); 543 544 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 545 BUS_DMA_NOWAIT, &sc->txwi_map); 546 if (error != 0) { 547 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 548 goto fail; 549 } 550 551 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 552 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 553 if (error != 0) { 554 printf("%s: could not allocate DMA memory\n", 555 sc->sc_dev.dv_xname); 556 goto fail; 557 } 558 559 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 560 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 561 if (error != 0) { 562 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 563 goto fail; 564 } 565 566 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 567 size, NULL, BUS_DMA_NOWAIT); 568 if (error != 0) { 569 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 570 goto fail; 571 } 572 573 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 574 BUS_DMASYNC_PREWRITE); 575 576 vaddr = sc->txwi_vaddr; 577 paddr = sc->txwi_map->dm_segs[0].ds_addr; 578 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 579 struct rt2860_tx_data *data = &sc->data[i]; 580 581 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 582 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 583 &data->map); 584 if (error != 0) { 585 printf("%s: could not create DMA map\n", 586 sc->sc_dev.dv_xname); 587 goto fail; 588 } 589 data->txwi = (struct rt2860_txwi *)vaddr; 590 data->paddr = paddr; 591 vaddr += RT2860_TXWI_DMASZ; 592 paddr += RT2860_TXWI_DMASZ; 593 594 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 595 } 596 597 return 0; 598 599 fail: rt2860_free_tx_pool(sc); 600 return error; 601 } 602 603 void 604 rt2860_free_tx_pool(struct rt2860_softc *sc) 605 { 606 if (sc->txwi_vaddr != NULL) { 607 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 608 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 609 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 610 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 611 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 612 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 613 } 614 if (sc->txwi_map != NULL) 615 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 616 617 while (!SLIST_EMPTY(&sc->data_pool)) { 618 struct rt2860_tx_data *data; 619 data = SLIST_FIRST(&sc->data_pool); 620 bus_dmamap_destroy(sc->sc_dmat, data->map); 621 SLIST_REMOVE_HEAD(&sc->data_pool, next); 622 } 623 } 624 625 int 626 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 627 { 628 int i, nsegs, size, error; 629 630 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 631 632 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 633 BUS_DMA_NOWAIT, &ring->map); 634 if (error != 0) { 635 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 636 goto fail; 637 } 638 639 /* Rx ring must be 4-DWORD aligned */ 640 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 641 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 642 if (error != 0) { 643 printf("%s: could not allocate DMA memory\n", 644 sc->sc_dev.dv_xname); 645 goto fail; 646 } 647 648 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 649 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT); 650 if (error != 0) { 651 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 652 goto fail; 653 } 654 655 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 656 BUS_DMA_NOWAIT); 657 if (error != 0) { 658 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 659 goto fail; 660 } 661 662 ring->paddr = ring->map->dm_segs[0].ds_addr; 663 664 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 665 struct rt2860_rx_data *data = &ring->data[i]; 666 struct rt2860_rxd *rxd = &ring->rxd[i]; 667 668 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 669 0, BUS_DMA_NOWAIT, &data->map); 670 if (error != 0) { 671 printf("%s: could not create DMA map\n", 672 sc->sc_dev.dv_xname); 673 goto fail; 674 } 675 676 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 677 if (data->m == NULL) { 678 printf("%s: could not allocate Rx mbuf\n", 679 sc->sc_dev.dv_xname); 680 error = ENOBUFS; 681 goto fail; 682 } 683 684 error = bus_dmamap_load(sc->sc_dmat, data->map, 685 mtod(data->m, void *), MCLBYTES, NULL, 686 BUS_DMA_READ | BUS_DMA_NOWAIT); 687 if (error != 0) { 688 printf("%s: could not load DMA map\n", 689 sc->sc_dev.dv_xname); 690 goto fail; 691 } 692 693 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 694 rxd->sdl0 = htole16(MCLBYTES); 695 } 696 697 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 698 699 return 0; 700 701 fail: rt2860_free_rx_ring(sc, ring); 702 return error; 703 } 704 705 void 706 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 707 { 708 int i; 709 710 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 711 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 712 713 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 714 BUS_DMASYNC_PREWRITE); 715 716 ring->cur = 0; 717 } 718 719 void 720 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 721 { 722 int i; 723 724 if (ring->rxd != NULL) { 725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 726 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 727 bus_dmamap_unload(sc->sc_dmat, ring->map); 728 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd, 729 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 730 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 731 } 732 if (ring->map != NULL) 733 bus_dmamap_destroy(sc->sc_dmat, ring->map); 734 735 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 736 struct rt2860_rx_data *data = &ring->data[i]; 737 738 if (data->m != NULL) { 739 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 740 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 741 bus_dmamap_unload(sc->sc_dmat, data->map); 742 m_freem(data->m); 743 } 744 if (data->map != NULL) 745 bus_dmamap_destroy(sc->sc_dmat, data->map); 746 } 747 } 748 749 struct ieee80211_node * 750 rt2860_node_alloc(struct ieee80211com *ic) 751 { 752 return malloc(sizeof (struct rt2860_node), M_DEVBUF, 753 M_NOWAIT | M_ZERO); 754 } 755 756 int 757 rt2860_media_change(struct ifnet *ifp) 758 { 759 struct rt2860_softc *sc = ifp->if_softc; 760 struct ieee80211com *ic = &sc->sc_ic; 761 uint8_t rate, ridx; 762 int error; 763 764 error = ieee80211_media_change(ifp); 765 if (error != ENETRESET) 766 return error; 767 768 if (ic->ic_fixed_rate != -1) { 769 rate = ic->ic_sup_rates[ic->ic_curmode]. 770 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 771 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 772 if (rt2860_rates[ridx].rate == rate) 773 break; 774 sc->fixed_ridx = ridx; 775 } 776 777 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 778 (IFF_UP | IFF_RUNNING)) { 779 rt2860_stop(ifp, 0); 780 rt2860_init(ifp); 781 } 782 return 0; 783 } 784 785 void 786 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 787 { 788 struct rt2860_softc *sc = arg; 789 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 790 791 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 792 } 793 794 void 795 rt2860_updatestats(struct rt2860_softc *sc) 796 { 797 struct ieee80211com *ic = &sc->sc_ic; 798 799 #ifndef IEEE80211_STA_ONLY 800 /* 801 * In IBSS or HostAP modes (when the hardware sends beacons), the 802 * MAC can run into a livelock and start sending CTS-to-self frames 803 * like crazy if protection is enabled. Fortunately, we can detect 804 * when such a situation occurs and reset the MAC. 805 */ 806 if (ic->ic_curmode != IEEE80211_M_STA) { 807 /* check if we're in a livelock situation.. */ 808 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 809 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 810 /* ..and reset MAC/BBP for a while.. */ 811 DPRINTF(("CTS-to-self livelock detected\n")); 812 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 813 RAL_BARRIER_WRITE(sc); 814 DELAY(1); 815 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 816 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 817 } 818 } 819 #endif 820 if (ic->ic_opmode == IEEE80211_M_STA) 821 rt2860_iter_func(sc, ic->ic_bss); 822 #ifndef IEEE80211_STA_ONLY 823 else 824 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc); 825 #endif 826 } 827 828 void 829 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 830 { 831 struct rt2860_softc *sc = ic->ic_softc; 832 struct rt2860_node *rn = (void *)ni; 833 struct ieee80211_rateset *rs = &ni->ni_rates; 834 uint8_t rate, wcid = 0; 835 int ridx, i, j; 836 837 if (isnew && ni->ni_associd != 0) { 838 /* only interested in true associations */ 839 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 840 841 /* init WCID table entry */ 842 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 843 ni->ni_macaddr, IEEE80211_ADDR_LEN); 844 } 845 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 846 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 847 848 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 849 /* start at lowest available bit-rate, AMRR will raise */ 850 ni->ni_txrate = 0; 851 852 for (i = 0; i < rs->rs_nrates; i++) { 853 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 854 /* convert 802.11 rate to hardware rate index */ 855 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 856 if (rt2860_rates[ridx].rate == rate) 857 break; 858 rn->ridx[i] = ridx; 859 /* determine rate of control response frames */ 860 for (j = i; j >= 0; j--) { 861 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 862 rt2860_rates[rn->ridx[i]].phy == 863 rt2860_rates[rn->ridx[j]].phy) 864 break; 865 } 866 if (j >= 0) { 867 rn->ctl_ridx[i] = rn->ridx[j]; 868 } else { 869 /* no basic rate found, use mandatory one */ 870 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 871 } 872 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 873 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 874 } 875 } 876 877 #ifndef IEEE80211_STA_ONLY 878 void 879 rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni) 880 { 881 struct rt2860_softc *sc = ic->ic_softc; 882 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 883 884 /* clear Rx WCID search table entry */ 885 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 886 } 887 #endif 888 889 #ifndef IEEE80211_NO_HT 890 int 891 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 892 uint8_t tid) 893 { 894 struct rt2860_softc *sc = ic->ic_softc; 895 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 896 uint32_t tmp; 897 898 /* update BA session mask */ 899 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 900 tmp |= (1 << tid) << 16; 901 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 902 return 0; 903 } 904 905 void 906 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 907 uint8_t tid) 908 { 909 struct rt2860_softc *sc = ic->ic_softc; 910 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 911 uint32_t tmp; 912 913 /* update BA session mask */ 914 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 915 tmp &= ~((1 << tid) << 16); 916 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 917 } 918 #endif 919 920 int 921 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 922 { 923 struct rt2860_softc *sc = ic->ic_if.if_softc; 924 enum ieee80211_state ostate; 925 uint32_t tmp; 926 927 ostate = ic->ic_state; 928 929 if (ostate == IEEE80211_S_RUN) { 930 /* turn link LED off */ 931 rt2860_set_leds(sc, RT2860_LED_RADIO); 932 } 933 934 switch (nstate) { 935 case IEEE80211_S_INIT: 936 if (ostate == IEEE80211_S_RUN) { 937 /* abort TSF synchronization */ 938 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 939 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 940 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 941 RT2860_TBTT_TIMER_EN)); 942 } 943 rt2860_set_gp_timer(sc, 0); 944 break; 945 946 case IEEE80211_S_SCAN: 947 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 948 if (ostate != IEEE80211_S_SCAN) 949 rt2860_set_gp_timer(sc, 150); 950 break; 951 952 case IEEE80211_S_AUTH: 953 case IEEE80211_S_ASSOC: 954 rt2860_set_gp_timer(sc, 0); 955 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 956 break; 957 958 case IEEE80211_S_RUN: 959 rt2860_set_gp_timer(sc, 0); 960 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 961 962 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 963 rt2860_updateslot(ic); 964 rt2860_enable_mrr(sc); 965 rt2860_set_txpreamble(sc); 966 rt2860_set_basicrates(sc); 967 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 968 } 969 970 #ifndef IEEE80211_STA_ONLY 971 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 972 ic->ic_opmode == IEEE80211_M_IBSS) 973 (void)rt2860_setup_beacon(sc); 974 #endif 975 976 if (ic->ic_opmode == IEEE80211_M_STA) { 977 /* fake a join to init the tx rate */ 978 rt2860_newassoc(ic, ic->ic_bss, 1); 979 } 980 981 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 982 rt2860_enable_tsf_sync(sc); 983 rt2860_set_gp_timer(sc, 500); 984 } 985 986 /* turn link LED on */ 987 rt2860_set_leds(sc, RT2860_LED_RADIO | 988 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 989 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 990 break; 991 } 992 993 return sc->sc_newstate(ic, nstate, arg); 994 } 995 996 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 997 uint16_t 998 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 999 { 1000 uint32_t tmp; 1001 uint16_t reg; 1002 int ntries; 1003 1004 addr *= 2; 1005 /*- 1006 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1007 * DATA0: F E D C 1008 * DATA1: B A 9 8 1009 * DATA2: 7 6 5 4 1010 * DATA3: 3 2 1 0 1011 */ 1012 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1013 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1014 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1015 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1016 for (ntries = 0; ntries < 500; ntries++) { 1017 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1018 if (!(tmp & RT3070_EFSROM_KICK)) 1019 break; 1020 DELAY(2); 1021 } 1022 if (ntries == 500) 1023 return 0xffff; 1024 1025 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1026 return 0xffff; /* address not found */ 1027 1028 /* determine to which 32-bit register our 16-bit word belongs */ 1029 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1030 tmp = RAL_READ(sc, reg); 1031 1032 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1033 } 1034 1035 /* 1036 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1037 * 93C66 or 93C86). 1038 */ 1039 uint16_t 1040 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1041 { 1042 uint32_t tmp; 1043 uint16_t val; 1044 int n; 1045 1046 /* clock C once before the first command */ 1047 RT2860_EEPROM_CTL(sc, 0); 1048 1049 RT2860_EEPROM_CTL(sc, RT2860_S); 1050 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1051 RT2860_EEPROM_CTL(sc, RT2860_S); 1052 1053 /* write start bit (1) */ 1054 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1055 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1056 1057 /* write READ opcode (10) */ 1058 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1059 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1060 RT2860_EEPROM_CTL(sc, RT2860_S); 1061 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1062 1063 /* write address (A5-A0 or A7-A0) */ 1064 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1065 for (; n >= 0; n--) { 1066 RT2860_EEPROM_CTL(sc, RT2860_S | 1067 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1068 RT2860_EEPROM_CTL(sc, RT2860_S | 1069 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1070 } 1071 1072 RT2860_EEPROM_CTL(sc, RT2860_S); 1073 1074 /* read data Q15-Q0 */ 1075 val = 0; 1076 for (n = 15; n >= 0; n--) { 1077 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1078 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1079 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1080 RT2860_EEPROM_CTL(sc, RT2860_S); 1081 } 1082 1083 RT2860_EEPROM_CTL(sc, 0); 1084 1085 /* clear Chip Select and clock C */ 1086 RT2860_EEPROM_CTL(sc, RT2860_S); 1087 RT2860_EEPROM_CTL(sc, 0); 1088 RT2860_EEPROM_CTL(sc, RT2860_C); 1089 1090 return val; 1091 } 1092 1093 static __inline uint16_t 1094 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1095 { 1096 /* either eFUSE ROM or EEPROM */ 1097 return sc->sc_srom_read(sc, addr); 1098 } 1099 1100 void 1101 rt2860_intr_coherent(struct rt2860_softc *sc) 1102 { 1103 uint32_t tmp; 1104 1105 /* DMA finds data coherent event when checking the DDONE bit */ 1106 1107 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1108 1109 /* restart DMA engine */ 1110 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1111 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1112 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1113 1114 (void)rt2860_txrx_enable(sc); 1115 } 1116 1117 void 1118 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1119 { 1120 struct ifnet *ifp = &sc->sc_ic.ic_if; 1121 struct ieee80211_amrr_node *amn; 1122 uint32_t stat; 1123 uint8_t wcid, mcs, pid; 1124 1125 /* drain Tx status FIFO (maxsize = 16) */ 1126 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1127 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1128 1129 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1130 1131 /* if no ACK was requested, no feedback is available */ 1132 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1133 continue; 1134 1135 /* update per-STA AMRR stats */ 1136 amn = &sc->amn[wcid]; 1137 amn->amn_txcnt++; 1138 if (stat & RT2860_TXQ_OK) { 1139 /* 1140 * Check if there were retries, ie if the Tx success 1141 * rate is different from the requested rate. Note 1142 * that it works only because we do not allow rate 1143 * fallback from OFDM to CCK. 1144 */ 1145 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1146 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1147 if (mcs + 1 != pid) 1148 amn->amn_retrycnt++; 1149 } else { 1150 amn->amn_retrycnt++; 1151 ifp->if_oerrors++; 1152 } 1153 } 1154 } 1155 1156 void 1157 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1158 { 1159 struct ieee80211com *ic = &sc->sc_ic; 1160 struct ifnet *ifp = &ic->ic_if; 1161 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1162 uint32_t hw; 1163 1164 rt2860_drain_stats_fifo(sc); 1165 1166 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1167 while (ring->next != hw) { 1168 struct rt2860_tx_data *data = ring->data[ring->next]; 1169 1170 if (data != NULL) { 1171 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1172 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1173 bus_dmamap_unload(sc->sc_dmat, data->map); 1174 m_freem(data->m); 1175 data->m= NULL; 1176 ieee80211_release_node(ic, data->ni); 1177 data->ni = NULL; 1178 1179 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1180 ring->data[ring->next] = NULL; 1181 1182 ifp->if_opackets++; 1183 } 1184 ring->queued--; 1185 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1186 } 1187 1188 sc->sc_tx_timer = 0; 1189 if (ring->queued < RT2860_TX_RING_COUNT) 1190 sc->qfullmsk &= ~(1 << qid); 1191 ifp->if_flags &= ~IFF_OACTIVE; 1192 rt2860_start(ifp); 1193 } 1194 1195 /* 1196 * Return the Rx chain with the highest RSSI for a given frame. 1197 */ 1198 static __inline uint8_t 1199 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1200 { 1201 uint8_t rxchain = 0; 1202 1203 if (sc->nrxchains > 1) { 1204 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1205 rxchain = 1; 1206 if (sc->nrxchains > 2) 1207 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1208 rxchain = 2; 1209 } 1210 return rxchain; 1211 } 1212 1213 void 1214 rt2860_rx_intr(struct rt2860_softc *sc) 1215 { 1216 struct ieee80211com *ic = &sc->sc_ic; 1217 struct ifnet *ifp = &ic->ic_if; 1218 struct ieee80211_frame *wh; 1219 struct ieee80211_rxinfo rxi; 1220 struct ieee80211_node *ni; 1221 struct mbuf *m, *m1; 1222 uint32_t hw; 1223 uint8_t ant, rssi; 1224 int error; 1225 #if NBPFILTER > 0 1226 struct rt2860_rx_radiotap_header *tap; 1227 struct mbuf mb; 1228 uint16_t phy; 1229 #endif 1230 1231 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1232 while (sc->rxq.cur != hw) { 1233 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1234 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1235 struct rt2860_rxwi *rxwi; 1236 1237 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1238 sc->rxq.cur * sizeof (struct rt2860_rxd), 1239 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1240 1241 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1242 DPRINTF(("RXD DDONE bit not set!\n")); 1243 break; /* should not happen */ 1244 } 1245 1246 if (__predict_false(rxd->flags & 1247 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1248 ifp->if_ierrors++; 1249 goto skip; 1250 } 1251 1252 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1253 /* report MIC failures to net80211 for TKIP */ 1254 ic->ic_stats.is_rx_locmicfail++; 1255 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1256 ifp->if_ierrors++; 1257 goto skip; 1258 } 1259 1260 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1261 if (__predict_false(m1 == NULL)) { 1262 ifp->if_ierrors++; 1263 goto skip; 1264 } 1265 1266 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1267 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1268 bus_dmamap_unload(sc->sc_dmat, data->map); 1269 1270 error = bus_dmamap_load(sc->sc_dmat, data->map, 1271 mtod(m1, void *), MCLBYTES, NULL, 1272 BUS_DMA_READ | BUS_DMA_NOWAIT); 1273 if (__predict_false(error != 0)) { 1274 m_freem(m1); 1275 1276 /* try to reload the old mbuf */ 1277 error = bus_dmamap_load(sc->sc_dmat, data->map, 1278 mtod(data->m, void *), MCLBYTES, NULL, 1279 BUS_DMA_READ | BUS_DMA_NOWAIT); 1280 if (__predict_false(error != 0)) { 1281 panic("%s: could not load old rx mbuf", 1282 sc->sc_dev.dv_xname); 1283 } 1284 /* physical address may have changed */ 1285 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1286 ifp->if_ierrors++; 1287 goto skip; 1288 } 1289 1290 /* 1291 * New mbuf successfully loaded, update Rx ring and continue 1292 * processing. 1293 */ 1294 m = data->m; 1295 data->m = m1; 1296 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1297 1298 rxwi = mtod(m, struct rt2860_rxwi *); 1299 1300 /* finalize mbuf */ 1301 m->m_pkthdr.rcvif = ifp; 1302 m->m_data = (caddr_t)(rxwi + 1); 1303 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff; 1304 1305 wh = mtod(m, struct ieee80211_frame *); 1306 rxi.rxi_flags = 0; 1307 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1308 /* frame is decrypted by hardware */ 1309 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1310 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1311 } 1312 1313 /* HW may insert 2 padding bytes after 802.11 header */ 1314 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1315 u_int hdrlen = ieee80211_get_hdrlen(wh); 1316 memmove((caddr_t)wh + 2, wh, hdrlen); 1317 m->m_data += 2; 1318 wh = mtod(m, struct ieee80211_frame *); 1319 } 1320 1321 ant = rt2860_maxrssi_chain(sc, rxwi); 1322 rssi = rxwi->rssi[ant]; 1323 1324 #if NBPFILTER > 0 1325 if (__predict_true(sc->sc_drvbpf == NULL)) 1326 goto skipbpf; 1327 1328 tap = &sc->sc_rxtap; 1329 tap->wr_flags = 0; 1330 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1331 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1332 tap->wr_antsignal = rssi; 1333 tap->wr_antenna = ant; 1334 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1335 tap->wr_rate = 2; /* in case it can't be found below */ 1336 phy = letoh16(rxwi->phy); 1337 switch (phy & RT2860_PHY_MODE) { 1338 case RT2860_PHY_CCK: 1339 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1340 case 0: tap->wr_rate = 2; break; 1341 case 1: tap->wr_rate = 4; break; 1342 case 2: tap->wr_rate = 11; break; 1343 case 3: tap->wr_rate = 22; break; 1344 } 1345 if (phy & RT2860_PHY_SHPRE) 1346 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1347 break; 1348 case RT2860_PHY_OFDM: 1349 switch (phy & RT2860_PHY_MCS) { 1350 case 0: tap->wr_rate = 12; break; 1351 case 1: tap->wr_rate = 18; break; 1352 case 2: tap->wr_rate = 24; break; 1353 case 3: tap->wr_rate = 36; break; 1354 case 4: tap->wr_rate = 48; break; 1355 case 5: tap->wr_rate = 72; break; 1356 case 6: tap->wr_rate = 96; break; 1357 case 7: tap->wr_rate = 108; break; 1358 } 1359 break; 1360 } 1361 mb.m_data = (caddr_t)tap; 1362 mb.m_len = sc->sc_rxtap_len; 1363 mb.m_next = m; 1364 mb.m_nextpkt = NULL; 1365 mb.m_type = 0; 1366 mb.m_flags = 0; 1367 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1368 skipbpf: 1369 #endif 1370 /* grab a reference to the source node */ 1371 ni = ieee80211_find_rxnode(ic, wh); 1372 1373 /* send the frame to the 802.11 layer */ 1374 rxi.rxi_rssi = rssi; 1375 rxi.rxi_tstamp = 0; /* unused */ 1376 ieee80211_input(ifp, m, ni, &rxi); 1377 1378 /* node is no longer needed */ 1379 ieee80211_release_node(ic, ni); 1380 1381 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1382 1383 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1384 sc->rxq.cur * sizeof (struct rt2860_rxd), 1385 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1386 1387 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1388 } 1389 1390 /* tell HW what we have processed */ 1391 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1392 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1393 } 1394 1395 void 1396 rt2860_tbtt_intr(struct rt2860_softc *sc) 1397 { 1398 struct ieee80211com *ic = &sc->sc_ic; 1399 1400 #ifndef IEEE80211_STA_ONLY 1401 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1402 /* one less beacon until next DTIM */ 1403 if (ic->ic_dtim_count == 0) 1404 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1405 else 1406 ic->ic_dtim_count--; 1407 1408 /* update dynamic parts of beacon */ 1409 rt2860_setup_beacon(sc); 1410 1411 /* flush buffered multicast frames */ 1412 if (ic->ic_dtim_count == 0) 1413 ieee80211_notify_dtim(ic); 1414 } 1415 #endif 1416 /* check if protection mode has changed */ 1417 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1418 rt2860_updateprot(ic); 1419 sc->sc_ic_flags = ic->ic_flags; 1420 } 1421 } 1422 1423 void 1424 rt2860_gp_intr(struct rt2860_softc *sc) 1425 { 1426 struct ieee80211com *ic = &sc->sc_ic; 1427 1428 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1429 1430 if (ic->ic_state == IEEE80211_S_SCAN) 1431 ieee80211_next_scan(&ic->ic_if); 1432 else if (ic->ic_state == IEEE80211_S_RUN) 1433 rt2860_updatestats(sc); 1434 } 1435 1436 int 1437 rt2860_intr(void *arg) 1438 { 1439 struct rt2860_softc *sc = arg; 1440 uint32_t r; 1441 1442 r = RAL_READ(sc, RT2860_INT_STATUS); 1443 if (__predict_false(r == 0xffffffff)) 1444 return 0; /* device likely went away */ 1445 if (r == 0) 1446 return 0; /* not for us */ 1447 1448 /* acknowledge interrupts */ 1449 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1450 1451 if (r & RT2860_TX_RX_COHERENT) 1452 rt2860_intr_coherent(sc); 1453 1454 if (r & RT2860_MAC_INT_2) /* TX status */ 1455 rt2860_drain_stats_fifo(sc); 1456 1457 if (r & RT2860_TX_DONE_INT5) 1458 rt2860_tx_intr(sc, 5); 1459 1460 if (r & RT2860_RX_DONE_INT) 1461 rt2860_rx_intr(sc); 1462 1463 if (r & RT2860_TX_DONE_INT4) 1464 rt2860_tx_intr(sc, 4); 1465 1466 if (r & RT2860_TX_DONE_INT3) 1467 rt2860_tx_intr(sc, 3); 1468 1469 if (r & RT2860_TX_DONE_INT2) 1470 rt2860_tx_intr(sc, 2); 1471 1472 if (r & RT2860_TX_DONE_INT1) 1473 rt2860_tx_intr(sc, 1); 1474 1475 if (r & RT2860_TX_DONE_INT0) 1476 rt2860_tx_intr(sc, 0); 1477 1478 if (r & RT2860_MAC_INT_0) /* TBTT */ 1479 rt2860_tbtt_intr(sc); 1480 1481 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1482 /* TBD wakeup */; 1483 1484 if (r & RT2860_MAC_INT_4) /* GP timer */ 1485 rt2860_gp_intr(sc); 1486 1487 return 1; 1488 } 1489 1490 int 1491 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1492 { 1493 struct ieee80211com *ic = &sc->sc_ic; 1494 struct rt2860_node *rn = (void *)ni; 1495 struct rt2860_tx_ring *ring; 1496 struct rt2860_tx_data *data; 1497 struct rt2860_txd *txd; 1498 struct rt2860_txwi *txwi; 1499 struct ieee80211_frame *wh; 1500 struct mbuf *m1; 1501 bus_dma_segment_t *seg; 1502 u_int hdrlen; 1503 uint16_t qos, dur; 1504 uint8_t type, qsel, mcs, pid, tid, qid; 1505 int nsegs, ntxds, hasqos, ridx, ctl_ridx, error; 1506 1507 /* the data pool contains at least one element, pick the first */ 1508 data = SLIST_FIRST(&sc->data_pool); 1509 1510 wh = mtod(m, struct ieee80211_frame *); 1511 hdrlen = ieee80211_get_hdrlen(wh); 1512 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1513 1514 if ((hasqos = ieee80211_has_qos(wh))) { 1515 qos = ieee80211_get_qos(wh); 1516 tid = qos & IEEE80211_QOS_TID; 1517 qid = ieee80211_up_to_ac(ic, tid); 1518 } else { 1519 qos = 0; 1520 tid = 0; 1521 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1522 sc->mgtqid : EDCA_AC_BE; 1523 } 1524 ring = &sc->txq[qid]; 1525 1526 /* pickup a rate index */ 1527 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1528 type != IEEE80211_FC0_TYPE_DATA) { 1529 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1530 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1531 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1532 } else if (ic->ic_fixed_rate != -1) { 1533 ridx = sc->fixed_ridx; 1534 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1535 } else { 1536 ridx = rn->ridx[ni->ni_txrate]; 1537 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1538 } 1539 1540 /* get MCS code from rate index */ 1541 mcs = rt2860_rates[ridx].mcs; 1542 1543 /* setup TX Wireless Information */ 1544 txwi = data->txwi; 1545 txwi->flags = 0; 1546 /* let HW generate seq numbers for non-QoS frames */ 1547 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1548 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1549 txwi->len = htole16(m->m_pkthdr.len); 1550 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1551 txwi->phy = htole16(RT2860_PHY_CCK); 1552 if (ridx != RT2860_RIDX_CCK1 && 1553 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1554 mcs |= RT2860_PHY_SHPRE; 1555 } else 1556 txwi->phy = htole16(RT2860_PHY_OFDM); 1557 txwi->phy |= htole16(mcs); 1558 1559 /* 1560 * We store the MCS code into the driver-private PacketID field. 1561 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1562 * that we know at which initial rate the frame was transmitted. 1563 * We add 1 to the MCS code because setting the PacketID field to 1564 * 0 means that we don't want feedback in TX_STAT_FIFO. 1565 */ 1566 pid = (mcs + 1) & 0xf; 1567 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1568 1569 /* check if RTS/CTS or CTS-to-self protection is required */ 1570 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1571 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1572 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1573 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1574 txwi->txop = RT2860_TX_TXOP_HT; 1575 else 1576 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1577 1578 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1579 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 1580 IEEE80211_QOS_ACK_POLICY_NOACK)) { 1581 txwi->xflags |= RT2860_TX_ACK; 1582 1583 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1584 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1585 else 1586 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1587 *(uint16_t *)wh->i_dur = htole16(dur); 1588 } 1589 #ifndef IEEE80211_STA_ONLY 1590 /* ask MAC to insert timestamp into probe responses */ 1591 if ((wh->i_fc[0] & 1592 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1593 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1594 /* NOTE: beacons do not pass through tx_data() */ 1595 txwi->flags |= RT2860_TX_TS; 1596 #endif 1597 1598 #if NBPFILTER > 0 1599 if (__predict_false(sc->sc_drvbpf != NULL)) { 1600 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1601 struct mbuf mb; 1602 1603 tap->wt_flags = 0; 1604 tap->wt_rate = rt2860_rates[ridx].rate; 1605 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1606 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1607 tap->wt_hwqueue = qid; 1608 if (mcs & RT2860_PHY_SHPRE) 1609 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1610 1611 mb.m_data = (caddr_t)tap; 1612 mb.m_len = sc->sc_txtap_len; 1613 mb.m_next = m; 1614 mb.m_nextpkt = NULL; 1615 mb.m_type = 0; 1616 mb.m_flags = 0; 1617 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1618 } 1619 #endif 1620 1621 /* copy and trim 802.11 header */ 1622 memcpy(txwi + 1, wh, hdrlen); 1623 m_adj(m, hdrlen); 1624 1625 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1626 BUS_DMA_NOWAIT); 1627 if (__predict_false(error != 0 && error != EFBIG)) { 1628 printf("%s: can't map mbuf (error %d)\n", 1629 sc->sc_dev.dv_xname, error); 1630 m_freem(m); 1631 return error; 1632 } 1633 if (__predict_true(error == 0)) { 1634 /* determine how many TXDs are required */ 1635 ntxds = 1 + (data->map->dm_nsegs / 2); 1636 1637 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1638 /* not enough free TXDs, force mbuf defrag */ 1639 bus_dmamap_unload(sc->sc_dmat, data->map); 1640 error = EFBIG; 1641 } 1642 } 1643 if (__predict_false(error != 0)) { 1644 /* too many fragments, linearize */ 1645 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1646 if (m1 == NULL) { 1647 m_freem(m); 1648 return ENOBUFS; 1649 } 1650 if (m->m_pkthdr.len > MHLEN) { 1651 MCLGET(m1, M_DONTWAIT); 1652 if (!(m1->m_flags & M_EXT)) { 1653 m_freem(m); 1654 m_freem(m1); 1655 return ENOBUFS; 1656 } 1657 } 1658 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1659 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1660 m_freem(m); 1661 m = m1; 1662 1663 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1664 BUS_DMA_NOWAIT); 1665 if (__predict_false(error != 0)) { 1666 printf("%s: can't map mbuf (error %d)\n", 1667 sc->sc_dev.dv_xname, error); 1668 m_freem(m); 1669 return error; 1670 } 1671 1672 /* determine how many TXDs are now required */ 1673 ntxds = 1 + (data->map->dm_nsegs / 2); 1674 1675 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1676 /* this is a hopeless case, drop the mbuf! */ 1677 bus_dmamap_unload(sc->sc_dmat, data->map); 1678 m_freem(m); 1679 return ENOBUFS; 1680 } 1681 } 1682 1683 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1684 1685 /* first segment is TXWI + 802.11 header */ 1686 txd = &ring->txd[ring->cur]; 1687 txd->sdp0 = htole32(data->paddr); 1688 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1689 txd->flags = qsel; 1690 1691 /* setup payload segments */ 1692 seg = data->map->dm_segs; 1693 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1694 txd->sdp1 = htole32(seg->ds_addr); 1695 txd->sdl1 = htole16(seg->ds_len); 1696 seg++; 1697 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1698 /* grab a new Tx descriptor */ 1699 txd = &ring->txd[ring->cur]; 1700 txd->sdp0 = htole32(seg->ds_addr); 1701 txd->sdl0 = htole16(seg->ds_len); 1702 txd->flags = qsel; 1703 seg++; 1704 } 1705 /* finalize last segment */ 1706 if (nsegs > 0) { 1707 txd->sdp1 = htole32(seg->ds_addr); 1708 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1709 } else { 1710 txd->sdl0 |= htole16(RT2860_TX_LS0); 1711 txd->sdl1 = 0; 1712 } 1713 1714 /* remove from the free pool and link it into the SW Tx slot */ 1715 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1716 data->m = m; 1717 data->ni = ni; 1718 ring->data[ring->cur] = data; 1719 1720 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1721 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1722 BUS_DMASYNC_PREWRITE); 1723 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1724 BUS_DMASYNC_PREWRITE); 1725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1726 BUS_DMASYNC_PREWRITE); 1727 1728 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1729 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1730 1731 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1732 ring->queued += ntxds; 1733 if (ring->queued >= RT2860_TX_RING_COUNT) 1734 sc->qfullmsk |= 1 << qid; 1735 1736 /* kick Tx */ 1737 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1738 1739 return 0; 1740 } 1741 1742 void 1743 rt2860_start(struct ifnet *ifp) 1744 { 1745 struct rt2860_softc *sc = ifp->if_softc; 1746 struct ieee80211com *ic = &sc->sc_ic; 1747 struct ieee80211_node *ni; 1748 struct mbuf *m; 1749 1750 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1751 return; 1752 1753 for (;;) { 1754 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1755 ifp->if_flags |= IFF_OACTIVE; 1756 break; 1757 } 1758 /* send pending management frames first */ 1759 IF_DEQUEUE(&ic->ic_mgtq, m); 1760 if (m != NULL) { 1761 ni = m->m_pkthdr.ph_cookie; 1762 goto sendit; 1763 } 1764 if (ic->ic_state != IEEE80211_S_RUN) 1765 break; 1766 1767 /* send buffered frames for power-save mode */ 1768 IF_DEQUEUE(&ic->ic_pwrsaveq, m); 1769 if (m != NULL) { 1770 ni = m->m_pkthdr.ph_cookie; 1771 goto sendit; 1772 } 1773 1774 /* encapsulate and send data frames */ 1775 IFQ_DEQUEUE(&ifp->if_snd, m); 1776 if (m == NULL) 1777 break; 1778 #if NBPFILTER > 0 1779 if (ifp->if_bpf != NULL) 1780 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1781 #endif 1782 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1783 continue; 1784 sendit: 1785 #if NBPFILTER > 0 1786 if (ic->ic_rawbpf != NULL) 1787 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1788 #endif 1789 if (rt2860_tx(sc, m, ni) != 0) { 1790 ieee80211_release_node(ic, ni); 1791 ifp->if_oerrors++; 1792 continue; 1793 } 1794 1795 sc->sc_tx_timer = 5; 1796 ifp->if_timer = 1; 1797 } 1798 } 1799 1800 void 1801 rt2860_watchdog(struct ifnet *ifp) 1802 { 1803 struct rt2860_softc *sc = ifp->if_softc; 1804 1805 ifp->if_timer = 0; 1806 1807 if (sc->sc_tx_timer > 0) { 1808 if (--sc->sc_tx_timer == 0) { 1809 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1810 rt2860_stop(ifp, 0); 1811 rt2860_init(ifp); 1812 ifp->if_oerrors++; 1813 return; 1814 } 1815 ifp->if_timer = 1; 1816 } 1817 1818 ieee80211_watchdog(ifp); 1819 } 1820 1821 int 1822 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1823 { 1824 struct rt2860_softc *sc = ifp->if_softc; 1825 struct ieee80211com *ic = &sc->sc_ic; 1826 struct ifaddr *ifa; 1827 struct ifreq *ifr; 1828 int s, error = 0; 1829 1830 s = splnet(); 1831 1832 switch (cmd) { 1833 case SIOCSIFADDR: 1834 ifa = (struct ifaddr *)data; 1835 ifp->if_flags |= IFF_UP; 1836 #ifdef INET 1837 if (ifa->ifa_addr->sa_family == AF_INET) 1838 arp_ifinit(&ic->ic_ac, ifa); 1839 #endif 1840 /* FALLTHROUGH */ 1841 case SIOCSIFFLAGS: 1842 if (ifp->if_flags & IFF_UP) { 1843 if (!(ifp->if_flags & IFF_RUNNING)) 1844 rt2860_init(ifp); 1845 } else { 1846 if (ifp->if_flags & IFF_RUNNING) 1847 rt2860_stop(ifp, 1); 1848 } 1849 break; 1850 1851 case SIOCADDMULTI: 1852 case SIOCDELMULTI: 1853 ifr = (struct ifreq *)data; 1854 error = (cmd == SIOCADDMULTI) ? 1855 ether_addmulti(ifr, &ic->ic_ac) : 1856 ether_delmulti(ifr, &ic->ic_ac); 1857 1858 if (error == ENETRESET) 1859 error = 0; 1860 break; 1861 1862 case SIOCS80211CHANNEL: 1863 /* 1864 * This allows for fast channel switching in monitor mode 1865 * (used by kismet). In IBSS mode, we must explicitly reset 1866 * the interface to generate a new beacon frame. 1867 */ 1868 error = ieee80211_ioctl(ifp, cmd, data); 1869 if (error == ENETRESET && 1870 ic->ic_opmode == IEEE80211_M_MONITOR) { 1871 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1872 (IFF_UP | IFF_RUNNING)) 1873 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1874 error = 0; 1875 } 1876 break; 1877 1878 default: 1879 error = ieee80211_ioctl(ifp, cmd, data); 1880 } 1881 1882 if (error == ENETRESET) { 1883 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1884 (IFF_UP | IFF_RUNNING)) { 1885 rt2860_stop(ifp, 0); 1886 rt2860_init(ifp); 1887 } 1888 error = 0; 1889 } 1890 1891 splx(s); 1892 1893 return error; 1894 } 1895 1896 /* 1897 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1898 * We access the BBP through the 8051 microcontroller unit which means that 1899 * the microcode must be loaded first. 1900 */ 1901 void 1902 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1903 { 1904 int ntries; 1905 1906 for (ntries = 0; ntries < 100; ntries++) { 1907 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1908 break; 1909 DELAY(1); 1910 } 1911 if (ntries == 100) { 1912 printf("%s: could not write to BBP through MCU\n", 1913 sc->sc_dev.dv_xname); 1914 return; 1915 } 1916 1917 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1918 RT2860_BBP_CSR_KICK | reg << 8 | val); 1919 RAL_BARRIER_WRITE(sc); 1920 1921 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1922 DELAY(1000); 1923 } 1924 1925 uint8_t 1926 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1927 { 1928 uint32_t val; 1929 int ntries; 1930 1931 for (ntries = 0; ntries < 100; ntries++) { 1932 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1933 break; 1934 DELAY(1); 1935 } 1936 if (ntries == 100) { 1937 printf("%s: could not read from BBP through MCU\n", 1938 sc->sc_dev.dv_xname); 1939 return 0; 1940 } 1941 1942 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1943 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1944 RAL_BARRIER_WRITE(sc); 1945 1946 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1947 DELAY(1000); 1948 1949 for (ntries = 0; ntries < 100; ntries++) { 1950 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1951 if (!(val & RT2860_BBP_CSR_KICK)) 1952 return val & 0xff; 1953 DELAY(1); 1954 } 1955 printf("%s: could not read from BBP through MCU\n", 1956 sc->sc_dev.dv_xname); 1957 1958 return 0; 1959 } 1960 1961 /* 1962 * Write to one of the 4 programmable 24-bit RF registers. 1963 */ 1964 void 1965 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 1966 { 1967 uint32_t tmp; 1968 int ntries; 1969 1970 for (ntries = 0; ntries < 100; ntries++) { 1971 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 1972 break; 1973 DELAY(1); 1974 } 1975 if (ntries == 100) { 1976 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1977 return; 1978 } 1979 1980 /* RF registers are 24-bit on the RT2860 */ 1981 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1982 (val & 0x3fffff) << 2 | (reg & 3); 1983 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 1984 } 1985 1986 uint8_t 1987 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 1988 { 1989 uint32_t tmp; 1990 int ntries; 1991 1992 for (ntries = 0; ntries < 100; ntries++) { 1993 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 1994 break; 1995 DELAY(1); 1996 } 1997 if (ntries == 100) { 1998 printf("%s: could not read RF register\n", 1999 sc->sc_dev.dv_xname); 2000 return 0xff; 2001 } 2002 tmp = RT3070_RF_KICK | reg << 8; 2003 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2004 2005 for (ntries = 0; ntries < 100; ntries++) { 2006 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2007 if (!(tmp & RT3070_RF_KICK)) 2008 break; 2009 DELAY(1); 2010 } 2011 if (ntries == 100) { 2012 printf("%s: could not read RF register\n", 2013 sc->sc_dev.dv_xname); 2014 return 0xff; 2015 } 2016 return tmp & 0xff; 2017 } 2018 2019 void 2020 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2021 { 2022 uint32_t tmp; 2023 int ntries; 2024 2025 for (ntries = 0; ntries < 10; ntries++) { 2026 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2027 break; 2028 DELAY(10); 2029 } 2030 if (ntries == 10) { 2031 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2032 return; 2033 } 2034 2035 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2036 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2037 } 2038 2039 /* 2040 * Send a command to the 8051 microcontroller unit. 2041 */ 2042 int 2043 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2044 { 2045 int slot, ntries; 2046 uint32_t tmp; 2047 uint8_t cid; 2048 2049 for (ntries = 0; ntries < 100; ntries++) { 2050 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2051 break; 2052 DELAY(2); 2053 } 2054 if (ntries == 100) 2055 return EIO; 2056 2057 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2058 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2059 RAL_BARRIER_WRITE(sc); 2060 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2061 2062 if (!wait) 2063 return 0; 2064 /* wait for the command to complete */ 2065 for (ntries = 0; ntries < 200; ntries++) { 2066 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2067 /* find the command slot */ 2068 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2069 if ((tmp & 0xff) == cid) 2070 break; 2071 if (slot < 4) 2072 break; 2073 DELAY(100); 2074 } 2075 if (ntries == 200) { 2076 /* clear command and status */ 2077 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2078 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2079 return ETIMEDOUT; 2080 } 2081 /* get command status (1 means success) */ 2082 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2083 tmp = (tmp >> (slot * 8)) & 0xff; 2084 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2085 cmd, slot, tmp)); 2086 /* clear command and status */ 2087 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2088 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2089 return (tmp == 1) ? 0 : EIO; 2090 } 2091 2092 void 2093 rt2860_enable_mrr(struct rt2860_softc *sc) 2094 { 2095 #define CCK(mcs) (mcs) 2096 #define OFDM(mcs) (1 << 3 | (mcs)) 2097 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2098 OFDM(6) << 28 | /* 54->48 */ 2099 OFDM(5) << 24 | /* 48->36 */ 2100 OFDM(4) << 20 | /* 36->24 */ 2101 OFDM(3) << 16 | /* 24->18 */ 2102 OFDM(2) << 12 | /* 18->12 */ 2103 OFDM(1) << 8 | /* 12-> 9 */ 2104 OFDM(0) << 4 | /* 9-> 6 */ 2105 OFDM(0)); /* 6-> 6 */ 2106 2107 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2108 CCK(2) << 12 | /* 11->5.5 */ 2109 CCK(1) << 8 | /* 5.5-> 2 */ 2110 CCK(0) << 4 | /* 2-> 1 */ 2111 CCK(0)); /* 1-> 1 */ 2112 #undef OFDM 2113 #undef CCK 2114 } 2115 2116 void 2117 rt2860_set_txpreamble(struct rt2860_softc *sc) 2118 { 2119 uint32_t tmp; 2120 2121 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2122 tmp &= ~RT2860_CCK_SHORT_EN; 2123 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2124 tmp |= RT2860_CCK_SHORT_EN; 2125 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2126 } 2127 2128 void 2129 rt2860_set_basicrates(struct rt2860_softc *sc) 2130 { 2131 struct ieee80211com *ic = &sc->sc_ic; 2132 2133 /* set basic rates mask */ 2134 if (ic->ic_curmode == IEEE80211_MODE_11B) 2135 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2136 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2137 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2138 else /* 11g */ 2139 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2140 } 2141 2142 void 2143 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2144 { 2145 uint32_t tmp; 2146 uint8_t agc; 2147 2148 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2149 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2150 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2151 rt2860_mcu_bbp_write(sc, 86, 0x00); 2152 2153 if (group == 0) { 2154 if (sc->ext_2ghz_lna) { 2155 rt2860_mcu_bbp_write(sc, 82, 0x62); 2156 rt2860_mcu_bbp_write(sc, 75, 0x46); 2157 } else { 2158 rt2860_mcu_bbp_write(sc, 82, 0x84); 2159 rt2860_mcu_bbp_write(sc, 75, 0x50); 2160 } 2161 } else { 2162 if (sc->mac_ver == 0x3572) 2163 rt2860_mcu_bbp_write(sc, 82, 0x94); 2164 else 2165 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2166 2167 if (sc->ext_5ghz_lna) 2168 rt2860_mcu_bbp_write(sc, 75, 0x46); 2169 else 2170 rt2860_mcu_bbp_write(sc, 75, 0x50); 2171 } 2172 2173 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2174 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2175 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2176 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2177 2178 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2179 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2180 if (sc->nrxchains > 1) 2181 tmp |= RT2860_LNA_PE1_EN; 2182 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2183 tmp |= RT3593_LNA_PE2_EN; 2184 if (group == 0) { /* 2GHz */ 2185 tmp |= RT2860_PA_PE_G0_EN; 2186 if (sc->ntxchains > 1) 2187 tmp |= RT2860_PA_PE_G1_EN; 2188 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2189 tmp |= RT3593_PA_PE_G2_EN; 2190 } else { /* 5GHz */ 2191 tmp |= RT2860_PA_PE_A0_EN; 2192 if (sc->ntxchains > 1) 2193 tmp |= RT2860_PA_PE_A1_EN; 2194 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2195 tmp |= RT3593_PA_PE_A2_EN; 2196 } 2197 if (sc->mac_ver == 0x3572) { 2198 rt3090_rf_write(sc, 8, 0x00); 2199 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2200 rt3090_rf_write(sc, 8, 0x80); 2201 } else 2202 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2203 2204 if (sc->mac_ver == 0x3593) { 2205 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2206 if (sc->sc_flags & RT2860_PCIE) { 2207 tmp &= ~0x01010000; 2208 if (group == 0) 2209 tmp |= 0x00010000; 2210 } else { 2211 tmp &= ~0x00008080; 2212 if (group == 0) 2213 tmp |= 0x00000080; 2214 } 2215 tmp = (tmp & ~0x00001000) | 0x00000010; 2216 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2217 } 2218 2219 /* set initial AGC value */ 2220 if (group == 0) { /* 2GHz band */ 2221 if (sc->mac_ver >= 0x3071) 2222 agc = 0x1c + sc->lna[0] * 2; 2223 else 2224 agc = 0x2e + sc->lna[0]; 2225 } else { /* 5GHz band */ 2226 if (sc->mac_ver == 0x3572) 2227 agc = 0x22 + (sc->lna[group] * 5) / 3; 2228 else 2229 agc = 0x32 + (sc->lna[group] * 5) / 3; 2230 } 2231 rt2860_mcu_bbp_write(sc, 66, agc); 2232 2233 DELAY(1000); 2234 } 2235 2236 void 2237 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2238 { 2239 const struct rfprog *rfprog = rt2860_rf2850; 2240 uint32_t r2, r3, r4; 2241 int8_t txpow1, txpow2; 2242 u_int i; 2243 2244 /* find the settings for this channel (we know it exists) */ 2245 for (i = 0; rfprog[i].chan != chan; i++); 2246 2247 r2 = rfprog[i].r2; 2248 if (sc->ntxchains == 1) 2249 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2250 if (sc->nrxchains == 1) 2251 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2252 else if (sc->nrxchains == 2) 2253 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2254 2255 /* use Tx power values from EEPROM */ 2256 txpow1 = sc->txpow1[i]; 2257 txpow2 = sc->txpow2[i]; 2258 if (chan > 14) { 2259 if (txpow1 >= 0) 2260 txpow1 = txpow1 << 1 | 1; 2261 else 2262 txpow1 = (7 + txpow1) << 1; 2263 if (txpow2 >= 0) 2264 txpow2 = txpow2 << 1 | 1; 2265 else 2266 txpow2 = (7 + txpow2) << 1; 2267 } 2268 r3 = rfprog[i].r3 | txpow1 << 7; 2269 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2270 2271 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2272 rt2860_rf_write(sc, RT2860_RF2, r2); 2273 rt2860_rf_write(sc, RT2860_RF3, r3); 2274 rt2860_rf_write(sc, RT2860_RF4, r4); 2275 2276 DELAY(200); 2277 2278 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2279 rt2860_rf_write(sc, RT2860_RF2, r2); 2280 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2281 rt2860_rf_write(sc, RT2860_RF4, r4); 2282 2283 DELAY(200); 2284 2285 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2286 rt2860_rf_write(sc, RT2860_RF2, r2); 2287 rt2860_rf_write(sc, RT2860_RF3, r3); 2288 rt2860_rf_write(sc, RT2860_RF4, r4); 2289 } 2290 2291 void 2292 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2293 { 2294 int8_t txpow1, txpow2; 2295 uint8_t rf; 2296 int i; 2297 2298 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2299 2300 /* find the settings for this channel (we know it exists) */ 2301 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2302 2303 /* use Tx power values from EEPROM */ 2304 txpow1 = sc->txpow1[i]; 2305 txpow2 = sc->txpow2[i]; 2306 2307 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2308 rf = rt3090_rf_read(sc, 3); 2309 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2310 rt3090_rf_write(sc, 3, rf); 2311 rf = rt3090_rf_read(sc, 6); 2312 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2313 rt3090_rf_write(sc, 6, rf); 2314 2315 /* set Tx0 power */ 2316 rf = rt3090_rf_read(sc, 12); 2317 rf = (rf & ~0x1f) | txpow1; 2318 rt3090_rf_write(sc, 12, rf); 2319 2320 /* set Tx1 power */ 2321 rf = rt3090_rf_read(sc, 13); 2322 rf = (rf & ~0x1f) | txpow2; 2323 rt3090_rf_write(sc, 13, rf); 2324 2325 rf = rt3090_rf_read(sc, 1); 2326 rf &= ~0xfc; 2327 if (sc->ntxchains == 1) 2328 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2329 else if (sc->ntxchains == 2) 2330 rf |= RT3070_TX2_PD; 2331 if (sc->nrxchains == 1) 2332 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2333 else if (sc->nrxchains == 2) 2334 rf |= RT3070_RX2_PD; 2335 rt3090_rf_write(sc, 1, rf); 2336 2337 /* set RF offset */ 2338 rf = rt3090_rf_read(sc, 23); 2339 rf = (rf & ~0x7f) | sc->freq; 2340 rt3090_rf_write(sc, 23, rf); 2341 2342 /* program RF filter */ 2343 rf = rt3090_rf_read(sc, 24); /* Tx */ 2344 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2345 rt3090_rf_write(sc, 24, rf); 2346 rf = rt3090_rf_read(sc, 31); /* Rx */ 2347 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2348 rt3090_rf_write(sc, 31, rf); 2349 2350 /* enable RF tuning */ 2351 rf = rt3090_rf_read(sc, 7); 2352 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2353 } 2354 2355 int 2356 rt3090_rf_init(struct rt2860_softc *sc) 2357 { 2358 uint32_t tmp; 2359 uint8_t rf, bbp; 2360 int i; 2361 2362 rf = rt3090_rf_read(sc, 30); 2363 /* toggle RF R30 bit 7 */ 2364 rt3090_rf_write(sc, 30, rf | 0x80); 2365 DELAY(1000); 2366 rt3090_rf_write(sc, 30, rf & ~0x80); 2367 2368 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2369 tmp &= ~0x1f000000; 2370 if (sc->patch_dac && sc->mac_rev < 0x0211) 2371 tmp |= 0x0d000000; /* 1.35V */ 2372 else 2373 tmp |= 0x01000000; /* 1.2V */ 2374 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2375 2376 /* patch LNA_PE_G1 */ 2377 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2378 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2379 2380 /* initialize RF registers to default value */ 2381 if (sc->mac_ver == 0x3572) { 2382 for (i = 0; i < nitems(rt3572_def_rf); i++) { 2383 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2384 rt3572_def_rf[i].val); 2385 } 2386 } else { 2387 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2388 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2389 rt3090_def_rf[i].val); 2390 } 2391 } 2392 2393 /* select 20MHz bandwidth */ 2394 rt3090_rf_write(sc, 31, 0x14); 2395 2396 rf = rt3090_rf_read(sc, 6); 2397 rt3090_rf_write(sc, 6, rf | 0x40); 2398 2399 if (sc->mac_ver != 0x3593) { 2400 /* calibrate filter for 20MHz bandwidth */ 2401 sc->rf24_20mhz = 0x1f; /* default value */ 2402 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2403 2404 /* select 40MHz bandwidth */ 2405 bbp = rt2860_mcu_bbp_read(sc, 4); 2406 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2407 rf = rt3090_rf_read(sc, 31); 2408 rt3090_rf_write(sc, 31, rf | 0x20); 2409 2410 /* calibrate filter for 40MHz bandwidth */ 2411 sc->rf24_40mhz = 0x2f; /* default value */ 2412 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2413 2414 /* go back to 20MHz bandwidth */ 2415 bbp = rt2860_mcu_bbp_read(sc, 4); 2416 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2417 } 2418 if (sc->mac_rev < 0x0211) 2419 rt3090_rf_write(sc, 27, 0x03); 2420 2421 tmp = RAL_READ(sc, RT3070_OPT_14); 2422 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2423 2424 if (sc->rf_rev == RT3070_RF_3020) 2425 rt3090_set_rx_antenna(sc, 0); 2426 2427 bbp = rt2860_mcu_bbp_read(sc, 138); 2428 if (sc->mac_ver == 0x3593) { 2429 if (sc->ntxchains == 1) 2430 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2431 else if (sc->ntxchains == 2) 2432 bbp |= 0x40; /* turn off DAC2 */ 2433 if (sc->nrxchains == 1) 2434 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2435 else if (sc->nrxchains == 2) 2436 bbp &= ~0x04; /* turn off ADC2 */ 2437 } else { 2438 if (sc->ntxchains == 1) 2439 bbp |= 0x20; /* turn off DAC1 */ 2440 if (sc->nrxchains == 1) 2441 bbp &= ~0x02; /* turn off ADC1 */ 2442 } 2443 rt2860_mcu_bbp_write(sc, 138, bbp); 2444 2445 rf = rt3090_rf_read(sc, 1); 2446 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2447 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2448 rt3090_rf_write(sc, 1, rf); 2449 2450 rf = rt3090_rf_read(sc, 15); 2451 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2452 2453 rf = rt3090_rf_read(sc, 17); 2454 rf &= ~RT3070_TX_LO1; 2455 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2456 rf |= 0x20; /* fix for long range Rx issue */ 2457 if (sc->txmixgain_2ghz >= 2) 2458 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2459 rt3090_rf_write(sc, 17, rf); 2460 2461 rf = rt3090_rf_read(sc, 20); 2462 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2463 2464 rf = rt3090_rf_read(sc, 21); 2465 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2466 2467 return 0; 2468 } 2469 2470 void 2471 rt3090_rf_wakeup(struct rt2860_softc *sc) 2472 { 2473 uint32_t tmp; 2474 uint8_t rf; 2475 2476 if (sc->mac_ver == 0x3593) { 2477 /* enable VCO */ 2478 rf = rt3090_rf_read(sc, 1); 2479 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2480 2481 /* initiate VCO calibration */ 2482 rf = rt3090_rf_read(sc, 3); 2483 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2484 2485 /* enable VCO bias current control */ 2486 rf = rt3090_rf_read(sc, 6); 2487 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2488 2489 /* initiate res calibration */ 2490 rf = rt3090_rf_read(sc, 2); 2491 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2492 2493 /* set reference current control to 0.33 mA */ 2494 rf = rt3090_rf_read(sc, 22); 2495 rf &= ~RT3593_CP_IC_MASK; 2496 rf |= 1 << RT3593_CP_IC_SHIFT; 2497 rt3090_rf_write(sc, 22, rf); 2498 2499 /* enable RX CTB */ 2500 rf = rt3090_rf_read(sc, 46); 2501 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2502 2503 rf = rt3090_rf_read(sc, 20); 2504 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2505 rt3090_rf_write(sc, 20, rf); 2506 } else { 2507 /* enable RF block */ 2508 rf = rt3090_rf_read(sc, 1); 2509 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2510 2511 /* enable VCO bias current control */ 2512 rf = rt3090_rf_read(sc, 7); 2513 rt3090_rf_write(sc, 7, rf | 0x30); 2514 2515 rf = rt3090_rf_read(sc, 9); 2516 rt3090_rf_write(sc, 9, rf | 0x0e); 2517 2518 /* enable RX CTB */ 2519 rf = rt3090_rf_read(sc, 21); 2520 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2521 2522 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2523 rf = rt3090_rf_read(sc, 27); 2524 rf &= ~0x77; 2525 if (sc->mac_rev < 0x0211) 2526 rf |= 0x03; 2527 rt3090_rf_write(sc, 27, rf); 2528 } 2529 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2530 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2531 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2532 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2533 } 2534 } 2535 2536 int 2537 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2538 uint8_t *val) 2539 { 2540 uint8_t rf22, rf24; 2541 uint8_t bbp55_pb, bbp55_sb, delta; 2542 int ntries; 2543 2544 /* program filter */ 2545 rf24 = rt3090_rf_read(sc, 24); 2546 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2547 rt3090_rf_write(sc, 24, rf24); 2548 2549 /* enable baseband loopback mode */ 2550 rf22 = rt3090_rf_read(sc, 22); 2551 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2552 2553 /* set power and frequency of passband test tone */ 2554 rt2860_mcu_bbp_write(sc, 24, 0x00); 2555 for (ntries = 0; ntries < 100; ntries++) { 2556 /* transmit test tone */ 2557 rt2860_mcu_bbp_write(sc, 25, 0x90); 2558 DELAY(1000); 2559 /* read received power */ 2560 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2561 if (bbp55_pb != 0) 2562 break; 2563 } 2564 if (ntries == 100) 2565 return ETIMEDOUT; 2566 2567 /* set power and frequency of stopband test tone */ 2568 rt2860_mcu_bbp_write(sc, 24, 0x06); 2569 for (ntries = 0; ntries < 100; ntries++) { 2570 /* transmit test tone */ 2571 rt2860_mcu_bbp_write(sc, 25, 0x90); 2572 DELAY(1000); 2573 /* read received power */ 2574 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2575 2576 delta = bbp55_pb - bbp55_sb; 2577 if (delta > target) 2578 break; 2579 2580 /* reprogram filter */ 2581 rf24++; 2582 rt3090_rf_write(sc, 24, rf24); 2583 } 2584 if (ntries < 100) { 2585 if (rf24 != init) 2586 rf24--; /* backtrack */ 2587 *val = rf24; 2588 rt3090_rf_write(sc, 24, rf24); 2589 } 2590 2591 /* restore initial state */ 2592 rt2860_mcu_bbp_write(sc, 24, 0x00); 2593 2594 /* disable baseband loopback mode */ 2595 rf22 = rt3090_rf_read(sc, 22); 2596 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2597 2598 return 0; 2599 } 2600 2601 void 2602 rt3090_rf_setup(struct rt2860_softc *sc) 2603 { 2604 uint8_t bbp; 2605 int i; 2606 2607 if (sc->mac_rev >= 0x0211) { 2608 /* enable DC filter */ 2609 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2610 2611 /* improve power consumption */ 2612 bbp = rt2860_mcu_bbp_read(sc, 31); 2613 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2614 } 2615 2616 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2617 if (sc->mac_rev < 0x0211) { 2618 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2619 sc->patch_dac ? 0x2c : 0x0f); 2620 } else 2621 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2622 2623 /* initialize RF registers from ROM */ 2624 for (i = 0; i < 10; i++) { 2625 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2626 continue; 2627 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2628 } 2629 } 2630 2631 void 2632 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2633 { 2634 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2635 which | (sc->leds & 0x7f), 0); 2636 } 2637 2638 /* 2639 * Hardware has a general-purpose programmable timer interrupt that can 2640 * periodically raise MAC_INT_4. 2641 */ 2642 void 2643 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2644 { 2645 uint32_t tmp; 2646 2647 /* disable GP timer before reprogramming it */ 2648 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2649 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2650 2651 if (ms == 0) 2652 return; 2653 2654 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2655 ms *= 16; /* Unit: 64us */ 2656 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2657 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2658 2659 /* enable GP timer */ 2660 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2661 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2662 } 2663 2664 void 2665 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2666 { 2667 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2668 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2669 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2670 bssid[4] | bssid[5] << 8); 2671 } 2672 2673 void 2674 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2675 { 2676 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2677 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2678 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2679 addr[4] | addr[5] << 8 | 0xff << 16); 2680 } 2681 2682 void 2683 rt2860_updateslot(struct ieee80211com *ic) 2684 { 2685 struct rt2860_softc *sc = ic->ic_softc; 2686 uint32_t tmp; 2687 2688 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2689 tmp &= ~0xff; 2690 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2691 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2692 } 2693 2694 void 2695 rt2860_updateprot(struct ieee80211com *ic) 2696 { 2697 struct rt2860_softc *sc = ic->ic_softc; 2698 uint32_t tmp; 2699 2700 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2701 /* setup protection frame rate (MCS code) */ 2702 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2703 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2704 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2705 2706 /* CCK frames don't require protection */ 2707 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2708 2709 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2710 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2711 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2712 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2713 tmp |= RT2860_PROT_CTRL_CTS; 2714 } 2715 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2716 } 2717 2718 void 2719 rt2860_updateedca(struct ieee80211com *ic) 2720 { 2721 struct rt2860_softc *sc = ic->ic_softc; 2722 int aci; 2723 2724 /* update MAC TX configuration registers */ 2725 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2726 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2727 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 2728 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 2729 ic->ic_edca_ac[aci].ac_aifsn << 8 | 2730 ic->ic_edca_ac[aci].ac_txoplimit); 2731 } 2732 2733 /* update SCH/DMA registers too */ 2734 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2735 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 2736 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 2737 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 2738 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 2739 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2740 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 2741 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 2742 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 2743 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 2744 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2745 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 2746 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 2747 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 2748 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 2749 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2750 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 2751 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 2752 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2753 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 2754 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 2755 } 2756 2757 int 2758 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2759 struct ieee80211_key *k) 2760 { 2761 struct rt2860_softc *sc = ic->ic_softc; 2762 bus_size_t base; 2763 uint32_t attr; 2764 uint8_t mode, wcid, iv[8]; 2765 2766 /* defer setting of WEP keys until interface is brought up */ 2767 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2768 (IFF_UP | IFF_RUNNING)) 2769 return 0; 2770 2771 /* map net80211 cipher to RT2860 security mode */ 2772 switch (k->k_cipher) { 2773 case IEEE80211_CIPHER_WEP40: 2774 mode = RT2860_MODE_WEP40; 2775 break; 2776 case IEEE80211_CIPHER_WEP104: 2777 mode = RT2860_MODE_WEP104; 2778 break; 2779 case IEEE80211_CIPHER_TKIP: 2780 mode = RT2860_MODE_TKIP; 2781 break; 2782 case IEEE80211_CIPHER_CCMP: 2783 mode = RT2860_MODE_AES_CCMP; 2784 break; 2785 default: 2786 return EINVAL; 2787 } 2788 2789 if (k->k_flags & IEEE80211_KEY_GROUP) { 2790 wcid = 0; /* NB: update WCID0 for group keys */ 2791 base = RT2860_SKEY(0, k->k_id); 2792 } else { 2793 wcid = ((struct rt2860_node *)ni)->wcid; 2794 base = RT2860_PKEY(wcid); 2795 } 2796 2797 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2798 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 2799 #ifndef IEEE80211_STA_ONLY 2800 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2801 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 2802 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 2803 } else 2804 #endif 2805 { 2806 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 2807 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 2808 } 2809 } else 2810 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 2811 2812 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 2813 (k->k_flags & IEEE80211_KEY_TX)) { 2814 /* set initial packet number in IV+EIV */ 2815 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 2816 k->k_cipher == IEEE80211_CIPHER_WEP104) { 2817 uint32_t val = arc4random(); 2818 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 2819 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 2820 val += 0x000100; 2821 iv[0] = val; 2822 iv[1] = val >> 8; 2823 iv[2] = val >> 16; 2824 iv[3] = k->k_id << 6; 2825 iv[4] = iv[5] = iv[6] = iv[7] = 0; 2826 } else { 2827 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 2828 iv[0] = k->k_tsc >> 8; 2829 iv[1] = (iv[0] | 0x20) & 0x7f; 2830 iv[2] = k->k_tsc; 2831 } else /* CCMP */ { 2832 iv[0] = k->k_tsc; 2833 iv[1] = k->k_tsc >> 8; 2834 iv[2] = 0; 2835 } 2836 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 2837 iv[4] = k->k_tsc >> 16; 2838 iv[5] = k->k_tsc >> 24; 2839 iv[6] = k->k_tsc >> 32; 2840 iv[7] = k->k_tsc >> 40; 2841 } 2842 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 2843 } 2844 2845 if (k->k_flags & IEEE80211_KEY_GROUP) { 2846 /* install group key */ 2847 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 2848 attr &= ~(0xf << (k->k_id * 4)); 2849 attr |= mode << (k->k_id * 4); 2850 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 2851 } else { 2852 /* install pairwise key */ 2853 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 2854 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2855 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 2856 } 2857 return 0; 2858 } 2859 2860 void 2861 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2862 struct ieee80211_key *k) 2863 { 2864 struct rt2860_softc *sc = ic->ic_softc; 2865 uint32_t attr; 2866 uint8_t wcid; 2867 2868 if (k->k_flags & IEEE80211_KEY_GROUP) { 2869 /* remove group key */ 2870 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 2871 attr &= ~(0xf << (k->k_id * 4)); 2872 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 2873 2874 } else { 2875 /* remove pairwise key */ 2876 wcid = ((struct rt2860_node *)ni)->wcid; 2877 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 2878 attr &= ~0xf; 2879 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 2880 } 2881 } 2882 2883 #if NBPFILTER > 0 2884 int8_t 2885 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 2886 { 2887 struct ieee80211com *ic = &sc->sc_ic; 2888 struct ieee80211_channel *c = ic->ic_ibss_chan; 2889 int delta; 2890 2891 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2892 u_int chan = ieee80211_chan2ieee(ic, c); 2893 delta = sc->rssi_5ghz[rxchain]; 2894 2895 /* determine channel group */ 2896 if (chan <= 64) 2897 delta -= sc->lna[1]; 2898 else if (chan <= 128) 2899 delta -= sc->lna[2]; 2900 else 2901 delta -= sc->lna[3]; 2902 } else 2903 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 2904 2905 return -12 - delta - rssi; 2906 } 2907 #endif 2908 2909 /* 2910 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 2911 * Used to adjust per-rate Tx power registers. 2912 */ 2913 static __inline uint32_t 2914 b4inc(uint32_t b32, int8_t delta) 2915 { 2916 int8_t i, b4; 2917 2918 for (i = 0; i < 8; i++) { 2919 b4 = b32 & 0xf; 2920 b4 += delta; 2921 if (b4 < 0) 2922 b4 = 0; 2923 else if (b4 > 0xf) 2924 b4 = 0xf; 2925 b32 = b32 >> 4 | b4 << 28; 2926 } 2927 return b32; 2928 } 2929 2930 const char * 2931 rt2860_get_rf(uint8_t rev) 2932 { 2933 switch (rev) { 2934 case RT2860_RF_2820: return "RT2820"; 2935 case RT2860_RF_2850: return "RT2850"; 2936 case RT2860_RF_2720: return "RT2720"; 2937 case RT2860_RF_2750: return "RT2750"; 2938 case RT3070_RF_3020: return "RT3020"; 2939 case RT3070_RF_2020: return "RT2020"; 2940 case RT3070_RF_3021: return "RT3021"; 2941 case RT3070_RF_3022: return "RT3022"; 2942 case RT3070_RF_3052: return "RT3052"; 2943 case RT3070_RF_3320: return "RT3320"; 2944 case RT3070_RF_3053: return "RT3053"; 2945 default: return "unknown"; 2946 } 2947 } 2948 2949 int 2950 rt2860_read_eeprom(struct rt2860_softc *sc) 2951 { 2952 struct ieee80211com *ic = &sc->sc_ic; 2953 int8_t delta_2ghz, delta_5ghz; 2954 uint32_t tmp; 2955 uint16_t val; 2956 int ridx, ant, i; 2957 2958 /* check whether the ROM is eFUSE ROM or EEPROM */ 2959 sc->sc_srom_read = rt2860_eeprom_read_2; 2960 if (sc->mac_ver >= 0x3071) { 2961 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 2962 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 2963 if (tmp & RT3070_SEL_EFUSE) 2964 sc->sc_srom_read = rt3090_efuse_read_2; 2965 } 2966 2967 /* read EEPROM version */ 2968 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 2969 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 2970 2971 /* read MAC address */ 2972 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 2973 ic->ic_myaddr[0] = val & 0xff; 2974 ic->ic_myaddr[1] = val >> 8; 2975 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 2976 ic->ic_myaddr[2] = val & 0xff; 2977 ic->ic_myaddr[3] = val >> 8; 2978 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 2979 ic->ic_myaddr[4] = val & 0xff; 2980 ic->ic_myaddr[5] = val >> 8; 2981 2982 /* read country code */ 2983 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 2984 DPRINTF(("EEPROM region code=0x%04x\n", val)); 2985 2986 /* read vendor BBP settings */ 2987 for (i = 0; i < 8; i++) { 2988 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 2989 sc->bbp[i].val = val & 0xff; 2990 sc->bbp[i].reg = val >> 8; 2991 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 2992 } 2993 if (sc->mac_ver >= 0x3071) { 2994 /* read vendor RF settings */ 2995 for (i = 0; i < 10; i++) { 2996 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 2997 sc->rf[i].val = val & 0xff; 2998 sc->rf[i].reg = val >> 8; 2999 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3000 sc->rf[i].val)); 3001 } 3002 } 3003 3004 /* read RF frequency offset from EEPROM */ 3005 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3006 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3007 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3008 if ((val >> 8) != 0xff) { 3009 /* read LEDs operating mode */ 3010 sc->leds = val >> 8; 3011 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3012 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3013 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3014 } else { 3015 /* broken EEPROM, use default settings */ 3016 sc->leds = 0x01; 3017 sc->led[0] = 0x5555; 3018 sc->led[1] = 0x2221; 3019 sc->led[2] = 0xa9f8; 3020 } 3021 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3022 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3023 3024 /* read RF information */ 3025 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3026 if (val == 0xffff) { 3027 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3028 if (sc->mac_ver == 0x3593) { 3029 /* default to RF3053 3T3R */ 3030 sc->rf_rev = RT3070_RF_3053; 3031 sc->ntxchains = 3; 3032 sc->nrxchains = 3; 3033 } else if (sc->mac_ver >= 0x3071) { 3034 /* default to RF3020 1T1R */ 3035 sc->rf_rev = RT3070_RF_3020; 3036 sc->ntxchains = 1; 3037 sc->nrxchains = 1; 3038 } else { 3039 /* default to RF2820 1T2R */ 3040 sc->rf_rev = RT2860_RF_2820; 3041 sc->ntxchains = 1; 3042 sc->nrxchains = 2; 3043 } 3044 } else { 3045 sc->rf_rev = (val >> 8) & 0xf; 3046 sc->ntxchains = (val >> 4) & 0xf; 3047 sc->nrxchains = val & 0xf; 3048 } 3049 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3050 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3051 3052 /* check if RF supports automatic Tx access gain control */ 3053 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3054 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3055 /* check if driver should patch the DAC issue */ 3056 if ((val >> 8) != 0xff) 3057 sc->patch_dac = (val >> 15) & 1; 3058 if ((val & 0xff) != 0xff) { 3059 sc->ext_5ghz_lna = (val >> 3) & 1; 3060 sc->ext_2ghz_lna = (val >> 2) & 1; 3061 /* check if RF supports automatic Tx access gain control */ 3062 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3063 /* check if we have a hardware radio switch */ 3064 sc->rfswitch = val & 1; 3065 } 3066 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3067 /* read PCIe power save level */ 3068 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3069 if ((val & 0xff) != 0xff) { 3070 sc->pslevel = val & 0x3; 3071 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3072 if ((val & 0xff80) != 0x9280) 3073 sc->pslevel = MIN(sc->pslevel, 1); 3074 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3075 } 3076 } 3077 3078 /* read power settings for 2GHz channels */ 3079 for (i = 0; i < 14; i += 2) { 3080 val = rt2860_srom_read(sc, 3081 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3082 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3083 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3084 3085 val = rt2860_srom_read(sc, 3086 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3087 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3088 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3089 } 3090 /* fix broken Tx power entries */ 3091 for (i = 0; i < 14; i++) { 3092 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 3093 sc->txpow1[i] = 5; 3094 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 3095 sc->txpow2[i] = 5; 3096 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3097 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3098 } 3099 /* read power settings for 5GHz channels */ 3100 for (i = 0; i < 40; i += 2) { 3101 val = rt2860_srom_read(sc, 3102 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3103 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3104 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3105 3106 val = rt2860_srom_read(sc, 3107 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3108 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3109 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3110 } 3111 /* fix broken Tx power entries */ 3112 for (i = 0; i < 40; i++) { 3113 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3114 sc->txpow1[14 + i] = 5; 3115 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3116 sc->txpow2[14 + i] = 5; 3117 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3118 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3119 sc->txpow2[14 + i])); 3120 } 3121 3122 /* read Tx power compensation for each Tx rate */ 3123 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3124 delta_2ghz = delta_5ghz = 0; 3125 if ((val & 0xff) != 0xff && (val & 0x80)) { 3126 delta_2ghz = val & 0xf; 3127 if (!(val & 0x40)) /* negative number */ 3128 delta_2ghz = -delta_2ghz; 3129 } 3130 val >>= 8; 3131 if ((val & 0xff) != 0xff && (val & 0x80)) { 3132 delta_5ghz = val & 0xf; 3133 if (!(val & 0x40)) /* negative number */ 3134 delta_5ghz = -delta_5ghz; 3135 } 3136 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3137 delta_2ghz, delta_5ghz)); 3138 3139 for (ridx = 0; ridx < 5; ridx++) { 3140 uint32_t reg; 3141 3142 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3143 reg = val; 3144 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3145 reg |= (uint32_t)val << 16; 3146 3147 sc->txpow20mhz[ridx] = reg; 3148 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3149 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3150 3151 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3152 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3153 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3154 } 3155 3156 /* read factory-calibrated samples for temperature compensation */ 3157 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3158 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3159 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3160 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3161 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3162 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3163 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3164 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3165 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3166 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3167 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3168 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3169 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3170 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3171 sc->step_2ghz = val >> 8; 3172 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3173 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3174 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3175 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3176 sc->tssi_2ghz[8], sc->step_2ghz)); 3177 /* check that ref value is correct, otherwise disable calibration */ 3178 if (sc->tssi_2ghz[4] == 0xff) 3179 sc->calib_2ghz = 0; 3180 3181 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3182 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3183 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3184 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3185 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3186 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3187 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3188 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3189 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3190 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3191 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3192 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3193 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3194 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3195 sc->step_5ghz = val >> 8; 3196 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3197 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3198 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3199 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3200 sc->tssi_5ghz[8], sc->step_5ghz)); 3201 /* check that ref value is correct, otherwise disable calibration */ 3202 if (sc->tssi_5ghz[4] == 0xff) 3203 sc->calib_5ghz = 0; 3204 3205 /* read RSSI offsets and LNA gains from EEPROM */ 3206 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3207 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3208 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3209 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3210 if (sc->mac_ver >= 0x3071) { 3211 /* 3212 * On RT3090 chips (limited to 2 Rx chains), this ROM 3213 * field contains the Tx mixer gain for the 2GHz band. 3214 */ 3215 if ((val & 0xff) != 0xff) 3216 sc->txmixgain_2ghz = val & 0x7; 3217 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3218 } else 3219 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3220 sc->lna[2] = val >> 8; /* channel group 2 */ 3221 3222 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3223 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3224 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3225 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3226 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3227 sc->lna[3] = val >> 8; /* channel group 3 */ 3228 3229 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3230 if (sc->mac_ver >= 0x3071) 3231 sc->lna[0] = RT3090_DEF_LNA; 3232 else /* channel group 0 */ 3233 sc->lna[0] = val & 0xff; 3234 sc->lna[1] = val >> 8; /* channel group 1 */ 3235 3236 /* fix broken 5GHz LNA entries */ 3237 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3238 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3239 sc->lna[2] = sc->lna[1]; 3240 } 3241 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3242 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3243 sc->lna[3] = sc->lna[1]; 3244 } 3245 3246 /* fix broken RSSI offset entries */ 3247 for (ant = 0; ant < 3; ant++) { 3248 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3249 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3250 ant + 1, sc->rssi_2ghz[ant])); 3251 sc->rssi_2ghz[ant] = 0; 3252 } 3253 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3254 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3255 ant + 1, sc->rssi_5ghz[ant])); 3256 sc->rssi_5ghz[ant] = 0; 3257 } 3258 } 3259 3260 return 0; 3261 } 3262 3263 int 3264 rt2860_bbp_init(struct rt2860_softc *sc) 3265 { 3266 int i, ntries; 3267 3268 /* wait for BBP to wake up */ 3269 for (ntries = 0; ntries < 20; ntries++) { 3270 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3271 if (bbp0 != 0 && bbp0 != 0xff) 3272 break; 3273 } 3274 if (ntries == 20) { 3275 printf("%s: timeout waiting for BBP to wake up\n", 3276 sc->sc_dev.dv_xname); 3277 return ETIMEDOUT; 3278 } 3279 3280 /* initialize BBP registers to default values */ 3281 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3282 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3283 rt2860_def_bbp[i].val); 3284 } 3285 3286 /* fix BBP84 for RT2860E */ 3287 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3288 rt2860_mcu_bbp_write(sc, 84, 0x19); 3289 3290 if (sc->mac_ver >= 0x3071) { 3291 rt2860_mcu_bbp_write(sc, 79, 0x13); 3292 rt2860_mcu_bbp_write(sc, 80, 0x05); 3293 rt2860_mcu_bbp_write(sc, 81, 0x33); 3294 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3295 rt2860_mcu_bbp_write(sc, 69, 0x16); 3296 rt2860_mcu_bbp_write(sc, 73, 0x12); 3297 } 3298 3299 return 0; 3300 } 3301 3302 int 3303 rt2860_txrx_enable(struct rt2860_softc *sc) 3304 { 3305 uint32_t tmp; 3306 int ntries; 3307 3308 /* enable Tx/Rx DMA engine */ 3309 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3310 RAL_BARRIER_READ_WRITE(sc); 3311 for (ntries = 0; ntries < 200; ntries++) { 3312 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3313 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3314 break; 3315 DELAY(1000); 3316 } 3317 if (ntries == 200) { 3318 printf("%s: timeout waiting for DMA engine\n", 3319 sc->sc_dev.dv_xname); 3320 return ETIMEDOUT; 3321 } 3322 3323 DELAY(50); 3324 3325 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3326 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3327 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3328 3329 /* set Rx filter */ 3330 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3331 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3332 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3333 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3334 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3335 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3336 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3337 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3338 } 3339 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3340 3341 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3342 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3343 3344 return 0; 3345 } 3346 3347 int 3348 rt2860_init(struct ifnet *ifp) 3349 { 3350 struct rt2860_softc *sc = ifp->if_softc; 3351 struct ieee80211com *ic = &sc->sc_ic; 3352 uint32_t tmp; 3353 uint8_t bbp1, bbp3; 3354 int i, qid, ridx, ntries, error; 3355 3356 /* for CardBus, power on the socket */ 3357 if (!(sc->sc_flags & RT2860_ENABLED)) { 3358 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3359 printf("%s: could not enable device\n", 3360 sc->sc_dev.dv_xname); 3361 return EIO; 3362 } 3363 sc->sc_flags |= RT2860_ENABLED; 3364 } 3365 3366 if (sc->rfswitch) { 3367 /* hardware has a radio switch on GPIO pin 2 */ 3368 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3369 printf("%s: radio is disabled by hardware switch\n", 3370 sc->sc_dev.dv_xname); 3371 #ifdef notyet 3372 rt2860_stop(ifp, 1); 3373 return EPERM; 3374 #endif 3375 } 3376 } 3377 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3378 3379 /* disable DMA */ 3380 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3381 tmp &= 0xff0; 3382 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3383 3384 /* PBF hardware reset */ 3385 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3386 RAL_BARRIER_WRITE(sc); 3387 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3388 3389 if ((error = rt2860_load_microcode(sc)) != 0) { 3390 printf("%s: could not load 8051 microcode\n", 3391 sc->sc_dev.dv_xname); 3392 rt2860_stop(ifp, 1); 3393 return error; 3394 } 3395 3396 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3397 rt2860_set_macaddr(sc, ic->ic_myaddr); 3398 3399 /* init Tx power for all Tx rates (from EEPROM) */ 3400 for (ridx = 0; ridx < 5; ridx++) { 3401 if (sc->txpow20mhz[ridx] == 0xffffffff) 3402 continue; 3403 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3404 } 3405 3406 for (ntries = 0; ntries < 100; ntries++) { 3407 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3408 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3409 break; 3410 DELAY(1000); 3411 } 3412 if (ntries == 100) { 3413 printf("%s: timeout waiting for DMA engine\n", 3414 sc->sc_dev.dv_xname); 3415 rt2860_stop(ifp, 1); 3416 return ETIMEDOUT; 3417 } 3418 tmp &= 0xff0; 3419 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3420 3421 /* reset Rx ring and all 6 Tx rings */ 3422 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3423 3424 /* PBF hardware reset */ 3425 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3426 RAL_BARRIER_WRITE(sc); 3427 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3428 3429 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3430 3431 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3432 RAL_BARRIER_WRITE(sc); 3433 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3434 3435 for (i = 0; i < nitems(rt2860_def_mac); i++) 3436 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3437 if (sc->mac_ver >= 0x3071) { 3438 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3439 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3440 4 << RT2860_DLY_PAPE_EN_SHIFT); 3441 } 3442 3443 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3444 sc->sc_flags |= RT2860_PCIE; 3445 /* PCIe has different clock cycle count than PCI */ 3446 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3447 tmp = (tmp & ~0xff) | 0x7d; 3448 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3449 } 3450 3451 /* wait while MAC is busy */ 3452 for (ntries = 0; ntries < 100; ntries++) { 3453 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3454 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3455 break; 3456 DELAY(1000); 3457 } 3458 if (ntries == 100) { 3459 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname); 3460 rt2860_stop(ifp, 1); 3461 return ETIMEDOUT; 3462 } 3463 3464 /* clear Host to MCU mailbox */ 3465 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3466 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3467 3468 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3469 DELAY(1000); 3470 3471 if ((error = rt2860_bbp_init(sc)) != 0) { 3472 rt2860_stop(ifp, 1); 3473 return error; 3474 } 3475 3476 /* clear RX WCID search table */ 3477 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3478 /* clear pairwise key table */ 3479 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3480 /* clear IV/EIV table */ 3481 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3482 /* clear WCID attribute table */ 3483 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3484 /* clear shared key table */ 3485 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3486 /* clear shared key mode */ 3487 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3488 3489 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3490 for (qid = 0; qid < 6; qid++) { 3491 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3492 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3493 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3494 } 3495 3496 /* init Rx ring */ 3497 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3498 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3499 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3500 3501 /* setup maximum buffer sizes */ 3502 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3503 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3504 3505 for (ntries = 0; ntries < 100; ntries++) { 3506 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3507 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3508 break; 3509 DELAY(1000); 3510 } 3511 if (ntries == 100) { 3512 printf("%s: timeout waiting for DMA engine\n", 3513 sc->sc_dev.dv_xname); 3514 rt2860_stop(ifp, 1); 3515 return ETIMEDOUT; 3516 } 3517 tmp &= 0xff0; 3518 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3519 3520 /* disable interrupts mitigation */ 3521 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3522 3523 /* write vendor-specific BBP values (from EEPROM) */ 3524 for (i = 0; i < 8; i++) { 3525 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3526 continue; 3527 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3528 } 3529 3530 /* select Main antenna for 1T1R devices */ 3531 if (sc->rf_rev == RT3070_RF_2020 || 3532 sc->rf_rev == RT3070_RF_3020 || 3533 sc->rf_rev == RT3070_RF_3320) 3534 rt3090_set_rx_antenna(sc, 0); 3535 3536 /* send LEDs operating mode to microcontroller */ 3537 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3538 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3539 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3540 3541 if (sc->mac_ver >= 0x3071) 3542 rt3090_rf_init(sc); 3543 3544 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3545 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3546 3547 if (sc->mac_ver >= 0x3071) 3548 rt3090_rf_wakeup(sc); 3549 3550 /* disable non-existing Rx chains */ 3551 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3552 bbp3 &= ~(1 << 3 | 1 << 4); 3553 if (sc->nrxchains == 2) 3554 bbp3 |= 1 << 3; 3555 else if (sc->nrxchains == 3) 3556 bbp3 |= 1 << 4; 3557 rt2860_mcu_bbp_write(sc, 3, bbp3); 3558 3559 /* disable non-existing Tx chains */ 3560 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3561 if (sc->ntxchains == 1) 3562 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3563 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3564 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3565 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3566 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3567 rt2860_mcu_bbp_write(sc, 1, bbp1); 3568 3569 if (sc->mac_ver >= 0x3071) 3570 rt3090_rf_setup(sc); 3571 3572 /* select default channel */ 3573 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3574 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3575 3576 /* reset RF from MCU */ 3577 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3578 3579 /* set RTS threshold */ 3580 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3581 tmp &= ~0xffff00; 3582 tmp |= ic->ic_rtsthreshold << 8; 3583 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3584 3585 /* setup initial protection mode */ 3586 sc->sc_ic_flags = ic->ic_flags; 3587 rt2860_updateprot(ic); 3588 3589 /* turn radio LED on */ 3590 rt2860_set_leds(sc, RT2860_LED_RADIO); 3591 3592 /* enable Tx/Rx DMA engine */ 3593 if ((error = rt2860_txrx_enable(sc)) != 0) { 3594 rt2860_stop(ifp, 1); 3595 return error; 3596 } 3597 3598 /* clear pending interrupts */ 3599 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3600 /* enable interrupts */ 3601 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3602 3603 if (sc->sc_flags & RT2860_ADVANCED_PS) 3604 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3605 3606 ifp->if_flags &= ~IFF_OACTIVE; 3607 ifp->if_flags |= IFF_RUNNING; 3608 3609 if (ic->ic_flags & IEEE80211_F_WEPON) { 3610 /* install WEP keys */ 3611 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3612 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3613 } 3614 3615 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3616 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3617 else 3618 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3619 3620 return 0; 3621 } 3622 3623 void 3624 rt2860_stop(struct ifnet *ifp, int disable) 3625 { 3626 struct rt2860_softc *sc = ifp->if_softc; 3627 struct ieee80211com *ic = &sc->sc_ic; 3628 uint32_t tmp; 3629 int qid; 3630 3631 if (ifp->if_flags & IFF_RUNNING) 3632 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3633 3634 sc->sc_tx_timer = 0; 3635 ifp->if_timer = 0; 3636 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3637 3638 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 3639 3640 /* disable interrupts */ 3641 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3642 3643 /* disable GP timer */ 3644 rt2860_set_gp_timer(sc, 0); 3645 3646 /* disable Rx */ 3647 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3648 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3649 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3650 3651 /* reset adapter */ 3652 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3653 RAL_BARRIER_WRITE(sc); 3654 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3655 3656 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3657 sc->qfullmsk = 0; 3658 for (qid = 0; qid < 6; qid++) 3659 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3660 rt2860_reset_rx_ring(sc, &sc->rxq); 3661 3662 /* for CardBus, power down the socket */ 3663 if (disable && sc->sc_disable != NULL) { 3664 if (sc->sc_flags & RT2860_ENABLED) { 3665 (*sc->sc_disable)(sc); 3666 sc->sc_flags &= ~RT2860_ENABLED; 3667 } 3668 } 3669 } 3670 3671 int 3672 rt2860_load_microcode(struct rt2860_softc *sc) 3673 { 3674 int ntries; 3675 3676 /* set "host program ram write selection" bit */ 3677 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 3678 /* write microcode image */ 3679 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 3680 /* kick microcontroller unit */ 3681 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 3682 RAL_BARRIER_WRITE(sc); 3683 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 3684 3685 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3686 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3687 3688 /* wait until microcontroller is ready */ 3689 RAL_BARRIER_READ_WRITE(sc); 3690 for (ntries = 0; ntries < 1000; ntries++) { 3691 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 3692 break; 3693 DELAY(1000); 3694 } 3695 if (ntries == 1000) { 3696 printf("%s: timeout waiting for MCU to initialize\n", 3697 sc->sc_dev.dv_xname); 3698 return ETIMEDOUT; 3699 } 3700 return 0; 3701 } 3702 3703 /* 3704 * This function is called periodically to adjust Tx power based on 3705 * temperature variation. 3706 */ 3707 void 3708 rt2860_calib(struct rt2860_softc *sc) 3709 { 3710 struct ieee80211com *ic = &sc->sc_ic; 3711 const uint8_t *tssi; 3712 uint8_t step, bbp49; 3713 int8_t ridx, d; 3714 3715 /* read current temperature */ 3716 bbp49 = rt2860_mcu_bbp_read(sc, 49); 3717 3718 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 3719 tssi = &sc->tssi_2ghz[4]; 3720 step = sc->step_2ghz; 3721 } else { 3722 tssi = &sc->tssi_5ghz[4]; 3723 step = sc->step_5ghz; 3724 } 3725 3726 if (bbp49 < tssi[0]) { /* lower than reference */ 3727 /* use higher Tx power than default */ 3728 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 3729 } else if (bbp49 > tssi[0]) { /* greater than reference */ 3730 /* use lower Tx power than default */ 3731 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 3732 } else { 3733 /* use default Tx power */ 3734 d = 0; 3735 } 3736 d *= step; 3737 3738 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 3739 3740 /* write adjusted Tx power values for each Tx rate */ 3741 for (ridx = 0; ridx < 5; ridx++) { 3742 if (sc->txpow20mhz[ridx] == 0xffffffff) 3743 continue; 3744 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 3745 b4inc(sc->txpow20mhz[ridx], d)); 3746 } 3747 } 3748 3749 void 3750 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 3751 { 3752 uint32_t tmp; 3753 3754 if (aux) { 3755 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3756 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 3757 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3758 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3759 } else { 3760 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3761 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 3762 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3763 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3764 } 3765 } 3766 3767 void 3768 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 3769 { 3770 struct ieee80211com *ic = &sc->sc_ic; 3771 u_int chan, group; 3772 3773 chan = ieee80211_chan2ieee(ic, c); 3774 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3775 return; 3776 3777 if (sc->mac_ver >= 0x3071) 3778 rt3090_set_chan(sc, chan); 3779 else 3780 rt2860_set_chan(sc, chan); 3781 3782 /* determine channel group */ 3783 if (chan <= 14) 3784 group = 0; 3785 else if (chan <= 64) 3786 group = 1; 3787 else if (chan <= 128) 3788 group = 2; 3789 else 3790 group = 3; 3791 3792 /* XXX necessary only when group has changed! */ 3793 rt2860_select_chan_group(sc, group); 3794 3795 DELAY(1000); 3796 } 3797 3798 #ifndef IEEE80211_STA_ONLY 3799 int 3800 rt2860_setup_beacon(struct rt2860_softc *sc) 3801 { 3802 struct ieee80211com *ic = &sc->sc_ic; 3803 struct rt2860_txwi txwi; 3804 struct mbuf *m; 3805 int ridx; 3806 3807 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL) 3808 return ENOBUFS; 3809 3810 memset(&txwi, 0, sizeof txwi); 3811 txwi.wcid = 0xff; 3812 txwi.len = htole16(m->m_pkthdr.len); 3813 /* send beacons at the lowest available rate */ 3814 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 3815 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 3816 txwi.phy = htole16(rt2860_rates[ridx].mcs); 3817 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 3818 txwi.phy |= htole16(RT2860_PHY_OFDM); 3819 txwi.txop = RT2860_TX_TXOP_HT; 3820 txwi.flags = RT2860_TX_TS; 3821 txwi.xflags = RT2860_TX_NSEQ; 3822 3823 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 3824 (uint8_t *)&txwi, sizeof txwi); 3825 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 3826 mtod(m, uint8_t *), m->m_pkthdr.len); 3827 3828 m_freem(m); 3829 3830 return 0; 3831 } 3832 #endif 3833 3834 void 3835 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 3836 { 3837 struct ieee80211com *ic = &sc->sc_ic; 3838 uint32_t tmp; 3839 3840 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 3841 3842 tmp &= ~0x1fffff; 3843 tmp |= ic->ic_bss->ni_intval * 16; 3844 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3845 if (ic->ic_opmode == IEEE80211_M_STA) { 3846 /* 3847 * Local TSF is always updated with remote TSF on beacon 3848 * reception. 3849 */ 3850 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3851 } 3852 #ifndef IEEE80211_STA_ONLY 3853 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3854 tmp |= RT2860_BCN_TX_EN; 3855 /* 3856 * Local TSF is updated with remote TSF on beacon reception 3857 * only if the remote TSF is greater than local TSF. 3858 */ 3859 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3860 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3861 tmp |= RT2860_BCN_TX_EN; 3862 /* SYNC with nobody */ 3863 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3864 } 3865 #endif 3866 3867 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 3868 } 3869