1 /* $OpenBSD: rt2661.c,v 1.65 2011/03/18 06:05:21 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 38 #include <machine/bus.h> 39 #include <machine/endian.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/if_ether.h> 55 #include <netinet/ip.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/ic/rt2661var.h> 62 #include <dev/ic/rt2661reg.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #ifdef RAL_DEBUG 69 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 70 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 71 int rt2661_debug = 1; 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 void rt2661_attachhook(void *); 78 int rt2661_alloc_tx_ring(struct rt2661_softc *, 79 struct rt2661_tx_ring *, int); 80 void rt2661_reset_tx_ring(struct rt2661_softc *, 81 struct rt2661_tx_ring *); 82 void rt2661_free_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *); 84 int rt2661_alloc_rx_ring(struct rt2661_softc *, 85 struct rt2661_rx_ring *, int); 86 void rt2661_reset_rx_ring(struct rt2661_softc *, 87 struct rt2661_rx_ring *); 88 void rt2661_free_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *); 90 struct ieee80211_node *rt2661_node_alloc(struct ieee80211com *); 91 int rt2661_media_change(struct ifnet *); 92 void rt2661_next_scan(void *); 93 void rt2661_iter_func(void *, struct ieee80211_node *); 94 void rt2661_updatestats(void *); 95 void rt2661_newassoc(struct ieee80211com *, struct ieee80211_node *, 96 int); 97 int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 98 int); 99 uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 100 void rt2661_tx_intr(struct rt2661_softc *); 101 void rt2661_tx_dma_intr(struct rt2661_softc *, 102 struct rt2661_tx_ring *); 103 void rt2661_rx_intr(struct rt2661_softc *); 104 #ifndef IEEE80211_STA_ONLY 105 void rt2661_mcu_beacon_expire(struct rt2661_softc *); 106 #endif 107 void rt2661_mcu_wakeup(struct rt2661_softc *); 108 void rt2661_mcu_cmd_intr(struct rt2661_softc *); 109 int rt2661_intr(void *); 110 #if NBPFILTER > 0 111 uint8_t rt2661_rxrate(const struct rt2661_rx_desc *); 112 #endif 113 int rt2661_ack_rate(struct ieee80211com *, int); 114 uint16_t rt2661_txtime(int, int, uint32_t); 115 uint8_t rt2661_plcp_signal(int); 116 void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 122 struct ieee80211_node *, int); 123 void rt2661_start(struct ifnet *); 124 void rt2661_watchdog(struct ifnet *); 125 int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 126 void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 127 uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 128 void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 129 int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 130 void rt2661_select_antenna(struct rt2661_softc *); 131 void rt2661_enable_mrr(struct rt2661_softc *); 132 void rt2661_set_txpreamble(struct rt2661_softc *); 133 void rt2661_set_basicrates(struct rt2661_softc *); 134 void rt2661_select_band(struct rt2661_softc *, 135 struct ieee80211_channel *); 136 void rt2661_set_chan(struct rt2661_softc *, 137 struct ieee80211_channel *); 138 void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 139 void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 140 void rt2661_update_promisc(struct rt2661_softc *); 141 void rt2661_updateslot(struct ieee80211com *); 142 void rt2661_set_slottime(struct rt2661_softc *); 143 const char *rt2661_get_rf(int); 144 void rt2661_read_eeprom(struct rt2661_softc *); 145 int rt2661_bbp_init(struct rt2661_softc *); 146 int rt2661_init(struct ifnet *); 147 void rt2661_stop(struct ifnet *, int); 148 int rt2661_load_microcode(struct rt2661_softc *); 149 void rt2661_rx_tune(struct rt2661_softc *); 150 #ifdef notyet 151 void rt2661_radar_start(struct rt2661_softc *); 152 int rt2661_radar_stop(struct rt2661_softc *); 153 #endif 154 #ifndef IEEE80211_STA_ONLY 155 int rt2661_prepare_beacon(struct rt2661_softc *); 156 #endif 157 void rt2661_enable_tsf_sync(struct rt2661_softc *); 158 int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 159 160 static const struct { 161 uint32_t reg; 162 uint32_t val; 163 } rt2661_def_mac[] = { 164 RT2661_DEF_MAC 165 }; 166 167 static const struct { 168 uint8_t reg; 169 uint8_t val; 170 } rt2661_def_bbp[] = { 171 RT2661_DEF_BBP 172 }; 173 174 static const struct rfprog { 175 uint8_t chan; 176 uint32_t r1, r2, r3, r4; 177 } rt2661_rf5225_1[] = { 178 RT2661_RF5225_1 179 }, rt2661_rf5225_2[] = { 180 RT2661_RF5225_2 181 }; 182 183 int 184 rt2661_attach(void *xsc, int id) 185 { 186 struct rt2661_softc *sc = xsc; 187 struct ieee80211com *ic = &sc->sc_ic; 188 uint32_t val; 189 int error, ac, ntries; 190 191 sc->sc_id = id; 192 193 sc->amrr.amrr_min_success_threshold = 1; 194 sc->amrr.amrr_max_success_threshold = 15; 195 timeout_set(&sc->amrr_to, rt2661_updatestats, sc); 196 timeout_set(&sc->scan_to, rt2661_next_scan, sc); 197 198 /* wait for NIC to initialize */ 199 for (ntries = 0; ntries < 1000; ntries++) { 200 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 201 break; 202 DELAY(1000); 203 } 204 if (ntries == 1000) { 205 printf("%s: timeout waiting for NIC to initialize\n", 206 sc->sc_dev.dv_xname); 207 return EIO; 208 } 209 210 /* retrieve RF rev. no and various other things from EEPROM */ 211 rt2661_read_eeprom(sc); 212 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 213 214 printf("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val, 215 rt2661_get_rf(sc->rf_rev)); 216 217 /* 218 * Allocate Tx and Rx rings. 219 */ 220 for (ac = 0; ac < 4; ac++) { 221 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 222 RT2661_TX_RING_COUNT); 223 if (error != 0) { 224 printf("%s: could not allocate Tx ring %d\n", 225 sc->sc_dev.dv_xname, ac); 226 goto fail1; 227 } 228 } 229 230 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 231 if (error != 0) { 232 printf("%s: could not allocate Mgt ring\n", 233 sc->sc_dev.dv_xname); 234 goto fail1; 235 } 236 237 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 238 if (error != 0) { 239 printf("%s: could not allocate Rx ring\n", 240 sc->sc_dev.dv_xname); 241 goto fail2; 242 } 243 244 if (rootvp == NULL) 245 mountroothook_establish(rt2661_attachhook, sc); 246 else 247 rt2661_attachhook(sc); 248 249 return 0; 250 251 fail2: rt2661_free_tx_ring(sc, &sc->mgtq); 252 fail1: while (--ac >= 0) 253 rt2661_free_tx_ring(sc, &sc->txq[ac]); 254 return ENXIO; 255 } 256 257 void 258 rt2661_attachhook(void *xsc) 259 { 260 struct rt2661_softc *sc = xsc; 261 struct ieee80211com *ic = &sc->sc_ic; 262 struct ifnet *ifp = &ic->ic_if; 263 const char *name = NULL; /* make lint happy */ 264 int i, error; 265 266 switch (sc->sc_id) { 267 case PCI_PRODUCT_RALINK_RT2561: 268 name = "ral-rt2561"; 269 break; 270 case PCI_PRODUCT_RALINK_RT2561S: 271 name = "ral-rt2561s"; 272 break; 273 case PCI_PRODUCT_RALINK_RT2661: 274 name = "ral-rt2661"; 275 break; 276 } 277 if ((error = loadfirmware(name, &sc->ucode, &sc->ucsize)) != 0) { 278 printf("%s: error %d, could not read firmware %s\n", 279 sc->sc_dev.dv_xname, error, name); 280 return; 281 } 282 283 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 284 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 285 ic->ic_state = IEEE80211_S_INIT; 286 287 /* set device capabilities */ 288 ic->ic_caps = 289 IEEE80211_C_MONITOR | /* monitor mode supported */ 290 #ifndef IEEE80211_STA_ONLY 291 IEEE80211_C_IBSS | /* IBSS mode supported */ 292 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 293 #endif 294 IEEE80211_C_TXPMGT | /* tx power management */ 295 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 296 IEEE80211_C_SHSLOT | /* short slot time supported */ 297 IEEE80211_C_WEP | /* s/w WEP */ 298 IEEE80211_C_RSN; /* WPA/RSN */ 299 300 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 301 /* set supported .11a rates */ 302 ic->ic_sup_rates[IEEE80211_MODE_11A] = 303 ieee80211_std_rateset_11a; 304 305 /* set supported .11a channels */ 306 for (i = 36; i <= 64; i += 4) { 307 ic->ic_channels[i].ic_freq = 308 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 309 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 310 } 311 for (i = 100; i <= 140; i += 4) { 312 ic->ic_channels[i].ic_freq = 313 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 314 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 315 } 316 for (i = 149; i <= 165; i += 4) { 317 ic->ic_channels[i].ic_freq = 318 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 319 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 320 } 321 } 322 323 /* set supported .11b and .11g rates */ 324 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 325 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 326 327 /* set supported .11b and .11g channels (1 through 14) */ 328 for (i = 1; i <= 14; i++) { 329 ic->ic_channels[i].ic_freq = 330 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 331 ic->ic_channels[i].ic_flags = 332 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 333 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 334 } 335 336 ifp->if_softc = sc; 337 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 338 ifp->if_ioctl = rt2661_ioctl; 339 ifp->if_start = rt2661_start; 340 ifp->if_watchdog = rt2661_watchdog; 341 IFQ_SET_READY(&ifp->if_snd); 342 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 343 344 if_attach(ifp); 345 ieee80211_ifattach(ifp); 346 ic->ic_node_alloc = rt2661_node_alloc; 347 ic->ic_newassoc = rt2661_newassoc; 348 ic->ic_updateslot = rt2661_updateslot; 349 350 /* override state transition machine */ 351 sc->sc_newstate = ic->ic_newstate; 352 ic->ic_newstate = rt2661_newstate; 353 ieee80211_media_init(ifp, rt2661_media_change, ieee80211_media_status); 354 355 #if NBPFILTER > 0 356 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 357 sizeof (struct ieee80211_frame) + 64); 358 359 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 360 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 361 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 362 363 sc->sc_txtap_len = sizeof sc->sc_txtapu; 364 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 365 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 366 #endif 367 } 368 369 int 370 rt2661_detach(void *xsc) 371 { 372 struct rt2661_softc *sc = xsc; 373 struct ifnet *ifp = &sc->sc_ic.ic_if; 374 int ac; 375 376 timeout_del(&sc->scan_to); 377 timeout_del(&sc->amrr_to); 378 379 ieee80211_ifdetach(ifp); /* free all nodes */ 380 if_detach(ifp); 381 382 for (ac = 0; ac < 4; ac++) 383 rt2661_free_tx_ring(sc, &sc->txq[ac]); 384 rt2661_free_tx_ring(sc, &sc->mgtq); 385 rt2661_free_rx_ring(sc, &sc->rxq); 386 387 if (sc->ucode != NULL) 388 free(sc->ucode, M_DEVBUF); 389 390 return 0; 391 } 392 393 void 394 rt2661_suspend(void *xsc) 395 { 396 struct rt2661_softc *sc = xsc; 397 struct ifnet *ifp = &sc->sc_ic.ic_if; 398 399 if (ifp->if_flags & IFF_RUNNING) { 400 rt2661_stop(ifp, 1); 401 sc->sc_flags &= ~RT2661_FWLOADED; 402 } 403 } 404 405 void 406 rt2661_resume(void *xsc) 407 { 408 struct rt2661_softc *sc = xsc; 409 struct ifnet *ifp = &sc->sc_ic.ic_if; 410 411 if (ifp->if_flags & IFF_UP) 412 rt2661_init(ifp); 413 } 414 415 int 416 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 417 int count) 418 { 419 int i, nsegs, error; 420 421 ring->count = count; 422 ring->queued = 0; 423 ring->cur = ring->next = ring->stat = 0; 424 425 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 426 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 427 if (error != 0) { 428 printf("%s: could not create desc DMA map\n", 429 sc->sc_dev.dv_xname); 430 goto fail; 431 } 432 433 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 434 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 435 if (error != 0) { 436 printf("%s: could not allocate DMA memory\n", 437 sc->sc_dev.dv_xname); 438 goto fail; 439 } 440 441 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 442 count * RT2661_TX_DESC_SIZE, (caddr_t *)&ring->desc, 443 BUS_DMA_NOWAIT); 444 if (error != 0) { 445 printf("%s: can't map desc DMA memory\n", 446 sc->sc_dev.dv_xname); 447 goto fail; 448 } 449 450 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 451 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 452 if (error != 0) { 453 printf("%s: could not load desc DMA map\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 ring->physaddr = ring->map->dm_segs->ds_addr; 459 460 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 461 M_NOWAIT | M_ZERO); 462 if (ring->data == NULL) { 463 printf("%s: could not allocate soft data\n", 464 sc->sc_dev.dv_xname); 465 error = ENOMEM; 466 goto fail; 467 } 468 469 for (i = 0; i < count; i++) { 470 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 471 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 472 &ring->data[i].map); 473 if (error != 0) { 474 printf("%s: could not create DMA map\n", 475 sc->sc_dev.dv_xname); 476 goto fail; 477 } 478 } 479 480 return 0; 481 482 fail: rt2661_free_tx_ring(sc, ring); 483 return error; 484 } 485 486 void 487 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 488 { 489 int i; 490 491 for (i = 0; i < ring->count; i++) { 492 struct rt2661_tx_desc *desc = &ring->desc[i]; 493 struct rt2661_tx_data *data = &ring->data[i]; 494 495 if (data->m != NULL) { 496 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 497 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 498 bus_dmamap_unload(sc->sc_dmat, data->map); 499 m_freem(data->m); 500 data->m = NULL; 501 } 502 503 /* 504 * The node has already been freed at that point so don't call 505 * ieee80211_release_node() here. 506 */ 507 data->ni = NULL; 508 509 desc->flags = 0; 510 } 511 512 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 513 BUS_DMASYNC_PREWRITE); 514 515 ring->queued = 0; 516 ring->cur = ring->next = ring->stat = 0; 517 } 518 519 void 520 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 521 { 522 int i; 523 524 if (ring->desc != NULL) { 525 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 526 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 527 bus_dmamap_unload(sc->sc_dmat, ring->map); 528 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->desc, 529 ring->count * RT2661_TX_DESC_SIZE); 530 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 531 } 532 533 if (ring->data != NULL) { 534 for (i = 0; i < ring->count; i++) { 535 struct rt2661_tx_data *data = &ring->data[i]; 536 537 if (data->m != NULL) { 538 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 539 data->map->dm_mapsize, 540 BUS_DMASYNC_POSTWRITE); 541 bus_dmamap_unload(sc->sc_dmat, data->map); 542 m_freem(data->m); 543 } 544 /* 545 * The node has already been freed at that point so 546 * don't call ieee80211_release_node() here. 547 */ 548 data->ni = NULL; 549 550 if (data->map != NULL) 551 bus_dmamap_destroy(sc->sc_dmat, data->map); 552 } 553 free(ring->data, M_DEVBUF); 554 } 555 } 556 557 int 558 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 559 int count) 560 { 561 int i, nsegs, error; 562 563 ring->count = count; 564 ring->cur = ring->next = 0; 565 566 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 567 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 568 if (error != 0) { 569 printf("%s: could not create desc DMA map\n", 570 sc->sc_dev.dv_xname); 571 goto fail; 572 } 573 574 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 575 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 576 if (error != 0) { 577 printf("%s: could not allocate DMA memory\n", 578 sc->sc_dev.dv_xname); 579 goto fail; 580 } 581 582 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 583 count * RT2661_RX_DESC_SIZE, (caddr_t *)&ring->desc, 584 BUS_DMA_NOWAIT); 585 if (error != 0) { 586 printf("%s: can't map desc DMA memory\n", 587 sc->sc_dev.dv_xname); 588 goto fail; 589 } 590 591 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 592 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 593 if (error != 0) { 594 printf("%s: could not load desc DMA map\n", 595 sc->sc_dev.dv_xname); 596 goto fail; 597 } 598 599 ring->physaddr = ring->map->dm_segs->ds_addr; 600 601 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 602 M_NOWAIT | M_ZERO); 603 if (ring->data == NULL) { 604 printf("%s: could not allocate soft data\n", 605 sc->sc_dev.dv_xname); 606 error = ENOMEM; 607 goto fail; 608 } 609 610 /* 611 * Pre-allocate Rx buffers and populate Rx ring. 612 */ 613 for (i = 0; i < count; i++) { 614 struct rt2661_rx_desc *desc = &sc->rxq.desc[i]; 615 struct rt2661_rx_data *data = &sc->rxq.data[i]; 616 617 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 618 0, BUS_DMA_NOWAIT, &data->map); 619 if (error != 0) { 620 printf("%s: could not create DMA map\n", 621 sc->sc_dev.dv_xname); 622 goto fail; 623 } 624 625 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 626 if (data->m == NULL) { 627 printf("%s: could not allocate rx mbuf\n", 628 sc->sc_dev.dv_xname); 629 error = ENOMEM; 630 goto fail; 631 } 632 MCLGET(data->m, M_DONTWAIT); 633 if (!(data->m->m_flags & M_EXT)) { 634 printf("%s: could not allocate rx mbuf cluster\n", 635 sc->sc_dev.dv_xname); 636 error = ENOMEM; 637 goto fail; 638 } 639 640 error = bus_dmamap_load(sc->sc_dmat, data->map, 641 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 642 if (error != 0) { 643 printf("%s: could not load rx buf DMA map", 644 sc->sc_dev.dv_xname); 645 goto fail; 646 } 647 648 desc->flags = htole32(RT2661_RX_BUSY); 649 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 653 BUS_DMASYNC_PREWRITE); 654 655 return 0; 656 657 fail: rt2661_free_rx_ring(sc, ring); 658 return error; 659 } 660 661 void 662 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 663 { 664 int i; 665 666 for (i = 0; i < ring->count; i++) 667 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 668 669 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 670 BUS_DMASYNC_PREWRITE); 671 672 ring->cur = ring->next = 0; 673 } 674 675 void 676 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 677 { 678 int i; 679 680 if (ring->desc != NULL) { 681 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 682 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 683 bus_dmamap_unload(sc->sc_dmat, ring->map); 684 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->desc, 685 ring->count * RT2661_RX_DESC_SIZE); 686 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 687 } 688 689 if (ring->data != NULL) { 690 for (i = 0; i < ring->count; i++) { 691 struct rt2661_rx_data *data = &ring->data[i]; 692 693 if (data->m != NULL) { 694 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 695 data->map->dm_mapsize, 696 BUS_DMASYNC_POSTREAD); 697 bus_dmamap_unload(sc->sc_dmat, data->map); 698 m_freem(data->m); 699 } 700 701 if (data->map != NULL) 702 bus_dmamap_destroy(sc->sc_dmat, data->map); 703 } 704 free(ring->data, M_DEVBUF); 705 } 706 } 707 708 struct ieee80211_node * 709 rt2661_node_alloc(struct ieee80211com *ic) 710 { 711 return malloc(sizeof (struct rt2661_node), M_DEVBUF, 712 M_NOWAIT | M_ZERO); 713 } 714 715 int 716 rt2661_media_change(struct ifnet *ifp) 717 { 718 int error; 719 720 error = ieee80211_media_change(ifp); 721 if (error != ENETRESET) 722 return error; 723 724 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 725 rt2661_init(ifp); 726 727 return 0; 728 } 729 730 /* 731 * This function is called periodically (every 200ms) during scanning to 732 * switch from one channel to another. 733 */ 734 void 735 rt2661_next_scan(void *arg) 736 { 737 struct rt2661_softc *sc = arg; 738 struct ieee80211com *ic = &sc->sc_ic; 739 struct ifnet *ifp = &ic->ic_if; 740 int s; 741 742 s = splnet(); 743 if (ic->ic_state == IEEE80211_S_SCAN) 744 ieee80211_next_scan(ifp); 745 splx(s); 746 } 747 748 /* 749 * This function is called for each neighbor node. 750 */ 751 void 752 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 753 { 754 struct rt2661_softc *sc = arg; 755 struct rt2661_node *rn = (struct rt2661_node *)ni; 756 757 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 758 } 759 760 /* 761 * This function is called periodically (every 500ms) in RUN state to update 762 * various settings like rate control statistics or Rx sensitivity. 763 */ 764 void 765 rt2661_updatestats(void *arg) 766 { 767 struct rt2661_softc *sc = arg; 768 struct ieee80211com *ic = &sc->sc_ic; 769 int s; 770 771 s = splnet(); 772 if (ic->ic_opmode == IEEE80211_M_STA) 773 rt2661_iter_func(sc, ic->ic_bss); 774 else 775 ieee80211_iterate_nodes(ic, rt2661_iter_func, arg); 776 777 /* update rx sensitivity every 1 sec */ 778 if (++sc->ncalls & 1) 779 rt2661_rx_tune(sc); 780 splx(s); 781 782 timeout_add_msec(&sc->amrr_to, 500); 783 } 784 785 void 786 rt2661_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 787 { 788 struct rt2661_softc *sc = ic->ic_softc; 789 int i; 790 791 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 792 793 /* set rate to some reasonable initial value */ 794 for (i = ni->ni_rates.rs_nrates - 1; 795 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 796 i--); 797 ni->ni_txrate = i; 798 } 799 800 int 801 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 802 { 803 struct rt2661_softc *sc = ic->ic_if.if_softc; 804 enum ieee80211_state ostate; 805 struct ieee80211_node *ni; 806 uint32_t tmp; 807 808 ostate = ic->ic_state; 809 timeout_del(&sc->scan_to); 810 timeout_del(&sc->amrr_to); 811 812 switch (nstate) { 813 case IEEE80211_S_INIT: 814 if (ostate == IEEE80211_S_RUN) { 815 /* abort TSF synchronization */ 816 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 817 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 818 } 819 break; 820 821 case IEEE80211_S_SCAN: 822 rt2661_set_chan(sc, ic->ic_bss->ni_chan); 823 timeout_add_msec(&sc->scan_to, 200); 824 break; 825 826 case IEEE80211_S_AUTH: 827 case IEEE80211_S_ASSOC: 828 rt2661_set_chan(sc, ic->ic_bss->ni_chan); 829 break; 830 831 case IEEE80211_S_RUN: 832 rt2661_set_chan(sc, ic->ic_bss->ni_chan); 833 834 ni = ic->ic_bss; 835 836 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 837 rt2661_set_slottime(sc); 838 rt2661_enable_mrr(sc); 839 rt2661_set_txpreamble(sc); 840 rt2661_set_basicrates(sc); 841 rt2661_set_bssid(sc, ni->ni_bssid); 842 } 843 844 #ifndef IEEE80211_STA_ONLY 845 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 846 ic->ic_opmode == IEEE80211_M_IBSS) 847 rt2661_prepare_beacon(sc); 848 #endif 849 850 if (ic->ic_opmode == IEEE80211_M_STA) { 851 /* fake a join to init the tx rate */ 852 rt2661_newassoc(ic, ni, 1); 853 } 854 855 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 856 sc->ncalls = 0; 857 sc->avg_rssi = -95; /* reset EMA */ 858 timeout_add_msec(&sc->amrr_to, 500); 859 rt2661_enable_tsf_sync(sc); 860 } 861 break; 862 } 863 864 return sc->sc_newstate(ic, nstate, arg); 865 } 866 867 /* 868 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 869 * 93C66). 870 */ 871 uint16_t 872 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 873 { 874 uint32_t tmp; 875 uint16_t val; 876 int n; 877 878 /* clock C once before the first command */ 879 RT2661_EEPROM_CTL(sc, 0); 880 881 RT2661_EEPROM_CTL(sc, RT2661_S); 882 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 883 RT2661_EEPROM_CTL(sc, RT2661_S); 884 885 /* write start bit (1) */ 886 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 887 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 888 889 /* write READ opcode (10) */ 890 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 891 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 892 RT2661_EEPROM_CTL(sc, RT2661_S); 893 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 894 895 /* write address (A5-A0 or A7-A0) */ 896 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 897 for (; n >= 0; n--) { 898 RT2661_EEPROM_CTL(sc, RT2661_S | 899 (((addr >> n) & 1) << RT2661_SHIFT_D)); 900 RT2661_EEPROM_CTL(sc, RT2661_S | 901 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 902 } 903 904 RT2661_EEPROM_CTL(sc, RT2661_S); 905 906 /* read data Q15-Q0 */ 907 val = 0; 908 for (n = 15; n >= 0; n--) { 909 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 910 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 911 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 912 RT2661_EEPROM_CTL(sc, RT2661_S); 913 } 914 915 RT2661_EEPROM_CTL(sc, 0); 916 917 /* clear Chip Select and clock C */ 918 RT2661_EEPROM_CTL(sc, RT2661_S); 919 RT2661_EEPROM_CTL(sc, 0); 920 RT2661_EEPROM_CTL(sc, RT2661_C); 921 922 return val; 923 } 924 925 void 926 rt2661_tx_intr(struct rt2661_softc *sc) 927 { 928 struct ieee80211com *ic = &sc->sc_ic; 929 struct ifnet *ifp = &ic->ic_if; 930 struct rt2661_tx_ring *txq; 931 struct rt2661_tx_data *data; 932 struct rt2661_node *rn; 933 int qid, retrycnt; 934 935 for (;;) { 936 const uint32_t val = RAL_READ(sc, RT2661_STA_CSR4); 937 if (!(val & RT2661_TX_STAT_VALID)) 938 break; 939 940 /* retrieve the queue in which this frame was sent */ 941 qid = RT2661_TX_QID(val); 942 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 943 944 /* retrieve rate control algorithm context */ 945 data = &txq->data[txq->stat]; 946 rn = (struct rt2661_node *)data->ni; 947 948 /* if no frame has been sent, ignore */ 949 if (rn == NULL) 950 continue; 951 952 switch (RT2661_TX_RESULT(val)) { 953 case RT2661_TX_SUCCESS: 954 retrycnt = RT2661_TX_RETRYCNT(val); 955 956 DPRINTFN(10, ("data frame sent successfully after " 957 "%d retries\n", retrycnt)); 958 rn->amn.amn_txcnt++; 959 if (retrycnt > 0) 960 rn->amn.amn_retrycnt++; 961 ifp->if_opackets++; 962 break; 963 964 case RT2661_TX_RETRY_FAIL: 965 DPRINTFN(9, ("sending data frame failed (too much " 966 "retries)\n")); 967 rn->amn.amn_txcnt++; 968 rn->amn.amn_retrycnt++; 969 ifp->if_oerrors++; 970 break; 971 972 default: 973 /* other failure */ 974 printf("%s: sending data frame failed 0x%08x\n", 975 sc->sc_dev.dv_xname, val); 976 ifp->if_oerrors++; 977 } 978 979 ieee80211_release_node(ic, data->ni); 980 data->ni = NULL; 981 982 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 983 984 txq->queued--; 985 if (++txq->stat >= txq->count) /* faster than % count */ 986 txq->stat = 0; 987 } 988 989 sc->sc_tx_timer = 0; 990 ifp->if_flags &= ~IFF_OACTIVE; 991 rt2661_start(ifp); 992 } 993 994 void 995 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 996 { 997 for (;;) { 998 struct rt2661_tx_desc *desc = &txq->desc[txq->next]; 999 struct rt2661_tx_data *data = &txq->data[txq->next]; 1000 1001 bus_dmamap_sync(sc->sc_dmat, txq->map, 1002 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1003 BUS_DMASYNC_POSTREAD); 1004 1005 if ((letoh32(desc->flags) & RT2661_TX_BUSY) || 1006 !(letoh32(desc->flags) & RT2661_TX_VALID)) 1007 break; 1008 1009 /* descriptor is no longer valid */ 1010 desc->flags &= ~htole32(RT2661_TX_VALID); 1011 1012 bus_dmamap_sync(sc->sc_dmat, txq->map, 1013 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1014 BUS_DMASYNC_PREWRITE); 1015 1016 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1017 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1018 bus_dmamap_unload(sc->sc_dmat, data->map); 1019 m_freem(data->m); 1020 data->m = NULL; 1021 /* node reference is released in rt2661_tx_intr() */ 1022 1023 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1024 1025 if (++txq->next >= txq->count) /* faster than % count */ 1026 txq->next = 0; 1027 } 1028 } 1029 1030 void 1031 rt2661_rx_intr(struct rt2661_softc *sc) 1032 { 1033 struct ieee80211com *ic = &sc->sc_ic; 1034 struct ifnet *ifp = &ic->ic_if; 1035 struct ieee80211_frame *wh; 1036 struct ieee80211_rxinfo rxi; 1037 struct ieee80211_node *ni; 1038 struct mbuf *mnew, *m; 1039 int error, rssi; 1040 1041 for (;;) { 1042 struct rt2661_rx_desc *desc = &sc->rxq.desc[sc->rxq.cur]; 1043 struct rt2661_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1044 1045 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1046 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1047 BUS_DMASYNC_POSTREAD); 1048 1049 if (letoh32(desc->flags) & RT2661_RX_BUSY) 1050 break; 1051 1052 if ((letoh32(desc->flags) & RT2661_RX_PHY_ERROR) || 1053 (letoh32(desc->flags) & RT2661_RX_CRC_ERROR)) { 1054 /* 1055 * This should not happen since we did not request 1056 * to receive those frames when we filled TXRX_CSR0. 1057 */ 1058 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1059 letoh32(desc->flags))); 1060 ifp->if_ierrors++; 1061 goto skip; 1062 } 1063 1064 if ((letoh32(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1065 ifp->if_ierrors++; 1066 goto skip; 1067 } 1068 1069 /* 1070 * Try to allocate a new mbuf for this ring element and load it 1071 * before processing the current mbuf. If the ring element 1072 * cannot be loaded, drop the received packet and reuse the old 1073 * mbuf. In the unlikely case that the old mbuf can't be 1074 * reloaded either, explicitly panic. 1075 */ 1076 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1077 if (mnew == NULL) { 1078 ifp->if_ierrors++; 1079 goto skip; 1080 } 1081 MCLGET(mnew, M_DONTWAIT); 1082 if (!(mnew->m_flags & M_EXT)) { 1083 m_freem(mnew); 1084 ifp->if_ierrors++; 1085 goto skip; 1086 } 1087 1088 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1089 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1090 bus_dmamap_unload(sc->sc_dmat, data->map); 1091 1092 error = bus_dmamap_load(sc->sc_dmat, data->map, 1093 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1094 if (error != 0) { 1095 m_freem(mnew); 1096 1097 /* try to reload the old mbuf */ 1098 error = bus_dmamap_load(sc->sc_dmat, data->map, 1099 mtod(data->m, void *), MCLBYTES, NULL, 1100 BUS_DMA_NOWAIT); 1101 if (error != 0) { 1102 /* very unlikely that it will fail... */ 1103 panic("%s: could not load old rx mbuf", 1104 sc->sc_dev.dv_xname); 1105 } 1106 /* physical address may have changed */ 1107 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1108 ifp->if_ierrors++; 1109 goto skip; 1110 } 1111 1112 /* 1113 * New mbuf successfully loaded, update Rx ring and continue 1114 * processing. 1115 */ 1116 m = data->m; 1117 data->m = mnew; 1118 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1119 1120 /* finalize mbuf */ 1121 m->m_pkthdr.rcvif = ifp; 1122 m->m_pkthdr.len = m->m_len = 1123 (letoh32(desc->flags) >> 16) & 0xfff; 1124 1125 #if NBPFILTER > 0 1126 if (sc->sc_drvbpf != NULL) { 1127 struct mbuf mb; 1128 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1129 uint32_t tsf_lo, tsf_hi; 1130 1131 /* get timestamp (low and high 32 bits) */ 1132 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1133 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1134 1135 tap->wr_tsf = 1136 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1137 tap->wr_flags = 0; 1138 tap->wr_rate = rt2661_rxrate(desc); 1139 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1140 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1141 tap->wr_antsignal = desc->rssi; 1142 1143 mb.m_data = (caddr_t)tap; 1144 mb.m_len = sc->sc_rxtap_len; 1145 mb.m_next = m; 1146 mb.m_nextpkt = NULL; 1147 mb.m_type = 0; 1148 mb.m_flags = 0; 1149 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1150 } 1151 #endif 1152 1153 wh = mtod(m, struct ieee80211_frame *); 1154 ni = ieee80211_find_rxnode(ic, wh); 1155 1156 /* send the frame to the 802.11 layer */ 1157 rxi.rxi_flags = 0; 1158 rxi.rxi_rssi = desc->rssi; 1159 rxi.rxi_tstamp = 0; /* unused */ 1160 ieee80211_input(ifp, m, ni, &rxi); 1161 1162 /*- 1163 * Keep track of the average RSSI using an Exponential Moving 1164 * Average (EMA) of 8 Wilder's days: 1165 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1166 */ 1167 rssi = rt2661_get_rssi(sc, desc->rssi); 1168 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1169 1170 /* node is no longer needed */ 1171 ieee80211_release_node(ic, ni); 1172 1173 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1174 1175 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1176 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1177 BUS_DMASYNC_PREWRITE); 1178 1179 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1180 1181 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1182 } 1183 } 1184 1185 #ifndef IEEE80211_STA_ONLY 1186 /* 1187 * This function is called in HostAP or IBSS modes when it's time to send a 1188 * new beacon (every ni_intval milliseconds). 1189 */ 1190 void 1191 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1192 { 1193 struct ieee80211com *ic = &sc->sc_ic; 1194 1195 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1196 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1197 sc->sc_flags |= RT2661_SET_SLOTTIME; 1198 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1199 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1200 rt2661_set_slottime(sc); 1201 } 1202 1203 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1204 /* update ERP Information Element */ 1205 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1206 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1207 } 1208 1209 DPRINTFN(15, ("beacon expired\n")); 1210 } 1211 #endif 1212 1213 void 1214 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1215 { 1216 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1217 1218 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1219 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1220 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1221 1222 /* send wakeup command to MCU */ 1223 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1224 } 1225 1226 void 1227 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1228 { 1229 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1230 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1231 } 1232 1233 int 1234 rt2661_intr(void *arg) 1235 { 1236 struct rt2661_softc *sc = arg; 1237 struct ifnet *ifp = &sc->sc_ic.ic_if; 1238 uint32_t r1, r2; 1239 1240 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1241 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1242 if (__predict_false(r1 == 0xffffffff && r2 == 0xffffffff)) 1243 return 0; /* device likely went away */ 1244 if (r1 == 0 && r2 == 0) 1245 return 0; /* not for us */ 1246 1247 /* disable MAC and MCU interrupts */ 1248 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1249 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1250 1251 /* acknowledge interrupts */ 1252 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1253 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1254 1255 /* don't re-enable interrupts if we're shutting down */ 1256 if (!(ifp->if_flags & IFF_RUNNING)) 1257 return 0; 1258 1259 if (r1 & RT2661_MGT_DONE) 1260 rt2661_tx_dma_intr(sc, &sc->mgtq); 1261 1262 if (r1 & RT2661_RX_DONE) 1263 rt2661_rx_intr(sc); 1264 1265 if (r1 & RT2661_TX0_DMA_DONE) 1266 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1267 1268 if (r1 & RT2661_TX1_DMA_DONE) 1269 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1270 1271 if (r1 & RT2661_TX2_DMA_DONE) 1272 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1273 1274 if (r1 & RT2661_TX3_DMA_DONE) 1275 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1276 1277 if (r1 & RT2661_TX_DONE) 1278 rt2661_tx_intr(sc); 1279 1280 if (r2 & RT2661_MCU_CMD_DONE) 1281 rt2661_mcu_cmd_intr(sc); 1282 1283 #ifndef IEEE80211_STA_ONLY 1284 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1285 rt2661_mcu_beacon_expire(sc); 1286 #endif 1287 1288 if (r2 & RT2661_MCU_WAKEUP) 1289 rt2661_mcu_wakeup(sc); 1290 1291 /* re-enable MAC and MCU interrupts */ 1292 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1293 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1294 1295 return 1; 1296 } 1297 1298 /* quickly determine if a given rate is CCK or OFDM */ 1299 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1300 1301 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1302 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1303 1304 /* 1305 * This function is only used by the Rx radiotap code. It returns the rate at 1306 * which a given frame was received. 1307 */ 1308 #if NBPFILTER > 0 1309 uint8_t 1310 rt2661_rxrate(const struct rt2661_rx_desc *desc) 1311 { 1312 if (letoh32(desc->flags) & RT2661_RX_OFDM) { 1313 /* reverse function of rt2661_plcp_signal */ 1314 switch (desc->rate & 0xf) { 1315 case 0xb: return 12; 1316 case 0xf: return 18; 1317 case 0xa: return 24; 1318 case 0xe: return 36; 1319 case 0x9: return 48; 1320 case 0xd: return 72; 1321 case 0x8: return 96; 1322 case 0xc: return 108; 1323 } 1324 } else { 1325 if (desc->rate == 10) 1326 return 2; 1327 if (desc->rate == 20) 1328 return 4; 1329 if (desc->rate == 55) 1330 return 11; 1331 if (desc->rate == 110) 1332 return 22; 1333 } 1334 return 2; /* should not get there */ 1335 } 1336 #endif 1337 1338 /* 1339 * Return the expected ack rate for a frame transmitted at rate `rate'. 1340 */ 1341 int 1342 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1343 { 1344 switch (rate) { 1345 /* CCK rates */ 1346 case 2: 1347 return 2; 1348 case 4: 1349 case 11: 1350 case 22: 1351 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1352 1353 /* OFDM rates */ 1354 case 12: 1355 case 18: 1356 return 12; 1357 case 24: 1358 case 36: 1359 return 24; 1360 case 48: 1361 case 72: 1362 case 96: 1363 case 108: 1364 return 48; 1365 } 1366 1367 /* default to 1Mbps */ 1368 return 2; 1369 } 1370 1371 /* 1372 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1373 * The function automatically determines the operating mode depending on the 1374 * given rate. `flags' indicates whether short preamble is in use or not. 1375 */ 1376 uint16_t 1377 rt2661_txtime(int len, int rate, uint32_t flags) 1378 { 1379 uint16_t txtime; 1380 1381 if (RAL_RATE_IS_OFDM(rate)) { 1382 /* IEEE Std 802.11g-2003, pp. 44 */ 1383 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1384 txtime = 16 + 4 + 4 * txtime + 6; 1385 } else { 1386 /* IEEE Std 802.11b-1999, pp. 28 */ 1387 txtime = (16 * len + rate - 1) / rate; 1388 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1389 txtime += 72 + 24; 1390 else 1391 txtime += 144 + 48; 1392 } 1393 return txtime; 1394 } 1395 1396 uint8_t 1397 rt2661_plcp_signal(int rate) 1398 { 1399 switch (rate) { 1400 /* CCK rates (returned values are device-dependent) */ 1401 case 2: return 0x0; 1402 case 4: return 0x1; 1403 case 11: return 0x2; 1404 case 22: return 0x3; 1405 1406 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1407 case 12: return 0xb; 1408 case 18: return 0xf; 1409 case 24: return 0xa; 1410 case 36: return 0xe; 1411 case 48: return 0x9; 1412 case 72: return 0xd; 1413 case 96: return 0x8; 1414 case 108: return 0xc; 1415 1416 /* unsupported rates (should not get there) */ 1417 default: return 0xff; 1418 } 1419 } 1420 1421 void 1422 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1423 uint32_t flags, uint16_t xflags, int len, int rate, 1424 const bus_dma_segment_t *segs, int nsegs, int ac) 1425 { 1426 struct ieee80211com *ic = &sc->sc_ic; 1427 uint16_t plcp_length; 1428 int i, remainder; 1429 1430 desc->flags = htole32(flags); 1431 desc->flags |= htole32(len << 16); 1432 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1433 1434 desc->xflags = htole16(xflags); 1435 desc->xflags |= htole16(nsegs << 13); 1436 1437 desc->wme = htole16( 1438 RT2661_QID(ac) | 1439 RT2661_AIFSN(2) | 1440 RT2661_LOGCWMIN(4) | 1441 RT2661_LOGCWMAX(10)); 1442 1443 /* 1444 * Remember in which queue this frame was sent. This field is driver 1445 * private data only. It will be made available by the NIC in STA_CSR4 1446 * on Tx interrupts. 1447 */ 1448 desc->qid = ac; 1449 1450 /* setup PLCP fields */ 1451 desc->plcp_signal = rt2661_plcp_signal(rate); 1452 desc->plcp_service = 4; 1453 1454 len += IEEE80211_CRC_LEN; 1455 if (RAL_RATE_IS_OFDM(rate)) { 1456 desc->flags |= htole32(RT2661_TX_OFDM); 1457 1458 plcp_length = len & 0xfff; 1459 desc->plcp_length_hi = plcp_length >> 6; 1460 desc->plcp_length_lo = plcp_length & 0x3f; 1461 } else { 1462 plcp_length = (16 * len + rate - 1) / rate; 1463 if (rate == 22) { 1464 remainder = (16 * len) % 22; 1465 if (remainder != 0 && remainder < 7) 1466 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1467 } 1468 desc->plcp_length_hi = plcp_length >> 8; 1469 desc->plcp_length_lo = plcp_length & 0xff; 1470 1471 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1472 desc->plcp_signal |= 0x08; 1473 } 1474 1475 /* RT2x61 supports scatter with up to 5 segments */ 1476 for (i = 0; i < nsegs; i++) { 1477 desc->addr[i] = htole32(segs[i].ds_addr); 1478 desc->len [i] = htole16(segs[i].ds_len); 1479 } 1480 } 1481 1482 int 1483 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1484 struct ieee80211_node *ni) 1485 { 1486 struct ieee80211com *ic = &sc->sc_ic; 1487 struct rt2661_tx_desc *desc; 1488 struct rt2661_tx_data *data; 1489 struct ieee80211_frame *wh; 1490 uint16_t dur; 1491 uint32_t flags = 0; 1492 int rate, error; 1493 1494 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1495 data = &sc->mgtq.data[sc->mgtq.cur]; 1496 1497 /* send mgt frames at the lowest available rate */ 1498 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1499 1500 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1501 BUS_DMA_NOWAIT); 1502 if (error != 0) { 1503 printf("%s: can't map mbuf (error %d)\n", 1504 sc->sc_dev.dv_xname, error); 1505 m_freem(m0); 1506 return error; 1507 } 1508 1509 #if NBPFILTER > 0 1510 if (sc->sc_drvbpf != NULL) { 1511 struct mbuf mb; 1512 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1513 1514 tap->wt_flags = 0; 1515 tap->wt_rate = rate; 1516 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1517 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1518 1519 mb.m_data = (caddr_t)tap; 1520 mb.m_len = sc->sc_txtap_len; 1521 mb.m_next = m0; 1522 mb.m_nextpkt = NULL; 1523 mb.m_type = 0; 1524 mb.m_flags = 0; 1525 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1526 } 1527 #endif 1528 1529 data->m = m0; 1530 data->ni = ni; 1531 1532 wh = mtod(m0, struct ieee80211_frame *); 1533 1534 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1535 flags |= RT2661_TX_NEED_ACK; 1536 1537 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1538 sc->sifs; 1539 *(uint16_t *)wh->i_dur = htole16(dur); 1540 1541 #ifndef IEEE80211_STA_ONLY 1542 /* tell hardware to set timestamp in probe responses */ 1543 if ((wh->i_fc[0] & 1544 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1545 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1546 flags |= RT2661_TX_TIMESTAMP; 1547 #endif 1548 } 1549 1550 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1551 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1552 RT2661_QID_MGT); 1553 1554 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1555 BUS_DMASYNC_PREWRITE); 1556 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1557 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1558 BUS_DMASYNC_PREWRITE); 1559 1560 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1561 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1562 1563 /* kick mgt */ 1564 sc->mgtq.queued++; 1565 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1566 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1567 1568 return 0; 1569 } 1570 1571 int 1572 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1573 struct ieee80211_node *ni, int ac) 1574 { 1575 struct ieee80211com *ic = &sc->sc_ic; 1576 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1577 struct rt2661_tx_desc *desc; 1578 struct rt2661_tx_data *data; 1579 struct ieee80211_frame *wh; 1580 struct ieee80211_key *k; 1581 struct mbuf *m1; 1582 uint16_t dur; 1583 uint32_t flags = 0; 1584 int pktlen, rate, needcts = 0, needrts = 0, error; 1585 1586 wh = mtod(m0, struct ieee80211_frame *); 1587 1588 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1589 k = ieee80211_get_txkey(ic, wh, ni); 1590 1591 if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL) 1592 return ENOBUFS; 1593 1594 /* packet header may have moved, reset our local pointer */ 1595 wh = mtod(m0, struct ieee80211_frame *); 1596 } 1597 1598 /* compute actual packet length (including CRC and crypto overhead) */ 1599 pktlen = m0->m_pkthdr.len + IEEE80211_CRC_LEN; 1600 1601 /* pickup a rate */ 1602 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1603 /* multicast frames are sent at the lowest avail. rate */ 1604 rate = ni->ni_rates.rs_rates[0]; 1605 } else if (ic->ic_fixed_rate != -1) { 1606 rate = ic->ic_sup_rates[ic->ic_curmode]. 1607 rs_rates[ic->ic_fixed_rate]; 1608 } else 1609 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1610 if (rate == 0) 1611 rate = 2; /* XXX should not happen */ 1612 rate &= IEEE80211_RATE_VAL; 1613 1614 /* 1615 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1616 * chance to contend for the wireless medium. 1617 */ 1618 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseq & 7)) 1619 flags |= RT2661_TX_IFS_SIFS; 1620 1621 /* check if RTS/CTS or CTS-to-self protection must be used */ 1622 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1623 /* multicast frames are not sent at OFDM rates in 802.11b/g */ 1624 if (pktlen > ic->ic_rtsthreshold) { 1625 needrts = 1; /* RTS/CTS based on frame length */ 1626 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1627 RAL_RATE_IS_OFDM(rate)) { 1628 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1629 needcts = 1; /* CTS-to-self */ 1630 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1631 needrts = 1; /* RTS/CTS */ 1632 } 1633 } 1634 if (needrts || needcts) { 1635 struct mbuf *mprot; 1636 int protrate, ackrate; 1637 1638 protrate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1639 ackrate = rt2661_ack_rate(ic, rate); 1640 1641 dur = rt2661_txtime(pktlen, rate, ic->ic_flags) + 1642 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1643 2 * sc->sifs; 1644 if (needrts) { 1645 dur += rt2661_txtime(RAL_CTS_SIZE, rt2661_ack_rate(ic, 1646 protrate), ic->ic_flags) + sc->sifs; 1647 mprot = ieee80211_get_rts(ic, wh, dur); 1648 } else { 1649 mprot = ieee80211_get_cts_to_self(ic, dur); 1650 } 1651 if (mprot == NULL) { 1652 printf("%s: could not allocate protection frame\n", 1653 sc->sc_dev.dv_xname); 1654 m_freem(m0); 1655 return ENOBUFS; 1656 } 1657 1658 desc = &txq->desc[txq->cur]; 1659 data = &txq->data[txq->cur]; 1660 1661 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, mprot, 1662 BUS_DMA_NOWAIT); 1663 if (error != 0) { 1664 printf("%s: can't map mbuf (error %d)\n", 1665 sc->sc_dev.dv_xname, error); 1666 m_freem(mprot); 1667 m_freem(m0); 1668 return error; 1669 } 1670 1671 data->m = mprot; 1672 /* avoid multiple free() of the same node for each fragment */ 1673 data->ni = ieee80211_ref_node(ni); 1674 1675 /* XXX may want to pass the protection frame to BPF */ 1676 1677 rt2661_setup_tx_desc(sc, desc, 1678 (needrts ? RT2661_TX_NEED_ACK : 0) | RT2661_TX_MORE_FRAG, 1679 0, mprot->m_pkthdr.len, protrate, data->map->dm_segs, 1680 data->map->dm_nsegs, ac); 1681 1682 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1683 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1684 bus_dmamap_sync(sc->sc_dmat, txq->map, 1685 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1686 BUS_DMASYNC_PREWRITE); 1687 1688 txq->queued++; 1689 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1690 1691 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1692 } 1693 1694 data = &txq->data[txq->cur]; 1695 desc = &txq->desc[txq->cur]; 1696 1697 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1698 BUS_DMA_NOWAIT); 1699 if (error != 0 && error != EFBIG) { 1700 printf("%s: can't map mbuf (error %d)\n", 1701 sc->sc_dev.dv_xname, error); 1702 m_freem(m0); 1703 return error; 1704 } 1705 if (error != 0) { 1706 /* too many fragments, linearize */ 1707 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1708 if (m1 == NULL) { 1709 m_freem(m0); 1710 return ENOBUFS; 1711 } 1712 if (m0->m_pkthdr.len > MHLEN) { 1713 MCLGET(m1, M_DONTWAIT); 1714 if (!(m1->m_flags & M_EXT)) { 1715 m_freem(m0); 1716 m_freem(m1); 1717 return ENOBUFS; 1718 } 1719 } 1720 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m1, caddr_t)); 1721 m1->m_pkthdr.len = m1->m_len = m0->m_pkthdr.len; 1722 m_freem(m0); 1723 m0 = m1; 1724 1725 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1726 BUS_DMA_NOWAIT); 1727 if (error != 0) { 1728 printf("%s: can't map mbuf (error %d)\n", 1729 sc->sc_dev.dv_xname, error); 1730 m_freem(m0); 1731 return error; 1732 } 1733 1734 /* packet header have moved, reset our local pointer */ 1735 wh = mtod(m0, struct ieee80211_frame *); 1736 } 1737 1738 #if NBPFILTER > 0 1739 if (sc->sc_drvbpf != NULL) { 1740 struct mbuf mb; 1741 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1742 1743 tap->wt_flags = 0; 1744 tap->wt_rate = rate; 1745 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1746 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1747 1748 mb.m_data = (caddr_t)tap; 1749 mb.m_len = sc->sc_txtap_len; 1750 mb.m_next = m0; 1751 mb.m_nextpkt = NULL; 1752 mb.m_type = 0; 1753 mb.m_flags = 0; 1754 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1755 } 1756 #endif 1757 1758 data->m = m0; 1759 data->ni = ni; 1760 1761 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1762 flags |= RT2661_TX_NEED_ACK; 1763 1764 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1765 ic->ic_flags) + sc->sifs; 1766 *(uint16_t *)wh->i_dur = htole16(dur); 1767 } 1768 1769 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1770 data->map->dm_segs, data->map->dm_nsegs, ac); 1771 1772 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1773 BUS_DMASYNC_PREWRITE); 1774 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1775 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1776 1777 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1778 m0->m_pkthdr.len, txq->cur, rate)); 1779 1780 /* kick Tx */ 1781 txq->queued++; 1782 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1783 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1784 1785 return 0; 1786 } 1787 1788 void 1789 rt2661_start(struct ifnet *ifp) 1790 { 1791 struct rt2661_softc *sc = ifp->if_softc; 1792 struct ieee80211com *ic = &sc->sc_ic; 1793 struct mbuf *m0; 1794 struct ieee80211_node *ni; 1795 1796 /* 1797 * net80211 may still try to send management frames even if the 1798 * IFF_RUNNING flag is not set... 1799 */ 1800 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1801 return; 1802 1803 for (;;) { 1804 IF_POLL(&ic->ic_mgtq, m0); 1805 if (m0 != NULL) { 1806 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1807 ifp->if_flags |= IFF_OACTIVE; 1808 break; 1809 } 1810 IF_DEQUEUE(&ic->ic_mgtq, m0); 1811 1812 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1813 m0->m_pkthdr.rcvif = NULL; 1814 #if NBPFILTER > 0 1815 if (ic->ic_rawbpf != NULL) 1816 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 1817 #endif 1818 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1819 break; 1820 1821 } else { 1822 if (ic->ic_state != IEEE80211_S_RUN) 1823 break; 1824 IFQ_POLL(&ifp->if_snd, m0); 1825 if (m0 == NULL) 1826 break; 1827 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1828 /* there is no place left in this ring */ 1829 ifp->if_flags |= IFF_OACTIVE; 1830 break; 1831 } 1832 IFQ_DEQUEUE(&ifp->if_snd, m0); 1833 #if NBPFILTER > 0 1834 if (ifp->if_bpf != NULL) 1835 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1836 #endif 1837 m0 = ieee80211_encap(ifp, m0, &ni); 1838 if (m0 == NULL) 1839 continue; 1840 #if NBPFILTER > 0 1841 if (ic->ic_rawbpf != NULL) 1842 bpf_mtap(ic->ic_rawbpf, m0, 1843 BPF_DIRECTION_OUT); 1844 #endif 1845 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1846 if (ni != NULL) 1847 ieee80211_release_node(ic, ni); 1848 ifp->if_oerrors++; 1849 break; 1850 } 1851 } 1852 1853 sc->sc_tx_timer = 5; 1854 ifp->if_timer = 1; 1855 } 1856 } 1857 1858 void 1859 rt2661_watchdog(struct ifnet *ifp) 1860 { 1861 struct rt2661_softc *sc = ifp->if_softc; 1862 1863 ifp->if_timer = 0; 1864 1865 if (sc->sc_tx_timer > 0) { 1866 if (--sc->sc_tx_timer == 0) { 1867 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1868 rt2661_init(ifp); 1869 ifp->if_oerrors++; 1870 return; 1871 } 1872 ifp->if_timer = 1; 1873 } 1874 1875 ieee80211_watchdog(ifp); 1876 } 1877 1878 int 1879 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1880 { 1881 struct rt2661_softc *sc = ifp->if_softc; 1882 struct ieee80211com *ic = &sc->sc_ic; 1883 struct ifaddr *ifa; 1884 struct ifreq *ifr; 1885 int s, error = 0; 1886 1887 s = splnet(); 1888 1889 switch (cmd) { 1890 case SIOCSIFADDR: 1891 ifa = (struct ifaddr *)data; 1892 ifp->if_flags |= IFF_UP; 1893 #ifdef INET 1894 if (ifa->ifa_addr->sa_family == AF_INET) 1895 arp_ifinit(&ic->ic_ac, ifa); 1896 #endif 1897 /* FALLTHROUGH */ 1898 case SIOCSIFFLAGS: 1899 if (ifp->if_flags & IFF_UP) { 1900 if (ifp->if_flags & IFF_RUNNING) 1901 rt2661_update_promisc(sc); 1902 else 1903 rt2661_init(ifp); 1904 } else { 1905 if (ifp->if_flags & IFF_RUNNING) 1906 rt2661_stop(ifp, 1); 1907 } 1908 break; 1909 1910 case SIOCADDMULTI: 1911 case SIOCDELMULTI: 1912 ifr = (struct ifreq *)data; 1913 error = (cmd == SIOCADDMULTI) ? 1914 ether_addmulti(ifr, &ic->ic_ac) : 1915 ether_delmulti(ifr, &ic->ic_ac); 1916 1917 if (error == ENETRESET) 1918 error = 0; 1919 break; 1920 1921 case SIOCS80211CHANNEL: 1922 /* 1923 * This allows for fast channel switching in monitor mode 1924 * (used by kismet). In IBSS mode, we must explicitly reset 1925 * the interface to generate a new beacon frame. 1926 */ 1927 error = ieee80211_ioctl(ifp, cmd, data); 1928 if (error == ENETRESET && 1929 ic->ic_opmode == IEEE80211_M_MONITOR) { 1930 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1931 (IFF_UP | IFF_RUNNING)) 1932 rt2661_set_chan(sc, ic->ic_ibss_chan); 1933 error = 0; 1934 } 1935 break; 1936 1937 default: 1938 error = ieee80211_ioctl(ifp, cmd, data); 1939 } 1940 1941 if (error == ENETRESET) { 1942 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1943 (IFF_UP | IFF_RUNNING)) 1944 rt2661_init(ifp); 1945 error = 0; 1946 } 1947 1948 splx(s); 1949 1950 return error; 1951 } 1952 1953 void 1954 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1955 { 1956 uint32_t tmp; 1957 int ntries; 1958 1959 for (ntries = 0; ntries < 100; ntries++) { 1960 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1961 break; 1962 DELAY(1); 1963 } 1964 if (ntries == 100) { 1965 printf("%s: could not write to BBP\n", sc->sc_dev.dv_xname); 1966 return; 1967 } 1968 1969 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1970 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1971 1972 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1973 } 1974 1975 uint8_t 1976 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1977 { 1978 uint32_t val; 1979 int ntries; 1980 1981 for (ntries = 0; ntries < 100; ntries++) { 1982 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1983 break; 1984 DELAY(1); 1985 } 1986 if (ntries == 100) { 1987 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 1988 return 0; 1989 } 1990 1991 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1992 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1993 1994 for (ntries = 0; ntries < 100; ntries++) { 1995 val = RAL_READ(sc, RT2661_PHY_CSR3); 1996 if (!(val & RT2661_BBP_BUSY)) 1997 return val & 0xff; 1998 DELAY(1); 1999 } 2000 2001 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2002 return 0; 2003 } 2004 2005 void 2006 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2007 { 2008 uint32_t tmp; 2009 int ntries; 2010 2011 for (ntries = 0; ntries < 100; ntries++) { 2012 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2013 break; 2014 DELAY(1); 2015 } 2016 if (ntries == 100) { 2017 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2018 return; 2019 } 2020 2021 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2022 (reg & 3); 2023 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2024 2025 /* remember last written value in sc */ 2026 sc->rf_regs[reg] = val; 2027 2028 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2029 } 2030 2031 int 2032 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2033 { 2034 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2035 return EIO; /* there is already a command pending */ 2036 2037 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2038 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2039 2040 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2041 2042 return 0; 2043 } 2044 2045 void 2046 rt2661_select_antenna(struct rt2661_softc *sc) 2047 { 2048 uint8_t bbp4, bbp77; 2049 uint32_t tmp; 2050 2051 bbp4 = rt2661_bbp_read(sc, 4); 2052 bbp77 = rt2661_bbp_read(sc, 77); 2053 2054 /* TBD */ 2055 2056 /* make sure Rx is disabled before switching antenna */ 2057 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2058 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2059 2060 rt2661_bbp_write(sc, 4, bbp4); 2061 rt2661_bbp_write(sc, 77, bbp77); 2062 2063 /* restore Rx filter */ 2064 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2065 } 2066 2067 /* 2068 * Enable multi-rate retries for frames sent at OFDM rates. 2069 * In 802.11b/g mode, allow fallback to CCK rates. 2070 */ 2071 void 2072 rt2661_enable_mrr(struct rt2661_softc *sc) 2073 { 2074 struct ieee80211com *ic = &sc->sc_ic; 2075 uint32_t tmp; 2076 2077 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2078 2079 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2080 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2081 tmp |= RT2661_MRR_CCK_FALLBACK; 2082 tmp |= RT2661_MRR_ENABLED; 2083 2084 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2085 } 2086 2087 void 2088 rt2661_set_txpreamble(struct rt2661_softc *sc) 2089 { 2090 uint32_t tmp; 2091 2092 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2093 2094 tmp &= ~RT2661_SHORT_PREAMBLE; 2095 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2096 tmp |= RT2661_SHORT_PREAMBLE; 2097 2098 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2099 } 2100 2101 void 2102 rt2661_set_basicrates(struct rt2661_softc *sc) 2103 { 2104 struct ieee80211com *ic = &sc->sc_ic; 2105 2106 /* update basic rate set */ 2107 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2108 /* 11b basic rates: 1, 2Mbps */ 2109 RAL_WRITE(sc, RT2661_TXRX_CSR5, 0x3); 2110 } else if (ic->ic_curmode == IEEE80211_MODE_11A) { 2111 /* 11a basic rates: 6, 12, 24Mbps */ 2112 RAL_WRITE(sc, RT2661_TXRX_CSR5, 0x150); 2113 } else { 2114 /* 11b/g basic rates: 1, 2, 5.5, 11Mbps */ 2115 RAL_WRITE(sc, RT2661_TXRX_CSR5, 0xf); 2116 } 2117 } 2118 2119 /* 2120 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2121 * driver. 2122 */ 2123 void 2124 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2125 { 2126 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2127 uint32_t tmp; 2128 2129 /* update all BBP registers that depend on the band */ 2130 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2131 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2132 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2133 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2134 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2135 } 2136 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2137 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2138 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2139 } 2140 2141 sc->bbp17 = bbp17; 2142 rt2661_bbp_write(sc, 17, bbp17); 2143 rt2661_bbp_write(sc, 96, bbp96); 2144 rt2661_bbp_write(sc, 104, bbp104); 2145 2146 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2147 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2148 rt2661_bbp_write(sc, 75, 0x80); 2149 rt2661_bbp_write(sc, 86, 0x80); 2150 rt2661_bbp_write(sc, 88, 0x80); 2151 } 2152 2153 rt2661_bbp_write(sc, 35, bbp35); 2154 rt2661_bbp_write(sc, 97, bbp97); 2155 rt2661_bbp_write(sc, 98, bbp98); 2156 2157 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2158 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2159 if (IEEE80211_IS_CHAN_2GHZ(c)) 2160 tmp |= RT2661_PA_PE_2GHZ; 2161 else 2162 tmp |= RT2661_PA_PE_5GHZ; 2163 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2164 2165 /* 802.11a uses a 16 microseconds short interframe space */ 2166 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2167 } 2168 2169 void 2170 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2171 { 2172 struct ieee80211com *ic = &sc->sc_ic; 2173 const struct rfprog *rfprog; 2174 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2175 int8_t power; 2176 u_int i, chan; 2177 2178 chan = ieee80211_chan2ieee(ic, c); 2179 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2180 return; 2181 2182 /* select the appropriate RF settings based on what EEPROM says */ 2183 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2184 2185 /* find the settings for this channel (we know it exists) */ 2186 for (i = 0; rfprog[i].chan != chan; i++); 2187 2188 power = sc->txpow[i]; 2189 if (power < 0) { 2190 bbp94 += power; 2191 power = 0; 2192 } else if (power > 31) { 2193 bbp94 += power - 31; 2194 power = 31; 2195 } 2196 2197 /* 2198 * If we are switching from the 2GHz band to the 5GHz band or 2199 * vice-versa, BBP registers need to be reprogrammed. 2200 */ 2201 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2202 rt2661_select_band(sc, c); 2203 rt2661_select_antenna(sc); 2204 } 2205 sc->sc_curchan = c; 2206 2207 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2208 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2209 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2210 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2211 2212 DELAY(200); 2213 2214 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2215 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2216 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2217 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2218 2219 DELAY(200); 2220 2221 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2222 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2223 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2224 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2225 2226 /* enable smart mode for MIMO-capable RFs */ 2227 bbp3 = rt2661_bbp_read(sc, 3); 2228 2229 bbp3 &= ~RT2661_SMART_MODE; 2230 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2231 bbp3 |= RT2661_SMART_MODE; 2232 2233 rt2661_bbp_write(sc, 3, bbp3); 2234 2235 if (bbp94 != RT2661_BBPR94_DEFAULT) 2236 rt2661_bbp_write(sc, 94, bbp94); 2237 2238 /* 5GHz radio needs a 1ms delay here */ 2239 if (IEEE80211_IS_CHAN_5GHZ(c)) 2240 DELAY(1000); 2241 } 2242 2243 void 2244 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2245 { 2246 uint32_t tmp; 2247 2248 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2249 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2250 2251 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2252 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2253 } 2254 2255 void 2256 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2257 { 2258 uint32_t tmp; 2259 2260 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2261 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2262 2263 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2264 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2265 } 2266 2267 void 2268 rt2661_update_promisc(struct rt2661_softc *sc) 2269 { 2270 struct ifnet *ifp = &sc->sc_ic.ic_if; 2271 uint32_t tmp; 2272 2273 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2274 2275 tmp &= ~RT2661_DROP_NOT_TO_ME; 2276 if (!(ifp->if_flags & IFF_PROMISC)) 2277 tmp |= RT2661_DROP_NOT_TO_ME; 2278 2279 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2280 2281 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2282 "entering" : "leaving")); 2283 } 2284 2285 void 2286 rt2661_updateslot(struct ieee80211com *ic) 2287 { 2288 struct rt2661_softc *sc = ic->ic_if.if_softc; 2289 2290 #ifndef IEEE80211_STA_ONLY 2291 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2292 /* 2293 * In HostAP mode, we defer setting of new slot time until 2294 * updated ERP Information Element has propagated to all 2295 * associated STAs. 2296 */ 2297 sc->sc_flags |= RT2661_UPDATE_SLOT; 2298 } else 2299 #endif 2300 rt2661_set_slottime(sc); 2301 } 2302 2303 void 2304 rt2661_set_slottime(struct rt2661_softc *sc) 2305 { 2306 struct ieee80211com *ic = &sc->sc_ic; 2307 uint8_t slottime; 2308 uint32_t tmp; 2309 2310 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2311 2312 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2313 tmp = (tmp & ~0xff) | slottime; 2314 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2315 2316 DPRINTF(("setting slot time to %uus\n", slottime)); 2317 } 2318 2319 const char * 2320 rt2661_get_rf(int rev) 2321 { 2322 switch (rev) { 2323 case RT2661_RF_5225: return "RT5225"; 2324 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2325 case RT2661_RF_2527: return "RT2527"; 2326 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2327 default: return "unknown"; 2328 } 2329 } 2330 2331 void 2332 rt2661_read_eeprom(struct rt2661_softc *sc) 2333 { 2334 struct ieee80211com *ic = &sc->sc_ic; 2335 uint16_t val; 2336 int i; 2337 2338 /* read MAC address */ 2339 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2340 ic->ic_myaddr[0] = val & 0xff; 2341 ic->ic_myaddr[1] = val >> 8; 2342 2343 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2344 ic->ic_myaddr[2] = val & 0xff; 2345 ic->ic_myaddr[3] = val >> 8; 2346 2347 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2348 ic->ic_myaddr[4] = val & 0xff; 2349 ic->ic_myaddr[5] = val >> 8; 2350 2351 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2352 /* XXX: test if different from 0xffff? */ 2353 sc->rf_rev = (val >> 11) & 0x1f; 2354 sc->hw_radio = (val >> 10) & 0x1; 2355 sc->rx_ant = (val >> 4) & 0x3; 2356 sc->tx_ant = (val >> 2) & 0x3; 2357 sc->nb_ant = val & 0x3; 2358 2359 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2360 2361 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2362 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2363 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2364 2365 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2366 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2367 2368 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2369 if ((val & 0xff) != 0xff) 2370 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2371 2372 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2373 if ((val & 0xff) != 0xff) 2374 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2375 2376 /* adjust RSSI correction for external low-noise amplifier */ 2377 if (sc->ext_2ghz_lna) 2378 sc->rssi_2ghz_corr -= 14; 2379 if (sc->ext_5ghz_lna) 2380 sc->rssi_5ghz_corr -= 14; 2381 2382 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2383 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2384 2385 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2386 if ((val >> 8) != 0xff) 2387 sc->rfprog = (val >> 8) & 0x3; 2388 if ((val & 0xff) != 0xff) 2389 sc->rffreq = val & 0xff; 2390 2391 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2392 2393 /* read Tx power for all a/b/g channels */ 2394 for (i = 0; i < 19; i++) { 2395 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2396 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2397 DPRINTF(("Channel=%d Tx power=%d\n", 2398 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2399 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2400 DPRINTF(("Channel=%d Tx power=%d\n", 2401 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2402 } 2403 2404 /* read vendor-specific BBP values */ 2405 for (i = 0; i < 16; i++) { 2406 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2407 if (val == 0 || val == 0xffff) 2408 continue; /* skip invalid entries */ 2409 sc->bbp_prom[i].reg = val >> 8; 2410 sc->bbp_prom[i].val = val & 0xff; 2411 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2412 sc->bbp_prom[i].val)); 2413 } 2414 } 2415 2416 int 2417 rt2661_bbp_init(struct rt2661_softc *sc) 2418 { 2419 int i, ntries; 2420 2421 /* wait for BBP to be ready */ 2422 for (ntries = 0; ntries < 100; ntries++) { 2423 const uint8_t val = rt2661_bbp_read(sc, 0); 2424 if (val != 0 && val != 0xff) 2425 break; 2426 DELAY(100); 2427 } 2428 if (ntries == 100) { 2429 printf("%s: timeout waiting for BBP\n", sc->sc_dev.dv_xname); 2430 return EIO; 2431 } 2432 2433 /* initialize BBP registers to default values */ 2434 for (i = 0; i < nitems(rt2661_def_bbp); i++) { 2435 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2436 rt2661_def_bbp[i].val); 2437 } 2438 2439 /* write vendor-specific BBP values (from EEPROM) */ 2440 for (i = 0; i < 16; i++) { 2441 if (sc->bbp_prom[i].reg == 0) 2442 continue; 2443 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2444 } 2445 2446 return 0; 2447 } 2448 2449 int 2450 rt2661_init(struct ifnet *ifp) 2451 { 2452 struct rt2661_softc *sc = ifp->if_softc; 2453 struct ieee80211com *ic = &sc->sc_ic; 2454 uint32_t tmp, sta[3]; 2455 int i, ntries; 2456 2457 /* for CardBus, power on the socket */ 2458 if (!(sc->sc_flags & RT2661_ENABLED)) { 2459 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2460 printf("%s: could not enable device\n", 2461 sc->sc_dev.dv_xname); 2462 return EIO; 2463 } 2464 sc->sc_flags |= RT2661_ENABLED; 2465 } 2466 2467 rt2661_stop(ifp, 0); 2468 2469 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2470 if (rt2661_load_microcode(sc) != 0) { 2471 printf("%s: could not load 8051 microcode\n", 2472 sc->sc_dev.dv_xname); 2473 rt2661_stop(ifp, 1); 2474 return EIO; 2475 } 2476 sc->sc_flags |= RT2661_FWLOADED; 2477 } 2478 2479 /* initialize Tx rings */ 2480 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2481 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2482 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2483 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2484 2485 /* initialize Mgt ring */ 2486 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2487 2488 /* initialize Rx ring */ 2489 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2490 2491 /* initialize Tx rings sizes */ 2492 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2493 RT2661_TX_RING_COUNT << 24 | 2494 RT2661_TX_RING_COUNT << 16 | 2495 RT2661_TX_RING_COUNT << 8 | 2496 RT2661_TX_RING_COUNT); 2497 2498 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2499 RT2661_TX_DESC_WSIZE << 16 | 2500 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2501 RT2661_MGT_RING_COUNT); 2502 2503 /* initialize Rx rings */ 2504 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2505 RT2661_RX_DESC_BACK << 16 | 2506 RT2661_RX_DESC_WSIZE << 8 | 2507 RT2661_RX_RING_COUNT); 2508 2509 /* XXX: some magic here */ 2510 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2511 2512 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2513 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2514 2515 /* load base address of Rx ring */ 2516 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2517 2518 /* initialize MAC registers to default values */ 2519 for (i = 0; i < nitems(rt2661_def_mac); i++) 2520 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2521 2522 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2523 rt2661_set_macaddr(sc, ic->ic_myaddr); 2524 2525 /* set host ready */ 2526 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2527 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2528 2529 /* wait for BBP/RF to wakeup */ 2530 for (ntries = 0; ntries < 1000; ntries++) { 2531 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2532 break; 2533 DELAY(1000); 2534 } 2535 if (ntries == 1000) { 2536 printf("timeout waiting for BBP/RF to wakeup\n"); 2537 rt2661_stop(ifp, 1); 2538 return EIO; 2539 } 2540 2541 if (rt2661_bbp_init(sc) != 0) { 2542 rt2661_stop(ifp, 1); 2543 return EIO; 2544 } 2545 2546 /* select default channel */ 2547 sc->sc_curchan = ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2548 rt2661_select_band(sc, sc->sc_curchan); 2549 rt2661_select_antenna(sc); 2550 rt2661_set_chan(sc, sc->sc_curchan); 2551 2552 /* update Rx filter */ 2553 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2554 2555 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2556 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2557 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2558 RT2661_DROP_ACKCTS; 2559 #ifndef IEEE80211_STA_ONLY 2560 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2561 #endif 2562 tmp |= RT2661_DROP_TODS; 2563 if (!(ifp->if_flags & IFF_PROMISC)) 2564 tmp |= RT2661_DROP_NOT_TO_ME; 2565 } 2566 2567 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2568 2569 /* clear STA registers */ 2570 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta)); 2571 2572 /* initialize ASIC */ 2573 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2574 2575 /* clear any pending interrupt */ 2576 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2577 2578 /* enable interrupts */ 2579 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2580 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2581 2582 /* kick Rx */ 2583 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2584 2585 ifp->if_flags &= ~IFF_OACTIVE; 2586 ifp->if_flags |= IFF_RUNNING; 2587 2588 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2589 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2590 else 2591 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2592 2593 return 0; 2594 } 2595 2596 void 2597 rt2661_stop(struct ifnet *ifp, int disable) 2598 { 2599 struct rt2661_softc *sc = ifp->if_softc; 2600 struct ieee80211com *ic = &sc->sc_ic; 2601 uint32_t tmp; 2602 int ac; 2603 2604 sc->sc_tx_timer = 0; 2605 ifp->if_timer = 0; 2606 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2607 2608 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2609 2610 /* abort Tx (for all 5 Tx rings) */ 2611 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2612 2613 /* disable Rx (value remains after reset!) */ 2614 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2615 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2616 2617 /* reset ASIC */ 2618 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2619 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2620 2621 /* disable interrupts */ 2622 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2623 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2624 2625 /* clear any pending interrupt */ 2626 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2627 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2628 2629 /* reset Tx and Rx rings */ 2630 for (ac = 0; ac < 4; ac++) 2631 rt2661_reset_tx_ring(sc, &sc->txq[ac]); 2632 rt2661_reset_tx_ring(sc, &sc->mgtq); 2633 rt2661_reset_rx_ring(sc, &sc->rxq); 2634 2635 /* for CardBus, power down the socket */ 2636 if (disable && sc->sc_disable != NULL) { 2637 if (sc->sc_flags & RT2661_ENABLED) { 2638 (*sc->sc_disable)(sc); 2639 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2640 } 2641 } 2642 } 2643 2644 int 2645 rt2661_load_microcode(struct rt2661_softc *sc) 2646 { 2647 int ntries; 2648 2649 /* reset 8051 */ 2650 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2651 2652 /* cancel any pending Host to MCU command */ 2653 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2654 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2655 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2656 2657 /* write 8051's microcode */ 2658 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2659 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, sc->ucode, sc->ucsize); 2660 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2661 2662 /* kick 8051's ass */ 2663 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2664 2665 /* wait for 8051 to initialize */ 2666 for (ntries = 0; ntries < 500; ntries++) { 2667 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2668 break; 2669 DELAY(100); 2670 } 2671 if (ntries == 500) { 2672 printf("%s: timeout waiting for MCU to initialize\n", 2673 sc->sc_dev.dv_xname); 2674 return EIO; 2675 } 2676 return 0; 2677 } 2678 2679 /* 2680 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2681 * false CCA count. This function is called periodically (every seconds) when 2682 * in the RUN state. Values taken from the reference driver. 2683 */ 2684 void 2685 rt2661_rx_tune(struct rt2661_softc *sc) 2686 { 2687 uint8_t bbp17; 2688 uint16_t cca; 2689 int lo, hi, dbm; 2690 2691 /* 2692 * Tuning range depends on operating band and on the presence of an 2693 * external low-noise amplifier. 2694 */ 2695 lo = 0x20; 2696 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2697 lo += 0x08; 2698 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2699 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2700 lo += 0x10; 2701 hi = lo + 0x20; 2702 2703 dbm = sc->avg_rssi; 2704 /* retrieve false CCA count since last call (clear on read) */ 2705 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2706 2707 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2708 2709 if (dbm < -74) { 2710 /* very bad RSSI, tune using false CCA count */ 2711 bbp17 = sc->bbp17; /* current value */ 2712 2713 hi -= 2 * (-74 - dbm); 2714 if (hi < lo) 2715 hi = lo; 2716 2717 if (bbp17 > hi) 2718 bbp17 = hi; 2719 else if (cca > 512) 2720 bbp17 = min(bbp17 + 1, hi); 2721 else if (cca < 100) 2722 bbp17 = max(bbp17 - 1, lo); 2723 2724 } else if (dbm < -66) { 2725 bbp17 = lo + 0x08; 2726 } else if (dbm < -58) { 2727 bbp17 = lo + 0x10; 2728 } else if (dbm < -35) { 2729 bbp17 = hi; 2730 } else { /* very good RSSI >= -35dBm */ 2731 bbp17 = 0x60; /* very low sensitivity */ 2732 } 2733 2734 if (bbp17 != sc->bbp17) { 2735 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2736 rt2661_bbp_write(sc, 17, bbp17); 2737 sc->bbp17 = bbp17; 2738 } 2739 } 2740 2741 #ifdef notyet 2742 /* 2743 * Enter/Leave radar detection mode. 2744 * This is for 802.11h additional regulatory domains. 2745 */ 2746 void 2747 rt2661_radar_start(struct rt2661_softc *sc) 2748 { 2749 uint32_t tmp; 2750 2751 /* disable Rx */ 2752 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2753 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2754 2755 rt2661_bbp_write(sc, 82, 0x20); 2756 rt2661_bbp_write(sc, 83, 0x00); 2757 rt2661_bbp_write(sc, 84, 0x40); 2758 2759 /* save current BBP registers values */ 2760 sc->bbp18 = rt2661_bbp_read(sc, 18); 2761 sc->bbp21 = rt2661_bbp_read(sc, 21); 2762 sc->bbp22 = rt2661_bbp_read(sc, 22); 2763 sc->bbp16 = rt2661_bbp_read(sc, 16); 2764 sc->bbp17 = rt2661_bbp_read(sc, 17); 2765 sc->bbp64 = rt2661_bbp_read(sc, 64); 2766 2767 rt2661_bbp_write(sc, 18, 0xff); 2768 rt2661_bbp_write(sc, 21, 0x3f); 2769 rt2661_bbp_write(sc, 22, 0x3f); 2770 rt2661_bbp_write(sc, 16, 0xbd); 2771 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2772 rt2661_bbp_write(sc, 64, 0x21); 2773 2774 /* restore Rx filter */ 2775 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2776 } 2777 2778 int 2779 rt2661_radar_stop(struct rt2661_softc *sc) 2780 { 2781 uint8_t bbp66; 2782 2783 /* read radar detection result */ 2784 bbp66 = rt2661_bbp_read(sc, 66); 2785 2786 /* restore BBP registers values */ 2787 rt2661_bbp_write(sc, 16, sc->bbp16); 2788 rt2661_bbp_write(sc, 17, sc->bbp17); 2789 rt2661_bbp_write(sc, 18, sc->bbp18); 2790 rt2661_bbp_write(sc, 21, sc->bbp21); 2791 rt2661_bbp_write(sc, 22, sc->bbp22); 2792 rt2661_bbp_write(sc, 64, sc->bbp64); 2793 2794 return bbp66 == 1; 2795 } 2796 #endif 2797 2798 #ifndef IEEE80211_STA_ONLY 2799 int 2800 rt2661_prepare_beacon(struct rt2661_softc *sc) 2801 { 2802 struct ieee80211com *ic = &sc->sc_ic; 2803 struct ieee80211_node *ni = ic->ic_bss; 2804 struct rt2661_tx_desc desc; 2805 struct mbuf *m0; 2806 int rate; 2807 2808 m0 = ieee80211_beacon_alloc(ic, ni); 2809 if (m0 == NULL) { 2810 printf("%s: could not allocate beacon frame\n", 2811 sc->sc_dev.dv_xname); 2812 return ENOBUFS; 2813 } 2814 2815 /* send beacons at the lowest available rate */ 2816 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2817 2818 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2819 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2820 2821 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2822 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2823 2824 /* copy beacon header and payload into NIC memory */ 2825 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2826 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2827 2828 m_freem(m0); 2829 2830 /* 2831 * Store offset of ERP Information Element so that we can update it 2832 * dynamically when the slot time changes. 2833 * XXX: this is ugly since it depends on how net80211 builds beacon 2834 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2835 */ 2836 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2837 sc->erp_csr = 2838 RT2661_HW_BEACON_BASE0 + 24 + 2839 sizeof (struct ieee80211_frame) + 2840 8 + 2 + 2 + 2841 ((ic->ic_flags & IEEE80211_F_HIDENWID) ? 2842 1 : 2 + ni->ni_esslen) + 2843 2 + min(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 2844 2 + 1 + 2845 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 2846 2; 2847 } 2848 2849 return 0; 2850 } 2851 #endif 2852 2853 /* 2854 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2855 * and HostAP operating modes. 2856 */ 2857 void 2858 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2859 { 2860 struct ieee80211com *ic = &sc->sc_ic; 2861 uint32_t tmp; 2862 2863 #ifndef IEEE80211_STA_ONLY 2864 if (ic->ic_opmode != IEEE80211_M_STA) { 2865 /* 2866 * Change default 16ms TBTT adjustment to 8ms. 2867 * Must be done before enabling beacon generation. 2868 */ 2869 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2870 } 2871 #endif 2872 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2873 2874 /* set beacon interval (in 1/16ms unit) */ 2875 tmp |= ic->ic_bss->ni_intval * 16; 2876 2877 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2878 if (ic->ic_opmode == IEEE80211_M_STA) 2879 tmp |= RT2661_TSF_MODE(1); 2880 #ifndef IEEE80211_STA_ONLY 2881 else 2882 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2883 #endif 2884 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2885 } 2886 2887 /* 2888 * Retrieve the "Received Signal Strength Indicator" from the raw values 2889 * contained in Rx descriptors. The computation depends on which band the 2890 * frame was received. Correction values taken from the reference driver. 2891 */ 2892 int 2893 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2894 { 2895 int lna, agc, rssi; 2896 2897 lna = (raw >> 5) & 0x3; 2898 agc = raw & 0x1f; 2899 2900 rssi = 2 * agc; 2901 2902 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2903 rssi += sc->rssi_2ghz_corr; 2904 2905 if (lna == 1) 2906 rssi -= 64; 2907 else if (lna == 2) 2908 rssi -= 74; 2909 else if (lna == 3) 2910 rssi -= 90; 2911 } else { 2912 rssi += sc->rssi_5ghz_corr; 2913 2914 if (lna == 1) 2915 rssi -= 64; 2916 else if (lna == 2) 2917 rssi -= 86; 2918 else if (lna == 3) 2919 rssi -= 100; 2920 } 2921 return rssi; 2922 } 2923