1 /* $OpenBSD: rt2661.c,v 1.66 2012/07/13 10:08:15 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 38 #include <machine/bus.h> 39 #include <machine/endian.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/if_ether.h> 55 #include <netinet/ip.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/ic/rt2661var.h> 62 #include <dev/ic/rt2661reg.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #ifdef RAL_DEBUG 69 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 70 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 71 int rt2661_debug = 1; 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 void rt2661_attachhook(void *); 78 int rt2661_alloc_tx_ring(struct rt2661_softc *, 79 struct rt2661_tx_ring *, int); 80 void rt2661_reset_tx_ring(struct rt2661_softc *, 81 struct rt2661_tx_ring *); 82 void rt2661_free_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *); 84 int rt2661_alloc_rx_ring(struct rt2661_softc *, 85 struct rt2661_rx_ring *, int); 86 void rt2661_reset_rx_ring(struct rt2661_softc *, 87 struct rt2661_rx_ring *); 88 void rt2661_free_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *); 90 struct ieee80211_node *rt2661_node_alloc(struct ieee80211com *); 91 int rt2661_media_change(struct ifnet *); 92 void rt2661_next_scan(void *); 93 void rt2661_iter_func(void *, struct ieee80211_node *); 94 void rt2661_updatestats(void *); 95 void rt2661_newassoc(struct ieee80211com *, struct ieee80211_node *, 96 int); 97 int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 98 int); 99 uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 100 void rt2661_tx_intr(struct rt2661_softc *); 101 void rt2661_tx_dma_intr(struct rt2661_softc *, 102 struct rt2661_tx_ring *); 103 void rt2661_rx_intr(struct rt2661_softc *); 104 #ifndef IEEE80211_STA_ONLY 105 void rt2661_mcu_beacon_expire(struct rt2661_softc *); 106 #endif 107 void rt2661_mcu_wakeup(struct rt2661_softc *); 108 void rt2661_mcu_cmd_intr(struct rt2661_softc *); 109 int rt2661_intr(void *); 110 #if NBPFILTER > 0 111 uint8_t rt2661_rxrate(const struct rt2661_rx_desc *); 112 #endif 113 int rt2661_ack_rate(struct ieee80211com *, int); 114 uint16_t rt2661_txtime(int, int, uint32_t); 115 uint8_t rt2661_plcp_signal(int); 116 void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 122 struct ieee80211_node *, int); 123 void rt2661_start(struct ifnet *); 124 void rt2661_watchdog(struct ifnet *); 125 int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 126 void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 127 uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 128 void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 129 int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 130 void rt2661_select_antenna(struct rt2661_softc *); 131 void rt2661_enable_mrr(struct rt2661_softc *); 132 void rt2661_set_txpreamble(struct rt2661_softc *); 133 void rt2661_set_basicrates(struct rt2661_softc *); 134 void rt2661_select_band(struct rt2661_softc *, 135 struct ieee80211_channel *); 136 void rt2661_set_chan(struct rt2661_softc *, 137 struct ieee80211_channel *); 138 void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 139 void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 140 void rt2661_update_promisc(struct rt2661_softc *); 141 void rt2661_updateslot(struct ieee80211com *); 142 void rt2661_set_slottime(struct rt2661_softc *); 143 const char *rt2661_get_rf(int); 144 void rt2661_read_eeprom(struct rt2661_softc *); 145 int rt2661_bbp_init(struct rt2661_softc *); 146 int rt2661_init(struct ifnet *); 147 void rt2661_stop(struct ifnet *, int); 148 int rt2661_load_microcode(struct rt2661_softc *); 149 void rt2661_rx_tune(struct rt2661_softc *); 150 #ifdef notyet 151 void rt2661_radar_start(struct rt2661_softc *); 152 int rt2661_radar_stop(struct rt2661_softc *); 153 #endif 154 #ifndef IEEE80211_STA_ONLY 155 int rt2661_prepare_beacon(struct rt2661_softc *); 156 #endif 157 void rt2661_enable_tsf_sync(struct rt2661_softc *); 158 int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 159 160 static const struct { 161 uint32_t reg; 162 uint32_t val; 163 } rt2661_def_mac[] = { 164 RT2661_DEF_MAC 165 }; 166 167 static const struct { 168 uint8_t reg; 169 uint8_t val; 170 } rt2661_def_bbp[] = { 171 RT2661_DEF_BBP 172 }; 173 174 static const struct rfprog { 175 uint8_t chan; 176 uint32_t r1, r2, r3, r4; 177 } rt2661_rf5225_1[] = { 178 RT2661_RF5225_1 179 }, rt2661_rf5225_2[] = { 180 RT2661_RF5225_2 181 }; 182 183 int 184 rt2661_attach(void *xsc, int id) 185 { 186 struct rt2661_softc *sc = xsc; 187 struct ieee80211com *ic = &sc->sc_ic; 188 uint32_t val; 189 int error, ac, ntries; 190 191 sc->sc_id = id; 192 193 sc->amrr.amrr_min_success_threshold = 1; 194 sc->amrr.amrr_max_success_threshold = 15; 195 timeout_set(&sc->amrr_to, rt2661_updatestats, sc); 196 timeout_set(&sc->scan_to, rt2661_next_scan, sc); 197 198 /* wait for NIC to initialize */ 199 for (ntries = 0; ntries < 1000; ntries++) { 200 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 201 break; 202 DELAY(1000); 203 } 204 if (ntries == 1000) { 205 printf("%s: timeout waiting for NIC to initialize\n", 206 sc->sc_dev.dv_xname); 207 return EIO; 208 } 209 210 /* retrieve RF rev. no and various other things from EEPROM */ 211 rt2661_read_eeprom(sc); 212 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 213 214 printf("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val, 215 rt2661_get_rf(sc->rf_rev)); 216 217 /* 218 * Allocate Tx and Rx rings. 219 */ 220 for (ac = 0; ac < 4; ac++) { 221 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 222 RT2661_TX_RING_COUNT); 223 if (error != 0) { 224 printf("%s: could not allocate Tx ring %d\n", 225 sc->sc_dev.dv_xname, ac); 226 goto fail1; 227 } 228 } 229 230 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 231 if (error != 0) { 232 printf("%s: could not allocate Mgt ring\n", 233 sc->sc_dev.dv_xname); 234 goto fail1; 235 } 236 237 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 238 if (error != 0) { 239 printf("%s: could not allocate Rx ring\n", 240 sc->sc_dev.dv_xname); 241 goto fail2; 242 } 243 244 if (rootvp == NULL) 245 mountroothook_establish(rt2661_attachhook, sc); 246 else 247 rt2661_attachhook(sc); 248 249 return 0; 250 251 fail2: rt2661_free_tx_ring(sc, &sc->mgtq); 252 fail1: while (--ac >= 0) 253 rt2661_free_tx_ring(sc, &sc->txq[ac]); 254 return ENXIO; 255 } 256 257 void 258 rt2661_attachhook(void *xsc) 259 { 260 struct rt2661_softc *sc = xsc; 261 struct ieee80211com *ic = &sc->sc_ic; 262 struct ifnet *ifp = &ic->ic_if; 263 const char *name = NULL; /* make lint happy */ 264 int i, error; 265 266 switch (sc->sc_id) { 267 case PCI_PRODUCT_RALINK_RT2561: 268 name = "ral-rt2561"; 269 break; 270 case PCI_PRODUCT_RALINK_RT2561S: 271 name = "ral-rt2561s"; 272 break; 273 case PCI_PRODUCT_RALINK_RT2661: 274 name = "ral-rt2661"; 275 break; 276 } 277 if ((error = loadfirmware(name, &sc->ucode, &sc->ucsize)) != 0) { 278 printf("%s: error %d, could not read firmware %s\n", 279 sc->sc_dev.dv_xname, error, name); 280 return; 281 } 282 283 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 284 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 285 ic->ic_state = IEEE80211_S_INIT; 286 287 /* set device capabilities */ 288 ic->ic_caps = 289 IEEE80211_C_MONITOR | /* monitor mode supported */ 290 #ifndef IEEE80211_STA_ONLY 291 IEEE80211_C_IBSS | /* IBSS mode supported */ 292 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 293 #endif 294 IEEE80211_C_TXPMGT | /* tx power management */ 295 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 296 IEEE80211_C_SHSLOT | /* short slot time supported */ 297 IEEE80211_C_WEP | /* s/w WEP */ 298 IEEE80211_C_RSN; /* WPA/RSN */ 299 300 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 301 /* set supported .11a rates */ 302 ic->ic_sup_rates[IEEE80211_MODE_11A] = 303 ieee80211_std_rateset_11a; 304 305 /* set supported .11a channels */ 306 for (i = 36; i <= 64; i += 4) { 307 ic->ic_channels[i].ic_freq = 308 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 309 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 310 } 311 for (i = 100; i <= 140; i += 4) { 312 ic->ic_channels[i].ic_freq = 313 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 314 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 315 } 316 for (i = 149; i <= 165; i += 4) { 317 ic->ic_channels[i].ic_freq = 318 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 319 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 320 } 321 } 322 323 /* set supported .11b and .11g rates */ 324 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 325 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 326 327 /* set supported .11b and .11g channels (1 through 14) */ 328 for (i = 1; i <= 14; i++) { 329 ic->ic_channels[i].ic_freq = 330 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 331 ic->ic_channels[i].ic_flags = 332 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 333 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 334 } 335 336 ifp->if_softc = sc; 337 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 338 ifp->if_ioctl = rt2661_ioctl; 339 ifp->if_start = rt2661_start; 340 ifp->if_watchdog = rt2661_watchdog; 341 IFQ_SET_READY(&ifp->if_snd); 342 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 343 344 if_attach(ifp); 345 ieee80211_ifattach(ifp); 346 ic->ic_node_alloc = rt2661_node_alloc; 347 ic->ic_newassoc = rt2661_newassoc; 348 ic->ic_updateslot = rt2661_updateslot; 349 350 /* override state transition machine */ 351 sc->sc_newstate = ic->ic_newstate; 352 ic->ic_newstate = rt2661_newstate; 353 ieee80211_media_init(ifp, rt2661_media_change, ieee80211_media_status); 354 355 #if NBPFILTER > 0 356 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 357 sizeof (struct ieee80211_frame) + 64); 358 359 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 360 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 361 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 362 363 sc->sc_txtap_len = sizeof sc->sc_txtapu; 364 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 365 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 366 #endif 367 } 368 369 int 370 rt2661_detach(void *xsc) 371 { 372 struct rt2661_softc *sc = xsc; 373 struct ifnet *ifp = &sc->sc_ic.ic_if; 374 int ac; 375 376 timeout_del(&sc->scan_to); 377 timeout_del(&sc->amrr_to); 378 379 ieee80211_ifdetach(ifp); /* free all nodes */ 380 if_detach(ifp); 381 382 for (ac = 0; ac < 4; ac++) 383 rt2661_free_tx_ring(sc, &sc->txq[ac]); 384 rt2661_free_tx_ring(sc, &sc->mgtq); 385 rt2661_free_rx_ring(sc, &sc->rxq); 386 387 if (sc->ucode != NULL) 388 free(sc->ucode, M_DEVBUF); 389 390 return 0; 391 } 392 393 void 394 rt2661_suspend(void *xsc) 395 { 396 struct rt2661_softc *sc = xsc; 397 struct ifnet *ifp = &sc->sc_ic.ic_if; 398 399 if (ifp->if_flags & IFF_RUNNING) { 400 rt2661_stop(ifp, 1); 401 sc->sc_flags &= ~RT2661_FWLOADED; 402 } 403 } 404 405 void 406 rt2661_resume(void *xsc) 407 { 408 struct rt2661_softc *sc = xsc; 409 struct ifnet *ifp = &sc->sc_ic.ic_if; 410 411 if (ifp->if_flags & IFF_UP) 412 rt2661_init(ifp); 413 } 414 415 int 416 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 417 int count) 418 { 419 int i, nsegs, error; 420 421 ring->count = count; 422 ring->queued = 0; 423 ring->cur = ring->next = ring->stat = 0; 424 425 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 426 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 427 if (error != 0) { 428 printf("%s: could not create desc DMA map\n", 429 sc->sc_dev.dv_xname); 430 goto fail; 431 } 432 433 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 434 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 435 if (error != 0) { 436 printf("%s: could not allocate DMA memory\n", 437 sc->sc_dev.dv_xname); 438 goto fail; 439 } 440 441 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 442 count * RT2661_TX_DESC_SIZE, (caddr_t *)&ring->desc, 443 BUS_DMA_NOWAIT); 444 if (error != 0) { 445 printf("%s: can't map desc DMA memory\n", 446 sc->sc_dev.dv_xname); 447 goto fail; 448 } 449 450 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 451 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 452 if (error != 0) { 453 printf("%s: could not load desc DMA map\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 ring->physaddr = ring->map->dm_segs->ds_addr; 459 460 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 461 M_NOWAIT | M_ZERO); 462 if (ring->data == NULL) { 463 printf("%s: could not allocate soft data\n", 464 sc->sc_dev.dv_xname); 465 error = ENOMEM; 466 goto fail; 467 } 468 469 for (i = 0; i < count; i++) { 470 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 471 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 472 &ring->data[i].map); 473 if (error != 0) { 474 printf("%s: could not create DMA map\n", 475 sc->sc_dev.dv_xname); 476 goto fail; 477 } 478 } 479 480 return 0; 481 482 fail: rt2661_free_tx_ring(sc, ring); 483 return error; 484 } 485 486 void 487 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 488 { 489 int i; 490 491 for (i = 0; i < ring->count; i++) { 492 struct rt2661_tx_desc *desc = &ring->desc[i]; 493 struct rt2661_tx_data *data = &ring->data[i]; 494 495 if (data->m != NULL) { 496 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 497 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 498 bus_dmamap_unload(sc->sc_dmat, data->map); 499 m_freem(data->m); 500 data->m = NULL; 501 } 502 503 /* 504 * The node has already been freed at that point so don't call 505 * ieee80211_release_node() here. 506 */ 507 data->ni = NULL; 508 509 desc->flags = 0; 510 } 511 512 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 513 BUS_DMASYNC_PREWRITE); 514 515 ring->queued = 0; 516 ring->cur = ring->next = ring->stat = 0; 517 } 518 519 void 520 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 521 { 522 int i; 523 524 if (ring->desc != NULL) { 525 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 526 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 527 bus_dmamap_unload(sc->sc_dmat, ring->map); 528 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->desc, 529 ring->count * RT2661_TX_DESC_SIZE); 530 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 531 } 532 533 if (ring->data != NULL) { 534 for (i = 0; i < ring->count; i++) { 535 struct rt2661_tx_data *data = &ring->data[i]; 536 537 if (data->m != NULL) { 538 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 539 data->map->dm_mapsize, 540 BUS_DMASYNC_POSTWRITE); 541 bus_dmamap_unload(sc->sc_dmat, data->map); 542 m_freem(data->m); 543 } 544 /* 545 * The node has already been freed at that point so 546 * don't call ieee80211_release_node() here. 547 */ 548 data->ni = NULL; 549 550 if (data->map != NULL) 551 bus_dmamap_destroy(sc->sc_dmat, data->map); 552 } 553 free(ring->data, M_DEVBUF); 554 } 555 } 556 557 int 558 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 559 int count) 560 { 561 int i, nsegs, error; 562 563 ring->count = count; 564 ring->cur = ring->next = 0; 565 566 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 567 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 568 if (error != 0) { 569 printf("%s: could not create desc DMA map\n", 570 sc->sc_dev.dv_xname); 571 goto fail; 572 } 573 574 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 575 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 576 if (error != 0) { 577 printf("%s: could not allocate DMA memory\n", 578 sc->sc_dev.dv_xname); 579 goto fail; 580 } 581 582 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 583 count * RT2661_RX_DESC_SIZE, (caddr_t *)&ring->desc, 584 BUS_DMA_NOWAIT); 585 if (error != 0) { 586 printf("%s: can't map desc DMA memory\n", 587 sc->sc_dev.dv_xname); 588 goto fail; 589 } 590 591 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 592 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 593 if (error != 0) { 594 printf("%s: could not load desc DMA map\n", 595 sc->sc_dev.dv_xname); 596 goto fail; 597 } 598 599 ring->physaddr = ring->map->dm_segs->ds_addr; 600 601 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 602 M_NOWAIT | M_ZERO); 603 if (ring->data == NULL) { 604 printf("%s: could not allocate soft data\n", 605 sc->sc_dev.dv_xname); 606 error = ENOMEM; 607 goto fail; 608 } 609 610 /* 611 * Pre-allocate Rx buffers and populate Rx ring. 612 */ 613 for (i = 0; i < count; i++) { 614 struct rt2661_rx_desc *desc = &sc->rxq.desc[i]; 615 struct rt2661_rx_data *data = &sc->rxq.data[i]; 616 617 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 618 0, BUS_DMA_NOWAIT, &data->map); 619 if (error != 0) { 620 printf("%s: could not create DMA map\n", 621 sc->sc_dev.dv_xname); 622 goto fail; 623 } 624 625 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 626 if (data->m == NULL) { 627 printf("%s: could not allocate rx mbuf\n", 628 sc->sc_dev.dv_xname); 629 error = ENOMEM; 630 goto fail; 631 } 632 MCLGET(data->m, M_DONTWAIT); 633 if (!(data->m->m_flags & M_EXT)) { 634 printf("%s: could not allocate rx mbuf cluster\n", 635 sc->sc_dev.dv_xname); 636 error = ENOMEM; 637 goto fail; 638 } 639 640 error = bus_dmamap_load(sc->sc_dmat, data->map, 641 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 642 if (error != 0) { 643 printf("%s: could not load rx buf DMA map", 644 sc->sc_dev.dv_xname); 645 goto fail; 646 } 647 648 desc->flags = htole32(RT2661_RX_BUSY); 649 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 653 BUS_DMASYNC_PREWRITE); 654 655 return 0; 656 657 fail: rt2661_free_rx_ring(sc, ring); 658 return error; 659 } 660 661 void 662 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 663 { 664 int i; 665 666 for (i = 0; i < ring->count; i++) 667 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 668 669 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 670 BUS_DMASYNC_PREWRITE); 671 672 ring->cur = ring->next = 0; 673 } 674 675 void 676 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 677 { 678 int i; 679 680 if (ring->desc != NULL) { 681 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 682 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 683 bus_dmamap_unload(sc->sc_dmat, ring->map); 684 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->desc, 685 ring->count * RT2661_RX_DESC_SIZE); 686 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 687 } 688 689 if (ring->data != NULL) { 690 for (i = 0; i < ring->count; i++) { 691 struct rt2661_rx_data *data = &ring->data[i]; 692 693 if (data->m != NULL) { 694 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 695 data->map->dm_mapsize, 696 BUS_DMASYNC_POSTREAD); 697 bus_dmamap_unload(sc->sc_dmat, data->map); 698 m_freem(data->m); 699 } 700 701 if (data->map != NULL) 702 bus_dmamap_destroy(sc->sc_dmat, data->map); 703 } 704 free(ring->data, M_DEVBUF); 705 } 706 } 707 708 struct ieee80211_node * 709 rt2661_node_alloc(struct ieee80211com *ic) 710 { 711 return malloc(sizeof (struct rt2661_node), M_DEVBUF, 712 M_NOWAIT | M_ZERO); 713 } 714 715 int 716 rt2661_media_change(struct ifnet *ifp) 717 { 718 int error; 719 720 error = ieee80211_media_change(ifp); 721 if (error != ENETRESET) 722 return error; 723 724 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 725 rt2661_init(ifp); 726 727 return 0; 728 } 729 730 /* 731 * This function is called periodically (every 200ms) during scanning to 732 * switch from one channel to another. 733 */ 734 void 735 rt2661_next_scan(void *arg) 736 { 737 struct rt2661_softc *sc = arg; 738 struct ieee80211com *ic = &sc->sc_ic; 739 struct ifnet *ifp = &ic->ic_if; 740 int s; 741 742 s = splnet(); 743 if (ic->ic_state == IEEE80211_S_SCAN) 744 ieee80211_next_scan(ifp); 745 splx(s); 746 } 747 748 /* 749 * This function is called for each neighbor node. 750 */ 751 void 752 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 753 { 754 struct rt2661_softc *sc = arg; 755 struct rt2661_node *rn = (struct rt2661_node *)ni; 756 757 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 758 } 759 760 /* 761 * This function is called periodically (every 500ms) in RUN state to update 762 * various settings like rate control statistics or Rx sensitivity. 763 */ 764 void 765 rt2661_updatestats(void *arg) 766 { 767 struct rt2661_softc *sc = arg; 768 struct ieee80211com *ic = &sc->sc_ic; 769 int s; 770 771 s = splnet(); 772 if (ic->ic_opmode == IEEE80211_M_STA) 773 rt2661_iter_func(sc, ic->ic_bss); 774 else 775 ieee80211_iterate_nodes(ic, rt2661_iter_func, arg); 776 777 /* update rx sensitivity every 1 sec */ 778 if (++sc->ncalls & 1) 779 rt2661_rx_tune(sc); 780 splx(s); 781 782 timeout_add_msec(&sc->amrr_to, 500); 783 } 784 785 void 786 rt2661_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 787 { 788 struct rt2661_softc *sc = ic->ic_softc; 789 int i; 790 791 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 792 793 /* set rate to some reasonable initial value */ 794 for (i = ni->ni_rates.rs_nrates - 1; 795 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 796 i--); 797 ni->ni_txrate = i; 798 } 799 800 int 801 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 802 { 803 struct rt2661_softc *sc = ic->ic_if.if_softc; 804 enum ieee80211_state ostate; 805 struct ieee80211_node *ni; 806 uint32_t tmp; 807 808 ostate = ic->ic_state; 809 timeout_del(&sc->scan_to); 810 timeout_del(&sc->amrr_to); 811 812 switch (nstate) { 813 case IEEE80211_S_INIT: 814 if (ostate == IEEE80211_S_RUN) { 815 /* abort TSF synchronization */ 816 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 817 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 818 } 819 break; 820 821 case IEEE80211_S_SCAN: 822 rt2661_set_chan(sc, ic->ic_bss->ni_chan); 823 timeout_add_msec(&sc->scan_to, 200); 824 break; 825 826 case IEEE80211_S_AUTH: 827 case IEEE80211_S_ASSOC: 828 rt2661_set_chan(sc, ic->ic_bss->ni_chan); 829 break; 830 831 case IEEE80211_S_RUN: 832 rt2661_set_chan(sc, ic->ic_bss->ni_chan); 833 834 ni = ic->ic_bss; 835 836 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 837 rt2661_set_slottime(sc); 838 rt2661_enable_mrr(sc); 839 rt2661_set_txpreamble(sc); 840 rt2661_set_basicrates(sc); 841 rt2661_set_bssid(sc, ni->ni_bssid); 842 } 843 844 #ifndef IEEE80211_STA_ONLY 845 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 846 ic->ic_opmode == IEEE80211_M_IBSS) 847 rt2661_prepare_beacon(sc); 848 #endif 849 850 if (ic->ic_opmode == IEEE80211_M_STA) { 851 /* fake a join to init the tx rate */ 852 rt2661_newassoc(ic, ni, 1); 853 } 854 855 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 856 sc->ncalls = 0; 857 sc->avg_rssi = -95; /* reset EMA */ 858 timeout_add_msec(&sc->amrr_to, 500); 859 rt2661_enable_tsf_sync(sc); 860 } 861 break; 862 } 863 864 return sc->sc_newstate(ic, nstate, arg); 865 } 866 867 /* 868 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 869 * 93C66). 870 */ 871 uint16_t 872 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 873 { 874 uint32_t tmp; 875 uint16_t val; 876 int n; 877 878 /* clock C once before the first command */ 879 RT2661_EEPROM_CTL(sc, 0); 880 881 RT2661_EEPROM_CTL(sc, RT2661_S); 882 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 883 RT2661_EEPROM_CTL(sc, RT2661_S); 884 885 /* write start bit (1) */ 886 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 887 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 888 889 /* write READ opcode (10) */ 890 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 891 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 892 RT2661_EEPROM_CTL(sc, RT2661_S); 893 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 894 895 /* write address (A5-A0 or A7-A0) */ 896 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 897 for (; n >= 0; n--) { 898 RT2661_EEPROM_CTL(sc, RT2661_S | 899 (((addr >> n) & 1) << RT2661_SHIFT_D)); 900 RT2661_EEPROM_CTL(sc, RT2661_S | 901 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 902 } 903 904 RT2661_EEPROM_CTL(sc, RT2661_S); 905 906 /* read data Q15-Q0 */ 907 val = 0; 908 for (n = 15; n >= 0; n--) { 909 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 910 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 911 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 912 RT2661_EEPROM_CTL(sc, RT2661_S); 913 } 914 915 RT2661_EEPROM_CTL(sc, 0); 916 917 /* clear Chip Select and clock C */ 918 RT2661_EEPROM_CTL(sc, RT2661_S); 919 RT2661_EEPROM_CTL(sc, 0); 920 RT2661_EEPROM_CTL(sc, RT2661_C); 921 922 return val; 923 } 924 925 void 926 rt2661_tx_intr(struct rt2661_softc *sc) 927 { 928 struct ieee80211com *ic = &sc->sc_ic; 929 struct ifnet *ifp = &ic->ic_if; 930 struct rt2661_tx_ring *txq; 931 struct rt2661_tx_data *data; 932 struct rt2661_node *rn; 933 int qid, retrycnt; 934 935 for (;;) { 936 const uint32_t val = RAL_READ(sc, RT2661_STA_CSR4); 937 if (!(val & RT2661_TX_STAT_VALID)) 938 break; 939 940 /* retrieve the queue in which this frame was sent */ 941 qid = RT2661_TX_QID(val); 942 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 943 944 /* retrieve rate control algorithm context */ 945 data = &txq->data[txq->stat]; 946 rn = (struct rt2661_node *)data->ni; 947 948 /* if no frame has been sent, ignore */ 949 if (rn == NULL) 950 continue; 951 952 switch (RT2661_TX_RESULT(val)) { 953 case RT2661_TX_SUCCESS: 954 retrycnt = RT2661_TX_RETRYCNT(val); 955 956 DPRINTFN(10, ("data frame sent successfully after " 957 "%d retries\n", retrycnt)); 958 rn->amn.amn_txcnt++; 959 if (retrycnt > 0) 960 rn->amn.amn_retrycnt++; 961 ifp->if_opackets++; 962 break; 963 964 case RT2661_TX_RETRY_FAIL: 965 DPRINTFN(9, ("sending data frame failed (too much " 966 "retries)\n")); 967 rn->amn.amn_txcnt++; 968 rn->amn.amn_retrycnt++; 969 ifp->if_oerrors++; 970 break; 971 972 default: 973 /* other failure */ 974 printf("%s: sending data frame failed 0x%08x\n", 975 sc->sc_dev.dv_xname, val); 976 ifp->if_oerrors++; 977 } 978 979 ieee80211_release_node(ic, data->ni); 980 data->ni = NULL; 981 982 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 983 984 txq->queued--; 985 if (++txq->stat >= txq->count) /* faster than % count */ 986 txq->stat = 0; 987 } 988 989 if (sc->mgtq.queued == 0 && sc->txq[0].queued == 0) 990 sc->sc_tx_timer = 0; 991 if (sc->mgtq.queued < RT2661_MGT_RING_COUNT && 992 sc->txq[0].queued < RT2661_TX_RING_COUNT - 1) { 993 if (sc->mgtq.queued < RT2661_MGT_RING_COUNT) 994 sc->sc_flags &= ~RT2661_MGT_OACTIVE; 995 if (sc->txq[0].queued < RT2661_TX_RING_COUNT - 1) 996 sc->sc_flags &= ~RT2661_DATA_OACTIVE; 997 if (!(sc->sc_flags & (RT2661_MGT_OACTIVE|RT2661_DATA_OACTIVE))) 998 ifp->if_flags &= ~IFF_OACTIVE; 999 rt2661_start(ifp); 1000 } 1001 } 1002 1003 void 1004 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1005 { 1006 for (;;) { 1007 struct rt2661_tx_desc *desc = &txq->desc[txq->next]; 1008 struct rt2661_tx_data *data = &txq->data[txq->next]; 1009 1010 bus_dmamap_sync(sc->sc_dmat, txq->map, 1011 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1012 BUS_DMASYNC_POSTREAD); 1013 1014 if ((letoh32(desc->flags) & RT2661_TX_BUSY) || 1015 !(letoh32(desc->flags) & RT2661_TX_VALID)) 1016 break; 1017 1018 /* descriptor is no longer valid */ 1019 desc->flags &= ~htole32(RT2661_TX_VALID); 1020 1021 bus_dmamap_sync(sc->sc_dmat, txq->map, 1022 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1023 BUS_DMASYNC_PREWRITE); 1024 1025 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1026 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1027 bus_dmamap_unload(sc->sc_dmat, data->map); 1028 m_freem(data->m); 1029 data->m = NULL; 1030 /* node reference is released in rt2661_tx_intr() */ 1031 1032 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1033 1034 if (++txq->next >= txq->count) /* faster than % count */ 1035 txq->next = 0; 1036 } 1037 } 1038 1039 void 1040 rt2661_rx_intr(struct rt2661_softc *sc) 1041 { 1042 struct ieee80211com *ic = &sc->sc_ic; 1043 struct ifnet *ifp = &ic->ic_if; 1044 struct ieee80211_frame *wh; 1045 struct ieee80211_rxinfo rxi; 1046 struct ieee80211_node *ni; 1047 struct mbuf *mnew, *m; 1048 int error, rssi; 1049 1050 for (;;) { 1051 struct rt2661_rx_desc *desc = &sc->rxq.desc[sc->rxq.cur]; 1052 struct rt2661_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1053 1054 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1055 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1056 BUS_DMASYNC_POSTREAD); 1057 1058 if (letoh32(desc->flags) & RT2661_RX_BUSY) 1059 break; 1060 1061 if ((letoh32(desc->flags) & RT2661_RX_PHY_ERROR) || 1062 (letoh32(desc->flags) & RT2661_RX_CRC_ERROR)) { 1063 /* 1064 * This should not happen since we did not request 1065 * to receive those frames when we filled TXRX_CSR0. 1066 */ 1067 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1068 letoh32(desc->flags))); 1069 ifp->if_ierrors++; 1070 goto skip; 1071 } 1072 1073 if ((letoh32(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1074 ifp->if_ierrors++; 1075 goto skip; 1076 } 1077 1078 /* 1079 * Try to allocate a new mbuf for this ring element and load it 1080 * before processing the current mbuf. If the ring element 1081 * cannot be loaded, drop the received packet and reuse the old 1082 * mbuf. In the unlikely case that the old mbuf can't be 1083 * reloaded either, explicitly panic. 1084 */ 1085 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1086 if (mnew == NULL) { 1087 ifp->if_ierrors++; 1088 goto skip; 1089 } 1090 MCLGET(mnew, M_DONTWAIT); 1091 if (!(mnew->m_flags & M_EXT)) { 1092 m_freem(mnew); 1093 ifp->if_ierrors++; 1094 goto skip; 1095 } 1096 1097 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1098 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1099 bus_dmamap_unload(sc->sc_dmat, data->map); 1100 1101 error = bus_dmamap_load(sc->sc_dmat, data->map, 1102 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1103 if (error != 0) { 1104 m_freem(mnew); 1105 1106 /* try to reload the old mbuf */ 1107 error = bus_dmamap_load(sc->sc_dmat, data->map, 1108 mtod(data->m, void *), MCLBYTES, NULL, 1109 BUS_DMA_NOWAIT); 1110 if (error != 0) { 1111 /* very unlikely that it will fail... */ 1112 panic("%s: could not load old rx mbuf", 1113 sc->sc_dev.dv_xname); 1114 } 1115 /* physical address may have changed */ 1116 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1117 ifp->if_ierrors++; 1118 goto skip; 1119 } 1120 1121 /* 1122 * New mbuf successfully loaded, update Rx ring and continue 1123 * processing. 1124 */ 1125 m = data->m; 1126 data->m = mnew; 1127 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1128 1129 /* finalize mbuf */ 1130 m->m_pkthdr.rcvif = ifp; 1131 m->m_pkthdr.len = m->m_len = 1132 (letoh32(desc->flags) >> 16) & 0xfff; 1133 1134 #if NBPFILTER > 0 1135 if (sc->sc_drvbpf != NULL) { 1136 struct mbuf mb; 1137 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1138 uint32_t tsf_lo, tsf_hi; 1139 1140 /* get timestamp (low and high 32 bits) */ 1141 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1142 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1143 1144 tap->wr_tsf = 1145 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1146 tap->wr_flags = 0; 1147 tap->wr_rate = rt2661_rxrate(desc); 1148 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1149 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1150 tap->wr_antsignal = desc->rssi; 1151 1152 mb.m_data = (caddr_t)tap; 1153 mb.m_len = sc->sc_rxtap_len; 1154 mb.m_next = m; 1155 mb.m_nextpkt = NULL; 1156 mb.m_type = 0; 1157 mb.m_flags = 0; 1158 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1159 } 1160 #endif 1161 1162 wh = mtod(m, struct ieee80211_frame *); 1163 ni = ieee80211_find_rxnode(ic, wh); 1164 1165 /* send the frame to the 802.11 layer */ 1166 rxi.rxi_flags = 0; 1167 rxi.rxi_rssi = desc->rssi; 1168 rxi.rxi_tstamp = 0; /* unused */ 1169 ieee80211_input(ifp, m, ni, &rxi); 1170 1171 /*- 1172 * Keep track of the average RSSI using an Exponential Moving 1173 * Average (EMA) of 8 Wilder's days: 1174 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1175 */ 1176 rssi = rt2661_get_rssi(sc, desc->rssi); 1177 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1178 1179 /* node is no longer needed */ 1180 ieee80211_release_node(ic, ni); 1181 1182 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1183 1184 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1185 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1186 BUS_DMASYNC_PREWRITE); 1187 1188 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1189 1190 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1191 } 1192 } 1193 1194 #ifndef IEEE80211_STA_ONLY 1195 /* 1196 * This function is called in HostAP or IBSS modes when it's time to send a 1197 * new beacon (every ni_intval milliseconds). 1198 */ 1199 void 1200 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1201 { 1202 struct ieee80211com *ic = &sc->sc_ic; 1203 1204 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1205 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1206 sc->sc_flags |= RT2661_SET_SLOTTIME; 1207 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1208 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1209 rt2661_set_slottime(sc); 1210 } 1211 1212 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1213 /* update ERP Information Element */ 1214 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1215 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1216 } 1217 1218 DPRINTFN(15, ("beacon expired\n")); 1219 } 1220 #endif 1221 1222 void 1223 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1224 { 1225 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1226 1227 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1228 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1229 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1230 1231 /* send wakeup command to MCU */ 1232 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1233 } 1234 1235 void 1236 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1237 { 1238 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1239 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1240 } 1241 1242 int 1243 rt2661_intr(void *arg) 1244 { 1245 struct rt2661_softc *sc = arg; 1246 struct ifnet *ifp = &sc->sc_ic.ic_if; 1247 uint32_t r1, r2; 1248 1249 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1250 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1251 if (__predict_false(r1 == 0xffffffff && r2 == 0xffffffff)) 1252 return 0; /* device likely went away */ 1253 if (r1 == 0 && r2 == 0) 1254 return 0; /* not for us */ 1255 1256 /* disable MAC and MCU interrupts */ 1257 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1258 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1259 1260 /* acknowledge interrupts */ 1261 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1262 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1263 1264 /* don't re-enable interrupts if we're shutting down */ 1265 if (!(ifp->if_flags & IFF_RUNNING)) 1266 return 0; 1267 1268 if (r1 & RT2661_MGT_DONE) 1269 rt2661_tx_dma_intr(sc, &sc->mgtq); 1270 1271 if (r1 & RT2661_RX_DONE) 1272 rt2661_rx_intr(sc); 1273 1274 if (r1 & RT2661_TX0_DMA_DONE) 1275 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1276 1277 if (r1 & RT2661_TX1_DMA_DONE) 1278 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1279 1280 if (r1 & RT2661_TX2_DMA_DONE) 1281 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1282 1283 if (r1 & RT2661_TX3_DMA_DONE) 1284 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1285 1286 if (r1 & RT2661_TX_DONE) 1287 rt2661_tx_intr(sc); 1288 1289 if (r2 & RT2661_MCU_CMD_DONE) 1290 rt2661_mcu_cmd_intr(sc); 1291 1292 #ifndef IEEE80211_STA_ONLY 1293 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1294 rt2661_mcu_beacon_expire(sc); 1295 #endif 1296 1297 if (r2 & RT2661_MCU_WAKEUP) 1298 rt2661_mcu_wakeup(sc); 1299 1300 /* re-enable MAC and MCU interrupts */ 1301 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1302 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1303 1304 return 1; 1305 } 1306 1307 /* quickly determine if a given rate is CCK or OFDM */ 1308 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1309 1310 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1311 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1312 1313 /* 1314 * This function is only used by the Rx radiotap code. It returns the rate at 1315 * which a given frame was received. 1316 */ 1317 #if NBPFILTER > 0 1318 uint8_t 1319 rt2661_rxrate(const struct rt2661_rx_desc *desc) 1320 { 1321 if (letoh32(desc->flags) & RT2661_RX_OFDM) { 1322 /* reverse function of rt2661_plcp_signal */ 1323 switch (desc->rate & 0xf) { 1324 case 0xb: return 12; 1325 case 0xf: return 18; 1326 case 0xa: return 24; 1327 case 0xe: return 36; 1328 case 0x9: return 48; 1329 case 0xd: return 72; 1330 case 0x8: return 96; 1331 case 0xc: return 108; 1332 } 1333 } else { 1334 if (desc->rate == 10) 1335 return 2; 1336 if (desc->rate == 20) 1337 return 4; 1338 if (desc->rate == 55) 1339 return 11; 1340 if (desc->rate == 110) 1341 return 22; 1342 } 1343 return 2; /* should not get there */ 1344 } 1345 #endif 1346 1347 /* 1348 * Return the expected ack rate for a frame transmitted at rate `rate'. 1349 */ 1350 int 1351 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1352 { 1353 switch (rate) { 1354 /* CCK rates */ 1355 case 2: 1356 return 2; 1357 case 4: 1358 case 11: 1359 case 22: 1360 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1361 1362 /* OFDM rates */ 1363 case 12: 1364 case 18: 1365 return 12; 1366 case 24: 1367 case 36: 1368 return 24; 1369 case 48: 1370 case 72: 1371 case 96: 1372 case 108: 1373 return 48; 1374 } 1375 1376 /* default to 1Mbps */ 1377 return 2; 1378 } 1379 1380 /* 1381 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1382 * The function automatically determines the operating mode depending on the 1383 * given rate. `flags' indicates whether short preamble is in use or not. 1384 */ 1385 uint16_t 1386 rt2661_txtime(int len, int rate, uint32_t flags) 1387 { 1388 uint16_t txtime; 1389 1390 if (RAL_RATE_IS_OFDM(rate)) { 1391 /* IEEE Std 802.11g-2003, pp. 44 */ 1392 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1393 txtime = 16 + 4 + 4 * txtime + 6; 1394 } else { 1395 /* IEEE Std 802.11b-1999, pp. 28 */ 1396 txtime = (16 * len + rate - 1) / rate; 1397 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1398 txtime += 72 + 24; 1399 else 1400 txtime += 144 + 48; 1401 } 1402 return txtime; 1403 } 1404 1405 uint8_t 1406 rt2661_plcp_signal(int rate) 1407 { 1408 switch (rate) { 1409 /* CCK rates (returned values are device-dependent) */ 1410 case 2: return 0x0; 1411 case 4: return 0x1; 1412 case 11: return 0x2; 1413 case 22: return 0x3; 1414 1415 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1416 case 12: return 0xb; 1417 case 18: return 0xf; 1418 case 24: return 0xa; 1419 case 36: return 0xe; 1420 case 48: return 0x9; 1421 case 72: return 0xd; 1422 case 96: return 0x8; 1423 case 108: return 0xc; 1424 1425 /* unsupported rates (should not get there) */ 1426 default: return 0xff; 1427 } 1428 } 1429 1430 void 1431 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1432 uint32_t flags, uint16_t xflags, int len, int rate, 1433 const bus_dma_segment_t *segs, int nsegs, int ac) 1434 { 1435 struct ieee80211com *ic = &sc->sc_ic; 1436 uint16_t plcp_length; 1437 int i, remainder; 1438 1439 desc->flags = htole32(flags); 1440 desc->flags |= htole32(len << 16); 1441 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1442 1443 desc->xflags = htole16(xflags); 1444 desc->xflags |= htole16(nsegs << 13); 1445 1446 desc->wme = htole16( 1447 RT2661_QID(ac) | 1448 RT2661_AIFSN(2) | 1449 RT2661_LOGCWMIN(4) | 1450 RT2661_LOGCWMAX(10)); 1451 1452 /* 1453 * Remember in which queue this frame was sent. This field is driver 1454 * private data only. It will be made available by the NIC in STA_CSR4 1455 * on Tx interrupts. 1456 */ 1457 desc->qid = ac; 1458 1459 /* setup PLCP fields */ 1460 desc->plcp_signal = rt2661_plcp_signal(rate); 1461 desc->plcp_service = 4; 1462 1463 len += IEEE80211_CRC_LEN; 1464 if (RAL_RATE_IS_OFDM(rate)) { 1465 desc->flags |= htole32(RT2661_TX_OFDM); 1466 1467 plcp_length = len & 0xfff; 1468 desc->plcp_length_hi = plcp_length >> 6; 1469 desc->plcp_length_lo = plcp_length & 0x3f; 1470 } else { 1471 plcp_length = (16 * len + rate - 1) / rate; 1472 if (rate == 22) { 1473 remainder = (16 * len) % 22; 1474 if (remainder != 0 && remainder < 7) 1475 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1476 } 1477 desc->plcp_length_hi = plcp_length >> 8; 1478 desc->plcp_length_lo = plcp_length & 0xff; 1479 1480 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1481 desc->plcp_signal |= 0x08; 1482 } 1483 1484 /* RT2x61 supports scatter with up to 5 segments */ 1485 for (i = 0; i < nsegs; i++) { 1486 desc->addr[i] = htole32(segs[i].ds_addr); 1487 desc->len [i] = htole16(segs[i].ds_len); 1488 } 1489 } 1490 1491 int 1492 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1493 struct ieee80211_node *ni) 1494 { 1495 struct ieee80211com *ic = &sc->sc_ic; 1496 struct rt2661_tx_desc *desc; 1497 struct rt2661_tx_data *data; 1498 struct ieee80211_frame *wh; 1499 uint16_t dur; 1500 uint32_t flags = 0; 1501 int rate, error; 1502 1503 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1504 data = &sc->mgtq.data[sc->mgtq.cur]; 1505 1506 /* send mgt frames at the lowest available rate */ 1507 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1508 1509 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1510 BUS_DMA_NOWAIT); 1511 if (error != 0) { 1512 printf("%s: can't map mbuf (error %d)\n", 1513 sc->sc_dev.dv_xname, error); 1514 m_freem(m0); 1515 return error; 1516 } 1517 1518 #if NBPFILTER > 0 1519 if (sc->sc_drvbpf != NULL) { 1520 struct mbuf mb; 1521 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1522 1523 tap->wt_flags = 0; 1524 tap->wt_rate = rate; 1525 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1526 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1527 1528 mb.m_data = (caddr_t)tap; 1529 mb.m_len = sc->sc_txtap_len; 1530 mb.m_next = m0; 1531 mb.m_nextpkt = NULL; 1532 mb.m_type = 0; 1533 mb.m_flags = 0; 1534 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1535 } 1536 #endif 1537 1538 data->m = m0; 1539 data->ni = ni; 1540 1541 wh = mtod(m0, struct ieee80211_frame *); 1542 1543 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1544 flags |= RT2661_TX_NEED_ACK; 1545 1546 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1547 sc->sifs; 1548 *(uint16_t *)wh->i_dur = htole16(dur); 1549 1550 #ifndef IEEE80211_STA_ONLY 1551 /* tell hardware to set timestamp in probe responses */ 1552 if ((wh->i_fc[0] & 1553 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1554 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1555 flags |= RT2661_TX_TIMESTAMP; 1556 #endif 1557 } 1558 1559 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1560 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1561 RT2661_QID_MGT); 1562 1563 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1564 BUS_DMASYNC_PREWRITE); 1565 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1566 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1567 BUS_DMASYNC_PREWRITE); 1568 1569 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1570 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1571 1572 /* kick mgt */ 1573 sc->mgtq.queued++; 1574 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1575 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1576 1577 return 0; 1578 } 1579 1580 int 1581 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1582 struct ieee80211_node *ni, int ac) 1583 { 1584 struct ieee80211com *ic = &sc->sc_ic; 1585 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1586 struct rt2661_tx_desc *desc; 1587 struct rt2661_tx_data *data; 1588 struct ieee80211_frame *wh; 1589 struct ieee80211_key *k; 1590 struct mbuf *m1; 1591 uint16_t dur; 1592 uint32_t flags = 0; 1593 int pktlen, rate, needcts = 0, needrts = 0, error; 1594 1595 wh = mtod(m0, struct ieee80211_frame *); 1596 1597 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1598 k = ieee80211_get_txkey(ic, wh, ni); 1599 1600 if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL) 1601 return ENOBUFS; 1602 1603 /* packet header may have moved, reset our local pointer */ 1604 wh = mtod(m0, struct ieee80211_frame *); 1605 } 1606 1607 /* compute actual packet length (including CRC and crypto overhead) */ 1608 pktlen = m0->m_pkthdr.len + IEEE80211_CRC_LEN; 1609 1610 /* pickup a rate */ 1611 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1612 /* multicast frames are sent at the lowest avail. rate */ 1613 rate = ni->ni_rates.rs_rates[0]; 1614 } else if (ic->ic_fixed_rate != -1) { 1615 rate = ic->ic_sup_rates[ic->ic_curmode]. 1616 rs_rates[ic->ic_fixed_rate]; 1617 } else 1618 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1619 if (rate == 0) 1620 rate = 2; /* XXX should not happen */ 1621 rate &= IEEE80211_RATE_VAL; 1622 1623 /* 1624 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1625 * chance to contend for the wireless medium. 1626 */ 1627 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseq & 7)) 1628 flags |= RT2661_TX_IFS_SIFS; 1629 1630 /* check if RTS/CTS or CTS-to-self protection must be used */ 1631 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1632 /* multicast frames are not sent at OFDM rates in 802.11b/g */ 1633 if (pktlen > ic->ic_rtsthreshold) { 1634 needrts = 1; /* RTS/CTS based on frame length */ 1635 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1636 RAL_RATE_IS_OFDM(rate)) { 1637 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1638 needcts = 1; /* CTS-to-self */ 1639 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1640 needrts = 1; /* RTS/CTS */ 1641 } 1642 } 1643 if (needrts || needcts) { 1644 struct mbuf *mprot; 1645 int protrate, ackrate; 1646 1647 protrate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1648 ackrate = rt2661_ack_rate(ic, rate); 1649 1650 dur = rt2661_txtime(pktlen, rate, ic->ic_flags) + 1651 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1652 2 * sc->sifs; 1653 if (needrts) { 1654 dur += rt2661_txtime(RAL_CTS_SIZE, rt2661_ack_rate(ic, 1655 protrate), ic->ic_flags) + sc->sifs; 1656 mprot = ieee80211_get_rts(ic, wh, dur); 1657 } else { 1658 mprot = ieee80211_get_cts_to_self(ic, dur); 1659 } 1660 if (mprot == NULL) { 1661 printf("%s: could not allocate protection frame\n", 1662 sc->sc_dev.dv_xname); 1663 m_freem(m0); 1664 return ENOBUFS; 1665 } 1666 1667 desc = &txq->desc[txq->cur]; 1668 data = &txq->data[txq->cur]; 1669 1670 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, mprot, 1671 BUS_DMA_NOWAIT); 1672 if (error != 0) { 1673 printf("%s: can't map mbuf (error %d)\n", 1674 sc->sc_dev.dv_xname, error); 1675 m_freem(mprot); 1676 m_freem(m0); 1677 return error; 1678 } 1679 1680 data->m = mprot; 1681 /* avoid multiple free() of the same node for each fragment */ 1682 data->ni = ieee80211_ref_node(ni); 1683 1684 /* XXX may want to pass the protection frame to BPF */ 1685 1686 rt2661_setup_tx_desc(sc, desc, 1687 (needrts ? RT2661_TX_NEED_ACK : 0) | RT2661_TX_MORE_FRAG, 1688 0, mprot->m_pkthdr.len, protrate, data->map->dm_segs, 1689 data->map->dm_nsegs, ac); 1690 1691 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1692 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1693 bus_dmamap_sync(sc->sc_dmat, txq->map, 1694 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1695 BUS_DMASYNC_PREWRITE); 1696 1697 txq->queued++; 1698 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1699 1700 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1701 } 1702 1703 data = &txq->data[txq->cur]; 1704 desc = &txq->desc[txq->cur]; 1705 1706 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1707 BUS_DMA_NOWAIT); 1708 if (error != 0 && error != EFBIG) { 1709 printf("%s: can't map mbuf (error %d)\n", 1710 sc->sc_dev.dv_xname, error); 1711 m_freem(m0); 1712 return error; 1713 } 1714 if (error != 0) { 1715 /* too many fragments, linearize */ 1716 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1717 if (m1 == NULL) { 1718 m_freem(m0); 1719 return ENOBUFS; 1720 } 1721 if (m0->m_pkthdr.len > MHLEN) { 1722 MCLGET(m1, M_DONTWAIT); 1723 if (!(m1->m_flags & M_EXT)) { 1724 m_freem(m0); 1725 m_freem(m1); 1726 return ENOBUFS; 1727 } 1728 } 1729 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m1, caddr_t)); 1730 m1->m_pkthdr.len = m1->m_len = m0->m_pkthdr.len; 1731 m_freem(m0); 1732 m0 = m1; 1733 1734 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1735 BUS_DMA_NOWAIT); 1736 if (error != 0) { 1737 printf("%s: can't map mbuf (error %d)\n", 1738 sc->sc_dev.dv_xname, error); 1739 m_freem(m0); 1740 return error; 1741 } 1742 1743 /* packet header have moved, reset our local pointer */ 1744 wh = mtod(m0, struct ieee80211_frame *); 1745 } 1746 1747 #if NBPFILTER > 0 1748 if (sc->sc_drvbpf != NULL) { 1749 struct mbuf mb; 1750 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1751 1752 tap->wt_flags = 0; 1753 tap->wt_rate = rate; 1754 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1755 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1756 1757 mb.m_data = (caddr_t)tap; 1758 mb.m_len = sc->sc_txtap_len; 1759 mb.m_next = m0; 1760 mb.m_nextpkt = NULL; 1761 mb.m_type = 0; 1762 mb.m_flags = 0; 1763 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1764 } 1765 #endif 1766 1767 data->m = m0; 1768 data->ni = ni; 1769 1770 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1771 flags |= RT2661_TX_NEED_ACK; 1772 1773 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1774 ic->ic_flags) + sc->sifs; 1775 *(uint16_t *)wh->i_dur = htole16(dur); 1776 } 1777 1778 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1779 data->map->dm_segs, data->map->dm_nsegs, ac); 1780 1781 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1782 BUS_DMASYNC_PREWRITE); 1783 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1784 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1785 1786 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1787 m0->m_pkthdr.len, txq->cur, rate)); 1788 1789 /* kick Tx */ 1790 txq->queued++; 1791 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1792 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1793 1794 return 0; 1795 } 1796 1797 void 1798 rt2661_start(struct ifnet *ifp) 1799 { 1800 struct rt2661_softc *sc = ifp->if_softc; 1801 struct ieee80211com *ic = &sc->sc_ic; 1802 struct mbuf *m0; 1803 struct ieee80211_node *ni; 1804 1805 /* 1806 * net80211 may still try to send management frames even if the 1807 * IFF_RUNNING flag is not set... 1808 */ 1809 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1810 return; 1811 1812 for (;;) { 1813 IF_POLL(&ic->ic_mgtq, m0); 1814 if (m0 != NULL) { 1815 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1816 ifp->if_flags |= IFF_OACTIVE; 1817 sc->sc_flags |= RT2661_MGT_OACTIVE; 1818 break; 1819 } 1820 IF_DEQUEUE(&ic->ic_mgtq, m0); 1821 1822 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1823 m0->m_pkthdr.rcvif = NULL; 1824 #if NBPFILTER > 0 1825 if (ic->ic_rawbpf != NULL) 1826 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 1827 #endif 1828 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1829 break; 1830 1831 } else { 1832 if (ic->ic_state != IEEE80211_S_RUN) 1833 break; 1834 IFQ_POLL(&ifp->if_snd, m0); 1835 if (m0 == NULL) 1836 break; 1837 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1838 /* there is no place left in this ring */ 1839 ifp->if_flags |= IFF_OACTIVE; 1840 sc->sc_flags |= RT2661_DATA_OACTIVE; 1841 break; 1842 } 1843 IFQ_DEQUEUE(&ifp->if_snd, m0); 1844 #if NBPFILTER > 0 1845 if (ifp->if_bpf != NULL) 1846 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1847 #endif 1848 m0 = ieee80211_encap(ifp, m0, &ni); 1849 if (m0 == NULL) 1850 continue; 1851 #if NBPFILTER > 0 1852 if (ic->ic_rawbpf != NULL) 1853 bpf_mtap(ic->ic_rawbpf, m0, 1854 BPF_DIRECTION_OUT); 1855 #endif 1856 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1857 if (ni != NULL) 1858 ieee80211_release_node(ic, ni); 1859 ifp->if_oerrors++; 1860 break; 1861 } 1862 } 1863 1864 sc->sc_tx_timer = 5; 1865 ifp->if_timer = 1; 1866 } 1867 } 1868 1869 void 1870 rt2661_watchdog(struct ifnet *ifp) 1871 { 1872 struct rt2661_softc *sc = ifp->if_softc; 1873 1874 ifp->if_timer = 0; 1875 1876 if (sc->sc_tx_timer > 0) { 1877 if (--sc->sc_tx_timer == 0) { 1878 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1879 rt2661_init(ifp); 1880 ifp->if_oerrors++; 1881 return; 1882 } 1883 ifp->if_timer = 1; 1884 } 1885 1886 ieee80211_watchdog(ifp); 1887 } 1888 1889 int 1890 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1891 { 1892 struct rt2661_softc *sc = ifp->if_softc; 1893 struct ieee80211com *ic = &sc->sc_ic; 1894 struct ifaddr *ifa; 1895 struct ifreq *ifr; 1896 int s, error = 0; 1897 1898 s = splnet(); 1899 1900 switch (cmd) { 1901 case SIOCSIFADDR: 1902 ifa = (struct ifaddr *)data; 1903 ifp->if_flags |= IFF_UP; 1904 #ifdef INET 1905 if (ifa->ifa_addr->sa_family == AF_INET) 1906 arp_ifinit(&ic->ic_ac, ifa); 1907 #endif 1908 /* FALLTHROUGH */ 1909 case SIOCSIFFLAGS: 1910 if (ifp->if_flags & IFF_UP) { 1911 if (ifp->if_flags & IFF_RUNNING) 1912 rt2661_update_promisc(sc); 1913 else 1914 rt2661_init(ifp); 1915 } else { 1916 if (ifp->if_flags & IFF_RUNNING) 1917 rt2661_stop(ifp, 1); 1918 } 1919 break; 1920 1921 case SIOCADDMULTI: 1922 case SIOCDELMULTI: 1923 ifr = (struct ifreq *)data; 1924 error = (cmd == SIOCADDMULTI) ? 1925 ether_addmulti(ifr, &ic->ic_ac) : 1926 ether_delmulti(ifr, &ic->ic_ac); 1927 1928 if (error == ENETRESET) 1929 error = 0; 1930 break; 1931 1932 case SIOCS80211CHANNEL: 1933 /* 1934 * This allows for fast channel switching in monitor mode 1935 * (used by kismet). In IBSS mode, we must explicitly reset 1936 * the interface to generate a new beacon frame. 1937 */ 1938 error = ieee80211_ioctl(ifp, cmd, data); 1939 if (error == ENETRESET && 1940 ic->ic_opmode == IEEE80211_M_MONITOR) { 1941 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1942 (IFF_UP | IFF_RUNNING)) 1943 rt2661_set_chan(sc, ic->ic_ibss_chan); 1944 error = 0; 1945 } 1946 break; 1947 1948 default: 1949 error = ieee80211_ioctl(ifp, cmd, data); 1950 } 1951 1952 if (error == ENETRESET) { 1953 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1954 (IFF_UP | IFF_RUNNING)) 1955 rt2661_init(ifp); 1956 error = 0; 1957 } 1958 1959 splx(s); 1960 1961 return error; 1962 } 1963 1964 void 1965 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1966 { 1967 uint32_t tmp; 1968 int ntries; 1969 1970 for (ntries = 0; ntries < 100; ntries++) { 1971 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1972 break; 1973 DELAY(1); 1974 } 1975 if (ntries == 100) { 1976 printf("%s: could not write to BBP\n", sc->sc_dev.dv_xname); 1977 return; 1978 } 1979 1980 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1981 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1982 1983 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1984 } 1985 1986 uint8_t 1987 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1988 { 1989 uint32_t val; 1990 int ntries; 1991 1992 for (ntries = 0; ntries < 100; ntries++) { 1993 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1994 break; 1995 DELAY(1); 1996 } 1997 if (ntries == 100) { 1998 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 1999 return 0; 2000 } 2001 2002 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2003 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2004 2005 for (ntries = 0; ntries < 100; ntries++) { 2006 val = RAL_READ(sc, RT2661_PHY_CSR3); 2007 if (!(val & RT2661_BBP_BUSY)) 2008 return val & 0xff; 2009 DELAY(1); 2010 } 2011 2012 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2013 return 0; 2014 } 2015 2016 void 2017 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2018 { 2019 uint32_t tmp; 2020 int ntries; 2021 2022 for (ntries = 0; ntries < 100; ntries++) { 2023 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2024 break; 2025 DELAY(1); 2026 } 2027 if (ntries == 100) { 2028 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2029 return; 2030 } 2031 2032 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2033 (reg & 3); 2034 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2035 2036 /* remember last written value in sc */ 2037 sc->rf_regs[reg] = val; 2038 2039 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2040 } 2041 2042 int 2043 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2044 { 2045 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2046 return EIO; /* there is already a command pending */ 2047 2048 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2049 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2050 2051 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2052 2053 return 0; 2054 } 2055 2056 void 2057 rt2661_select_antenna(struct rt2661_softc *sc) 2058 { 2059 uint8_t bbp4, bbp77; 2060 uint32_t tmp; 2061 2062 bbp4 = rt2661_bbp_read(sc, 4); 2063 bbp77 = rt2661_bbp_read(sc, 77); 2064 2065 /* TBD */ 2066 2067 /* make sure Rx is disabled before switching antenna */ 2068 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2069 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2070 2071 rt2661_bbp_write(sc, 4, bbp4); 2072 rt2661_bbp_write(sc, 77, bbp77); 2073 2074 /* restore Rx filter */ 2075 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2076 } 2077 2078 /* 2079 * Enable multi-rate retries for frames sent at OFDM rates. 2080 * In 802.11b/g mode, allow fallback to CCK rates. 2081 */ 2082 void 2083 rt2661_enable_mrr(struct rt2661_softc *sc) 2084 { 2085 struct ieee80211com *ic = &sc->sc_ic; 2086 uint32_t tmp; 2087 2088 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2089 2090 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2091 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2092 tmp |= RT2661_MRR_CCK_FALLBACK; 2093 tmp |= RT2661_MRR_ENABLED; 2094 2095 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2096 } 2097 2098 void 2099 rt2661_set_txpreamble(struct rt2661_softc *sc) 2100 { 2101 uint32_t tmp; 2102 2103 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2104 2105 tmp &= ~RT2661_SHORT_PREAMBLE; 2106 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2107 tmp |= RT2661_SHORT_PREAMBLE; 2108 2109 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2110 } 2111 2112 void 2113 rt2661_set_basicrates(struct rt2661_softc *sc) 2114 { 2115 struct ieee80211com *ic = &sc->sc_ic; 2116 2117 /* update basic rate set */ 2118 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2119 /* 11b basic rates: 1, 2Mbps */ 2120 RAL_WRITE(sc, RT2661_TXRX_CSR5, 0x3); 2121 } else if (ic->ic_curmode == IEEE80211_MODE_11A) { 2122 /* 11a basic rates: 6, 12, 24Mbps */ 2123 RAL_WRITE(sc, RT2661_TXRX_CSR5, 0x150); 2124 } else { 2125 /* 11b/g basic rates: 1, 2, 5.5, 11Mbps */ 2126 RAL_WRITE(sc, RT2661_TXRX_CSR5, 0xf); 2127 } 2128 } 2129 2130 /* 2131 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2132 * driver. 2133 */ 2134 void 2135 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2136 { 2137 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2138 uint32_t tmp; 2139 2140 /* update all BBP registers that depend on the band */ 2141 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2142 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2143 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2144 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2145 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2146 } 2147 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2148 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2149 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2150 } 2151 2152 sc->bbp17 = bbp17; 2153 rt2661_bbp_write(sc, 17, bbp17); 2154 rt2661_bbp_write(sc, 96, bbp96); 2155 rt2661_bbp_write(sc, 104, bbp104); 2156 2157 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2158 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2159 rt2661_bbp_write(sc, 75, 0x80); 2160 rt2661_bbp_write(sc, 86, 0x80); 2161 rt2661_bbp_write(sc, 88, 0x80); 2162 } 2163 2164 rt2661_bbp_write(sc, 35, bbp35); 2165 rt2661_bbp_write(sc, 97, bbp97); 2166 rt2661_bbp_write(sc, 98, bbp98); 2167 2168 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2169 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2170 if (IEEE80211_IS_CHAN_2GHZ(c)) 2171 tmp |= RT2661_PA_PE_2GHZ; 2172 else 2173 tmp |= RT2661_PA_PE_5GHZ; 2174 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2175 2176 /* 802.11a uses a 16 microseconds short interframe space */ 2177 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2178 } 2179 2180 void 2181 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2182 { 2183 struct ieee80211com *ic = &sc->sc_ic; 2184 const struct rfprog *rfprog; 2185 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2186 int8_t power; 2187 u_int i, chan; 2188 2189 chan = ieee80211_chan2ieee(ic, c); 2190 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2191 return; 2192 2193 /* select the appropriate RF settings based on what EEPROM says */ 2194 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2195 2196 /* find the settings for this channel (we know it exists) */ 2197 for (i = 0; rfprog[i].chan != chan; i++); 2198 2199 power = sc->txpow[i]; 2200 if (power < 0) { 2201 bbp94 += power; 2202 power = 0; 2203 } else if (power > 31) { 2204 bbp94 += power - 31; 2205 power = 31; 2206 } 2207 2208 /* 2209 * If we are switching from the 2GHz band to the 5GHz band or 2210 * vice-versa, BBP registers need to be reprogrammed. 2211 */ 2212 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2213 rt2661_select_band(sc, c); 2214 rt2661_select_antenna(sc); 2215 } 2216 sc->sc_curchan = c; 2217 2218 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2219 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2220 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2221 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2222 2223 DELAY(200); 2224 2225 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2226 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2227 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2228 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2229 2230 DELAY(200); 2231 2232 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2233 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2234 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2235 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2236 2237 /* enable smart mode for MIMO-capable RFs */ 2238 bbp3 = rt2661_bbp_read(sc, 3); 2239 2240 bbp3 &= ~RT2661_SMART_MODE; 2241 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2242 bbp3 |= RT2661_SMART_MODE; 2243 2244 rt2661_bbp_write(sc, 3, bbp3); 2245 2246 if (bbp94 != RT2661_BBPR94_DEFAULT) 2247 rt2661_bbp_write(sc, 94, bbp94); 2248 2249 /* 5GHz radio needs a 1ms delay here */ 2250 if (IEEE80211_IS_CHAN_5GHZ(c)) 2251 DELAY(1000); 2252 } 2253 2254 void 2255 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2256 { 2257 uint32_t tmp; 2258 2259 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2260 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2261 2262 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2263 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2264 } 2265 2266 void 2267 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2268 { 2269 uint32_t tmp; 2270 2271 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2272 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2273 2274 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2275 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2276 } 2277 2278 void 2279 rt2661_update_promisc(struct rt2661_softc *sc) 2280 { 2281 struct ifnet *ifp = &sc->sc_ic.ic_if; 2282 uint32_t tmp; 2283 2284 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2285 2286 tmp &= ~RT2661_DROP_NOT_TO_ME; 2287 if (!(ifp->if_flags & IFF_PROMISC)) 2288 tmp |= RT2661_DROP_NOT_TO_ME; 2289 2290 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2291 2292 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2293 "entering" : "leaving")); 2294 } 2295 2296 void 2297 rt2661_updateslot(struct ieee80211com *ic) 2298 { 2299 struct rt2661_softc *sc = ic->ic_if.if_softc; 2300 2301 #ifndef IEEE80211_STA_ONLY 2302 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2303 /* 2304 * In HostAP mode, we defer setting of new slot time until 2305 * updated ERP Information Element has propagated to all 2306 * associated STAs. 2307 */ 2308 sc->sc_flags |= RT2661_UPDATE_SLOT; 2309 } else 2310 #endif 2311 rt2661_set_slottime(sc); 2312 } 2313 2314 void 2315 rt2661_set_slottime(struct rt2661_softc *sc) 2316 { 2317 struct ieee80211com *ic = &sc->sc_ic; 2318 uint8_t slottime; 2319 uint32_t tmp; 2320 2321 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2322 2323 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2324 tmp = (tmp & ~0xff) | slottime; 2325 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2326 2327 DPRINTF(("setting slot time to %uus\n", slottime)); 2328 } 2329 2330 const char * 2331 rt2661_get_rf(int rev) 2332 { 2333 switch (rev) { 2334 case RT2661_RF_5225: return "RT5225"; 2335 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2336 case RT2661_RF_2527: return "RT2527"; 2337 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2338 default: return "unknown"; 2339 } 2340 } 2341 2342 void 2343 rt2661_read_eeprom(struct rt2661_softc *sc) 2344 { 2345 struct ieee80211com *ic = &sc->sc_ic; 2346 uint16_t val; 2347 int i; 2348 2349 /* read MAC address */ 2350 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2351 ic->ic_myaddr[0] = val & 0xff; 2352 ic->ic_myaddr[1] = val >> 8; 2353 2354 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2355 ic->ic_myaddr[2] = val & 0xff; 2356 ic->ic_myaddr[3] = val >> 8; 2357 2358 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2359 ic->ic_myaddr[4] = val & 0xff; 2360 ic->ic_myaddr[5] = val >> 8; 2361 2362 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2363 /* XXX: test if different from 0xffff? */ 2364 sc->rf_rev = (val >> 11) & 0x1f; 2365 sc->hw_radio = (val >> 10) & 0x1; 2366 sc->rx_ant = (val >> 4) & 0x3; 2367 sc->tx_ant = (val >> 2) & 0x3; 2368 sc->nb_ant = val & 0x3; 2369 2370 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2371 2372 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2373 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2374 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2375 2376 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2377 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2378 2379 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2380 if ((val & 0xff) != 0xff) 2381 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2382 2383 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2384 if ((val & 0xff) != 0xff) 2385 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2386 2387 /* adjust RSSI correction for external low-noise amplifier */ 2388 if (sc->ext_2ghz_lna) 2389 sc->rssi_2ghz_corr -= 14; 2390 if (sc->ext_5ghz_lna) 2391 sc->rssi_5ghz_corr -= 14; 2392 2393 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2394 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2395 2396 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2397 if ((val >> 8) != 0xff) 2398 sc->rfprog = (val >> 8) & 0x3; 2399 if ((val & 0xff) != 0xff) 2400 sc->rffreq = val & 0xff; 2401 2402 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2403 2404 /* read Tx power for all a/b/g channels */ 2405 for (i = 0; i < 19; i++) { 2406 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2407 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2408 DPRINTF(("Channel=%d Tx power=%d\n", 2409 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2410 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2411 DPRINTF(("Channel=%d Tx power=%d\n", 2412 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2413 } 2414 2415 /* read vendor-specific BBP values */ 2416 for (i = 0; i < 16; i++) { 2417 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2418 if (val == 0 || val == 0xffff) 2419 continue; /* skip invalid entries */ 2420 sc->bbp_prom[i].reg = val >> 8; 2421 sc->bbp_prom[i].val = val & 0xff; 2422 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2423 sc->bbp_prom[i].val)); 2424 } 2425 } 2426 2427 int 2428 rt2661_bbp_init(struct rt2661_softc *sc) 2429 { 2430 int i, ntries; 2431 2432 /* wait for BBP to be ready */ 2433 for (ntries = 0; ntries < 100; ntries++) { 2434 const uint8_t val = rt2661_bbp_read(sc, 0); 2435 if (val != 0 && val != 0xff) 2436 break; 2437 DELAY(100); 2438 } 2439 if (ntries == 100) { 2440 printf("%s: timeout waiting for BBP\n", sc->sc_dev.dv_xname); 2441 return EIO; 2442 } 2443 2444 /* initialize BBP registers to default values */ 2445 for (i = 0; i < nitems(rt2661_def_bbp); i++) { 2446 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2447 rt2661_def_bbp[i].val); 2448 } 2449 2450 /* write vendor-specific BBP values (from EEPROM) */ 2451 for (i = 0; i < 16; i++) { 2452 if (sc->bbp_prom[i].reg == 0) 2453 continue; 2454 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2455 } 2456 2457 return 0; 2458 } 2459 2460 int 2461 rt2661_init(struct ifnet *ifp) 2462 { 2463 struct rt2661_softc *sc = ifp->if_softc; 2464 struct ieee80211com *ic = &sc->sc_ic; 2465 uint32_t tmp, sta[3]; 2466 int i, ntries; 2467 2468 /* for CardBus, power on the socket */ 2469 if (!(sc->sc_flags & RT2661_ENABLED)) { 2470 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2471 printf("%s: could not enable device\n", 2472 sc->sc_dev.dv_xname); 2473 return EIO; 2474 } 2475 sc->sc_flags |= RT2661_ENABLED; 2476 } 2477 2478 rt2661_stop(ifp, 0); 2479 2480 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2481 if (rt2661_load_microcode(sc) != 0) { 2482 printf("%s: could not load 8051 microcode\n", 2483 sc->sc_dev.dv_xname); 2484 rt2661_stop(ifp, 1); 2485 return EIO; 2486 } 2487 sc->sc_flags |= RT2661_FWLOADED; 2488 } 2489 2490 /* initialize Tx rings */ 2491 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2492 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2493 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2494 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2495 2496 /* initialize Mgt ring */ 2497 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2498 2499 /* initialize Rx ring */ 2500 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2501 2502 /* initialize Tx rings sizes */ 2503 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2504 RT2661_TX_RING_COUNT << 24 | 2505 RT2661_TX_RING_COUNT << 16 | 2506 RT2661_TX_RING_COUNT << 8 | 2507 RT2661_TX_RING_COUNT); 2508 2509 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2510 RT2661_TX_DESC_WSIZE << 16 | 2511 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2512 RT2661_MGT_RING_COUNT); 2513 2514 /* initialize Rx rings */ 2515 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2516 RT2661_RX_DESC_BACK << 16 | 2517 RT2661_RX_DESC_WSIZE << 8 | 2518 RT2661_RX_RING_COUNT); 2519 2520 /* XXX: some magic here */ 2521 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2522 2523 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2524 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2525 2526 /* load base address of Rx ring */ 2527 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2528 2529 /* initialize MAC registers to default values */ 2530 for (i = 0; i < nitems(rt2661_def_mac); i++) 2531 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2532 2533 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2534 rt2661_set_macaddr(sc, ic->ic_myaddr); 2535 2536 /* set host ready */ 2537 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2538 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2539 2540 /* wait for BBP/RF to wakeup */ 2541 for (ntries = 0; ntries < 1000; ntries++) { 2542 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2543 break; 2544 DELAY(1000); 2545 } 2546 if (ntries == 1000) { 2547 printf("timeout waiting for BBP/RF to wakeup\n"); 2548 rt2661_stop(ifp, 1); 2549 return EIO; 2550 } 2551 2552 if (rt2661_bbp_init(sc) != 0) { 2553 rt2661_stop(ifp, 1); 2554 return EIO; 2555 } 2556 2557 /* select default channel */ 2558 sc->sc_curchan = ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2559 rt2661_select_band(sc, sc->sc_curchan); 2560 rt2661_select_antenna(sc); 2561 rt2661_set_chan(sc, sc->sc_curchan); 2562 2563 /* update Rx filter */ 2564 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2565 2566 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2567 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2568 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2569 RT2661_DROP_ACKCTS; 2570 #ifndef IEEE80211_STA_ONLY 2571 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2572 #endif 2573 tmp |= RT2661_DROP_TODS; 2574 if (!(ifp->if_flags & IFF_PROMISC)) 2575 tmp |= RT2661_DROP_NOT_TO_ME; 2576 } 2577 2578 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2579 2580 /* clear STA registers */ 2581 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta)); 2582 2583 /* initialize ASIC */ 2584 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2585 2586 /* clear any pending interrupt */ 2587 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2588 2589 /* enable interrupts */ 2590 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2591 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2592 2593 /* kick Rx */ 2594 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2595 2596 ifp->if_flags &= ~IFF_OACTIVE; 2597 ifp->if_flags |= IFF_RUNNING; 2598 2599 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2600 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2601 else 2602 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2603 2604 return 0; 2605 } 2606 2607 void 2608 rt2661_stop(struct ifnet *ifp, int disable) 2609 { 2610 struct rt2661_softc *sc = ifp->if_softc; 2611 struct ieee80211com *ic = &sc->sc_ic; 2612 uint32_t tmp; 2613 int ac; 2614 2615 sc->sc_tx_timer = 0; 2616 sc->sc_flags &= ~(RT2661_MGT_OACTIVE|RT2661_DATA_OACTIVE); 2617 ifp->if_timer = 0; 2618 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2619 2620 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2621 2622 /* abort Tx (for all 5 Tx rings) */ 2623 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2624 2625 /* disable Rx (value remains after reset!) */ 2626 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2627 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2628 2629 /* reset ASIC */ 2630 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2631 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2632 2633 /* disable interrupts */ 2634 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2635 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2636 2637 /* clear any pending interrupt */ 2638 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2639 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2640 2641 /* reset Tx and Rx rings */ 2642 for (ac = 0; ac < 4; ac++) 2643 rt2661_reset_tx_ring(sc, &sc->txq[ac]); 2644 rt2661_reset_tx_ring(sc, &sc->mgtq); 2645 rt2661_reset_rx_ring(sc, &sc->rxq); 2646 2647 /* for CardBus, power down the socket */ 2648 if (disable && sc->sc_disable != NULL) { 2649 if (sc->sc_flags & RT2661_ENABLED) { 2650 (*sc->sc_disable)(sc); 2651 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2652 } 2653 } 2654 } 2655 2656 int 2657 rt2661_load_microcode(struct rt2661_softc *sc) 2658 { 2659 int ntries; 2660 2661 /* reset 8051 */ 2662 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2663 2664 /* cancel any pending Host to MCU command */ 2665 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2666 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2667 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2668 2669 /* write 8051's microcode */ 2670 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2671 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, sc->ucode, sc->ucsize); 2672 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2673 2674 /* kick 8051's ass */ 2675 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2676 2677 /* wait for 8051 to initialize */ 2678 for (ntries = 0; ntries < 500; ntries++) { 2679 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2680 break; 2681 DELAY(100); 2682 } 2683 if (ntries == 500) { 2684 printf("%s: timeout waiting for MCU to initialize\n", 2685 sc->sc_dev.dv_xname); 2686 return EIO; 2687 } 2688 return 0; 2689 } 2690 2691 /* 2692 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2693 * false CCA count. This function is called periodically (every seconds) when 2694 * in the RUN state. Values taken from the reference driver. 2695 */ 2696 void 2697 rt2661_rx_tune(struct rt2661_softc *sc) 2698 { 2699 uint8_t bbp17; 2700 uint16_t cca; 2701 int lo, hi, dbm; 2702 2703 /* 2704 * Tuning range depends on operating band and on the presence of an 2705 * external low-noise amplifier. 2706 */ 2707 lo = 0x20; 2708 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2709 lo += 0x08; 2710 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2711 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2712 lo += 0x10; 2713 hi = lo + 0x20; 2714 2715 dbm = sc->avg_rssi; 2716 /* retrieve false CCA count since last call (clear on read) */ 2717 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2718 2719 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2720 2721 if (dbm < -74) { 2722 /* very bad RSSI, tune using false CCA count */ 2723 bbp17 = sc->bbp17; /* current value */ 2724 2725 hi -= 2 * (-74 - dbm); 2726 if (hi < lo) 2727 hi = lo; 2728 2729 if (bbp17 > hi) 2730 bbp17 = hi; 2731 else if (cca > 512) 2732 bbp17 = min(bbp17 + 1, hi); 2733 else if (cca < 100) 2734 bbp17 = max(bbp17 - 1, lo); 2735 2736 } else if (dbm < -66) { 2737 bbp17 = lo + 0x08; 2738 } else if (dbm < -58) { 2739 bbp17 = lo + 0x10; 2740 } else if (dbm < -35) { 2741 bbp17 = hi; 2742 } else { /* very good RSSI >= -35dBm */ 2743 bbp17 = 0x60; /* very low sensitivity */ 2744 } 2745 2746 if (bbp17 != sc->bbp17) { 2747 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2748 rt2661_bbp_write(sc, 17, bbp17); 2749 sc->bbp17 = bbp17; 2750 } 2751 } 2752 2753 #ifdef notyet 2754 /* 2755 * Enter/Leave radar detection mode. 2756 * This is for 802.11h additional regulatory domains. 2757 */ 2758 void 2759 rt2661_radar_start(struct rt2661_softc *sc) 2760 { 2761 uint32_t tmp; 2762 2763 /* disable Rx */ 2764 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2765 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2766 2767 rt2661_bbp_write(sc, 82, 0x20); 2768 rt2661_bbp_write(sc, 83, 0x00); 2769 rt2661_bbp_write(sc, 84, 0x40); 2770 2771 /* save current BBP registers values */ 2772 sc->bbp18 = rt2661_bbp_read(sc, 18); 2773 sc->bbp21 = rt2661_bbp_read(sc, 21); 2774 sc->bbp22 = rt2661_bbp_read(sc, 22); 2775 sc->bbp16 = rt2661_bbp_read(sc, 16); 2776 sc->bbp17 = rt2661_bbp_read(sc, 17); 2777 sc->bbp64 = rt2661_bbp_read(sc, 64); 2778 2779 rt2661_bbp_write(sc, 18, 0xff); 2780 rt2661_bbp_write(sc, 21, 0x3f); 2781 rt2661_bbp_write(sc, 22, 0x3f); 2782 rt2661_bbp_write(sc, 16, 0xbd); 2783 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2784 rt2661_bbp_write(sc, 64, 0x21); 2785 2786 /* restore Rx filter */ 2787 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2788 } 2789 2790 int 2791 rt2661_radar_stop(struct rt2661_softc *sc) 2792 { 2793 uint8_t bbp66; 2794 2795 /* read radar detection result */ 2796 bbp66 = rt2661_bbp_read(sc, 66); 2797 2798 /* restore BBP registers values */ 2799 rt2661_bbp_write(sc, 16, sc->bbp16); 2800 rt2661_bbp_write(sc, 17, sc->bbp17); 2801 rt2661_bbp_write(sc, 18, sc->bbp18); 2802 rt2661_bbp_write(sc, 21, sc->bbp21); 2803 rt2661_bbp_write(sc, 22, sc->bbp22); 2804 rt2661_bbp_write(sc, 64, sc->bbp64); 2805 2806 return bbp66 == 1; 2807 } 2808 #endif 2809 2810 #ifndef IEEE80211_STA_ONLY 2811 int 2812 rt2661_prepare_beacon(struct rt2661_softc *sc) 2813 { 2814 struct ieee80211com *ic = &sc->sc_ic; 2815 struct ieee80211_node *ni = ic->ic_bss; 2816 struct rt2661_tx_desc desc; 2817 struct mbuf *m0; 2818 int rate; 2819 2820 m0 = ieee80211_beacon_alloc(ic, ni); 2821 if (m0 == NULL) { 2822 printf("%s: could not allocate beacon frame\n", 2823 sc->sc_dev.dv_xname); 2824 return ENOBUFS; 2825 } 2826 2827 /* send beacons at the lowest available rate */ 2828 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2829 2830 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2831 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2832 2833 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2834 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2835 2836 /* copy beacon header and payload into NIC memory */ 2837 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2838 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2839 2840 m_freem(m0); 2841 2842 /* 2843 * Store offset of ERP Information Element so that we can update it 2844 * dynamically when the slot time changes. 2845 * XXX: this is ugly since it depends on how net80211 builds beacon 2846 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2847 */ 2848 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2849 sc->erp_csr = 2850 RT2661_HW_BEACON_BASE0 + 24 + 2851 sizeof (struct ieee80211_frame) + 2852 8 + 2 + 2 + 2853 ((ic->ic_flags & IEEE80211_F_HIDENWID) ? 2854 1 : 2 + ni->ni_esslen) + 2855 2 + min(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 2856 2 + 1 + 2857 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 2858 2; 2859 } 2860 2861 return 0; 2862 } 2863 #endif 2864 2865 /* 2866 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2867 * and HostAP operating modes. 2868 */ 2869 void 2870 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2871 { 2872 struct ieee80211com *ic = &sc->sc_ic; 2873 uint32_t tmp; 2874 2875 #ifndef IEEE80211_STA_ONLY 2876 if (ic->ic_opmode != IEEE80211_M_STA) { 2877 /* 2878 * Change default 16ms TBTT adjustment to 8ms. 2879 * Must be done before enabling beacon generation. 2880 */ 2881 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2882 } 2883 #endif 2884 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2885 2886 /* set beacon interval (in 1/16ms unit) */ 2887 tmp |= ic->ic_bss->ni_intval * 16; 2888 2889 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2890 if (ic->ic_opmode == IEEE80211_M_STA) 2891 tmp |= RT2661_TSF_MODE(1); 2892 #ifndef IEEE80211_STA_ONLY 2893 else 2894 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2895 #endif 2896 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2897 } 2898 2899 /* 2900 * Retrieve the "Received Signal Strength Indicator" from the raw values 2901 * contained in Rx descriptors. The computation depends on which band the 2902 * frame was received. Correction values taken from the reference driver. 2903 */ 2904 int 2905 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2906 { 2907 int lna, agc, rssi; 2908 2909 lna = (raw >> 5) & 0x3; 2910 agc = raw & 0x1f; 2911 2912 rssi = 2 * agc; 2913 2914 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2915 rssi += sc->rssi_2ghz_corr; 2916 2917 if (lna == 1) 2918 rssi -= 64; 2919 else if (lna == 2) 2920 rssi -= 74; 2921 else if (lna == 3) 2922 rssi -= 90; 2923 } else { 2924 rssi += sc->rssi_5ghz_corr; 2925 2926 if (lna == 1) 2927 rssi -= 64; 2928 else if (lna == 2) 2929 rssi -= 86; 2930 else if (lna == 3) 2931 rssi -= 100; 2932 } 2933 return rssi; 2934 } 2935