1 /* $OpenBSD: re.c,v 1.193 2016/08/10 14:27:17 deraadt Exp $ */ 2 /* $FreeBSD: if_re.c,v 1.31 2004/09/04 07:54:05 ru Exp $ */ 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Realtek 8139C+/8169/8169S/8110S PCI NIC driver 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 */ 42 43 /* 44 * This driver is designed to support Realtek's next generation of 45 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 46 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 47 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 48 * 49 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 50 * with the older 8139 family, however it also supports a special 51 * C+ mode of operation that provides several new performance enhancing 52 * features. These include: 53 * 54 * o Descriptor based DMA mechanism. Each descriptor represents 55 * a single packet fragment. Data buffers may be aligned on 56 * any byte boundary. 57 * 58 * o 64-bit DMA 59 * 60 * o TCP/IP checksum offload for both RX and TX 61 * 62 * o High and normal priority transmit DMA rings 63 * 64 * o VLAN tag insertion and extraction 65 * 66 * o TCP large send (segmentation offload) 67 * 68 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 69 * programming API is fairly straightforward. The RX filtering, EEPROM 70 * access and PHY access is the same as it is on the older 8139 series 71 * chips. 72 * 73 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 74 * same programming API and feature set as the 8139C+ with the following 75 * differences and additions: 76 * 77 * o 1000Mbps mode 78 * 79 * o Jumbo frames 80 * 81 * o GMII and TBI ports/registers for interfacing with copper 82 * or fiber PHYs 83 * 84 * o RX and TX DMA rings can have up to 1024 descriptors 85 * (the 8139C+ allows a maximum of 64) 86 * 87 * o Slight differences in register layout from the 8139C+ 88 * 89 * The TX start and timer interrupt registers are at different locations 90 * on the 8169 than they are on the 8139C+. Also, the status word in the 91 * RX descriptor has a slightly different bit layout. The 8169 does not 92 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 93 * copper gigE PHY. 94 * 95 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 96 * (the 'S' stands for 'single-chip'). These devices have the same 97 * programming API as the older 8169, but also have some vendor-specific 98 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 99 * part designed to be pin-compatible with the Realtek 8100 10/100 chip. 100 * 101 * This driver takes advantage of the RX and TX checksum offload and 102 * VLAN tag insertion/extraction features. It also implements TX 103 * interrupt moderation using the timer interrupt registers, which 104 * significantly reduces TX interrupt load. There is also support 105 * for jumbo frames, however the 8169/8169S/8110S can not transmit 106 * jumbo frames larger than 7440, so the max MTU possible with this 107 * driver is 7422 bytes. 108 */ 109 110 #include "bpfilter.h" 111 #include "vlan.h" 112 113 #include <sys/param.h> 114 #include <sys/endian.h> 115 #include <sys/systm.h> 116 #include <sys/sockio.h> 117 #include <sys/mbuf.h> 118 #include <sys/malloc.h> 119 #include <sys/kernel.h> 120 #include <sys/device.h> 121 #include <sys/timeout.h> 122 #include <sys/socket.h> 123 #include <sys/atomic.h> 124 125 #include <machine/bus.h> 126 127 #include <net/if.h> 128 #include <net/if_media.h> 129 130 #include <netinet/in.h> 131 #include <netinet/ip.h> 132 #include <netinet/if_ether.h> 133 134 #if NBPFILTER > 0 135 #include <net/bpf.h> 136 #endif 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 141 #include <dev/pci/pcidevs.h> 142 143 #include <dev/ic/rtl81x9reg.h> 144 #include <dev/ic/revar.h> 145 146 #ifdef RE_DEBUG 147 int redebug = 0; 148 #define DPRINTF(x) do { if (redebug) printf x; } while (0) 149 #else 150 #define DPRINTF(x) 151 #endif 152 153 static inline void re_set_bufaddr(struct rl_desc *, bus_addr_t); 154 155 int re_encap(struct rl_softc *, struct mbuf *, struct rl_txq *, int *); 156 157 int re_newbuf(struct rl_softc *); 158 int re_rx_list_init(struct rl_softc *); 159 void re_rx_list_fill(struct rl_softc *); 160 int re_tx_list_init(struct rl_softc *); 161 int re_rxeof(struct rl_softc *); 162 int re_txeof(struct rl_softc *); 163 void re_tick(void *); 164 void re_start(struct ifnet *); 165 int re_ioctl(struct ifnet *, u_long, caddr_t); 166 void re_watchdog(struct ifnet *); 167 int re_ifmedia_upd(struct ifnet *); 168 void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 169 170 void re_set_jumbo(struct rl_softc *); 171 172 void re_eeprom_putbyte(struct rl_softc *, int); 173 void re_eeprom_getword(struct rl_softc *, int, u_int16_t *); 174 void re_read_eeprom(struct rl_softc *, caddr_t, int, int); 175 176 int re_gmii_readreg(struct device *, int, int); 177 void re_gmii_writereg(struct device *, int, int, int); 178 179 int re_miibus_readreg(struct device *, int, int); 180 void re_miibus_writereg(struct device *, int, int, int); 181 void re_miibus_statchg(struct device *); 182 183 void re_iff(struct rl_softc *); 184 185 void re_setup_hw_im(struct rl_softc *); 186 void re_setup_sim_im(struct rl_softc *); 187 void re_disable_hw_im(struct rl_softc *); 188 void re_disable_sim_im(struct rl_softc *); 189 void re_config_imtype(struct rl_softc *, int); 190 void re_setup_intr(struct rl_softc *, int, int); 191 #ifndef SMALL_KERNEL 192 int re_wol(struct ifnet*, int); 193 #endif 194 195 void in_delayed_cksum(struct mbuf *); 196 197 struct cfdriver re_cd = { 198 0, "re", DV_IFNET 199 }; 200 201 extern char *hw_vendor, *hw_prod; 202 203 #define EE_SET(x) \ 204 CSR_WRITE_1(sc, RL_EECMD, \ 205 CSR_READ_1(sc, RL_EECMD) | x) 206 207 #define EE_CLR(x) \ 208 CSR_WRITE_1(sc, RL_EECMD, \ 209 CSR_READ_1(sc, RL_EECMD) & ~x) 210 211 #define RL_FRAMELEN(mtu) \ 212 (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + \ 213 ETHER_VLAN_ENCAP_LEN) 214 215 static const struct re_revision { 216 u_int32_t re_chipid; 217 const char *re_name; 218 } re_revisions[] = { 219 { RL_HWREV_8100, "RTL8100" }, 220 { RL_HWREV_8100E, "RTL8100E" }, 221 { RL_HWREV_8100E_SPIN2, "RTL8100E 2" }, 222 { RL_HWREV_8101, "RTL8101" }, 223 { RL_HWREV_8101E, "RTL8101E" }, 224 { RL_HWREV_8102E, "RTL8102E" }, 225 { RL_HWREV_8106E, "RTL8106E" }, 226 { RL_HWREV_8401E, "RTL8401E" }, 227 { RL_HWREV_8402, "RTL8402" }, 228 { RL_HWREV_8411, "RTL8411" }, 229 { RL_HWREV_8411B, "RTL8411B" }, 230 { RL_HWREV_8102EL, "RTL8102EL" }, 231 { RL_HWREV_8102EL_SPIN1, "RTL8102EL 1" }, 232 { RL_HWREV_8103E, "RTL8103E" }, 233 { RL_HWREV_8110S, "RTL8110S" }, 234 { RL_HWREV_8139CPLUS, "RTL8139C+" }, 235 { RL_HWREV_8168B_SPIN1, "RTL8168 1" }, 236 { RL_HWREV_8168B_SPIN2, "RTL8168 2" }, 237 { RL_HWREV_8168B_SPIN3, "RTL8168 3" }, 238 { RL_HWREV_8168C, "RTL8168C/8111C" }, 239 { RL_HWREV_8168C_SPIN2, "RTL8168C/8111C" }, 240 { RL_HWREV_8168CP, "RTL8168CP/8111CP" }, 241 { RL_HWREV_8168F, "RTL8168F/8111F" }, 242 { RL_HWREV_8168G, "RTL8168G/8111G" }, 243 { RL_HWREV_8168GU, "RTL8168GU/8111GU" }, 244 { RL_HWREV_8168H, "RTL8168H/8111H" }, 245 { RL_HWREV_8105E, "RTL8105E" }, 246 { RL_HWREV_8105E_SPIN1, "RTL8105E" }, 247 { RL_HWREV_8168D, "RTL8168D/8111D" }, 248 { RL_HWREV_8168DP, "RTL8168DP/8111DP" }, 249 { RL_HWREV_8168E, "RTL8168E/8111E" }, 250 { RL_HWREV_8168E_VL, "RTL8168E/8111E-VL" }, 251 { RL_HWREV_8168EP, "RTL8168EP/8111EP" }, 252 { RL_HWREV_8169, "RTL8169" }, 253 { RL_HWREV_8169_8110SB, "RTL8169/8110SB" }, 254 { RL_HWREV_8169_8110SBL, "RTL8169SBL" }, 255 { RL_HWREV_8169_8110SCd, "RTL8169/8110SCd" }, 256 { RL_HWREV_8169_8110SCe, "RTL8169/8110SCe" }, 257 { RL_HWREV_8169S, "RTL8169S" }, 258 259 { 0, NULL } 260 }; 261 262 263 static inline void 264 re_set_bufaddr(struct rl_desc *d, bus_addr_t addr) 265 { 266 d->rl_bufaddr_lo = htole32((uint32_t)addr); 267 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 268 d->rl_bufaddr_hi = htole32((uint64_t)addr >> 32); 269 else 270 d->rl_bufaddr_hi = 0; 271 } 272 273 /* 274 * Send a read command and address to the EEPROM, check for ACK. 275 */ 276 void 277 re_eeprom_putbyte(struct rl_softc *sc, int addr) 278 { 279 int d, i; 280 281 d = addr | (RL_9346_READ << sc->rl_eewidth); 282 283 /* 284 * Feed in each bit and strobe the clock. 285 */ 286 287 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 288 if (d & i) 289 EE_SET(RL_EE_DATAIN); 290 else 291 EE_CLR(RL_EE_DATAIN); 292 DELAY(100); 293 EE_SET(RL_EE_CLK); 294 DELAY(150); 295 EE_CLR(RL_EE_CLK); 296 DELAY(100); 297 } 298 } 299 300 /* 301 * Read a word of data stored in the EEPROM at address 'addr.' 302 */ 303 void 304 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 305 { 306 int i; 307 u_int16_t word = 0; 308 309 /* 310 * Send address of word we want to read. 311 */ 312 re_eeprom_putbyte(sc, addr); 313 314 /* 315 * Start reading bits from EEPROM. 316 */ 317 for (i = 0x8000; i; i >>= 1) { 318 EE_SET(RL_EE_CLK); 319 DELAY(100); 320 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 321 word |= i; 322 EE_CLR(RL_EE_CLK); 323 DELAY(100); 324 } 325 326 *dest = word; 327 } 328 329 /* 330 * Read a sequence of words from the EEPROM. 331 */ 332 void 333 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 334 { 335 int i; 336 u_int16_t word = 0, *ptr; 337 338 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 339 340 DELAY(100); 341 342 for (i = 0; i < cnt; i++) { 343 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 344 re_eeprom_getword(sc, off + i, &word); 345 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 346 ptr = (u_int16_t *)(dest + (i * 2)); 347 *ptr = word; 348 } 349 350 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 351 } 352 353 int 354 re_gmii_readreg(struct device *self, int phy, int reg) 355 { 356 struct rl_softc *sc = (struct rl_softc *)self; 357 u_int32_t rval; 358 int i; 359 360 if (phy != 7) 361 return (0); 362 363 /* Let the rgephy driver read the GMEDIASTAT register */ 364 365 if (reg == RL_GMEDIASTAT) { 366 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 367 return (rval); 368 } 369 370 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 371 372 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 373 rval = CSR_READ_4(sc, RL_PHYAR); 374 if (rval & RL_PHYAR_BUSY) 375 break; 376 DELAY(25); 377 } 378 379 if (i == RL_PHY_TIMEOUT) { 380 printf ("%s: PHY read failed\n", sc->sc_dev.dv_xname); 381 return (0); 382 } 383 384 DELAY(20); 385 386 return (rval & RL_PHYAR_PHYDATA); 387 } 388 389 void 390 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 391 { 392 struct rl_softc *sc = (struct rl_softc *)dev; 393 u_int32_t rval; 394 int i; 395 396 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 397 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 398 399 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 400 rval = CSR_READ_4(sc, RL_PHYAR); 401 if (!(rval & RL_PHYAR_BUSY)) 402 break; 403 DELAY(25); 404 } 405 406 if (i == RL_PHY_TIMEOUT) 407 printf ("%s: PHY write failed\n", sc->sc_dev.dv_xname); 408 409 DELAY(20); 410 } 411 412 int 413 re_miibus_readreg(struct device *dev, int phy, int reg) 414 { 415 struct rl_softc *sc = (struct rl_softc *)dev; 416 u_int16_t rval = 0; 417 u_int16_t re8139_reg = 0; 418 int s; 419 420 s = splnet(); 421 422 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) { 423 rval = re_gmii_readreg(dev, phy, reg); 424 splx(s); 425 return (rval); 426 } 427 428 /* Pretend the internal PHY is only at address 0 */ 429 if (phy) { 430 splx(s); 431 return (0); 432 } 433 switch(reg) { 434 case MII_BMCR: 435 re8139_reg = RL_BMCR; 436 break; 437 case MII_BMSR: 438 re8139_reg = RL_BMSR; 439 break; 440 case MII_ANAR: 441 re8139_reg = RL_ANAR; 442 break; 443 case MII_ANER: 444 re8139_reg = RL_ANER; 445 break; 446 case MII_ANLPAR: 447 re8139_reg = RL_LPAR; 448 break; 449 case MII_PHYIDR1: 450 case MII_PHYIDR2: 451 splx(s); 452 return (0); 453 /* 454 * Allow the rlphy driver to read the media status 455 * register. If we have a link partner which does not 456 * support NWAY, this is the register which will tell 457 * us the results of parallel detection. 458 */ 459 case RL_MEDIASTAT: 460 rval = CSR_READ_1(sc, RL_MEDIASTAT); 461 splx(s); 462 return (rval); 463 default: 464 printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg); 465 splx(s); 466 return (0); 467 } 468 rval = CSR_READ_2(sc, re8139_reg); 469 if (re8139_reg == RL_BMCR) { 470 /* 8139C+ has different bit layout. */ 471 rval &= ~(BMCR_LOOP | BMCR_ISO); 472 } 473 splx(s); 474 return (rval); 475 } 476 477 void 478 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 479 { 480 struct rl_softc *sc = (struct rl_softc *)dev; 481 u_int16_t re8139_reg = 0; 482 int s; 483 484 s = splnet(); 485 486 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) { 487 re_gmii_writereg(dev, phy, reg, data); 488 splx(s); 489 return; 490 } 491 492 /* Pretend the internal PHY is only at address 0 */ 493 if (phy) { 494 splx(s); 495 return; 496 } 497 switch(reg) { 498 case MII_BMCR: 499 re8139_reg = RL_BMCR; 500 /* 8139C+ has different bit layout. */ 501 data &= ~(BMCR_LOOP | BMCR_ISO); 502 break; 503 case MII_BMSR: 504 re8139_reg = RL_BMSR; 505 break; 506 case MII_ANAR: 507 re8139_reg = RL_ANAR; 508 break; 509 case MII_ANER: 510 re8139_reg = RL_ANER; 511 break; 512 case MII_ANLPAR: 513 re8139_reg = RL_LPAR; 514 break; 515 case MII_PHYIDR1: 516 case MII_PHYIDR2: 517 splx(s); 518 return; 519 break; 520 default: 521 printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg); 522 splx(s); 523 return; 524 } 525 CSR_WRITE_2(sc, re8139_reg, data); 526 splx(s); 527 } 528 529 void 530 re_miibus_statchg(struct device *dev) 531 { 532 struct rl_softc *sc = (struct rl_softc *)dev; 533 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 534 struct mii_data *mii = &sc->sc_mii; 535 536 if ((ifp->if_flags & IFF_RUNNING) == 0) 537 return; 538 539 sc->rl_flags &= ~RL_FLAG_LINK; 540 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 541 (IFM_ACTIVE | IFM_AVALID)) { 542 switch (IFM_SUBTYPE(mii->mii_media_active)) { 543 case IFM_10_T: 544 case IFM_100_TX: 545 sc->rl_flags |= RL_FLAG_LINK; 546 break; 547 case IFM_1000_T: 548 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 549 break; 550 sc->rl_flags |= RL_FLAG_LINK; 551 break; 552 default: 553 break; 554 } 555 } 556 557 /* 558 * Realtek controllers do not provide an interface to 559 * Tx/Rx MACs for resolved speed, duplex and flow-control 560 * parameters. 561 */ 562 } 563 564 void 565 re_iff(struct rl_softc *sc) 566 { 567 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 568 int h = 0; 569 u_int32_t hashes[2]; 570 u_int32_t rxfilt; 571 struct arpcom *ac = &sc->sc_arpcom; 572 struct ether_multi *enm; 573 struct ether_multistep step; 574 575 rxfilt = CSR_READ_4(sc, RL_RXCFG); 576 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | 577 RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI); 578 ifp->if_flags &= ~IFF_ALLMULTI; 579 580 /* 581 * Always accept frames destined to our station address. 582 * Always accept broadcast frames. 583 */ 584 rxfilt |= RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 585 586 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 587 ifp->if_flags |= IFF_ALLMULTI; 588 rxfilt |= RL_RXCFG_RX_MULTI; 589 if (ifp->if_flags & IFF_PROMISC) 590 rxfilt |= RL_RXCFG_RX_ALLPHYS; 591 hashes[0] = hashes[1] = 0xFFFFFFFF; 592 } else { 593 rxfilt |= RL_RXCFG_RX_MULTI; 594 /* Program new filter. */ 595 bzero(hashes, sizeof(hashes)); 596 597 ETHER_FIRST_MULTI(step, ac, enm); 598 while (enm != NULL) { 599 h = ether_crc32_be(enm->enm_addrlo, 600 ETHER_ADDR_LEN) >> 26; 601 602 if (h < 32) 603 hashes[0] |= (1 << h); 604 else 605 hashes[1] |= (1 << (h - 32)); 606 607 ETHER_NEXT_MULTI(step, enm); 608 } 609 } 610 611 /* 612 * For some unfathomable reason, Realtek decided to reverse 613 * the order of the multicast hash registers in the PCI Express 614 * parts. This means we have to write the hash pattern in reverse 615 * order for those devices. 616 */ 617 if (sc->rl_flags & RL_FLAG_PCIE) { 618 CSR_WRITE_4(sc, RL_MAR0, swap32(hashes[1])); 619 CSR_WRITE_4(sc, RL_MAR4, swap32(hashes[0])); 620 } else { 621 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 622 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 623 } 624 625 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 626 } 627 628 void 629 re_reset(struct rl_softc *sc) 630 { 631 int i; 632 633 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 634 635 for (i = 0; i < RL_TIMEOUT; i++) { 636 DELAY(10); 637 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 638 break; 639 } 640 if (i == RL_TIMEOUT) 641 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 642 643 if (sc->rl_flags & RL_FLAG_MACRESET) 644 CSR_WRITE_1(sc, RL_LDPS, 1); 645 } 646 647 /* 648 * Attach the interface. Allocate softc structures, do ifmedia 649 * setup and ethernet/BPF attach. 650 */ 651 int 652 re_attach(struct rl_softc *sc, const char *intrstr) 653 { 654 u_char eaddr[ETHER_ADDR_LEN]; 655 u_int16_t as[ETHER_ADDR_LEN / 2]; 656 struct ifnet *ifp; 657 u_int16_t re_did = 0; 658 int error = 0, i; 659 const struct re_revision *rr; 660 const char *re_name = NULL; 661 int ntxsegs; 662 663 sc->sc_hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 664 665 switch (sc->sc_hwrev) { 666 case RL_HWREV_8139CPLUS: 667 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 668 sc->rl_max_mtu = RL_MTU; 669 break; 670 case RL_HWREV_8100E: 671 case RL_HWREV_8100E_SPIN2: 672 case RL_HWREV_8101E: 673 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 674 sc->rl_max_mtu = RL_MTU; 675 break; 676 case RL_HWREV_8103E: 677 sc->rl_flags |= RL_FLAG_MACSLEEP; 678 /* FALLTHROUGH */ 679 case RL_HWREV_8102E: 680 case RL_HWREV_8102EL: 681 case RL_HWREV_8102EL_SPIN1: 682 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 683 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | 684 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 685 sc->rl_max_mtu = RL_MTU; 686 break; 687 case RL_HWREV_8401E: 688 case RL_HWREV_8105E: 689 case RL_HWREV_8105E_SPIN1: 690 case RL_HWREV_8106E: 691 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 692 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 693 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 694 sc->rl_max_mtu = RL_MTU; 695 break; 696 case RL_HWREV_8402: 697 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 698 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 699 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 700 RL_FLAG_CMDSTOP_WAIT_TXQ; 701 sc->rl_max_mtu = RL_MTU; 702 break; 703 case RL_HWREV_8168B_SPIN1: 704 case RL_HWREV_8168B_SPIN2: 705 sc->rl_flags |= RL_FLAG_WOLRXENB; 706 /* FALLTHROUGH */ 707 case RL_HWREV_8168B_SPIN3: 708 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 709 sc->rl_max_mtu = RL_MTU; 710 break; 711 case RL_HWREV_8168C_SPIN2: 712 sc->rl_flags |= RL_FLAG_MACSLEEP; 713 /* FALLTHROUGH */ 714 case RL_HWREV_8168C: 715 case RL_HWREV_8168CP: 716 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 717 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 718 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 719 sc->rl_max_mtu = RL_JUMBO_MTU_6K; 720 break; 721 case RL_HWREV_8168D: 722 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 723 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 724 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 725 RL_FLAG_WOL_MANLINK; 726 sc->rl_max_mtu = RL_JUMBO_MTU_9K; 727 break; 728 case RL_HWREV_8168DP: 729 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 730 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 731 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 732 sc->rl_max_mtu = RL_JUMBO_MTU_9K; 733 break; 734 case RL_HWREV_8168E: 735 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 736 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 737 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 738 RL_FLAG_WOL_MANLINK; 739 sc->rl_max_mtu = RL_JUMBO_MTU_9K; 740 break; 741 case RL_HWREV_8168E_VL: 742 sc->rl_flags |= RL_FLAG_EARLYOFF | RL_FLAG_PHYWAKE | RL_FLAG_PAR | 743 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 744 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_CMDSTOP_WAIT_TXQ | 745 RL_FLAG_WOL_MANLINK; 746 sc->rl_max_mtu = RL_JUMBO_MTU_6K; 747 break; 748 case RL_HWREV_8168F: 749 sc->rl_flags |= RL_FLAG_EARLYOFF; 750 /* FALLTHROUGH */ 751 case RL_HWREV_8411: 752 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 753 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 754 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_CMDSTOP_WAIT_TXQ | 755 RL_FLAG_WOL_MANLINK; 756 sc->rl_max_mtu = RL_JUMBO_MTU_9K; 757 break; 758 case RL_HWREV_8168EP: 759 case RL_HWREV_8168G: 760 case RL_HWREV_8168GU: 761 case RL_HWREV_8168H: 762 case RL_HWREV_8411B: 763 if (sc->sc_product == PCI_PRODUCT_REALTEK_RT8101E) { 764 /* RTL8106EUS */ 765 sc->rl_flags |= RL_FLAG_FASTETHER; 766 sc->rl_max_mtu = RL_MTU; 767 } else { 768 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 769 sc->rl_max_mtu = RL_JUMBO_MTU_9K; 770 } 771 772 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 773 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 774 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 775 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED; 776 break; 777 case RL_HWREV_8169_8110SB: 778 case RL_HWREV_8169_8110SBL: 779 case RL_HWREV_8169_8110SCd: 780 case RL_HWREV_8169_8110SCe: 781 sc->rl_flags |= RL_FLAG_PHYWAKE; 782 /* FALLTHROUGH */ 783 case RL_HWREV_8169: 784 case RL_HWREV_8169S: 785 case RL_HWREV_8110S: 786 sc->rl_flags |= RL_FLAG_MACRESET; 787 sc->rl_max_mtu = RL_JUMBO_MTU_7K; 788 break; 789 default: 790 break; 791 } 792 793 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) { 794 sc->rl_cfg0 = RL_8139_CFG0; 795 sc->rl_cfg1 = RL_8139_CFG1; 796 sc->rl_cfg2 = 0; 797 sc->rl_cfg3 = RL_8139_CFG3; 798 sc->rl_cfg4 = RL_8139_CFG4; 799 sc->rl_cfg5 = RL_8139_CFG5; 800 } else { 801 sc->rl_cfg0 = RL_CFG0; 802 sc->rl_cfg1 = RL_CFG1; 803 sc->rl_cfg2 = RL_CFG2; 804 sc->rl_cfg3 = RL_CFG3; 805 sc->rl_cfg4 = RL_CFG4; 806 sc->rl_cfg5 = RL_CFG5; 807 } 808 809 /* Reset the adapter. */ 810 re_reset(sc); 811 812 sc->rl_tx_time = 5; /* 125us */ 813 sc->rl_rx_time = 2; /* 50us */ 814 if (sc->rl_flags & RL_FLAG_PCIE) 815 sc->rl_sim_time = 75; /* 75us */ 816 else 817 sc->rl_sim_time = 125; /* 125us */ 818 sc->rl_imtype = RL_IMTYPE_SIM; /* simulated interrupt moderation */ 819 820 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 821 sc->rl_bus_speed = 33; /* XXX */ 822 else if (sc->rl_flags & RL_FLAG_PCIE) 823 sc->rl_bus_speed = 125; 824 else { 825 u_int8_t cfg2; 826 827 cfg2 = CSR_READ_1(sc, sc->rl_cfg2); 828 switch (cfg2 & RL_CFG2_PCI_MASK) { 829 case RL_CFG2_PCI_33MHZ: 830 sc->rl_bus_speed = 33; 831 break; 832 case RL_CFG2_PCI_66MHZ: 833 sc->rl_bus_speed = 66; 834 break; 835 default: 836 printf("%s: unknown bus speed, assume 33MHz\n", 837 sc->sc_dev.dv_xname); 838 sc->rl_bus_speed = 33; 839 break; 840 } 841 842 if (cfg2 & RL_CFG2_PCI_64BIT) 843 sc->rl_flags |= RL_FLAG_PCI64; 844 } 845 846 re_config_imtype(sc, sc->rl_imtype); 847 848 if (sc->rl_flags & RL_FLAG_PAR) { 849 /* 850 * XXX Should have a better way to extract station 851 * address from EEPROM. 852 */ 853 for (i = 0; i < ETHER_ADDR_LEN; i++) 854 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 855 } else { 856 sc->rl_eewidth = RL_9356_ADDR_LEN; 857 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 858 if (re_did != 0x8129) 859 sc->rl_eewidth = RL_9346_ADDR_LEN; 860 861 /* 862 * Get station address from the EEPROM. 863 */ 864 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 865 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 866 as[i] = letoh16(as[i]); 867 bcopy(as, eaddr, ETHER_ADDR_LEN); 868 } 869 870 /* 871 * Set RX length mask, TX poll request register 872 * and descriptor count. 873 */ 874 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) { 875 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 876 sc->rl_txstart = RL_TXSTART; 877 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 878 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 879 ntxsegs = RL_8139_NTXSEGS; 880 } else { 881 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 882 sc->rl_txstart = RL_GTXSTART; 883 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 884 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 885 ntxsegs = RL_8169_NTXSEGS; 886 } 887 888 bcopy(eaddr, (char *)&sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 889 890 for (rr = re_revisions; rr->re_name != NULL; rr++) { 891 if (rr->re_chipid == sc->sc_hwrev) 892 re_name = rr->re_name; 893 } 894 895 if (re_name == NULL) 896 printf(": unknown ASIC (0x%04x)", sc->sc_hwrev >> 16); 897 else 898 printf(": %s (0x%04x)", re_name, sc->sc_hwrev >> 16); 899 900 printf(", %s, address %s\n", intrstr, 901 ether_sprintf(sc->sc_arpcom.ac_enaddr)); 902 903 if (sc->rl_ldata.rl_tx_desc_cnt > 904 PAGE_SIZE / sizeof(struct rl_desc)) { 905 sc->rl_ldata.rl_tx_desc_cnt = 906 PAGE_SIZE / sizeof(struct rl_desc); 907 } 908 909 /* Allocate DMA'able memory for the TX ring */ 910 if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_TX_LIST_SZ(sc), 911 RL_RING_ALIGN, 0, &sc->rl_ldata.rl_tx_listseg, 1, 912 &sc->rl_ldata.rl_tx_listnseg, BUS_DMA_NOWAIT | 913 BUS_DMA_ZERO)) != 0) { 914 printf("%s: can't allocate tx listseg, error = %d\n", 915 sc->sc_dev.dv_xname, error); 916 goto fail_0; 917 } 918 919 /* Load the map for the TX ring. */ 920 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_tx_listseg, 921 sc->rl_ldata.rl_tx_listnseg, RL_TX_LIST_SZ(sc), 922 (caddr_t *)&sc->rl_ldata.rl_tx_list, 923 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 924 printf("%s: can't map tx list, error = %d\n", 925 sc->sc_dev.dv_xname, error); 926 goto fail_1; 927 } 928 929 if ((error = bus_dmamap_create(sc->sc_dmat, RL_TX_LIST_SZ(sc), 1, 930 RL_TX_LIST_SZ(sc), 0, 0, 931 &sc->rl_ldata.rl_tx_list_map)) != 0) { 932 printf("%s: can't create tx list map, error = %d\n", 933 sc->sc_dev.dv_xname, error); 934 goto fail_2; 935 } 936 937 if ((error = bus_dmamap_load(sc->sc_dmat, 938 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 939 RL_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 940 printf("%s: can't load tx list, error = %d\n", 941 sc->sc_dev.dv_xname, error); 942 goto fail_3; 943 } 944 945 /* Create DMA maps for TX buffers */ 946 for (i = 0; i < RL_TX_QLEN; i++) { 947 error = bus_dmamap_create(sc->sc_dmat, 948 RL_JUMBO_FRAMELEN, ntxsegs, RL_JUMBO_FRAMELEN, 949 0, 0, &sc->rl_ldata.rl_txq[i].txq_dmamap); 950 if (error) { 951 printf("%s: can't create DMA map for TX\n", 952 sc->sc_dev.dv_xname); 953 goto fail_4; 954 } 955 } 956 957 /* Allocate DMA'able memory for the RX ring */ 958 if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_RX_DMAMEM_SZ(sc), 959 RL_RING_ALIGN, 0, &sc->rl_ldata.rl_rx_listseg, 1, 960 &sc->rl_ldata.rl_rx_listnseg, BUS_DMA_NOWAIT | 961 BUS_DMA_ZERO)) != 0) { 962 printf("%s: can't allocate rx listnseg, error = %d\n", 963 sc->sc_dev.dv_xname, error); 964 goto fail_4; 965 } 966 967 /* Load the map for the RX ring. */ 968 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_rx_listseg, 969 sc->rl_ldata.rl_rx_listnseg, RL_RX_DMAMEM_SZ(sc), 970 (caddr_t *)&sc->rl_ldata.rl_rx_list, 971 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 972 printf("%s: can't map rx list, error = %d\n", 973 sc->sc_dev.dv_xname, error); 974 goto fail_5; 975 976 } 977 978 if ((error = bus_dmamap_create(sc->sc_dmat, RL_RX_DMAMEM_SZ(sc), 1, 979 RL_RX_DMAMEM_SZ(sc), 0, 0, 980 &sc->rl_ldata.rl_rx_list_map)) != 0) { 981 printf("%s: can't create rx list map, error = %d\n", 982 sc->sc_dev.dv_xname, error); 983 goto fail_6; 984 } 985 986 if ((error = bus_dmamap_load(sc->sc_dmat, 987 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 988 RL_RX_DMAMEM_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 989 printf("%s: can't load rx list, error = %d\n", 990 sc->sc_dev.dv_xname, error); 991 goto fail_7; 992 } 993 994 /* Create DMA maps for RX buffers */ 995 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 996 error = bus_dmamap_create(sc->sc_dmat, 997 RL_FRAMELEN(sc->rl_max_mtu), 1, 998 RL_FRAMELEN(sc->rl_max_mtu), 0, 0, 999 &sc->rl_ldata.rl_rxsoft[i].rxs_dmamap); 1000 if (error) { 1001 printf("%s: can't create DMA map for RX\n", 1002 sc->sc_dev.dv_xname); 1003 goto fail_8; 1004 } 1005 } 1006 1007 ifp = &sc->sc_arpcom.ac_if; 1008 ifp->if_softc = sc; 1009 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 1010 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1011 ifp->if_xflags = IFXF_MPSAFE; 1012 ifp->if_ioctl = re_ioctl; 1013 ifp->if_start = re_start; 1014 ifp->if_watchdog = re_watchdog; 1015 ifp->if_hardmtu = sc->rl_max_mtu; 1016 IFQ_SET_MAXLEN(&ifp->if_snd, RL_TX_QLEN); 1017 1018 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_TCPv4 | 1019 IFCAP_CSUM_UDPv4; 1020 1021 /* 1022 * RTL8168/8111C generates wrong IP checksummed frame if the 1023 * packet has IP options so disable TX IP checksum offloading. 1024 */ 1025 switch (sc->sc_hwrev) { 1026 case RL_HWREV_8168C: 1027 case RL_HWREV_8168C_SPIN2: 1028 case RL_HWREV_8168CP: 1029 break; 1030 default: 1031 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1032 } 1033 1034 #if NVLAN > 0 1035 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1036 #endif 1037 1038 #ifndef SMALL_KERNEL 1039 ifp->if_capabilities |= IFCAP_WOL; 1040 ifp->if_wol = re_wol; 1041 re_wol(ifp, 0); 1042 #endif 1043 timeout_set(&sc->timer_handle, re_tick, sc); 1044 1045 /* Take PHY out of power down mode. */ 1046 if (sc->rl_flags & RL_FLAG_PHYWAKE_PM) { 1047 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1048 if (sc->sc_hwrev == RL_HWREV_8401E) 1049 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1050 } 1051 if (sc->rl_flags & RL_FLAG_PHYWAKE) { 1052 re_gmii_writereg((struct device *)sc, 1, 0x1f, 0); 1053 re_gmii_writereg((struct device *)sc, 1, 0x0e, 0); 1054 } 1055 1056 /* Do MII setup */ 1057 sc->sc_mii.mii_ifp = ifp; 1058 sc->sc_mii.mii_readreg = re_miibus_readreg; 1059 sc->sc_mii.mii_writereg = re_miibus_writereg; 1060 sc->sc_mii.mii_statchg = re_miibus_statchg; 1061 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, re_ifmedia_upd, 1062 re_ifmedia_sts); 1063 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1064 MII_OFFSET_ANY, MIIF_DOPAUSE); 1065 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1066 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 1067 ifmedia_add(&sc->sc_mii.mii_media, 1068 IFM_ETHER|IFM_NONE, 0, NULL); 1069 ifmedia_set(&sc->sc_mii.mii_media, 1070 IFM_ETHER|IFM_NONE); 1071 } else 1072 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1073 1074 /* 1075 * Call MI attach routine. 1076 */ 1077 if_attach(ifp); 1078 ether_ifattach(ifp); 1079 1080 return (0); 1081 1082 fail_8: 1083 /* Destroy DMA maps for RX buffers. */ 1084 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1085 if (sc->rl_ldata.rl_rxsoft[i].rxs_dmamap != NULL) 1086 bus_dmamap_destroy(sc->sc_dmat, 1087 sc->rl_ldata.rl_rxsoft[i].rxs_dmamap); 1088 } 1089 1090 /* Free DMA'able memory for the RX ring. */ 1091 bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map); 1092 fail_7: 1093 bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map); 1094 fail_6: 1095 bus_dmamem_unmap(sc->sc_dmat, 1096 (caddr_t)sc->rl_ldata.rl_rx_list, RL_RX_DMAMEM_SZ(sc)); 1097 fail_5: 1098 bus_dmamem_free(sc->sc_dmat, 1099 &sc->rl_ldata.rl_rx_listseg, sc->rl_ldata.rl_rx_listnseg); 1100 1101 fail_4: 1102 /* Destroy DMA maps for TX buffers. */ 1103 for (i = 0; i < RL_TX_QLEN; i++) { 1104 if (sc->rl_ldata.rl_txq[i].txq_dmamap != NULL) 1105 bus_dmamap_destroy(sc->sc_dmat, 1106 sc->rl_ldata.rl_txq[i].txq_dmamap); 1107 } 1108 1109 /* Free DMA'able memory for the TX ring. */ 1110 bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map); 1111 fail_3: 1112 bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map); 1113 fail_2: 1114 bus_dmamem_unmap(sc->sc_dmat, 1115 (caddr_t)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ(sc)); 1116 fail_1: 1117 bus_dmamem_free(sc->sc_dmat, 1118 &sc->rl_ldata.rl_tx_listseg, sc->rl_ldata.rl_tx_listnseg); 1119 fail_0: 1120 return (1); 1121 } 1122 1123 1124 int 1125 re_newbuf(struct rl_softc *sc) 1126 { 1127 struct mbuf *m; 1128 bus_dmamap_t map; 1129 struct rl_desc *d; 1130 struct rl_rxsoft *rxs; 1131 u_int32_t cmdstat; 1132 int error, idx; 1133 1134 m = MCLGETI(NULL, M_DONTWAIT, NULL, RL_FRAMELEN(sc->rl_max_mtu)); 1135 if (!m) 1136 return (ENOBUFS); 1137 1138 /* 1139 * Initialize mbuf length fields and fixup 1140 * alignment so that the frame payload is 1141 * longword aligned on strict alignment archs. 1142 */ 1143 m->m_len = m->m_pkthdr.len = RL_FRAMELEN(sc->rl_max_mtu); 1144 m->m_data += RE_ETHER_ALIGN; 1145 1146 idx = sc->rl_ldata.rl_rx_prodidx; 1147 rxs = &sc->rl_ldata.rl_rxsoft[idx]; 1148 map = rxs->rxs_dmamap; 1149 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1150 BUS_DMA_READ|BUS_DMA_NOWAIT); 1151 if (error) { 1152 m_freem(m); 1153 return (ENOBUFS); 1154 } 1155 1156 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1157 BUS_DMASYNC_PREREAD); 1158 1159 d = &sc->rl_ldata.rl_rx_list[idx]; 1160 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1161 cmdstat = letoh32(d->rl_cmdstat); 1162 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1163 if (cmdstat & RL_RDESC_STAT_OWN) { 1164 printf("%s: tried to map busy RX descriptor\n", 1165 sc->sc_dev.dv_xname); 1166 m_freem(m); 1167 return (ENOBUFS); 1168 } 1169 1170 rxs->rxs_mbuf = m; 1171 1172 d->rl_vlanctl = 0; 1173 cmdstat = map->dm_segs[0].ds_len; 1174 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1175 cmdstat |= RL_RDESC_CMD_EOR; 1176 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1177 d->rl_cmdstat = htole32(cmdstat); 1178 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1179 cmdstat |= RL_RDESC_CMD_OWN; 1180 d->rl_cmdstat = htole32(cmdstat); 1181 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1182 1183 sc->rl_ldata.rl_rx_prodidx = RL_NEXT_RX_DESC(sc, idx); 1184 1185 return (0); 1186 } 1187 1188 1189 int 1190 re_tx_list_init(struct rl_softc *sc) 1191 { 1192 int i; 1193 1194 memset(sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ(sc)); 1195 for (i = 0; i < RL_TX_QLEN; i++) { 1196 sc->rl_ldata.rl_txq[i].txq_mbuf = NULL; 1197 } 1198 1199 bus_dmamap_sync(sc->sc_dmat, 1200 sc->rl_ldata.rl_tx_list_map, 0, 1201 sc->rl_ldata.rl_tx_list_map->dm_mapsize, 1202 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1203 sc->rl_ldata.rl_txq_prodidx = 0; 1204 sc->rl_ldata.rl_txq_considx = 0; 1205 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1206 sc->rl_ldata.rl_tx_nextfree = 0; 1207 1208 return (0); 1209 } 1210 1211 int 1212 re_rx_list_init(struct rl_softc *sc) 1213 { 1214 bzero(sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ(sc)); 1215 1216 sc->rl_ldata.rl_rx_prodidx = 0; 1217 sc->rl_ldata.rl_rx_considx = 0; 1218 sc->rl_head = sc->rl_tail = NULL; 1219 1220 if_rxr_init(&sc->rl_ldata.rl_rx_ring, 2, sc->rl_ldata.rl_rx_desc_cnt); 1221 re_rx_list_fill(sc); 1222 1223 return (0); 1224 } 1225 1226 void 1227 re_rx_list_fill(struct rl_softc *sc) 1228 { 1229 u_int slots; 1230 1231 for (slots = if_rxr_get(&sc->rl_ldata.rl_rx_ring, 1232 sc->rl_ldata.rl_rx_desc_cnt); 1233 slots > 0; slots--) { 1234 if (re_newbuf(sc) == ENOBUFS) 1235 break; 1236 } 1237 if_rxr_put(&sc->rl_ldata.rl_rx_ring, slots); 1238 } 1239 1240 /* 1241 * RX handler for C+ and 8169. For the gigE chips, we support 1242 * the reception of jumbo frames that have been fragmented 1243 * across multiple 2K mbuf cluster buffers. 1244 */ 1245 int 1246 re_rxeof(struct rl_softc *sc) 1247 { 1248 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1249 struct mbuf *m; 1250 struct ifnet *ifp; 1251 int i, total_len, rx = 0; 1252 struct rl_desc *cur_rx; 1253 struct rl_rxsoft *rxs; 1254 u_int32_t rxstat, rxvlan; 1255 1256 ifp = &sc->sc_arpcom.ac_if; 1257 1258 for (i = sc->rl_ldata.rl_rx_considx; 1259 if_rxr_inuse(&sc->rl_ldata.rl_rx_ring) > 0; 1260 i = RL_NEXT_RX_DESC(sc, i)) { 1261 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1262 RL_RXDESCSYNC(sc, i, 1263 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1264 rxstat = letoh32(cur_rx->rl_cmdstat); 1265 rxvlan = letoh32(cur_rx->rl_vlanctl); 1266 RL_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1267 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1268 break; 1269 total_len = rxstat & sc->rl_rxlenmask; 1270 rxs = &sc->rl_ldata.rl_rxsoft[i]; 1271 m = rxs->rxs_mbuf; 1272 rxs->rxs_mbuf = NULL; 1273 if_rxr_put(&sc->rl_ldata.rl_rx_ring, 1); 1274 rx = 1; 1275 1276 /* Invalidate the RX mbuf and unload its map */ 1277 1278 bus_dmamap_sync(sc->sc_dmat, 1279 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1280 BUS_DMASYNC_POSTREAD); 1281 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1282 1283 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 1284 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 1285 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 1286 continue; 1287 } else if (!(rxstat & RL_RDESC_STAT_EOF)) { 1288 m->m_len = RL_FRAMELEN(sc->rl_max_mtu); 1289 if (sc->rl_head == NULL) 1290 sc->rl_head = sc->rl_tail = m; 1291 else { 1292 m->m_flags &= ~M_PKTHDR; 1293 sc->rl_tail->m_next = m; 1294 sc->rl_tail = m; 1295 } 1296 continue; 1297 } 1298 1299 /* 1300 * NOTE: for the 8139C+, the frame length field 1301 * is always 12 bits in size, but for the gigE chips, 1302 * it is 13 bits (since the max RX frame length is 16K). 1303 * Unfortunately, all 32 bits in the status word 1304 * were already used, so to make room for the extra 1305 * length bit, Realtek took out the 'frame alignment 1306 * error' bit and shifted the other status bits 1307 * over one slot. The OWN, EOR, FS and LS bits are 1308 * still in the same places. We have already extracted 1309 * the frame length and checked the OWN bit, so rather 1310 * than using an alternate bit mapping, we shift the 1311 * status bits one space to the right so we can evaluate 1312 * them using the 8169 status as though it was in the 1313 * same format as that of the 8139C+. 1314 */ 1315 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) 1316 rxstat >>= 1; 1317 1318 /* 1319 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1320 * set, but if CRC is clear, it will still be a valid frame. 1321 */ 1322 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0 && 1323 !(rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1324 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT))) { 1325 ifp->if_ierrors++; 1326 /* 1327 * If this is part of a multi-fragment packet, 1328 * discard all the pieces. 1329 */ 1330 if (sc->rl_head != NULL) { 1331 m_freem(sc->rl_head); 1332 sc->rl_head = sc->rl_tail = NULL; 1333 } 1334 continue; 1335 } 1336 1337 if (sc->rl_head != NULL) { 1338 m->m_len = total_len % RL_FRAMELEN(sc->rl_max_mtu); 1339 if (m->m_len == 0) 1340 m->m_len = RL_FRAMELEN(sc->rl_max_mtu); 1341 /* 1342 * Special case: if there's 4 bytes or less 1343 * in this buffer, the mbuf can be discarded: 1344 * the last 4 bytes is the CRC, which we don't 1345 * care about anyway. 1346 */ 1347 if (m->m_len <= ETHER_CRC_LEN) { 1348 sc->rl_tail->m_len -= 1349 (ETHER_CRC_LEN - m->m_len); 1350 m_freem(m); 1351 } else { 1352 m->m_len -= ETHER_CRC_LEN; 1353 m->m_flags &= ~M_PKTHDR; 1354 sc->rl_tail->m_next = m; 1355 } 1356 m = sc->rl_head; 1357 sc->rl_head = sc->rl_tail = NULL; 1358 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1359 } else 1360 m->m_pkthdr.len = m->m_len = 1361 (total_len - ETHER_CRC_LEN); 1362 1363 /* Do RX checksumming */ 1364 1365 if (sc->rl_flags & RL_FLAG_DESCV2) { 1366 /* Check IP header checksum */ 1367 if ((rxvlan & RL_RDESC_IPV4) && 1368 !(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1369 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1370 1371 /* Check TCP/UDP checksum */ 1372 if ((rxvlan & (RL_RDESC_IPV4|RL_RDESC_IPV6)) && 1373 (((rxstat & RL_RDESC_STAT_TCP) && 1374 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1375 ((rxstat & RL_RDESC_STAT_UDP) && 1376 !(rxstat & RL_RDESC_STAT_UDPSUMBAD)))) 1377 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 1378 M_UDP_CSUM_IN_OK; 1379 } else { 1380 /* Check IP header checksum */ 1381 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1382 !(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1383 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1384 1385 /* Check TCP/UDP checksum */ 1386 if ((RL_TCPPKT(rxstat) && 1387 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1388 (RL_UDPPKT(rxstat) && 1389 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) 1390 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 1391 M_UDP_CSUM_IN_OK; 1392 } 1393 #if NVLAN > 0 1394 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1395 m->m_pkthdr.ether_vtag = 1396 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1397 m->m_flags |= M_VLANTAG; 1398 } 1399 #endif 1400 1401 ml_enqueue(&ml, m); 1402 } 1403 1404 sc->rl_ldata.rl_rx_considx = i; 1405 re_rx_list_fill(sc); 1406 1407 if_input(ifp, &ml); 1408 1409 return (rx); 1410 } 1411 1412 int 1413 re_txeof(struct rl_softc *sc) 1414 { 1415 struct ifnet *ifp; 1416 struct rl_txq *txq; 1417 uint32_t txstat; 1418 int idx, descidx, tx_free, freed = 0; 1419 1420 ifp = &sc->sc_arpcom.ac_if; 1421 1422 for (idx = sc->rl_ldata.rl_txq_considx; 1423 idx != sc->rl_ldata.rl_txq_prodidx; idx = RL_NEXT_TXQ(sc, idx)) { 1424 txq = &sc->rl_ldata.rl_txq[idx]; 1425 1426 descidx = txq->txq_descidx; 1427 RL_TXDESCSYNC(sc, descidx, 1428 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1429 txstat = 1430 letoh32(sc->rl_ldata.rl_tx_list[descidx].rl_cmdstat); 1431 RL_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1432 KASSERT((txstat & RL_TDESC_CMD_EOF) != 0); 1433 if (txstat & RL_TDESC_CMD_OWN) 1434 break; 1435 1436 freed += txq->txq_nsegs; 1437 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1438 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1439 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1440 m_freem(txq->txq_mbuf); 1441 txq->txq_mbuf = NULL; 1442 1443 if (txstat & (RL_TDESC_STAT_EXCESSCOL | RL_TDESC_STAT_COLCNT)) 1444 ifp->if_collisions++; 1445 if (txstat & RL_TDESC_STAT_TXERRSUM) 1446 ifp->if_oerrors++; 1447 else 1448 ifp->if_opackets++; 1449 } 1450 1451 if (freed == 0) 1452 return (0); 1453 1454 tx_free = atomic_add_int_nv(&sc->rl_ldata.rl_tx_free, freed); 1455 KASSERT(tx_free <= sc->rl_ldata.rl_tx_desc_cnt); 1456 1457 sc->rl_ldata.rl_txq_considx = idx; 1458 1459 /* 1460 * Some chips will ignore a second TX request issued while an 1461 * existing transmission is in progress. If the transmitter goes 1462 * idle but there are still packets waiting to be sent, we need 1463 * to restart the channel here to flush them out. This only 1464 * seems to be required with the PCIe devices. 1465 */ 1466 if (ifq_is_oactive(&ifp->if_snd)) 1467 ifq_restart(&ifp->if_snd); 1468 else if (tx_free < sc->rl_ldata.rl_tx_desc_cnt) 1469 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1470 else 1471 ifp->if_timer = 0; 1472 1473 return (1); 1474 } 1475 1476 void 1477 re_tick(void *xsc) 1478 { 1479 struct rl_softc *sc = xsc; 1480 struct mii_data *mii; 1481 int s; 1482 1483 mii = &sc->sc_mii; 1484 1485 s = splnet(); 1486 1487 mii_tick(mii); 1488 1489 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 1490 re_miibus_statchg(&sc->sc_dev); 1491 1492 splx(s); 1493 1494 timeout_add_sec(&sc->timer_handle, 1); 1495 } 1496 1497 int 1498 re_intr(void *arg) 1499 { 1500 struct rl_softc *sc = arg; 1501 struct ifnet *ifp; 1502 u_int16_t status; 1503 int claimed = 0, rx, tx; 1504 1505 ifp = &sc->sc_arpcom.ac_if; 1506 1507 if (!(ifp->if_flags & IFF_RUNNING)) 1508 return (0); 1509 1510 /* Disable interrupts. */ 1511 CSR_WRITE_2(sc, RL_IMR, 0); 1512 1513 rx = tx = 0; 1514 status = CSR_READ_2(sc, RL_ISR); 1515 /* If the card has gone away the read returns 0xffff. */ 1516 if (status == 0xffff) 1517 return (0); 1518 if (status) 1519 CSR_WRITE_2(sc, RL_ISR, status); 1520 1521 if (status & RL_ISR_TIMEOUT_EXPIRED) 1522 claimed = 1; 1523 1524 if (status & RL_INTRS_CPLUS) { 1525 if (status & (sc->rl_rx_ack | RL_ISR_RX_ERR)) { 1526 rx |= re_rxeof(sc); 1527 claimed = 1; 1528 } 1529 1530 if (status & (sc->rl_tx_ack | RL_ISR_TX_ERR)) { 1531 tx |= re_txeof(sc); 1532 claimed = 1; 1533 } 1534 1535 if (status & RL_ISR_SYSTEM_ERR) { 1536 KERNEL_LOCK(); 1537 re_init(ifp); 1538 KERNEL_UNLOCK(); 1539 claimed = 1; 1540 } 1541 } 1542 1543 if (sc->rl_imtype == RL_IMTYPE_SIM) { 1544 if (sc->rl_timerintr) { 1545 if ((tx | rx) == 0) { 1546 /* 1547 * Nothing needs to be processed, fallback 1548 * to use TX/RX interrupts. 1549 */ 1550 re_setup_intr(sc, 1, RL_IMTYPE_NONE); 1551 1552 /* 1553 * Recollect, mainly to avoid the possible 1554 * race introduced by changing interrupt 1555 * masks. 1556 */ 1557 re_rxeof(sc); 1558 re_txeof(sc); 1559 } else 1560 CSR_WRITE_4(sc, RL_TIMERCNT, 1); /* reload */ 1561 } else if (tx | rx) { 1562 /* 1563 * Assume that using simulated interrupt moderation 1564 * (hardware timer based) could reduce the interrupt 1565 * rate. 1566 */ 1567 re_setup_intr(sc, 1, RL_IMTYPE_SIM); 1568 } 1569 } 1570 1571 CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs); 1572 1573 return (claimed); 1574 } 1575 1576 int 1577 re_encap(struct rl_softc *sc, struct mbuf *m, struct rl_txq *txq, int *used) 1578 { 1579 bus_dmamap_t map; 1580 struct mbuf *mp, mh; 1581 int error, seg, nsegs, uidx, startidx, curidx, lastidx, pad; 1582 int off; 1583 struct ip *ip; 1584 struct rl_desc *d; 1585 u_int32_t cmdstat, vlanctl = 0, csum_flags = 0; 1586 1587 /* 1588 * Set up checksum offload. Note: checksum offload bits must 1589 * appear in all descriptors of a multi-descriptor transmit 1590 * attempt. This is according to testing done with an 8169 1591 * chip. This is a requirement. 1592 */ 1593 1594 /* 1595 * Set RL_TDESC_CMD_IPCSUM if any checksum offloading 1596 * is requested. Otherwise, RL_TDESC_CMD_TCPCSUM/ 1597 * RL_TDESC_CMD_UDPCSUM does not take affect. 1598 */ 1599 1600 if ((sc->rl_flags & RL_FLAG_JUMBOV2) && 1601 m->m_pkthdr.len > RL_MTU && 1602 (m->m_pkthdr.csum_flags & 1603 (M_IPV4_CSUM_OUT|M_TCP_CSUM_OUT|M_UDP_CSUM_OUT)) != 0) { 1604 mp = m_getptr(m, ETHER_HDR_LEN, &off); 1605 mh.m_flags = 0; 1606 mh.m_data = mtod(mp, caddr_t) + off; 1607 mh.m_next = mp->m_next; 1608 mh.m_pkthdr.len = mp->m_pkthdr.len - ETHER_HDR_LEN; 1609 mh.m_len = mp->m_len - off; 1610 ip = (struct ip *)mh.m_data; 1611 1612 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1613 ip->ip_sum = in_cksum(&mh, sizeof(struct ip)); 1614 if (m->m_pkthdr.csum_flags & (M_TCP_CSUM_OUT|M_UDP_CSUM_OUT)) 1615 in_delayed_cksum(&mh); 1616 1617 m->m_pkthdr.csum_flags &= 1618 ~(M_IPV4_CSUM_OUT|M_TCP_CSUM_OUT|M_UDP_CSUM_OUT); 1619 } 1620 1621 if ((m->m_pkthdr.csum_flags & 1622 (M_IPV4_CSUM_OUT|M_TCP_CSUM_OUT|M_UDP_CSUM_OUT)) != 0) { 1623 if (sc->rl_flags & RL_FLAG_DESCV2) { 1624 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 1625 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1626 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 1627 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1628 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 1629 } else { 1630 csum_flags |= RL_TDESC_CMD_IPCSUM; 1631 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1632 csum_flags |= RL_TDESC_CMD_TCPCSUM; 1633 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1634 csum_flags |= RL_TDESC_CMD_UDPCSUM; 1635 } 1636 } 1637 1638 map = txq->txq_dmamap; 1639 1640 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1641 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1642 switch (error) { 1643 case 0: 1644 break; 1645 1646 case EFBIG: 1647 if (m_defrag(m, M_DONTWAIT) == 0 && 1648 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1649 BUS_DMA_WRITE|BUS_DMA_NOWAIT) == 0) 1650 break; 1651 1652 /* FALLTHROUGH */ 1653 default: 1654 return (ENOMEM); 1655 } 1656 1657 nsegs = map->dm_nsegs; 1658 pad = 0; 1659 1660 /* 1661 * With some of the RealTek chips, using the checksum offload 1662 * support in conjunction with the autopadding feature results 1663 * in the transmission of corrupt frames. For example, if we 1664 * need to send a really small IP fragment that's less than 60 1665 * bytes in size, and IP header checksumming is enabled, the 1666 * resulting ethernet frame that appears on the wire will 1667 * have garbled payload. To work around this, if TX IP checksum 1668 * offload is enabled, we always manually pad short frames out 1669 * to the minimum ethernet frame size. 1670 */ 1671 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 1672 m->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 1673 (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) != 0) { 1674 pad = 1; 1675 nsegs++; 1676 } 1677 1678 if (*used + nsegs + 1 >= sc->rl_ldata.rl_tx_free) { 1679 error = ENOBUFS; 1680 goto fail_unload; 1681 } 1682 1683 /* 1684 * Make sure that the caches are synchronized before we 1685 * ask the chip to start DMA for the packet data. 1686 */ 1687 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1688 BUS_DMASYNC_PREWRITE); 1689 1690 /* 1691 * Set up hardware VLAN tagging. Note: vlan tag info must 1692 * appear in all descriptors of a multi-descriptor 1693 * transmission attempt. 1694 */ 1695 #if NVLAN > 0 1696 if (m->m_flags & M_VLANTAG) 1697 vlanctl |= swap16(m->m_pkthdr.ether_vtag) | 1698 RL_TDESC_VLANCTL_TAG; 1699 #endif 1700 1701 /* 1702 * Map the segment array into descriptors. Note that we set the 1703 * start-of-frame and end-of-frame markers for either TX or RX, but 1704 * they really only have meaning in the TX case. (In the RX case, 1705 * it's the chip that tells us where packets begin and end.) 1706 * We also keep track of the end of the ring and set the 1707 * end-of-ring bits as needed, and we set the ownership bits 1708 * in all except the very first descriptor. (The caller will 1709 * set this descriptor later when it start transmission or 1710 * reception.) 1711 */ 1712 curidx = startidx = sc->rl_ldata.rl_tx_nextfree; 1713 lastidx = -1; 1714 for (seg = 0; seg < map->dm_nsegs; 1715 seg++, curidx = RL_NEXT_TX_DESC(sc, curidx)) { 1716 d = &sc->rl_ldata.rl_tx_list[curidx]; 1717 RL_TXDESCSYNC(sc, curidx, 1718 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1719 cmdstat = letoh32(d->rl_cmdstat); 1720 RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_PREREAD); 1721 if (cmdstat & RL_TDESC_STAT_OWN) { 1722 printf("%s: tried to map busy TX descriptor\n", 1723 sc->sc_dev.dv_xname); 1724 for (; seg > 0; seg --) { 1725 uidx = (curidx + sc->rl_ldata.rl_tx_desc_cnt - 1726 seg) % sc->rl_ldata.rl_tx_desc_cnt; 1727 sc->rl_ldata.rl_tx_list[uidx].rl_cmdstat = 0; 1728 RL_TXDESCSYNC(sc, uidx, 1729 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1730 } 1731 error = EBUSY; 1732 goto fail_unload; 1733 } 1734 1735 d->rl_vlanctl = htole32(vlanctl); 1736 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1737 cmdstat = csum_flags | map->dm_segs[seg].ds_len; 1738 if (seg == 0) 1739 cmdstat |= RL_TDESC_CMD_SOF; 1740 else 1741 cmdstat |= RL_TDESC_CMD_OWN; 1742 if (curidx == sc->rl_ldata.rl_tx_desc_cnt - 1) 1743 cmdstat |= RL_TDESC_CMD_EOR; 1744 if (seg == nsegs - 1) { 1745 cmdstat |= RL_TDESC_CMD_EOF; 1746 lastidx = curidx; 1747 } 1748 d->rl_cmdstat = htole32(cmdstat); 1749 RL_TXDESCSYNC(sc, curidx, 1750 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1751 } 1752 if (pad) { 1753 d = &sc->rl_ldata.rl_tx_list[curidx]; 1754 d->rl_vlanctl = htole32(vlanctl); 1755 re_set_bufaddr(d, RL_TXPADDADDR(sc)); 1756 cmdstat = csum_flags | 1757 RL_TDESC_CMD_OWN | RL_TDESC_CMD_EOF | 1758 (RL_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1759 if (curidx == sc->rl_ldata.rl_tx_desc_cnt - 1) 1760 cmdstat |= RL_TDESC_CMD_EOR; 1761 d->rl_cmdstat = htole32(cmdstat); 1762 RL_TXDESCSYNC(sc, curidx, 1763 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1764 lastidx = curidx; 1765 curidx = RL_NEXT_TX_DESC(sc, curidx); 1766 } 1767 KASSERT(lastidx != -1); 1768 1769 /* Transfer ownership of packet to the chip. */ 1770 1771 sc->rl_ldata.rl_tx_list[startidx].rl_cmdstat |= 1772 htole32(RL_TDESC_CMD_OWN); 1773 RL_TXDESCSYNC(sc, startidx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1774 1775 /* update info of TX queue and descriptors */ 1776 txq->txq_mbuf = m; 1777 txq->txq_descidx = lastidx; 1778 txq->txq_nsegs = nsegs; 1779 1780 sc->rl_ldata.rl_tx_nextfree = curidx; 1781 1782 *used += nsegs; 1783 1784 return (0); 1785 1786 fail_unload: 1787 bus_dmamap_unload(sc->sc_dmat, map); 1788 1789 return (error); 1790 } 1791 1792 /* 1793 * Main transmit routine for C+ and gigE NICs. 1794 */ 1795 1796 void 1797 re_start(struct ifnet *ifp) 1798 { 1799 struct rl_softc *sc = ifp->if_softc; 1800 struct mbuf *m; 1801 int idx, used = 0, txq_free, error; 1802 1803 if (!ISSET(sc->rl_flags, RL_FLAG_LINK)) { 1804 IFQ_PURGE(&ifp->if_snd); 1805 return; 1806 } 1807 1808 txq_free = sc->rl_ldata.rl_txq_considx; 1809 idx = sc->rl_ldata.rl_txq_prodidx; 1810 if (txq_free <= idx) 1811 txq_free += RL_TX_QLEN; 1812 txq_free -= idx; 1813 1814 for (;;) { 1815 if (txq_free <= 1) { 1816 ifq_set_oactive(&ifp->if_snd); 1817 break; 1818 } 1819 1820 m = ifq_deq_begin(&ifp->if_snd); 1821 if (m == NULL) 1822 break; 1823 1824 error = re_encap(sc, m, &sc->rl_ldata.rl_txq[idx], &used); 1825 if (error == 0) 1826 ifq_deq_commit(&ifp->if_snd, m); 1827 else if (error == ENOBUFS) { 1828 ifq_deq_rollback(&ifp->if_snd, m); 1829 ifq_set_oactive(&ifp->if_snd); 1830 break; 1831 } else { 1832 ifq_deq_commit(&ifp->if_snd, m); 1833 m_freem(m); 1834 ifp->if_oerrors++; 1835 continue; 1836 } 1837 1838 #if NBPFILTER > 0 1839 if (ifp->if_bpf) 1840 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1841 #endif 1842 idx = RL_NEXT_TXQ(sc, idx); 1843 txq_free--; 1844 } 1845 1846 if (used == 0) 1847 return; 1848 1849 ifp->if_timer = 5; 1850 atomic_sub_int(&sc->rl_ldata.rl_tx_free, used); 1851 KASSERT(sc->rl_ldata.rl_tx_free >= 0); 1852 1853 sc->rl_ldata.rl_txq_prodidx = idx; 1854 1855 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1856 } 1857 1858 int 1859 re_init(struct ifnet *ifp) 1860 { 1861 struct rl_softc *sc = ifp->if_softc; 1862 u_int16_t cfg; 1863 uint32_t rxcfg; 1864 int s; 1865 union { 1866 u_int32_t align_dummy; 1867 u_char eaddr[ETHER_ADDR_LEN]; 1868 } eaddr; 1869 1870 s = splnet(); 1871 1872 /* 1873 * Cancel pending I/O and free all RX/TX buffers. 1874 */ 1875 re_stop(ifp); 1876 1877 /* Put controller into known state. */ 1878 re_reset(sc); 1879 1880 /* 1881 * Enable C+ RX and TX mode, as well as VLAN stripping and 1882 * RX checksum offload. We must configure the C+ register 1883 * before all others. 1884 */ 1885 cfg = RL_CPLUSCMD_TXENB | RL_CPLUSCMD_PCI_MRW | 1886 RL_CPLUSCMD_RXCSUM_ENB; 1887 1888 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1889 cfg |= RL_CPLUSCMD_VLANSTRIP; 1890 1891 if (sc->rl_flags & RL_FLAG_MACSTAT) 1892 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 1893 else 1894 cfg |= RL_CPLUSCMD_RXENB; 1895 1896 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 1897 1898 /* 1899 * Init our MAC address. Even though the chipset 1900 * documentation doesn't mention it, we need to enter "Config 1901 * register write enable" mode to modify the ID registers. 1902 */ 1903 bcopy(sc->sc_arpcom.ac_enaddr, eaddr.eaddr, ETHER_ADDR_LEN); 1904 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1905 CSR_WRITE_4(sc, RL_IDR4, 1906 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 1907 CSR_WRITE_4(sc, RL_IDR0, 1908 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 1909 /* 1910 * Default on PC Engines APU1 is to have all LEDs off unless 1911 * there is network activity. Override to provide a link status 1912 * LED. 1913 */ 1914 if (sc->sc_hwrev == RL_HWREV_8168E && 1915 hw_vendor != NULL && hw_prod != NULL && 1916 strcmp(hw_vendor, "PC Engines") == 0 && 1917 strcmp(hw_prod, "APU") == 0) { 1918 CSR_SETBIT_1(sc, RL_CFG4, RL_CFG4_CUSTOM_LED); 1919 CSR_WRITE_1(sc, RL_LEDSEL, RL_LED_LINK | RL_LED_ACT << 4); 1920 } 1921 /* 1922 * Protect config register again 1923 */ 1924 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1925 1926 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1927 re_set_jumbo(sc); 1928 1929 /* 1930 * For C+ mode, initialize the RX descriptors and mbufs. 1931 */ 1932 re_rx_list_init(sc); 1933 re_tx_list_init(sc); 1934 1935 /* 1936 * Load the addresses of the RX and TX lists into the chip. 1937 */ 1938 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 1939 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr)); 1940 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 1941 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr)); 1942 1943 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 1944 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr)); 1945 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 1946 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr)); 1947 1948 if (sc->rl_flags & RL_FLAG_RXDV_GATED) 1949 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 1950 ~0x00080000); 1951 1952 /* 1953 * Set the initial TX and RX configuration. 1954 */ 1955 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1956 1957 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 1958 1959 rxcfg = RL_RXCFG_CONFIG; 1960 if (sc->rl_flags & RL_FLAG_EARLYOFF) 1961 rxcfg |= RL_RXCFG_EARLYOFF; 1962 else if (sc->rl_flags & RL_FLAG_EARLYOFFV2) 1963 rxcfg |= RL_RXCFG_EARLYOFFV2; 1964 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1965 1966 /* 1967 * Enable transmit and receive. 1968 */ 1969 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 1970 1971 /* Program promiscuous mode and multicast filters. */ 1972 re_iff(sc); 1973 1974 /* 1975 * Enable interrupts. 1976 */ 1977 re_setup_intr(sc, 1, sc->rl_imtype); 1978 CSR_WRITE_2(sc, RL_ISR, sc->rl_imtype); 1979 1980 /* Start RX/TX process. */ 1981 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1982 1983 /* 1984 * For 8169 gigE NICs, set the max allowed RX packet 1985 * size so we can receive jumbo frames. 1986 */ 1987 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) { 1988 if (sc->rl_flags & RL_FLAG_PCIE && 1989 (sc->rl_flags & RL_FLAG_JUMBOV2) == 0) 1990 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 1991 else 1992 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 1993 } 1994 1995 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 1996 RL_CFG1_DRVLOAD); 1997 1998 ifp->if_flags |= IFF_RUNNING; 1999 ifq_clr_oactive(&ifp->if_snd); 2000 2001 splx(s); 2002 2003 sc->rl_flags &= ~RL_FLAG_LINK; 2004 mii_mediachg(&sc->sc_mii); 2005 2006 timeout_add_sec(&sc->timer_handle, 1); 2007 2008 return (0); 2009 } 2010 2011 /* 2012 * Set media options. 2013 */ 2014 int 2015 re_ifmedia_upd(struct ifnet *ifp) 2016 { 2017 struct rl_softc *sc; 2018 2019 sc = ifp->if_softc; 2020 2021 return (mii_mediachg(&sc->sc_mii)); 2022 } 2023 2024 /* 2025 * Report current media status. 2026 */ 2027 void 2028 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2029 { 2030 struct rl_softc *sc; 2031 2032 sc = ifp->if_softc; 2033 2034 mii_pollstat(&sc->sc_mii); 2035 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2036 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2037 } 2038 2039 int 2040 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2041 { 2042 struct rl_softc *sc = ifp->if_softc; 2043 struct ifreq *ifr = (struct ifreq *) data; 2044 int s, error = 0; 2045 2046 s = splnet(); 2047 2048 switch(command) { 2049 case SIOCSIFADDR: 2050 ifp->if_flags |= IFF_UP; 2051 if (!(ifp->if_flags & IFF_RUNNING)) 2052 re_init(ifp); 2053 break; 2054 case SIOCSIFFLAGS: 2055 if (ifp->if_flags & IFF_UP) { 2056 if (ifp->if_flags & IFF_RUNNING) 2057 error = ENETRESET; 2058 else 2059 re_init(ifp); 2060 } else { 2061 if (ifp->if_flags & IFF_RUNNING) 2062 re_stop(ifp); 2063 } 2064 break; 2065 case SIOCGIFMEDIA: 2066 case SIOCSIFMEDIA: 2067 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 2068 break; 2069 case SIOCGIFRXR: 2070 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 2071 NULL, RL_FRAMELEN(sc->rl_max_mtu), &sc->rl_ldata.rl_rx_ring); 2072 break; 2073 default: 2074 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 2075 } 2076 2077 if (error == ENETRESET) { 2078 if (ifp->if_flags & IFF_RUNNING) 2079 re_iff(sc); 2080 error = 0; 2081 } 2082 2083 splx(s); 2084 return (error); 2085 } 2086 2087 void 2088 re_watchdog(struct ifnet *ifp) 2089 { 2090 struct rl_softc *sc; 2091 int s; 2092 2093 sc = ifp->if_softc; 2094 s = splnet(); 2095 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2096 2097 re_txeof(sc); 2098 re_rxeof(sc); 2099 2100 re_init(ifp); 2101 2102 splx(s); 2103 } 2104 2105 /* 2106 * Stop the adapter and free any mbufs allocated to the 2107 * RX and TX lists. 2108 */ 2109 void 2110 re_stop(struct ifnet *ifp) 2111 { 2112 struct rl_softc *sc; 2113 int i; 2114 2115 sc = ifp->if_softc; 2116 2117 ifp->if_timer = 0; 2118 sc->rl_flags &= ~RL_FLAG_LINK; 2119 sc->rl_timerintr = 0; 2120 2121 timeout_del(&sc->timer_handle); 2122 ifp->if_flags &= ~IFF_RUNNING; 2123 2124 /* 2125 * Disable accepting frames to put RX MAC into idle state. 2126 * Otherwise it's possible to get frames while stop command 2127 * execution is in progress and controller can DMA the frame 2128 * to already freed RX buffer during that period. 2129 */ 2130 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 2131 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | RL_RXCFG_RX_INDIV | 2132 RL_RXCFG_RX_MULTI)); 2133 2134 if (sc->rl_flags & RL_FLAG_WAIT_TXPOLL) { 2135 for (i = RL_TIMEOUT; i > 0; i--) { 2136 if ((CSR_READ_1(sc, sc->rl_txstart) & 2137 RL_TXSTART_START) == 0) 2138 break; 2139 DELAY(20); 2140 } 2141 if (i == 0) 2142 printf("%s: stopping TX poll timed out!\n", 2143 sc->sc_dev.dv_xname); 2144 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2145 } else if (sc->rl_flags & RL_FLAG_CMDSTOP) { 2146 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2147 RL_CMD_RX_ENB); 2148 if (sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) { 2149 for (i = RL_TIMEOUT; i > 0; i--) { 2150 if ((CSR_READ_4(sc, RL_TXCFG) & 2151 RL_TXCFG_QUEUE_EMPTY) != 0) 2152 break; 2153 DELAY(100); 2154 } 2155 if (i == 0) 2156 printf("%s: stopping TXQ timed out!\n", 2157 sc->sc_dev.dv_xname); 2158 } 2159 } else 2160 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2161 DELAY(1000); 2162 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2163 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2164 2165 intr_barrier(sc->sc_ih); 2166 ifq_barrier(&ifp->if_snd); 2167 2168 ifq_clr_oactive(&ifp->if_snd); 2169 mii_down(&sc->sc_mii); 2170 2171 if (sc->rl_head != NULL) { 2172 m_freem(sc->rl_head); 2173 sc->rl_head = sc->rl_tail = NULL; 2174 } 2175 2176 /* Free the TX list buffers. */ 2177 for (i = 0; i < RL_TX_QLEN; i++) { 2178 if (sc->rl_ldata.rl_txq[i].txq_mbuf != NULL) { 2179 bus_dmamap_unload(sc->sc_dmat, 2180 sc->rl_ldata.rl_txq[i].txq_dmamap); 2181 m_freem(sc->rl_ldata.rl_txq[i].txq_mbuf); 2182 sc->rl_ldata.rl_txq[i].txq_mbuf = NULL; 2183 } 2184 } 2185 2186 /* Free the RX list buffers. */ 2187 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2188 if (sc->rl_ldata.rl_rxsoft[i].rxs_mbuf != NULL) { 2189 bus_dmamap_unload(sc->sc_dmat, 2190 sc->rl_ldata.rl_rxsoft[i].rxs_dmamap); 2191 m_freem(sc->rl_ldata.rl_rxsoft[i].rxs_mbuf); 2192 sc->rl_ldata.rl_rxsoft[i].rxs_mbuf = NULL; 2193 } 2194 } 2195 } 2196 2197 void 2198 re_setup_hw_im(struct rl_softc *sc) 2199 { 2200 KASSERT(sc->rl_flags & RL_FLAG_HWIM); 2201 2202 /* 2203 * Interrupt moderation 2204 * 2205 * 0xABCD 2206 * A - unknown (maybe TX related) 2207 * B - TX timer (unit: 25us) 2208 * C - unknown (maybe RX related) 2209 * D - RX timer (unit: 25us) 2210 * 2211 * 2212 * re(4)'s interrupt moderation is actually controlled by 2213 * two variables, like most other NICs (bge, bnx etc.) 2214 * o timer 2215 * o number of packets [P] 2216 * 2217 * The logic relationship between these two variables is 2218 * similar to other NICs too: 2219 * if (timer expire || packets > [P]) 2220 * Interrupt is delivered 2221 * 2222 * Currently we only know how to set 'timer', but not 2223 * 'number of packets', which should be ~30, as far as I 2224 * tested (sink ~900Kpps, interrupt rate is 30KHz) 2225 */ 2226 CSR_WRITE_2(sc, RL_IM, 2227 RL_IM_RXTIME(sc->rl_rx_time) | 2228 RL_IM_TXTIME(sc->rl_tx_time) | 2229 RL_IM_MAGIC); 2230 } 2231 2232 void 2233 re_disable_hw_im(struct rl_softc *sc) 2234 { 2235 if (sc->rl_flags & RL_FLAG_HWIM) 2236 CSR_WRITE_2(sc, RL_IM, 0); 2237 } 2238 2239 void 2240 re_setup_sim_im(struct rl_softc *sc) 2241 { 2242 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 2243 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); /* XXX */ 2244 else { 2245 u_int32_t nticks; 2246 2247 /* 2248 * Datasheet says tick decreases at bus speed, 2249 * but it seems the clock runs a little bit 2250 * faster, so we do some compensation here. 2251 */ 2252 nticks = (sc->rl_sim_time * sc->rl_bus_speed * 8) / 5; 2253 CSR_WRITE_4(sc, RL_TIMERINT_8169, nticks); 2254 } 2255 CSR_WRITE_4(sc, RL_TIMERCNT, 1); /* reload */ 2256 sc->rl_timerintr = 1; 2257 } 2258 2259 void 2260 re_disable_sim_im(struct rl_softc *sc) 2261 { 2262 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 2263 CSR_WRITE_4(sc, RL_TIMERINT, 0); 2264 else 2265 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0); 2266 sc->rl_timerintr = 0; 2267 } 2268 2269 void 2270 re_config_imtype(struct rl_softc *sc, int imtype) 2271 { 2272 switch (imtype) { 2273 case RL_IMTYPE_HW: 2274 KASSERT(sc->rl_flags & RL_FLAG_HWIM); 2275 /* FALLTHROUGH */ 2276 case RL_IMTYPE_NONE: 2277 sc->rl_intrs = RL_INTRS_CPLUS; 2278 sc->rl_rx_ack = RL_ISR_RX_OK | RL_ISR_FIFO_OFLOW | 2279 RL_ISR_RX_OVERRUN; 2280 sc->rl_tx_ack = RL_ISR_TX_OK; 2281 break; 2282 2283 case RL_IMTYPE_SIM: 2284 sc->rl_intrs = RL_INTRS_TIMER; 2285 sc->rl_rx_ack = RL_ISR_TIMEOUT_EXPIRED; 2286 sc->rl_tx_ack = RL_ISR_TIMEOUT_EXPIRED; 2287 break; 2288 2289 default: 2290 panic("%s: unknown imtype %d", 2291 sc->sc_dev.dv_xname, imtype); 2292 } 2293 } 2294 2295 void 2296 re_set_jumbo(struct rl_softc *sc) 2297 { 2298 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2299 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2300 RL_CFG3_JUMBO_EN0); 2301 2302 switch (sc->sc_hwrev) { 2303 case RL_HWREV_8168DP: 2304 break; 2305 case RL_HWREV_8168E: 2306 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2307 RL_CFG4_8168E_JUMBO_EN1); 2308 break; 2309 default: 2310 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2311 RL_CFG4_JUMBO_EN1); 2312 break; 2313 } 2314 2315 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2316 } 2317 2318 void 2319 re_setup_intr(struct rl_softc *sc, int enable_intrs, int imtype) 2320 { 2321 re_config_imtype(sc, imtype); 2322 2323 if (enable_intrs) 2324 CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs); 2325 else 2326 CSR_WRITE_2(sc, RL_IMR, 0); 2327 2328 switch (imtype) { 2329 case RL_IMTYPE_NONE: 2330 re_disable_sim_im(sc); 2331 re_disable_hw_im(sc); 2332 break; 2333 2334 case RL_IMTYPE_HW: 2335 KASSERT(sc->rl_flags & RL_FLAG_HWIM); 2336 re_disable_sim_im(sc); 2337 re_setup_hw_im(sc); 2338 break; 2339 2340 case RL_IMTYPE_SIM: 2341 re_disable_hw_im(sc); 2342 re_setup_sim_im(sc); 2343 break; 2344 2345 default: 2346 panic("%s: unknown imtype %d", 2347 sc->sc_dev.dv_xname, imtype); 2348 } 2349 } 2350 2351 #ifndef SMALL_KERNEL 2352 int 2353 re_wol(struct ifnet *ifp, int enable) 2354 { 2355 struct rl_softc *sc = ifp->if_softc; 2356 u_int8_t val; 2357 2358 if (enable) { 2359 if ((CSR_READ_1(sc, sc->rl_cfg1) & RL_CFG1_PME) == 0) { 2360 printf("%s: power management is disabled, " 2361 "cannot do WOL\n", sc->sc_dev.dv_xname); 2362 return (ENOTSUP); 2363 } 2364 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_AUXPWR) == 0) 2365 printf("%s: no auxiliary power, cannot do WOL from D3 " 2366 "(power-off) state\n", sc->sc_dev.dv_xname); 2367 } 2368 2369 re_iff(sc); 2370 2371 /* Temporarily enable write to configuration registers. */ 2372 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2373 2374 /* Always disable all wake events except magic packet. */ 2375 if (enable) { 2376 val = CSR_READ_1(sc, sc->rl_cfg5); 2377 val &= ~(RL_CFG5_WOL_UCAST | RL_CFG5_WOL_MCAST | 2378 RL_CFG5_WOL_BCAST); 2379 CSR_WRITE_1(sc, sc->rl_cfg5, val); 2380 2381 val = CSR_READ_1(sc, sc->rl_cfg3); 2382 val |= RL_CFG3_WOL_MAGIC; 2383 val &= ~RL_CFG3_WOL_LINK; 2384 CSR_WRITE_1(sc, sc->rl_cfg3, val); 2385 } else { 2386 val = CSR_READ_1(sc, sc->rl_cfg5); 2387 val &= ~(RL_CFG5_WOL_UCAST | RL_CFG5_WOL_MCAST | 2388 RL_CFG5_WOL_BCAST); 2389 CSR_WRITE_1(sc, sc->rl_cfg5, val); 2390 2391 val = CSR_READ_1(sc, sc->rl_cfg3); 2392 val &= ~(RL_CFG3_WOL_MAGIC | RL_CFG3_WOL_LINK); 2393 CSR_WRITE_1(sc, sc->rl_cfg3, val); 2394 } 2395 2396 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2397 2398 return (0); 2399 } 2400 #endif 2401