1 /* $OpenBSD: re.c,v 1.136 2011/06/15 13:19:19 jsg Exp $ */ 2 /* $FreeBSD: if_re.c,v 1.31 2004/09/04 07:54:05 ru Exp $ */ 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 */ 42 43 /* 44 * This driver is designed to support RealTek's next generation of 45 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 46 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 47 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 48 * 49 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 50 * with the older 8139 family, however it also supports a special 51 * C+ mode of operation that provides several new performance enhancing 52 * features. These include: 53 * 54 * o Descriptor based DMA mechanism. Each descriptor represents 55 * a single packet fragment. Data buffers may be aligned on 56 * any byte boundary. 57 * 58 * o 64-bit DMA 59 * 60 * o TCP/IP checksum offload for both RX and TX 61 * 62 * o High and normal priority transmit DMA rings 63 * 64 * o VLAN tag insertion and extraction 65 * 66 * o TCP large send (segmentation offload) 67 * 68 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 69 * programming API is fairly straightforward. The RX filtering, EEPROM 70 * access and PHY access is the same as it is on the older 8139 series 71 * chips. 72 * 73 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 74 * same programming API and feature set as the 8139C+ with the following 75 * differences and additions: 76 * 77 * o 1000Mbps mode 78 * 79 * o Jumbo frames 80 * 81 * o GMII and TBI ports/registers for interfacing with copper 82 * or fiber PHYs 83 * 84 * o RX and TX DMA rings can have up to 1024 descriptors 85 * (the 8139C+ allows a maximum of 64) 86 * 87 * o Slight differences in register layout from the 8139C+ 88 * 89 * The TX start and timer interrupt registers are at different locations 90 * on the 8169 than they are on the 8139C+. Also, the status word in the 91 * RX descriptor has a slightly different bit layout. The 8169 does not 92 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 93 * copper gigE PHY. 94 * 95 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 96 * (the 'S' stands for 'single-chip'). These devices have the same 97 * programming API as the older 8169, but also have some vendor-specific 98 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 99 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 100 * 101 * This driver takes advantage of the RX and TX checksum offload and 102 * VLAN tag insertion/extraction features. It also implements TX 103 * interrupt moderation using the timer interrupt registers, which 104 * significantly reduces TX interrupt load. There is also support 105 * for jumbo frames, however the 8169/8169S/8110S can not transmit 106 * jumbo frames larger than 7440, so the max MTU possible with this 107 * driver is 7422 bytes. 108 */ 109 110 #include "bpfilter.h" 111 #include "vlan.h" 112 113 #include <sys/param.h> 114 #include <sys/endian.h> 115 #include <sys/systm.h> 116 #include <sys/sockio.h> 117 #include <sys/mbuf.h> 118 #include <sys/malloc.h> 119 #include <sys/kernel.h> 120 #include <sys/device.h> 121 #include <sys/timeout.h> 122 #include <sys/socket.h> 123 124 #include <net/if.h> 125 #include <net/if_dl.h> 126 #include <net/if_media.h> 127 128 #ifdef INET 129 #include <netinet/in.h> 130 #include <netinet/in_systm.h> 131 #include <netinet/in_var.h> 132 #include <netinet/ip.h> 133 #include <netinet/if_ether.h> 134 #endif 135 136 #if NVLAN > 0 137 #include <net/if_types.h> 138 #include <net/if_vlan_var.h> 139 #endif 140 141 #if NBPFILTER > 0 142 #include <net/bpf.h> 143 #endif 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <dev/ic/rtl81x9reg.h> 152 #include <dev/ic/revar.h> 153 154 #ifdef RE_DEBUG 155 int redebug = 0; 156 #define DPRINTF(x) do { if (redebug) printf x; } while (0) 157 #else 158 #define DPRINTF(x) 159 #endif 160 161 static inline void re_set_bufaddr(struct rl_desc *, bus_addr_t); 162 163 int re_encap(struct rl_softc *, struct mbuf *, int *); 164 165 int re_newbuf(struct rl_softc *); 166 int re_rx_list_init(struct rl_softc *); 167 void re_rx_list_fill(struct rl_softc *); 168 int re_tx_list_init(struct rl_softc *); 169 int re_rxeof(struct rl_softc *); 170 int re_txeof(struct rl_softc *); 171 void re_tick(void *); 172 void re_start(struct ifnet *); 173 int re_ioctl(struct ifnet *, u_long, caddr_t); 174 void re_watchdog(struct ifnet *); 175 int re_ifmedia_upd(struct ifnet *); 176 void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 void re_eeprom_putbyte(struct rl_softc *, int); 179 void re_eeprom_getword(struct rl_softc *, int, u_int16_t *); 180 void re_read_eeprom(struct rl_softc *, caddr_t, int, int); 181 182 int re_gmii_readreg(struct device *, int, int); 183 void re_gmii_writereg(struct device *, int, int, int); 184 185 int re_miibus_readreg(struct device *, int, int); 186 void re_miibus_writereg(struct device *, int, int, int); 187 void re_miibus_statchg(struct device *); 188 189 void re_iff(struct rl_softc *); 190 191 void re_setup_hw_im(struct rl_softc *); 192 void re_setup_sim_im(struct rl_softc *); 193 void re_disable_hw_im(struct rl_softc *); 194 void re_disable_sim_im(struct rl_softc *); 195 void re_config_imtype(struct rl_softc *, int); 196 void re_setup_intr(struct rl_softc *, int, int); 197 #ifndef SMALL_KERNEL 198 int re_wol(struct ifnet*, int); 199 #endif 200 201 #ifdef RE_DIAG 202 int re_diag(struct rl_softc *); 203 #endif 204 205 struct cfdriver re_cd = { 206 0, "re", DV_IFNET 207 }; 208 209 #define EE_SET(x) \ 210 CSR_WRITE_1(sc, RL_EECMD, \ 211 CSR_READ_1(sc, RL_EECMD) | x) 212 213 #define EE_CLR(x) \ 214 CSR_WRITE_1(sc, RL_EECMD, \ 215 CSR_READ_1(sc, RL_EECMD) & ~x) 216 217 static const struct re_revision { 218 u_int32_t re_chipid; 219 const char *re_name; 220 } re_revisions[] = { 221 { RL_HWREV_8100, "RTL8100" }, 222 { RL_HWREV_8100E_SPIN1, "RTL8100E 1" }, 223 { RL_HWREV_8100E_SPIN2, "RTL8100E 2" }, 224 { RL_HWREV_8101, "RTL8101" }, 225 { RL_HWREV_8101E, "RTL8101E" }, 226 { RL_HWREV_8102E, "RTL8102E" }, 227 { RL_HWREV_8401E, "RTL8401E" }, 228 { RL_HWREV_8102EL, "RTL8102EL" }, 229 { RL_HWREV_8102EL_SPIN1, "RTL8102EL 1" }, 230 { RL_HWREV_8103E, "RTL8103E" }, 231 { RL_HWREV_8110S, "RTL8110S" }, 232 { RL_HWREV_8139CPLUS, "RTL8139C+" }, 233 { RL_HWREV_8168_SPIN1, "RTL8168 1" }, 234 { RL_HWREV_8168_SPIN2, "RTL8168 2" }, 235 { RL_HWREV_8168_SPIN3, "RTL8168 3" }, 236 { RL_HWREV_8168C, "RTL8168C/8111C" }, 237 { RL_HWREV_8168C_SPIN2, "RTL8168C/8111C" }, 238 { RL_HWREV_8168CP, "RTL8168CP/8111CP" }, 239 { RL_HWREV_8105E, "RTL8105E" }, 240 { RL_HWREV_8168D, "RTL8168D/8111D" }, 241 { RL_HWREV_8168DP, "RTL8168DP/8111DP" }, 242 { RL_HWREV_8168E, "RTL8168E/8111E" }, 243 { RL_HWREV_8168E_VL, "RTL8168E/8111E-VL" }, 244 { RL_HWREV_8169, "RTL8169" }, 245 { RL_HWREV_8169_8110SB, "RTL8169/8110SB" }, 246 { RL_HWREV_8169_8110SBL, "RTL8169SBL" }, 247 { RL_HWREV_8169_8110SCd, "RTL8169/8110SCd" }, 248 { RL_HWREV_8169_8110SCe, "RTL8169/8110SCe" }, 249 { RL_HWREV_8169S, "RTL8169S" }, 250 251 { 0, NULL } 252 }; 253 254 255 static inline void 256 re_set_bufaddr(struct rl_desc *d, bus_addr_t addr) 257 { 258 d->rl_bufaddr_lo = htole32((uint32_t)addr); 259 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 260 d->rl_bufaddr_hi = htole32((uint64_t)addr >> 32); 261 else 262 d->rl_bufaddr_hi = 0; 263 } 264 265 /* 266 * Send a read command and address to the EEPROM, check for ACK. 267 */ 268 void 269 re_eeprom_putbyte(struct rl_softc *sc, int addr) 270 { 271 int d, i; 272 273 d = addr | (RL_9346_READ << sc->rl_eewidth); 274 275 /* 276 * Feed in each bit and strobe the clock. 277 */ 278 279 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 280 if (d & i) 281 EE_SET(RL_EE_DATAIN); 282 else 283 EE_CLR(RL_EE_DATAIN); 284 DELAY(100); 285 EE_SET(RL_EE_CLK); 286 DELAY(150); 287 EE_CLR(RL_EE_CLK); 288 DELAY(100); 289 } 290 } 291 292 /* 293 * Read a word of data stored in the EEPROM at address 'addr.' 294 */ 295 void 296 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 297 { 298 int i; 299 u_int16_t word = 0; 300 301 /* 302 * Send address of word we want to read. 303 */ 304 re_eeprom_putbyte(sc, addr); 305 306 /* 307 * Start reading bits from EEPROM. 308 */ 309 for (i = 0x8000; i; i >>= 1) { 310 EE_SET(RL_EE_CLK); 311 DELAY(100); 312 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 313 word |= i; 314 EE_CLR(RL_EE_CLK); 315 DELAY(100); 316 } 317 318 *dest = word; 319 } 320 321 /* 322 * Read a sequence of words from the EEPROM. 323 */ 324 void 325 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 326 { 327 int i; 328 u_int16_t word = 0, *ptr; 329 330 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 331 332 DELAY(100); 333 334 for (i = 0; i < cnt; i++) { 335 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 336 re_eeprom_getword(sc, off + i, &word); 337 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 338 ptr = (u_int16_t *)(dest + (i * 2)); 339 *ptr = word; 340 } 341 342 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 343 } 344 345 int 346 re_gmii_readreg(struct device *self, int phy, int reg) 347 { 348 struct rl_softc *sc = (struct rl_softc *)self; 349 u_int32_t rval; 350 int i; 351 352 if (phy != 7) 353 return (0); 354 355 /* Let the rgephy driver read the GMEDIASTAT register */ 356 357 if (reg == RL_GMEDIASTAT) { 358 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 359 return (rval); 360 } 361 362 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 363 364 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 365 rval = CSR_READ_4(sc, RL_PHYAR); 366 if (rval & RL_PHYAR_BUSY) 367 break; 368 DELAY(25); 369 } 370 371 if (i == RL_PHY_TIMEOUT) { 372 printf ("%s: PHY read failed\n", sc->sc_dev.dv_xname); 373 return (0); 374 } 375 376 DELAY(20); 377 378 return (rval & RL_PHYAR_PHYDATA); 379 } 380 381 void 382 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 383 { 384 struct rl_softc *sc = (struct rl_softc *)dev; 385 u_int32_t rval; 386 int i; 387 388 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 389 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 390 391 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 392 rval = CSR_READ_4(sc, RL_PHYAR); 393 if (!(rval & RL_PHYAR_BUSY)) 394 break; 395 DELAY(25); 396 } 397 398 if (i == RL_PHY_TIMEOUT) 399 printf ("%s: PHY write failed\n", sc->sc_dev.dv_xname); 400 401 DELAY(20); 402 } 403 404 int 405 re_miibus_readreg(struct device *dev, int phy, int reg) 406 { 407 struct rl_softc *sc = (struct rl_softc *)dev; 408 u_int16_t rval = 0; 409 u_int16_t re8139_reg = 0; 410 int s; 411 412 s = splnet(); 413 414 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) { 415 rval = re_gmii_readreg(dev, phy, reg); 416 splx(s); 417 return (rval); 418 } 419 420 /* Pretend the internal PHY is only at address 0 */ 421 if (phy) { 422 splx(s); 423 return (0); 424 } 425 switch(reg) { 426 case MII_BMCR: 427 re8139_reg = RL_BMCR; 428 break; 429 case MII_BMSR: 430 re8139_reg = RL_BMSR; 431 break; 432 case MII_ANAR: 433 re8139_reg = RL_ANAR; 434 break; 435 case MII_ANER: 436 re8139_reg = RL_ANER; 437 break; 438 case MII_ANLPAR: 439 re8139_reg = RL_LPAR; 440 break; 441 case MII_PHYIDR1: 442 case MII_PHYIDR2: 443 splx(s); 444 return (0); 445 /* 446 * Allow the rlphy driver to read the media status 447 * register. If we have a link partner which does not 448 * support NWAY, this is the register which will tell 449 * us the results of parallel detection. 450 */ 451 case RL_MEDIASTAT: 452 rval = CSR_READ_1(sc, RL_MEDIASTAT); 453 splx(s); 454 return (rval); 455 default: 456 printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg); 457 splx(s); 458 return (0); 459 } 460 rval = CSR_READ_2(sc, re8139_reg); 461 if (re8139_reg == RL_BMCR) { 462 /* 8139C+ has different bit layout. */ 463 rval &= ~(BMCR_LOOP | BMCR_ISO); 464 } 465 splx(s); 466 return (rval); 467 } 468 469 void 470 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 471 { 472 struct rl_softc *sc = (struct rl_softc *)dev; 473 u_int16_t re8139_reg = 0; 474 int s; 475 476 s = splnet(); 477 478 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) { 479 re_gmii_writereg(dev, phy, reg, data); 480 splx(s); 481 return; 482 } 483 484 /* Pretend the internal PHY is only at address 0 */ 485 if (phy) { 486 splx(s); 487 return; 488 } 489 switch(reg) { 490 case MII_BMCR: 491 re8139_reg = RL_BMCR; 492 /* 8139C+ has different bit layout. */ 493 data &= ~(BMCR_LOOP | BMCR_ISO); 494 break; 495 case MII_BMSR: 496 re8139_reg = RL_BMSR; 497 break; 498 case MII_ANAR: 499 re8139_reg = RL_ANAR; 500 break; 501 case MII_ANER: 502 re8139_reg = RL_ANER; 503 break; 504 case MII_ANLPAR: 505 re8139_reg = RL_LPAR; 506 break; 507 case MII_PHYIDR1: 508 case MII_PHYIDR2: 509 splx(s); 510 return; 511 break; 512 default: 513 printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg); 514 splx(s); 515 return; 516 } 517 CSR_WRITE_2(sc, re8139_reg, data); 518 splx(s); 519 } 520 521 void 522 re_miibus_statchg(struct device *dev) 523 { 524 } 525 526 void 527 re_iff(struct rl_softc *sc) 528 { 529 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 530 int h = 0; 531 u_int32_t hashes[2]; 532 u_int32_t rxfilt; 533 struct arpcom *ac = &sc->sc_arpcom; 534 struct ether_multi *enm; 535 struct ether_multistep step; 536 537 rxfilt = CSR_READ_4(sc, RL_RXCFG); 538 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | 539 RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI); 540 ifp->if_flags &= ~IFF_ALLMULTI; 541 542 /* 543 * Always accept frames destined to our station address. 544 * Always accept broadcast frames. 545 */ 546 rxfilt |= RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 547 548 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 549 ifp->if_flags |= IFF_ALLMULTI; 550 rxfilt |= RL_RXCFG_RX_MULTI; 551 if (ifp->if_flags & IFF_PROMISC) 552 rxfilt |= RL_RXCFG_RX_ALLPHYS; 553 hashes[0] = hashes[1] = 0xFFFFFFFF; 554 } else { 555 rxfilt |= RL_RXCFG_RX_MULTI; 556 /* Program new filter. */ 557 bzero(hashes, sizeof(hashes)); 558 559 ETHER_FIRST_MULTI(step, ac, enm); 560 while (enm != NULL) { 561 h = ether_crc32_be(enm->enm_addrlo, 562 ETHER_ADDR_LEN) >> 26; 563 564 if (h < 32) 565 hashes[0] |= (1 << h); 566 else 567 hashes[1] |= (1 << (h - 32)); 568 569 ETHER_NEXT_MULTI(step, enm); 570 } 571 } 572 573 /* 574 * For some unfathomable reason, RealTek decided to reverse 575 * the order of the multicast hash registers in the PCI Express 576 * parts. This means we have to write the hash pattern in reverse 577 * order for those devices. 578 */ 579 if (sc->rl_flags & RL_FLAG_INVMAR) { 580 CSR_WRITE_4(sc, RL_MAR0, swap32(hashes[1])); 581 CSR_WRITE_4(sc, RL_MAR4, swap32(hashes[0])); 582 } else { 583 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 584 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 585 } 586 587 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 588 } 589 590 void 591 re_reset(struct rl_softc *sc) 592 { 593 int i; 594 595 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 596 597 for (i = 0; i < RL_TIMEOUT; i++) { 598 DELAY(10); 599 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 600 break; 601 } 602 if (i == RL_TIMEOUT) 603 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 604 605 if (sc->rl_flags & RL_FLAG_MACLDPS) 606 CSR_WRITE_1(sc, RL_LDPS, 1); 607 } 608 609 #ifdef RE_DIAG 610 611 /* 612 * The following routine is designed to test for a defect on some 613 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 614 * lines connected to the bus, however for a 32-bit only card, they 615 * should be pulled high. The result of this defect is that the 616 * NIC will not work right if you plug it into a 64-bit slot: DMA 617 * operations will be done with 64-bit transfers, which will fail 618 * because the 64-bit data lines aren't connected. 619 * 620 * There's no way to work around this (short of talking a soldering 621 * iron to the board), however we can detect it. The method we use 622 * here is to put the NIC into digital loopback mode, set the receiver 623 * to promiscuous mode, and then try to send a frame. We then compare 624 * the frame data we sent to what was received. If the data matches, 625 * then the NIC is working correctly, otherwise we know the user has 626 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 627 * slot. In the latter case, there's no way the NIC can work correctly, 628 * so we print out a message on the console and abort the device attach. 629 */ 630 631 int 632 re_diag(struct rl_softc *sc) 633 { 634 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 635 struct mbuf *m0; 636 struct ether_header *eh; 637 struct rl_rxsoft *rxs; 638 struct rl_desc *cur_rx; 639 bus_dmamap_t dmamap; 640 u_int16_t status; 641 u_int32_t rxstat; 642 int total_len, i, s, error = 0, phyaddr; 643 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 644 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 645 646 DPRINTF(("inside re_diag\n")); 647 /* Allocate a single mbuf */ 648 649 MGETHDR(m0, M_DONTWAIT, MT_DATA); 650 if (m0 == NULL) 651 return (ENOBUFS); 652 653 /* 654 * Initialize the NIC in test mode. This sets the chip up 655 * so that it can send and receive frames, but performs the 656 * following special functions: 657 * - Puts receiver in promiscuous mode 658 * - Enables digital loopback mode 659 * - Leaves interrupts turned off 660 */ 661 662 ifp->if_flags |= IFF_PROMISC; 663 sc->rl_testmode = 1; 664 re_reset(sc); 665 re_init(ifp); 666 sc->rl_flags |= RL_FLAG_LINK; 667 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 668 phyaddr = 0; 669 else 670 phyaddr = 1; 671 672 re_miibus_writereg((struct device *)sc, phyaddr, MII_BMCR, 673 BMCR_RESET); 674 for (i = 0; i < RL_TIMEOUT; i++) { 675 status = re_miibus_readreg((struct device *)sc, 676 phyaddr, MII_BMCR); 677 if (!(status & BMCR_RESET)) 678 break; 679 } 680 681 re_miibus_writereg((struct device *)sc, phyaddr, MII_BMCR, 682 BMCR_LOOP); 683 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 684 685 DELAY(100000); 686 687 /* Put some data in the mbuf */ 688 689 eh = mtod(m0, struct ether_header *); 690 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 691 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 692 eh->ether_type = htons(ETHERTYPE_IP); 693 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 694 695 /* 696 * Queue the packet, start transmission. 697 */ 698 699 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 700 s = splnet(); 701 IFQ_ENQUEUE(&ifp->if_snd, m0, NULL, error); 702 re_start(ifp); 703 splx(s); 704 m0 = NULL; 705 706 DPRINTF(("re_diag: transmission started\n")); 707 708 /* Wait for it to propagate through the chip */ 709 710 DELAY(100000); 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 status = CSR_READ_2(sc, RL_ISR); 713 CSR_WRITE_2(sc, RL_ISR, status); 714 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 715 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 716 break; 717 DELAY(10); 718 } 719 if (i == RL_TIMEOUT) { 720 printf("%s: diagnostic failed, failed to receive packet " 721 "in loopback mode\n", sc->sc_dev.dv_xname); 722 error = EIO; 723 goto done; 724 } 725 726 /* 727 * The packet should have been dumped into the first 728 * entry in the RX DMA ring. Grab it from there. 729 */ 730 731 rxs = &sc->rl_ldata.rl_rxsoft[0]; 732 dmamap = rxs->rxs_dmamap; 733 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 734 BUS_DMASYNC_POSTREAD); 735 bus_dmamap_unload(sc->sc_dmat, dmamap); 736 737 m0 = rxs->rxs_mbuf; 738 rxs->rxs_mbuf = NULL; 739 eh = mtod(m0, struct ether_header *); 740 741 RL_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 742 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 743 rxstat = letoh32(cur_rx->rl_cmdstat); 744 total_len = rxstat & sc->rl_rxlenmask; 745 746 if (total_len != ETHER_MIN_LEN) { 747 printf("%s: diagnostic failed, received short packet\n", 748 sc->sc_dev.dv_xname); 749 error = EIO; 750 goto done; 751 } 752 753 DPRINTF(("re_diag: packet received\n")); 754 755 /* Test that the received packet data matches what we sent. */ 756 757 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 758 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 759 ntohs(eh->ether_type) != ETHERTYPE_IP) { 760 printf("%s: WARNING, DMA FAILURE!\n", sc->sc_dev.dv_xname); 761 printf("%s: expected TX data: %s", 762 sc->sc_dev.dv_xname, ether_sprintf(dst)); 763 printf("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 764 printf("%s: received RX data: %s", 765 sc->sc_dev.dv_xname, 766 ether_sprintf(eh->ether_dhost)); 767 printf("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 768 ntohs(eh->ether_type)); 769 printf("%s: You may have a defective 32-bit NIC plugged " 770 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 771 printf("%s: Please re-install the NIC in a 32-bit slot " 772 "for proper operation.\n", sc->sc_dev.dv_xname); 773 printf("%s: Read the re(4) man page for more details.\n", 774 sc->sc_dev.dv_xname); 775 error = EIO; 776 } 777 778 done: 779 /* Turn interface off, release resources */ 780 sc->rl_testmode = 0; 781 sc->rl_flags &= ~RL_FLAG_LINK; 782 ifp->if_flags &= ~IFF_PROMISC; 783 re_stop(ifp); 784 if (m0 != NULL) 785 m_freem(m0); 786 DPRINTF(("leaving re_diag\n")); 787 788 return (error); 789 } 790 791 #endif 792 793 #ifdef __armish__ 794 /* 795 * Thecus N2100 doesn't store the full mac address in eeprom 796 * so we read the old mac address from the device before the reset 797 * in hopes that the proper mac address is already there. 798 */ 799 union { 800 u_int32_t eaddr_word[2]; 801 u_char eaddr[ETHER_ADDR_LEN]; 802 } boot_eaddr; 803 int boot_eaddr_valid; 804 #endif /* __armish__ */ 805 /* 806 * Attach the interface. Allocate softc structures, do ifmedia 807 * setup and ethernet/BPF attach. 808 */ 809 int 810 re_attach(struct rl_softc *sc, const char *intrstr) 811 { 812 u_char eaddr[ETHER_ADDR_LEN]; 813 u_int16_t as[ETHER_ADDR_LEN / 2]; 814 struct ifnet *ifp; 815 u_int16_t re_did = 0; 816 int error = 0, i; 817 const struct re_revision *rr; 818 const char *re_name = NULL; 819 820 sc->sc_hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 821 822 switch (sc->sc_hwrev) { 823 case RL_HWREV_8139CPLUS: 824 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_AUTOPAD; 825 break; 826 case RL_HWREV_8100E_SPIN1: 827 case RL_HWREV_8100E_SPIN2: 828 case RL_HWREV_8101E: 829 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 830 RL_FLAG_PHYWAKE; 831 break; 832 case RL_HWREV_8103E: 833 sc->rl_flags |= RL_FLAG_MACSLEEP; 834 /* FALLTHROUGH */ 835 case RL_HWREV_8102E: 836 case RL_HWREV_8102EL: 837 case RL_HWREV_8102EL_SPIN1: 838 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 839 RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 840 RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 841 break; 842 case RL_HWREV_8401E: 843 case RL_HWREV_8105E: 844 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 845 RL_FLAG_PHYWAKE_PM | RL_FLAG_PAR | RL_FLAG_DESCV2 | 846 RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 847 break; 848 case RL_HWREV_8168_SPIN1: 849 case RL_HWREV_8168_SPIN2: 850 case RL_HWREV_8168_SPIN3: 851 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 852 RL_FLAG_MACSTAT | RL_FLAG_HWIM; 853 break; 854 case RL_HWREV_8168C_SPIN2: 855 sc->rl_flags |= RL_FLAG_MACSLEEP; 856 /* FALLTHROUGH */ 857 case RL_HWREV_8168C: 858 case RL_HWREV_8168CP: 859 case RL_HWREV_8168D: 860 case RL_HWREV_8168DP: 861 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 862 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 863 RL_FLAG_HWIM | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 864 /* 865 * These controllers support jumbo frame but it seems 866 * that enabling it requires touching additional magic 867 * registers. Depending on MAC revisions some 868 * controllers need to disable checksum offload. So 869 * disable jumbo frame until I have better idea what 870 * it really requires to make it support. 871 * RTL8168C/CP : supports up to 6KB jumbo frame. 872 * RTL8111C/CP : supports up to 9KB jumbo frame. 873 */ 874 sc->rl_flags |= RL_FLAG_NOJUMBO; 875 break; 876 case RL_HWREV_8168E: 877 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 878 RL_FLAG_PHYWAKE_PM | RL_FLAG_PAR | RL_FLAG_DESCV2 | 879 RL_FLAG_MACSTAT | RL_FLAG_HWIM | RL_FLAG_CMDSTOP | 880 RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO; 881 break; 882 case RL_HWREV_8168E_VL: 883 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 884 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 885 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO; 886 break; 887 case RL_HWREV_8169_8110SB: 888 case RL_HWREV_8169_8110SBL: 889 case RL_HWREV_8169_8110SCd: 890 case RL_HWREV_8169_8110SCe: 891 sc->rl_flags |= RL_FLAG_PHYWAKE; 892 /* FALLTHROUGH */ 893 case RL_HWREV_8169: 894 case RL_HWREV_8169S: 895 case RL_HWREV_8110S: 896 sc->rl_flags |= RL_FLAG_MACLDPS; 897 break; 898 default: 899 break; 900 } 901 902 /* Reset the adapter. */ 903 re_reset(sc); 904 905 sc->rl_tx_time = 5; /* 125us */ 906 sc->rl_rx_time = 2; /* 50us */ 907 if (sc->rl_flags & RL_FLAG_PCIE) 908 sc->rl_sim_time = 75; /* 75us */ 909 else 910 sc->rl_sim_time = 125; /* 125us */ 911 sc->rl_imtype = RL_IMTYPE_SIM; /* simulated interrupt moderation */ 912 913 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 914 sc->rl_bus_speed = 33; /* XXX */ 915 else if (sc->rl_flags & RL_FLAG_PCIE) 916 sc->rl_bus_speed = 125; 917 else { 918 u_int8_t cfg2; 919 920 cfg2 = CSR_READ_1(sc, RL_CFG2); 921 switch (cfg2 & RL_CFG2_PCI_MASK) { 922 case RL_CFG2_PCI_33MHZ: 923 sc->rl_bus_speed = 33; 924 break; 925 case RL_CFG2_PCI_66MHZ: 926 sc->rl_bus_speed = 66; 927 break; 928 default: 929 printf("%s: unknown bus speed, assume 33MHz\n", 930 sc->sc_dev.dv_xname); 931 sc->rl_bus_speed = 33; 932 break; 933 } 934 935 if (cfg2 & RL_CFG2_PCI_64BIT) 936 sc->rl_flags |= RL_FLAG_PCI64; 937 } 938 939 re_config_imtype(sc, sc->rl_imtype); 940 941 if (sc->rl_flags & RL_FLAG_PAR) { 942 /* 943 * XXX Should have a better way to extract station 944 * address from EEPROM. 945 */ 946 for (i = 0; i < ETHER_ADDR_LEN; i++) 947 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 948 } else { 949 sc->rl_eewidth = RL_9356_ADDR_LEN; 950 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 951 if (re_did != 0x8129) 952 sc->rl_eewidth = RL_9346_ADDR_LEN; 953 954 /* 955 * Get station address from the EEPROM. 956 */ 957 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 958 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 959 as[i] = letoh16(as[i]); 960 bcopy(as, eaddr, sizeof(eaddr)); 961 962 #ifdef __armish__ 963 /* 964 * On the Thecus N2100, the MAC address in the EEPROM is 965 * always 00:14:fd:10:00:00. The proper MAC address is 966 * stored in flash. Fortunately RedBoot configures the 967 * proper MAC address (for the first onboard interface) 968 * which we can read from the IDR. 969 */ 970 if (eaddr[0] == 0x00 && eaddr[1] == 0x14 && 971 eaddr[2] == 0xfd && eaddr[3] == 0x10 && 972 eaddr[4] == 0x00 && eaddr[5] == 0x00) { 973 if (boot_eaddr_valid == 0) { 974 boot_eaddr.eaddr_word[1] = 975 letoh32(CSR_READ_4(sc, RL_IDR4)); 976 boot_eaddr.eaddr_word[0] = 977 letoh32(CSR_READ_4(sc, RL_IDR0)); 978 boot_eaddr_valid = 1; 979 } 980 981 bcopy(boot_eaddr.eaddr, eaddr, sizeof(eaddr)); 982 eaddr[5] += sc->sc_dev.dv_unit; 983 } 984 #endif 985 } 986 987 /* 988 * Set RX length mask, TX poll request register 989 * and TX descriptor count. 990 */ 991 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) { 992 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 993 sc->rl_txstart = RL_TXSTART; 994 sc->rl_ldata.rl_tx_desc_cnt = RL_TX_DESC_CNT_8139; 995 } else { 996 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 997 sc->rl_txstart = RL_GTXSTART; 998 sc->rl_ldata.rl_tx_desc_cnt = RL_TX_DESC_CNT_8169; 999 } 1000 1001 bcopy(eaddr, (char *)&sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 1002 1003 for (rr = re_revisions; rr->re_name != NULL; rr++) { 1004 if (rr->re_chipid == sc->sc_hwrev) 1005 re_name = rr->re_name; 1006 } 1007 1008 if (re_name == NULL) 1009 printf(": unknown ASIC (0x%04x)", sc->sc_hwrev >> 16); 1010 else 1011 printf(": %s (0x%04x)", re_name, sc->sc_hwrev >> 16); 1012 1013 printf(", %s, address %s\n", intrstr, 1014 ether_sprintf(sc->sc_arpcom.ac_enaddr)); 1015 1016 if (sc->rl_ldata.rl_tx_desc_cnt > 1017 PAGE_SIZE / sizeof(struct rl_desc)) { 1018 sc->rl_ldata.rl_tx_desc_cnt = 1019 PAGE_SIZE / sizeof(struct rl_desc); 1020 } 1021 1022 /* Allocate DMA'able memory for the TX ring */ 1023 if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_TX_LIST_SZ(sc), 1024 RL_RING_ALIGN, 0, &sc->rl_ldata.rl_tx_listseg, 1, 1025 &sc->rl_ldata.rl_tx_listnseg, BUS_DMA_NOWAIT | 1026 BUS_DMA_ZERO)) != 0) { 1027 printf("%s: can't allocate tx listseg, error = %d\n", 1028 sc->sc_dev.dv_xname, error); 1029 goto fail_0; 1030 } 1031 1032 /* Load the map for the TX ring. */ 1033 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_tx_listseg, 1034 sc->rl_ldata.rl_tx_listnseg, RL_TX_LIST_SZ(sc), 1035 (caddr_t *)&sc->rl_ldata.rl_tx_list, 1036 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 1037 printf("%s: can't map tx list, error = %d\n", 1038 sc->sc_dev.dv_xname, error); 1039 goto fail_1; 1040 } 1041 1042 if ((error = bus_dmamap_create(sc->sc_dmat, RL_TX_LIST_SZ(sc), 1, 1043 RL_TX_LIST_SZ(sc), 0, 0, 1044 &sc->rl_ldata.rl_tx_list_map)) != 0) { 1045 printf("%s: can't create tx list map, error = %d\n", 1046 sc->sc_dev.dv_xname, error); 1047 goto fail_2; 1048 } 1049 1050 if ((error = bus_dmamap_load(sc->sc_dmat, 1051 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1052 RL_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 1053 printf("%s: can't load tx list, error = %d\n", 1054 sc->sc_dev.dv_xname, error); 1055 goto fail_3; 1056 } 1057 1058 /* Create DMA maps for TX buffers */ 1059 for (i = 0; i < RL_TX_QLEN; i++) { 1060 error = bus_dmamap_create(sc->sc_dmat, 1061 RL_JUMBO_FRAMELEN, 1062 RL_TX_DESC_CNT(sc) - RL_NTXDESC_RSVD, RL_TDESC_CMD_FRAGLEN, 1063 0, 0, &sc->rl_ldata.rl_txq[i].txq_dmamap); 1064 if (error) { 1065 printf("%s: can't create DMA map for TX\n", 1066 sc->sc_dev.dv_xname); 1067 goto fail_4; 1068 } 1069 } 1070 1071 /* Allocate DMA'able memory for the RX ring */ 1072 if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_RX_DMAMEM_SZ, 1073 RL_RING_ALIGN, 0, &sc->rl_ldata.rl_rx_listseg, 1, 1074 &sc->rl_ldata.rl_rx_listnseg, BUS_DMA_NOWAIT | 1075 BUS_DMA_ZERO)) != 0) { 1076 printf("%s: can't allocate rx listnseg, error = %d\n", 1077 sc->sc_dev.dv_xname, error); 1078 goto fail_4; 1079 } 1080 1081 /* Load the map for the RX ring. */ 1082 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_rx_listseg, 1083 sc->rl_ldata.rl_rx_listnseg, RL_RX_DMAMEM_SZ, 1084 (caddr_t *)&sc->rl_ldata.rl_rx_list, 1085 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 1086 printf("%s: can't map rx list, error = %d\n", 1087 sc->sc_dev.dv_xname, error); 1088 goto fail_5; 1089 1090 } 1091 1092 if ((error = bus_dmamap_create(sc->sc_dmat, RL_RX_DMAMEM_SZ, 1, 1093 RL_RX_DMAMEM_SZ, 0, 0, 1094 &sc->rl_ldata.rl_rx_list_map)) != 0) { 1095 printf("%s: can't create rx list map, error = %d\n", 1096 sc->sc_dev.dv_xname, error); 1097 goto fail_6; 1098 } 1099 1100 if ((error = bus_dmamap_load(sc->sc_dmat, 1101 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1102 RL_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 1103 printf("%s: can't load rx list, error = %d\n", 1104 sc->sc_dev.dv_xname, error); 1105 goto fail_7; 1106 } 1107 1108 /* Create DMA maps for RX buffers */ 1109 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1110 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 1111 0, 0, &sc->rl_ldata.rl_rxsoft[i].rxs_dmamap); 1112 if (error) { 1113 printf("%s: can't create DMA map for RX\n", 1114 sc->sc_dev.dv_xname); 1115 goto fail_8; 1116 } 1117 } 1118 1119 ifp = &sc->sc_arpcom.ac_if; 1120 ifp->if_softc = sc; 1121 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 1122 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1123 ifp->if_ioctl = re_ioctl; 1124 ifp->if_start = re_start; 1125 ifp->if_watchdog = re_watchdog; 1126 if ((sc->rl_flags & RL_FLAG_NOJUMBO) == 0) 1127 ifp->if_hardmtu = RL_JUMBO_MTU; 1128 IFQ_SET_MAXLEN(&ifp->if_snd, RL_TX_QLEN); 1129 IFQ_SET_READY(&ifp->if_snd); 1130 1131 m_clsetwms(ifp, MCLBYTES, 2, RL_RX_DESC_CNT); 1132 1133 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1134 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1135 1136 #if NVLAN > 0 1137 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1138 #endif 1139 1140 #ifndef SMALL_KERNEL 1141 ifp->if_capabilities |= IFCAP_WOL; 1142 ifp->if_wol = re_wol; 1143 re_wol(ifp, 0); 1144 #endif 1145 timeout_set(&sc->timer_handle, re_tick, sc); 1146 1147 /* Take PHY out of power down mode. */ 1148 if (sc->rl_flags & RL_FLAG_PHYWAKE_PM) { 1149 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1150 if (sc->sc_hwrev == RL_HWREV_8401E) 1151 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1152 } 1153 if (sc->rl_flags & RL_FLAG_PHYWAKE) { 1154 re_gmii_writereg((struct device *)sc, 1, 0x1f, 0); 1155 re_gmii_writereg((struct device *)sc, 1, 0x0e, 0); 1156 } 1157 1158 /* Do MII setup */ 1159 sc->sc_mii.mii_ifp = ifp; 1160 sc->sc_mii.mii_readreg = re_miibus_readreg; 1161 sc->sc_mii.mii_writereg = re_miibus_writereg; 1162 sc->sc_mii.mii_statchg = re_miibus_statchg; 1163 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, re_ifmedia_upd, 1164 re_ifmedia_sts); 1165 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1166 MII_OFFSET_ANY, MIIF_DOPAUSE); 1167 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1168 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 1169 ifmedia_add(&sc->sc_mii.mii_media, 1170 IFM_ETHER|IFM_NONE, 0, NULL); 1171 ifmedia_set(&sc->sc_mii.mii_media, 1172 IFM_ETHER|IFM_NONE); 1173 } else 1174 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1175 1176 /* 1177 * Call MI attach routine. 1178 */ 1179 re_reset(sc); 1180 if_attach(ifp); 1181 ether_ifattach(ifp); 1182 1183 #ifdef RE_DIAG 1184 /* 1185 * Perform hardware diagnostic on the original RTL8169. 1186 * Some 32-bit cards were incorrectly wired and would 1187 * malfunction if plugged into a 64-bit slot. 1188 */ 1189 if (sc->sc_hwrev == RL_HWREV_8169) { 1190 error = re_diag(sc); 1191 if (error) { 1192 printf("%s: attach aborted due to hardware diag failure\n", 1193 sc->sc_dev.dv_xname); 1194 ether_ifdetach(ifp); 1195 goto fail_8; 1196 } 1197 } 1198 #endif 1199 1200 return (0); 1201 1202 fail_8: 1203 /* Destroy DMA maps for RX buffers. */ 1204 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1205 if (sc->rl_ldata.rl_rxsoft[i].rxs_dmamap != NULL) 1206 bus_dmamap_destroy(sc->sc_dmat, 1207 sc->rl_ldata.rl_rxsoft[i].rxs_dmamap); 1208 } 1209 1210 /* Free DMA'able memory for the RX ring. */ 1211 bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map); 1212 fail_7: 1213 bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map); 1214 fail_6: 1215 bus_dmamem_unmap(sc->sc_dmat, 1216 (caddr_t)sc->rl_ldata.rl_rx_list, RL_RX_DMAMEM_SZ); 1217 fail_5: 1218 bus_dmamem_free(sc->sc_dmat, 1219 &sc->rl_ldata.rl_rx_listseg, sc->rl_ldata.rl_rx_listnseg); 1220 1221 fail_4: 1222 /* Destroy DMA maps for TX buffers. */ 1223 for (i = 0; i < RL_TX_QLEN; i++) { 1224 if (sc->rl_ldata.rl_txq[i].txq_dmamap != NULL) 1225 bus_dmamap_destroy(sc->sc_dmat, 1226 sc->rl_ldata.rl_txq[i].txq_dmamap); 1227 } 1228 1229 /* Free DMA'able memory for the TX ring. */ 1230 bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map); 1231 fail_3: 1232 bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map); 1233 fail_2: 1234 bus_dmamem_unmap(sc->sc_dmat, 1235 (caddr_t)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ(sc)); 1236 fail_1: 1237 bus_dmamem_free(sc->sc_dmat, 1238 &sc->rl_ldata.rl_tx_listseg, sc->rl_ldata.rl_tx_listnseg); 1239 fail_0: 1240 return (1); 1241 } 1242 1243 1244 int 1245 re_newbuf(struct rl_softc *sc) 1246 { 1247 struct mbuf *m; 1248 bus_dmamap_t map; 1249 struct rl_desc *d; 1250 struct rl_rxsoft *rxs; 1251 u_int32_t cmdstat; 1252 int error, idx; 1253 1254 m = MCLGETI(NULL, M_DONTWAIT, &sc->sc_arpcom.ac_if, MCLBYTES); 1255 if (!m) 1256 return (ENOBUFS); 1257 1258 /* 1259 * Initialize mbuf length fields and fixup 1260 * alignment so that the frame payload is 1261 * longword aligned on strict alignment archs. 1262 */ 1263 m->m_len = m->m_pkthdr.len = RE_RX_DESC_BUFLEN; 1264 m->m_data += RE_ETHER_ALIGN; 1265 1266 idx = sc->rl_ldata.rl_rx_prodidx; 1267 rxs = &sc->rl_ldata.rl_rxsoft[idx]; 1268 map = rxs->rxs_dmamap; 1269 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1270 BUS_DMA_READ|BUS_DMA_NOWAIT); 1271 if (error) { 1272 m_freem(m); 1273 return (ENOBUFS); 1274 } 1275 1276 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1277 BUS_DMASYNC_PREREAD); 1278 1279 d = &sc->rl_ldata.rl_rx_list[idx]; 1280 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1281 cmdstat = letoh32(d->rl_cmdstat); 1282 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1283 if (cmdstat & RL_RDESC_STAT_OWN) { 1284 printf("%s: tried to map busy RX descriptor\n", 1285 sc->sc_dev.dv_xname); 1286 m_freem(m); 1287 return (ENOBUFS); 1288 } 1289 1290 rxs->rxs_mbuf = m; 1291 1292 d->rl_vlanctl = 0; 1293 cmdstat = map->dm_segs[0].ds_len; 1294 if (idx == (RL_RX_DESC_CNT - 1)) 1295 cmdstat |= RL_RDESC_CMD_EOR; 1296 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1297 d->rl_cmdstat = htole32(cmdstat); 1298 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1299 cmdstat |= RL_RDESC_CMD_OWN; 1300 d->rl_cmdstat = htole32(cmdstat); 1301 RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1302 1303 sc->rl_ldata.rl_rx_prodidx = RL_NEXT_RX_DESC(sc, idx); 1304 sc->rl_ldata.rl_rx_cnt++; 1305 1306 return (0); 1307 } 1308 1309 1310 int 1311 re_tx_list_init(struct rl_softc *sc) 1312 { 1313 int i; 1314 1315 memset(sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ(sc)); 1316 for (i = 0; i < RL_TX_QLEN; i++) { 1317 sc->rl_ldata.rl_txq[i].txq_mbuf = NULL; 1318 } 1319 1320 bus_dmamap_sync(sc->sc_dmat, 1321 sc->rl_ldata.rl_tx_list_map, 0, 1322 sc->rl_ldata.rl_tx_list_map->dm_mapsize, 1323 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1324 sc->rl_ldata.rl_txq_prodidx = 0; 1325 sc->rl_ldata.rl_txq_considx = 0; 1326 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT(sc); 1327 sc->rl_ldata.rl_tx_nextfree = 0; 1328 1329 return (0); 1330 } 1331 1332 int 1333 re_rx_list_init(struct rl_softc *sc) 1334 { 1335 bzero(sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1336 1337 sc->rl_ldata.rl_rx_prodidx = 0; 1338 sc->rl_ldata.rl_rx_considx = 0; 1339 sc->rl_ldata.rl_rx_cnt = 0; 1340 sc->rl_head = sc->rl_tail = NULL; 1341 1342 re_rx_list_fill(sc); 1343 1344 return (0); 1345 } 1346 1347 void 1348 re_rx_list_fill(struct rl_softc *sc) 1349 { 1350 while (sc->rl_ldata.rl_rx_cnt < RL_RX_DESC_CNT) { 1351 if (re_newbuf(sc) == ENOBUFS) 1352 break; 1353 } 1354 } 1355 1356 /* 1357 * RX handler for C+ and 8169. For the gigE chips, we support 1358 * the reception of jumbo frames that have been fragmented 1359 * across multiple 2K mbuf cluster buffers. 1360 */ 1361 int 1362 re_rxeof(struct rl_softc *sc) 1363 { 1364 struct mbuf *m; 1365 struct ifnet *ifp; 1366 int i, total_len, rx = 0; 1367 struct rl_desc *cur_rx; 1368 struct rl_rxsoft *rxs; 1369 u_int32_t rxstat, rxvlan; 1370 1371 ifp = &sc->sc_arpcom.ac_if; 1372 1373 for (i = sc->rl_ldata.rl_rx_considx; sc->rl_ldata.rl_rx_cnt > 0; 1374 i = RL_NEXT_RX_DESC(sc, i)) { 1375 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1376 RL_RXDESCSYNC(sc, i, 1377 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1378 rxstat = letoh32(cur_rx->rl_cmdstat); 1379 rxvlan = letoh32(cur_rx->rl_vlanctl); 1380 RL_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1381 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1382 break; 1383 total_len = rxstat & sc->rl_rxlenmask; 1384 rxs = &sc->rl_ldata.rl_rxsoft[i]; 1385 m = rxs->rxs_mbuf; 1386 rxs->rxs_mbuf = NULL; 1387 sc->rl_ldata.rl_rx_cnt--; 1388 rx = 1; 1389 1390 /* Invalidate the RX mbuf and unload its map */ 1391 1392 bus_dmamap_sync(sc->sc_dmat, 1393 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1394 BUS_DMASYNC_POSTREAD); 1395 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1396 1397 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1398 m->m_len = RE_RX_DESC_BUFLEN; 1399 if (sc->rl_head == NULL) 1400 sc->rl_head = sc->rl_tail = m; 1401 else { 1402 m->m_flags &= ~M_PKTHDR; 1403 sc->rl_tail->m_next = m; 1404 sc->rl_tail = m; 1405 } 1406 continue; 1407 } 1408 1409 /* 1410 * NOTE: for the 8139C+, the frame length field 1411 * is always 12 bits in size, but for the gigE chips, 1412 * it is 13 bits (since the max RX frame length is 16K). 1413 * Unfortunately, all 32 bits in the status word 1414 * were already used, so to make room for the extra 1415 * length bit, RealTek took out the 'frame alignment 1416 * error' bit and shifted the other status bits 1417 * over one slot. The OWN, EOR, FS and LS bits are 1418 * still in the same places. We have already extracted 1419 * the frame length and checked the OWN bit, so rather 1420 * than using an alternate bit mapping, we shift the 1421 * status bits one space to the right so we can evaluate 1422 * them using the 8169 status as though it was in the 1423 * same format as that of the 8139C+. 1424 */ 1425 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) 1426 rxstat >>= 1; 1427 1428 /* 1429 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1430 * set, but if CRC is clear, it will still be a valid frame. 1431 */ 1432 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1433 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1434 ifp->if_ierrors++; 1435 /* 1436 * If this is part of a multi-fragment packet, 1437 * discard all the pieces. 1438 */ 1439 if (sc->rl_head != NULL) { 1440 m_freem(sc->rl_head); 1441 sc->rl_head = sc->rl_tail = NULL; 1442 } 1443 continue; 1444 } 1445 1446 if (sc->rl_head != NULL) { 1447 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1448 if (m->m_len == 0) 1449 m->m_len = RE_RX_DESC_BUFLEN; 1450 /* 1451 * Special case: if there's 4 bytes or less 1452 * in this buffer, the mbuf can be discarded: 1453 * the last 4 bytes is the CRC, which we don't 1454 * care about anyway. 1455 */ 1456 if (m->m_len <= ETHER_CRC_LEN) { 1457 sc->rl_tail->m_len -= 1458 (ETHER_CRC_LEN - m->m_len); 1459 m_freem(m); 1460 } else { 1461 m->m_len -= ETHER_CRC_LEN; 1462 m->m_flags &= ~M_PKTHDR; 1463 sc->rl_tail->m_next = m; 1464 } 1465 m = sc->rl_head; 1466 sc->rl_head = sc->rl_tail = NULL; 1467 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1468 } else 1469 m->m_pkthdr.len = m->m_len = 1470 (total_len - ETHER_CRC_LEN); 1471 1472 ifp->if_ipackets++; 1473 m->m_pkthdr.rcvif = ifp; 1474 1475 /* Do RX checksumming */ 1476 1477 if (sc->rl_flags & RL_FLAG_DESCV2) { 1478 /* Check IP header checksum */ 1479 if ((rxvlan & RL_RDESC_IPV4) && 1480 !(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1481 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1482 1483 /* Check TCP/UDP checksum */ 1484 if ((rxvlan & (RL_RDESC_IPV4|RL_RDESC_IPV6)) && 1485 (((rxstat & RL_RDESC_STAT_TCP) && 1486 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1487 ((rxstat & RL_RDESC_STAT_UDP) && 1488 !(rxstat & RL_RDESC_STAT_UDPSUMBAD)))) 1489 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 1490 M_UDP_CSUM_IN_OK; 1491 } else { 1492 /* Check IP header checksum */ 1493 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1494 !(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1495 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1496 1497 /* Check TCP/UDP checksum */ 1498 if ((RL_TCPPKT(rxstat) && 1499 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1500 (RL_UDPPKT(rxstat) && 1501 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) 1502 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 1503 M_UDP_CSUM_IN_OK; 1504 } 1505 #if NVLAN > 0 1506 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1507 m->m_pkthdr.ether_vtag = 1508 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1509 m->m_flags |= M_VLANTAG; 1510 } 1511 #endif 1512 1513 #if NBPFILTER > 0 1514 if (ifp->if_bpf) 1515 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1516 #endif 1517 ether_input_mbuf(ifp, m); 1518 } 1519 1520 sc->rl_ldata.rl_rx_considx = i; 1521 re_rx_list_fill(sc); 1522 1523 return (rx); 1524 } 1525 1526 int 1527 re_txeof(struct rl_softc *sc) 1528 { 1529 struct ifnet *ifp; 1530 struct rl_txq *txq; 1531 uint32_t txstat; 1532 int idx, descidx, tx = 0; 1533 1534 ifp = &sc->sc_arpcom.ac_if; 1535 1536 for (idx = sc->rl_ldata.rl_txq_considx;; idx = RL_NEXT_TXQ(sc, idx)) { 1537 txq = &sc->rl_ldata.rl_txq[idx]; 1538 1539 if (txq->txq_mbuf == NULL) { 1540 KASSERT(idx == sc->rl_ldata.rl_txq_prodidx); 1541 break; 1542 } 1543 1544 descidx = txq->txq_descidx; 1545 RL_TXDESCSYNC(sc, descidx, 1546 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1547 txstat = 1548 letoh32(sc->rl_ldata.rl_tx_list[descidx].rl_cmdstat); 1549 RL_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1550 KASSERT((txstat & RL_TDESC_CMD_EOF) != 0); 1551 if (txstat & RL_TDESC_CMD_OWN) 1552 break; 1553 1554 tx = 1; 1555 sc->rl_ldata.rl_tx_free += txq->txq_nsegs; 1556 KASSERT(sc->rl_ldata.rl_tx_free <= RL_TX_DESC_CNT(sc)); 1557 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1558 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1559 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1560 m_freem(txq->txq_mbuf); 1561 txq->txq_mbuf = NULL; 1562 1563 if (txstat & (RL_TDESC_STAT_EXCESSCOL | RL_TDESC_STAT_COLCNT)) 1564 ifp->if_collisions++; 1565 if (txstat & RL_TDESC_STAT_TXERRSUM) 1566 ifp->if_oerrors++; 1567 else 1568 ifp->if_opackets++; 1569 } 1570 1571 sc->rl_ldata.rl_txq_considx = idx; 1572 1573 if (sc->rl_ldata.rl_tx_free > RL_NTXDESC_RSVD) 1574 ifp->if_flags &= ~IFF_OACTIVE; 1575 1576 /* 1577 * Some chips will ignore a second TX request issued while an 1578 * existing transmission is in progress. If the transmitter goes 1579 * idle but there are still packets waiting to be sent, we need 1580 * to restart the channel here to flush them out. This only 1581 * seems to be required with the PCIe devices. 1582 */ 1583 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT(sc)) 1584 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1585 else 1586 ifp->if_timer = 0; 1587 1588 return (tx); 1589 } 1590 1591 void 1592 re_tick(void *xsc) 1593 { 1594 struct rl_softc *sc = xsc; 1595 struct mii_data *mii; 1596 struct ifnet *ifp; 1597 int s; 1598 1599 ifp = &sc->sc_arpcom.ac_if; 1600 mii = &sc->sc_mii; 1601 1602 s = splnet(); 1603 1604 mii_tick(mii); 1605 if (sc->rl_flags & RL_FLAG_LINK) { 1606 if (!(mii->mii_media_status & IFM_ACTIVE)) 1607 sc->rl_flags &= ~RL_FLAG_LINK; 1608 } else { 1609 if (mii->mii_media_status & IFM_ACTIVE && 1610 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1611 sc->rl_flags |= RL_FLAG_LINK; 1612 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1613 re_start(ifp); 1614 } 1615 } 1616 splx(s); 1617 1618 timeout_add_sec(&sc->timer_handle, 1); 1619 } 1620 1621 int 1622 re_intr(void *arg) 1623 { 1624 struct rl_softc *sc = arg; 1625 struct ifnet *ifp; 1626 u_int16_t status; 1627 int claimed = 0, rx, tx; 1628 1629 ifp = &sc->sc_arpcom.ac_if; 1630 1631 if (!(ifp->if_flags & IFF_RUNNING)) 1632 return (0); 1633 1634 rx = tx = 0; 1635 status = CSR_READ_2(sc, RL_ISR); 1636 /* If the card has gone away the read returns 0xffff. */ 1637 if (status == 0xffff) 1638 return (0); 1639 if (status) 1640 CSR_WRITE_2(sc, RL_ISR, status); 1641 1642 if (status & RL_ISR_TIMEOUT_EXPIRED) 1643 claimed = 1; 1644 1645 if (status & RL_INTRS_CPLUS) { 1646 if (status & (sc->rl_rx_ack | RL_ISR_RX_ERR)) { 1647 rx |= re_rxeof(sc); 1648 claimed = 1; 1649 } 1650 1651 if (status & (sc->rl_tx_ack | RL_ISR_TX_ERR)) { 1652 tx |= re_txeof(sc); 1653 claimed = 1; 1654 } 1655 1656 if (status & RL_ISR_SYSTEM_ERR) { 1657 re_reset(sc); 1658 re_init(ifp); 1659 claimed = 1; 1660 } 1661 1662 if (status & RL_ISR_LINKCHG) { 1663 timeout_del(&sc->timer_handle); 1664 re_tick(sc); 1665 claimed = 1; 1666 } 1667 } 1668 1669 if (sc->rl_imtype == RL_IMTYPE_SIM) { 1670 if ((sc->rl_flags & RL_FLAG_TIMERINTR)) { 1671 if ((tx | rx) == 0) { 1672 /* 1673 * Nothing needs to be processed, fallback 1674 * to use TX/RX interrupts. 1675 */ 1676 re_setup_intr(sc, 1, RL_IMTYPE_NONE); 1677 1678 /* 1679 * Recollect, mainly to avoid the possible 1680 * race introduced by changing interrupt 1681 * masks. 1682 */ 1683 re_rxeof(sc); 1684 tx = re_txeof(sc); 1685 } else 1686 CSR_WRITE_4(sc, RL_TIMERCNT, 1); /* reload */ 1687 } else if (tx | rx) { 1688 /* 1689 * Assume that using simulated interrupt moderation 1690 * (hardware timer based) could reduce the interrupt 1691 * rate. 1692 */ 1693 re_setup_intr(sc, 1, RL_IMTYPE_SIM); 1694 } 1695 } 1696 1697 if (tx && !IFQ_IS_EMPTY(&ifp->if_snd)) 1698 re_start(ifp); 1699 1700 return (claimed); 1701 } 1702 1703 int 1704 re_encap(struct rl_softc *sc, struct mbuf *m, int *idx) 1705 { 1706 bus_dmamap_t map; 1707 int error, seg, nsegs, uidx, startidx, curidx, lastidx, pad; 1708 struct rl_desc *d; 1709 u_int32_t cmdstat, vlanctl = 0, csum_flags = 0; 1710 struct rl_txq *txq; 1711 1712 if (sc->rl_ldata.rl_tx_free <= RL_NTXDESC_RSVD) 1713 return (EFBIG); 1714 1715 /* 1716 * Set up checksum offload. Note: checksum offload bits must 1717 * appear in all descriptors of a multi-descriptor transmit 1718 * attempt. This is according to testing done with an 8169 1719 * chip. This is a requirement. 1720 */ 1721 1722 /* 1723 * Set RL_TDESC_CMD_IPCSUM if any checksum offloading 1724 * is requested. Otherwise, RL_TDESC_CMD_TCPCSUM/ 1725 * RL_TDESC_CMD_UDPCSUM does not take affect. 1726 */ 1727 1728 if ((m->m_pkthdr.csum_flags & 1729 (M_IPV4_CSUM_OUT|M_TCP_CSUM_OUT|M_UDP_CSUM_OUT)) != 0) { 1730 if (sc->rl_flags & RL_FLAG_DESCV2) { 1731 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 1732 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1733 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 1734 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1735 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 1736 } else { 1737 csum_flags |= RL_TDESC_CMD_IPCSUM; 1738 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1739 csum_flags |= RL_TDESC_CMD_TCPCSUM; 1740 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1741 csum_flags |= RL_TDESC_CMD_UDPCSUM; 1742 } 1743 } 1744 1745 txq = &sc->rl_ldata.rl_txq[*idx]; 1746 map = txq->txq_dmamap; 1747 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1748 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1749 if (error) { 1750 /* XXX try to defrag if EFBIG? */ 1751 printf("%s: can't map mbuf (error %d)\n", 1752 sc->sc_dev.dv_xname, error); 1753 return (error); 1754 } 1755 1756 nsegs = map->dm_nsegs; 1757 pad = 0; 1758 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 1759 m->m_pkthdr.len <= RL_IP4CSUMTX_PADLEN && 1760 (csum_flags & RL_TDESC_CMD_IPCSUM) != 0) { 1761 pad = 1; 1762 nsegs++; 1763 } 1764 1765 if (nsegs > sc->rl_ldata.rl_tx_free - RL_NTXDESC_RSVD) { 1766 error = EFBIG; 1767 goto fail_unload; 1768 } 1769 1770 /* 1771 * Make sure that the caches are synchronized before we 1772 * ask the chip to start DMA for the packet data. 1773 */ 1774 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1775 BUS_DMASYNC_PREWRITE); 1776 1777 /* 1778 * Set up hardware VLAN tagging. Note: vlan tag info must 1779 * appear in all descriptors of a multi-descriptor 1780 * transmission attempt. 1781 */ 1782 #if NVLAN > 0 1783 if (m->m_flags & M_VLANTAG) 1784 vlanctl |= swap16(m->m_pkthdr.ether_vtag) | 1785 RL_TDESC_VLANCTL_TAG; 1786 #endif 1787 1788 /* 1789 * Map the segment array into descriptors. Note that we set the 1790 * start-of-frame and end-of-frame markers for either TX or RX, but 1791 * they really only have meaning in the TX case. (In the RX case, 1792 * it's the chip that tells us where packets begin and end.) 1793 * We also keep track of the end of the ring and set the 1794 * end-of-ring bits as needed, and we set the ownership bits 1795 * in all except the very first descriptor. (The caller will 1796 * set this descriptor later when it start transmission or 1797 * reception.) 1798 */ 1799 curidx = startidx = sc->rl_ldata.rl_tx_nextfree; 1800 lastidx = -1; 1801 for (seg = 0; seg < map->dm_nsegs; 1802 seg++, curidx = RL_NEXT_TX_DESC(sc, curidx)) { 1803 d = &sc->rl_ldata.rl_tx_list[curidx]; 1804 RL_TXDESCSYNC(sc, curidx, 1805 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1806 cmdstat = letoh32(d->rl_cmdstat); 1807 RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_PREREAD); 1808 if (cmdstat & RL_TDESC_STAT_OWN) { 1809 printf("%s: tried to map busy TX descriptor\n", 1810 sc->sc_dev.dv_xname); 1811 for (; seg > 0; seg --) { 1812 uidx = (curidx + RL_TX_DESC_CNT(sc) - seg) % 1813 RL_TX_DESC_CNT(sc); 1814 sc->rl_ldata.rl_tx_list[uidx].rl_cmdstat = 0; 1815 RL_TXDESCSYNC(sc, uidx, 1816 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1817 } 1818 error = ENOBUFS; 1819 goto fail_unload; 1820 } 1821 1822 d->rl_vlanctl = htole32(vlanctl); 1823 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1824 cmdstat = csum_flags | map->dm_segs[seg].ds_len; 1825 if (seg == 0) 1826 cmdstat |= RL_TDESC_CMD_SOF; 1827 else 1828 cmdstat |= RL_TDESC_CMD_OWN; 1829 if (curidx == (RL_TX_DESC_CNT(sc) - 1)) 1830 cmdstat |= RL_TDESC_CMD_EOR; 1831 if (seg == nsegs - 1) { 1832 cmdstat |= RL_TDESC_CMD_EOF; 1833 lastidx = curidx; 1834 } 1835 d->rl_cmdstat = htole32(cmdstat); 1836 RL_TXDESCSYNC(sc, curidx, 1837 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1838 } 1839 if (pad) { 1840 d = &sc->rl_ldata.rl_tx_list[curidx]; 1841 d->rl_vlanctl = htole32(vlanctl); 1842 re_set_bufaddr(d, RL_TXPADDADDR(sc)); 1843 cmdstat = csum_flags | 1844 RL_TDESC_CMD_OWN | RL_TDESC_CMD_EOF | 1845 (RL_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1846 if (curidx == (RL_TX_DESC_CNT(sc) - 1)) 1847 cmdstat |= RL_TDESC_CMD_EOR; 1848 d->rl_cmdstat = htole32(cmdstat); 1849 RL_TXDESCSYNC(sc, curidx, 1850 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1851 lastidx = curidx; 1852 curidx = RL_NEXT_TX_DESC(sc, curidx); 1853 } 1854 KASSERT(lastidx != -1); 1855 1856 /* Transfer ownership of packet to the chip. */ 1857 1858 sc->rl_ldata.rl_tx_list[startidx].rl_cmdstat |= 1859 htole32(RL_TDESC_CMD_OWN); 1860 RL_TXDESCSYNC(sc, startidx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1861 1862 /* update info of TX queue and descriptors */ 1863 txq->txq_mbuf = m; 1864 txq->txq_descidx = lastidx; 1865 txq->txq_nsegs = nsegs; 1866 1867 sc->rl_ldata.rl_tx_free -= nsegs; 1868 sc->rl_ldata.rl_tx_nextfree = curidx; 1869 1870 *idx = RL_NEXT_TXQ(sc, *idx); 1871 1872 return (0); 1873 1874 fail_unload: 1875 bus_dmamap_unload(sc->sc_dmat, map); 1876 1877 return (error); 1878 } 1879 1880 /* 1881 * Main transmit routine for C+ and gigE NICs. 1882 */ 1883 1884 void 1885 re_start(struct ifnet *ifp) 1886 { 1887 struct rl_softc *sc; 1888 int idx, queued = 0; 1889 1890 sc = ifp->if_softc; 1891 1892 if (ifp->if_flags & IFF_OACTIVE) 1893 return; 1894 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 1895 return; 1896 1897 idx = sc->rl_ldata.rl_txq_prodidx; 1898 for (;;) { 1899 struct mbuf *m; 1900 int error; 1901 1902 IFQ_POLL(&ifp->if_snd, m); 1903 if (m == NULL) 1904 break; 1905 1906 if (sc->rl_ldata.rl_txq[idx].txq_mbuf != NULL) { 1907 KASSERT(idx == sc->rl_ldata.rl_txq_considx); 1908 ifp->if_flags |= IFF_OACTIVE; 1909 break; 1910 } 1911 1912 error = re_encap(sc, m, &idx); 1913 if (error == EFBIG && 1914 sc->rl_ldata.rl_tx_free == RL_TX_DESC_CNT(sc)) { 1915 IFQ_DEQUEUE(&ifp->if_snd, m); 1916 m_freem(m); 1917 ifp->if_oerrors++; 1918 continue; 1919 } 1920 if (error) { 1921 ifp->if_flags |= IFF_OACTIVE; 1922 break; 1923 } 1924 1925 IFQ_DEQUEUE(&ifp->if_snd, m); 1926 queued++; 1927 1928 #if NBPFILTER > 0 1929 /* 1930 * If there's a BPF listener, bounce a copy of this frame 1931 * to him. 1932 */ 1933 if (ifp->if_bpf) 1934 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1935 #endif 1936 } 1937 1938 if (queued == 0) 1939 return; 1940 1941 sc->rl_ldata.rl_txq_prodidx = idx; 1942 1943 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1944 1945 /* 1946 * Set a timeout in case the chip goes out to lunch. 1947 */ 1948 ifp->if_timer = 5; 1949 } 1950 1951 int 1952 re_init(struct ifnet *ifp) 1953 { 1954 struct rl_softc *sc = ifp->if_softc; 1955 u_int16_t cfg; 1956 int s; 1957 union { 1958 u_int32_t align_dummy; 1959 u_char eaddr[ETHER_ADDR_LEN]; 1960 } eaddr; 1961 1962 s = splnet(); 1963 1964 /* 1965 * Cancel pending I/O and free all RX/TX buffers. 1966 */ 1967 re_stop(ifp); 1968 1969 /* 1970 * Enable C+ RX and TX mode, as well as RX checksum offload. 1971 * We must configure the C+ register before all others. 1972 */ 1973 cfg = RL_CPLUSCMD_TXENB | RL_CPLUSCMD_PCI_MRW; 1974 1975 if (ifp->if_capabilities & IFCAP_CSUM_IPv4) 1976 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 1977 1978 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1979 cfg |= RL_CPLUSCMD_VLANSTRIP; 1980 1981 if (sc->rl_flags & RL_FLAG_MACSTAT) 1982 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 1983 else 1984 cfg |= RL_CPLUSCMD_RXENB; 1985 1986 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 1987 1988 /* 1989 * Init our MAC address. Even though the chipset 1990 * documentation doesn't mention it, we need to enter "Config 1991 * register write enable" mode to modify the ID registers. 1992 */ 1993 bcopy(sc->sc_arpcom.ac_enaddr, eaddr.eaddr, ETHER_ADDR_LEN); 1994 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1995 CSR_WRITE_4(sc, RL_IDR4, 1996 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 1997 CSR_WRITE_4(sc, RL_IDR0, 1998 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 1999 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2000 2001 /* 2002 * For C+ mode, initialize the RX descriptors and mbufs. 2003 */ 2004 re_rx_list_init(sc); 2005 re_tx_list_init(sc); 2006 2007 /* 2008 * Load the addresses of the RX and TX lists into the chip. 2009 */ 2010 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2011 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr)); 2012 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2013 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr)); 2014 2015 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2016 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr)); 2017 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2018 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr)); 2019 2020 /* 2021 * Enable transmit and receive. 2022 */ 2023 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2024 2025 /* 2026 * Set the initial TX and RX configuration. 2027 */ 2028 if (sc->rl_testmode) { 2029 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 2030 CSR_WRITE_4(sc, RL_TXCFG, 2031 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2032 else 2033 CSR_WRITE_4(sc, RL_TXCFG, 2034 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2035 } else 2036 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2037 2038 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2039 2040 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2041 2042 /* Program promiscuous mode and multicast filters. */ 2043 re_iff(sc); 2044 2045 /* 2046 * Enable interrupts. 2047 */ 2048 if (sc->rl_testmode) 2049 CSR_WRITE_2(sc, RL_IMR, 0); 2050 else 2051 re_setup_intr(sc, 1, sc->rl_imtype); 2052 CSR_WRITE_2(sc, RL_ISR, sc->rl_imtype); 2053 2054 /* Start RX/TX process. */ 2055 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2056 #ifdef notdef 2057 /* Enable receiver and transmitter. */ 2058 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2059 #endif 2060 2061 /* 2062 * For 8169 gigE NICs, set the max allowed RX packet 2063 * size so we can receive jumbo frames. 2064 */ 2065 if (sc->sc_hwrev != RL_HWREV_8139CPLUS) 2066 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2067 2068 if (sc->rl_testmode) { 2069 splx(s); 2070 return (0); 2071 } 2072 2073 mii_mediachg(&sc->sc_mii); 2074 2075 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2076 2077 ifp->if_flags |= IFF_RUNNING; 2078 ifp->if_flags &= ~IFF_OACTIVE; 2079 2080 splx(s); 2081 2082 sc->rl_flags &= ~RL_FLAG_LINK; 2083 2084 timeout_add_sec(&sc->timer_handle, 1); 2085 2086 return (0); 2087 } 2088 2089 /* 2090 * Set media options. 2091 */ 2092 int 2093 re_ifmedia_upd(struct ifnet *ifp) 2094 { 2095 struct rl_softc *sc; 2096 2097 sc = ifp->if_softc; 2098 2099 return (mii_mediachg(&sc->sc_mii)); 2100 } 2101 2102 /* 2103 * Report current media status. 2104 */ 2105 void 2106 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2107 { 2108 struct rl_softc *sc; 2109 2110 sc = ifp->if_softc; 2111 2112 mii_pollstat(&sc->sc_mii); 2113 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2114 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2115 } 2116 2117 int 2118 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2119 { 2120 struct rl_softc *sc = ifp->if_softc; 2121 struct ifreq *ifr = (struct ifreq *) data; 2122 struct ifaddr *ifa = (struct ifaddr *)data; 2123 int s, error = 0; 2124 2125 s = splnet(); 2126 2127 switch(command) { 2128 case SIOCSIFADDR: 2129 ifp->if_flags |= IFF_UP; 2130 if (!(ifp->if_flags & IFF_RUNNING)) 2131 re_init(ifp); 2132 #ifdef INET 2133 if (ifa->ifa_addr->sa_family == AF_INET) 2134 arp_ifinit(&sc->sc_arpcom, ifa); 2135 #endif /* INET */ 2136 break; 2137 case SIOCSIFFLAGS: 2138 if (ifp->if_flags & IFF_UP) { 2139 if (ifp->if_flags & IFF_RUNNING) 2140 error = ENETRESET; 2141 else 2142 re_init(ifp); 2143 } else { 2144 if (ifp->if_flags & IFF_RUNNING) 2145 re_stop(ifp); 2146 } 2147 break; 2148 case SIOCGIFMEDIA: 2149 case SIOCSIFMEDIA: 2150 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 2151 break; 2152 default: 2153 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 2154 } 2155 2156 if (error == ENETRESET) { 2157 if (ifp->if_flags & IFF_RUNNING) 2158 re_iff(sc); 2159 error = 0; 2160 } 2161 2162 splx(s); 2163 return (error); 2164 } 2165 2166 void 2167 re_watchdog(struct ifnet *ifp) 2168 { 2169 struct rl_softc *sc; 2170 int s; 2171 2172 sc = ifp->if_softc; 2173 s = splnet(); 2174 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2175 ifp->if_oerrors++; 2176 2177 re_txeof(sc); 2178 re_rxeof(sc); 2179 2180 re_init(ifp); 2181 2182 splx(s); 2183 } 2184 2185 /* 2186 * Stop the adapter and free any mbufs allocated to the 2187 * RX and TX lists. 2188 */ 2189 void 2190 re_stop(struct ifnet *ifp) 2191 { 2192 struct rl_softc *sc; 2193 int i; 2194 2195 sc = ifp->if_softc; 2196 2197 ifp->if_timer = 0; 2198 sc->rl_flags &= ~(RL_FLAG_LINK|RL_FLAG_TIMERINTR); 2199 2200 timeout_del(&sc->timer_handle); 2201 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2202 2203 mii_down(&sc->sc_mii); 2204 2205 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2206 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2207 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2208 2209 if (sc->rl_head != NULL) { 2210 m_freem(sc->rl_head); 2211 sc->rl_head = sc->rl_tail = NULL; 2212 } 2213 2214 /* Free the TX list buffers. */ 2215 for (i = 0; i < RL_TX_QLEN; i++) { 2216 if (sc->rl_ldata.rl_txq[i].txq_mbuf != NULL) { 2217 bus_dmamap_unload(sc->sc_dmat, 2218 sc->rl_ldata.rl_txq[i].txq_dmamap); 2219 m_freem(sc->rl_ldata.rl_txq[i].txq_mbuf); 2220 sc->rl_ldata.rl_txq[i].txq_mbuf = NULL; 2221 } 2222 } 2223 2224 /* Free the RX list buffers. */ 2225 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2226 if (sc->rl_ldata.rl_rxsoft[i].rxs_mbuf != NULL) { 2227 bus_dmamap_unload(sc->sc_dmat, 2228 sc->rl_ldata.rl_rxsoft[i].rxs_dmamap); 2229 m_freem(sc->rl_ldata.rl_rxsoft[i].rxs_mbuf); 2230 sc->rl_ldata.rl_rxsoft[i].rxs_mbuf = NULL; 2231 } 2232 } 2233 } 2234 2235 void 2236 re_setup_hw_im(struct rl_softc *sc) 2237 { 2238 KASSERT(sc->rl_flags & RL_FLAG_HWIM); 2239 2240 /* 2241 * Interrupt moderation 2242 * 2243 * 0xABCD 2244 * A - unknown (maybe TX related) 2245 * B - TX timer (unit: 25us) 2246 * C - unknown (maybe RX related) 2247 * D - RX timer (unit: 25us) 2248 * 2249 * 2250 * re(4)'s interrupt moderation is actually controlled by 2251 * two variables, like most other NICs (bge, bnx etc.) 2252 * o timer 2253 * o number of packets [P] 2254 * 2255 * The logic relationship between these two variables is 2256 * similar to other NICs too: 2257 * if (timer expire || packets > [P]) 2258 * Interrupt is delivered 2259 * 2260 * Currently we only know how to set 'timer', but not 2261 * 'number of packets', which should be ~30, as far as I 2262 * tested (sink ~900Kpps, interrupt rate is 30KHz) 2263 */ 2264 CSR_WRITE_2(sc, RL_IM, 2265 RL_IM_RXTIME(sc->rl_rx_time) | 2266 RL_IM_TXTIME(sc->rl_tx_time) | 2267 RL_IM_MAGIC); 2268 } 2269 2270 void 2271 re_disable_hw_im(struct rl_softc *sc) 2272 { 2273 if (sc->rl_flags & RL_FLAG_HWIM) 2274 CSR_WRITE_2(sc, RL_IM, 0); 2275 } 2276 2277 void 2278 re_setup_sim_im(struct rl_softc *sc) 2279 { 2280 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 2281 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); /* XXX */ 2282 else { 2283 u_int32_t ticks; 2284 2285 /* 2286 * Datasheet says tick decreases at bus speed, 2287 * but it seems the clock runs a little bit 2288 * faster, so we do some compensation here. 2289 */ 2290 ticks = (sc->rl_sim_time * sc->rl_bus_speed * 8) / 5; 2291 CSR_WRITE_4(sc, RL_TIMERINT_8169, ticks); 2292 } 2293 CSR_WRITE_4(sc, RL_TIMERCNT, 1); /* reload */ 2294 sc->rl_flags |= RL_FLAG_TIMERINTR; 2295 } 2296 2297 void 2298 re_disable_sim_im(struct rl_softc *sc) 2299 { 2300 if (sc->sc_hwrev == RL_HWREV_8139CPLUS) 2301 CSR_WRITE_4(sc, RL_TIMERINT, 0); 2302 else 2303 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0); 2304 sc->rl_flags &= ~RL_FLAG_TIMERINTR; 2305 } 2306 2307 void 2308 re_config_imtype(struct rl_softc *sc, int imtype) 2309 { 2310 switch (imtype) { 2311 case RL_IMTYPE_HW: 2312 KASSERT(sc->rl_flags & RL_FLAG_HWIM); 2313 /* FALLTHROUGH */ 2314 case RL_IMTYPE_NONE: 2315 sc->rl_intrs = RL_INTRS_CPLUS; 2316 sc->rl_rx_ack = RL_ISR_RX_OK | RL_ISR_FIFO_OFLOW | 2317 RL_ISR_RX_OVERRUN; 2318 sc->rl_tx_ack = RL_ISR_TX_OK; 2319 break; 2320 2321 case RL_IMTYPE_SIM: 2322 sc->rl_intrs = RL_INTRS_TIMER; 2323 sc->rl_rx_ack = RL_ISR_TIMEOUT_EXPIRED; 2324 sc->rl_tx_ack = RL_ISR_TIMEOUT_EXPIRED; 2325 break; 2326 2327 default: 2328 panic("%s: unknown imtype %d", 2329 sc->sc_dev.dv_xname, imtype); 2330 } 2331 } 2332 2333 void 2334 re_setup_intr(struct rl_softc *sc, int enable_intrs, int imtype) 2335 { 2336 re_config_imtype(sc, imtype); 2337 2338 if (enable_intrs) 2339 CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs); 2340 else 2341 CSR_WRITE_2(sc, RL_IMR, 0); 2342 2343 switch (imtype) { 2344 case RL_IMTYPE_NONE: 2345 re_disable_sim_im(sc); 2346 re_disable_hw_im(sc); 2347 break; 2348 2349 case RL_IMTYPE_HW: 2350 KASSERT(sc->rl_flags & RL_FLAG_HWIM); 2351 re_disable_sim_im(sc); 2352 re_setup_hw_im(sc); 2353 break; 2354 2355 case RL_IMTYPE_SIM: 2356 re_disable_hw_im(sc); 2357 re_setup_sim_im(sc); 2358 break; 2359 2360 default: 2361 panic("%s: unknown imtype %d", 2362 sc->sc_dev.dv_xname, imtype); 2363 } 2364 } 2365 2366 #ifndef SMALL_KERNEL 2367 int 2368 re_wol(struct ifnet *ifp, int enable) 2369 { 2370 struct rl_softc *sc = ifp->if_softc; 2371 int i; 2372 u_int8_t val; 2373 struct re_wolcfg { 2374 u_int8_t enable; 2375 u_int8_t reg; 2376 u_int8_t bit; 2377 } re_wolcfg[] = { 2378 /* Always disable all wake events expect magic packet. */ 2379 { 0, RL_CFG5, RL_CFG5_WOL_UCAST }, 2380 { 0, RL_CFG5, RL_CFG5_WOL_MCAST }, 2381 { 0, RL_CFG5, RL_CFG5_WOL_BCAST }, 2382 { 1, RL_CFG3, RL_CFG3_WOL_MAGIC }, 2383 { 0, RL_CFG3, RL_CFG3_WOL_LINK } 2384 }; 2385 2386 if (enable) { 2387 if ((CSR_READ_1(sc, RL_CFG1) & RL_CFG1_PME) == 0) { 2388 printf("%s: power management is disabled, " 2389 "cannot do WOL\n", sc->sc_dev.dv_xname); 2390 return (ENOTSUP); 2391 } 2392 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_AUXPWR) == 0) 2393 printf("%s: no auxiliary power, cannot do WOL from D3 " 2394 "(power-off) state\n", sc->sc_dev.dv_xname); 2395 } 2396 2397 /* Temporarily enable write to configuration registers. */ 2398 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2399 2400 for (i = 0; i < nitems(re_wolcfg); i++) { 2401 val = CSR_READ_1(sc, re_wolcfg[i].reg); 2402 if (enable && re_wolcfg[i].enable) 2403 val |= re_wolcfg[i].bit; 2404 else 2405 val &= ~re_wolcfg[i].bit; 2406 CSR_WRITE_1(sc, re_wolcfg[i].reg, val); 2407 } 2408 2409 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2410 2411 return (0); 2412 } 2413 #endif 2414