1 /* $OpenBSD: r92creg.h,v 1.3 2016/03/07 19:41:49 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define R92C_MAX_CHAINS 2 21 #define R92C_MAX_TX_PWR 0x3f 22 #define R92C_H2C_NBOX 4 23 24 /* 25 * MAC registers. 26 */ 27 /* System Configuration. */ 28 #define R92C_SYS_ISO_CTRL 0x000 29 #define R92C_SYS_FUNC_EN 0x002 30 #define R92C_APS_FSMCO 0x004 31 #define R92C_SYS_CLKR 0x008 32 #define R92C_AFE_MISC 0x010 33 #define R92C_SPS0_CTRL 0x011 34 #define R92C_SPS_OCP_CFG 0x018 35 #define R92C_RSV_CTRL 0x01c 36 #define R92C_RF_CTRL 0x01f 37 #define R92C_LDOA15_CTRL 0x020 38 #define R92C_LDOV12D_CTRL 0x021 39 #define R92C_LDOHCI12_CTRL 0x022 40 #define R92C_LPLDO_CTRL 0x023 41 #define R92C_AFE_XTAL_CTRL 0x024 42 #define R92C_AFE_PLL_CTRL 0x028 43 #define R92C_EFUSE_CTRL 0x030 44 #define R92C_EFUSE_TEST 0x034 45 #define R92C_PWR_DATA 0x038 46 #define R92C_CAL_TIMER 0x03c 47 #define R92C_ACLK_MON 0x03e 48 #define R92C_GPIO_MUXCFG 0x040 49 #define R92C_GPIO_IO_SEL 0x042 50 #define R92C_MAC_PINMUX_CFG 0x043 51 #define R92C_GPIO_PIN_CTRL 0x044 52 #define R92C_GPIO_INTM 0x048 53 #define R92C_LEDCFG0 0x04c 54 #define R92C_LEDCFG1 0x04d 55 #define R92C_LEDCFG2 0x04e 56 #define R92C_LEDCFG3 0x04f 57 #define R92C_FSIMR 0x050 58 #define R92C_FSISR 0x054 59 #define R92C_HSIMR 0x058 60 #define R92C_HSISR 0x05c 61 #define R92C_MCUFWDL 0x080 62 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 63 #define R88E_HIMR 0x0b0 64 #define R88E_HISR 0x0b4 65 #define R88E_HIMRE 0x0b8 66 #define R88E_HISRE 0x0bc 67 #define R92C_EFUSE_ACCESS 0x0cf 68 #define R92C_BIST_SCAN 0x0d0 69 #define R92C_BIST_RPT 0x0d4 70 #define R92C_BIST_ROM_RPT 0x0d8 71 #define R92C_USB_SIE_INTF 0x0e0 72 #define R92C_PCIE_MIO_INTF 0x0e4 73 #define R92C_PCIE_MIO_INTD 0x0e8 74 #define R92C_HPON_FSM 0x0ec 75 #define R92C_SYS_CFG 0x0f0 76 /* MAC General Configuration. */ 77 #define R92C_CR 0x100 78 #define R92C_PBP 0x104 79 #define R92C_TRXDMA_CTRL 0x10c 80 #define R92C_TRXFF_BNDY 0x114 81 #define R92C_TRXFF_STATUS 0x118 82 #define R92C_RXFF_PTR 0x11c 83 #define R92C_HIMR 0x120 84 #define R92C_HISR 0x124 85 #define R92C_HIMRE 0x128 86 #define R92C_HISRE 0x12c 87 #define R92C_CPWM 0x12f 88 #define R92C_FWIMR 0x130 89 #define R92C_FWISR 0x134 90 #define R92C_PKTBUF_DBG_CTRL 0x140 91 #define R92C_PKTBUF_DBG_DATA_L 0x144 92 #define R92C_PKTBUF_DBG_DATA_H 0x148 93 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 94 #define R92C_TCUNIT_BASE 0x164 95 #define R92C_MBIST_START 0x174 96 #define R92C_MBIST_DONE 0x178 97 #define R92C_MBIST_FAIL 0x17c 98 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 99 #define R92C_C2HEVT_MSG_TEST 0x1b8 100 #define R92C_C2HEVT_CLEAR 0x1bf 101 #define R92C_MCUTST_1 0x1c0 102 #define R92C_FMETHR 0x1c8 103 #define R92C_HMETFR 0x1cc 104 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 105 #define R92C_LLT_INIT 0x1e0 106 #define R92C_BB_ACCESS_CTRL 0x1e8 107 #define R92C_BB_ACCESS_DATA 0x1ec 108 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 109 /* Tx DMA Configuration. */ 110 #define R92C_RQPN 0x200 111 #define R92C_FIFOPAGE 0x204 112 #define R92C_TDECTRL 0x208 113 #define R92C_TXDMA_OFFSET_CHK 0x20c 114 #define R92C_TXDMA_STATUS 0x210 115 #define R92C_RQPN_NPQ 0x214 116 /* Rx DMA Configuration. */ 117 #define R92C_RXDMA_AGG_PG_TH 0x280 118 #define R92C_RXPKT_NUM 0x284 119 #define R92C_RXDMA_STATUS 0x288 120 121 #define R92C_PCIE_CTRL_REG 0x300 122 #define R92C_INT_MIG 0x304 123 #define R92C_BCNQ_DESA 0x308 124 #define R92C_HQ_DESA 0x310 125 #define R92C_MGQ_DESA 0x318 126 #define R92C_VOQ_DESA 0x320 127 #define R92C_VIQ_DESA 0x328 128 #define R92C_BEQ_DESA 0x330 129 #define R92C_BKQ_DESA 0x338 130 #define R92C_RX_DESA 0x340 131 #define R92C_DBI 0x348 132 #define R92C_MDIO 0x354 133 #define R92C_DBG_SEL 0x360 134 #define R92C_PCIE_HRPWM 0x361 135 #define R92C_PCIE_HCPWM 0x363 136 #define R92C_UART_CTRL 0x364 137 #define R92C_UART_TX_DES 0x370 138 #define R92C_UART_RX_DES 0x378 139 140 #define R92C_VOQ_INFORMATION 0x0400 141 #define R92C_VIQ_INFORMATION 0x0404 142 #define R92C_BEQ_INFORMATION 0x0408 143 #define R92C_BKQ_INFORMATION 0x040C 144 #define R92C_MGQ_INFORMATION 0x0410 145 #define R92C_HGQ_INFORMATION 0x0414 146 #define R92C_BCNQ_INFORMATION 0x0418 147 #define R92C_CPU_MGQ_INFORMATION 0x041C 148 149 /* Protocol Configuration. */ 150 #define R92C_FWHW_TXQ_CTRL 0x420 151 #define R92C_HWSEQ_CTRL 0x423 152 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 153 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 154 #define R92C_SPEC_SIFS 0x428 155 #define R92C_RL 0x42a 156 #define R92C_DARFRC 0x430 157 #define R92C_RARFRC 0x438 158 #define R92C_RRSR 0x440 159 #define R92C_ARFR(i) (0x444 + (i) * 4) 160 #define R92C_AGGLEN_LMT 0x458 161 #define R92C_AMPDU_MIN_SPACE 0x45c 162 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 163 #define R92C_FAST_EDCA_CTRL 0x460 164 #define R92C_RD_RESP_PKT_TH 0x463 165 #define R92C_INIRTS_RATE_SEL 0x480 166 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 167 #define R92C_MAX_AGGR_NUM 0x4ca 168 /* EDCA Configuration. */ 169 #define R92C_EDCA_VO_PARAM 0x500 170 #define R92C_EDCA_VI_PARAM 0x504 171 #define R92C_EDCA_BE_PARAM 0x508 172 #define R92C_EDCA_BK_PARAM 0x50c 173 #define R92C_BCNTCFG 0x510 174 #define R92C_PIFS 0x512 175 #define R92C_RDG_PIFS 0x513 176 #define R92C_SIFS_CCK 0x514 177 #define R92C_SIFS_OFDM 0x516 178 #define R92C_AGGR_BREAK_TIME 0x51a 179 #define R92C_SLOT 0x51b 180 #define R92C_TX_PTCL_CTRL 0x520 181 #define R92C_TXPAUSE 0x522 182 #define R92C_DIS_TXREQ_CLR 0x523 183 #define R92C_RD_CTRL 0x524 184 #define R92C_TBTT_PROHIBIT 0x540 185 #define R92C_RD_NAV_NXT 0x544 186 #define R92C_NAV_PROT_LEN 0x546 187 #define R92C_BCN_CTRL 0x550 188 #define R92C_USTIME_TSF 0x551 189 #define R92C_MBID_NUM 0x552 190 #define R92C_DUAL_TSF_RST 0x553 191 #define R92C_BCN_INTERVAL 0x554 192 #define R92C_DRVERLYINT 0x558 193 #define R92C_BCNDMATIM 0x559 194 #define R92C_ATIMWND 0x55a 195 #define R92C_BCN_MAX_ERR 0x55d 196 #define R92C_RXTSF_OFFSET_CCK 0x55e 197 #define R92C_RXTSF_OFFSET_OFDM 0x55f 198 #define R92C_TSFTR 0x560 199 #define R92C_INIT_TSFTR 0x564 200 #define R92C_PSTIMER 0x580 201 #define R92C_TIMER0 0x584 202 #define R92C_TIMER1 0x588 203 #define R92C_ACMHWCTRL 0x5c0 204 #define R92C_ACMRSTCTRL 0x5c1 205 #define R92C_ACMAVG 0x5c2 206 #define R92C_VO_ADMTIME 0x5c4 207 #define R92C_VI_ADMTIME 0x5c6 208 #define R92C_BE_ADMTIME 0x5c8 209 #define R92C_EDCA_RANDOM_GEN 0x5cc 210 #define R92C_SCH_TXCMD 0x5d0 211 /* WMAC Configuration. */ 212 #define R92C_APSD_CTRL 0x600 213 #define R92C_BWOPMODE 0x603 214 #define R92C_TCR 0x604 215 #define R92C_RCR 0x608 216 #define R92C_RX_DRVINFO_SZ 0x60f 217 #define R92C_MACID 0x610 218 #define R92C_BSSID 0x618 219 #define R92C_MAR 0x620 220 #define R92C_MAC_SPEC_SIFS 0x63a 221 #define R92C_R2T_SIFS 0x63c 222 #define R92C_T2T_SIFS 0x63e 223 #define R92C_ACKTO 0x640 224 #define R92C_CAMCMD 0x670 225 #define R92C_CAMWRITE 0x674 226 #define R92C_CAMREAD 0x678 227 #define R92C_CAMDBG 0x67c 228 #define R92C_SECCFG 0x680 229 #define R92C_RXFLTMAP0 0x6a0 230 #define R92C_RXFLTMAP1 0x6a2 231 #define R92C_RXFLTMAP2 0x6a4 232 233 /* Bits for R92C_SYS_ISO_CTRL. */ 234 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 235 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 236 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 237 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 238 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 239 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 240 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 241 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 242 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 243 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 244 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 245 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 246 247 /* Bits for R92C_SYS_FUNC_EN. */ 248 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 249 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 250 #define R92C_SYS_FUNC_EN_USBA 0x0004 251 #define R92C_SYS_FUNC_EN_UPLL 0x0008 252 #define R92C_SYS_FUNC_EN_USBD 0x0010 253 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 254 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 255 #define R92C_SYS_FUNC_EN_PPLL 0x0080 256 #define R92C_SYS_FUNC_EN_PCIED 0x0100 257 #define R92C_SYS_FUNC_EN_DIOE 0x0200 258 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 259 #define R92C_SYS_FUNC_EN_DCORE 0x0800 260 #define R92C_SYS_FUNC_EN_ELDR 0x1000 261 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 262 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 263 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 264 265 /* Bits for R92C_APS_FSMCO. */ 266 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 267 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 268 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 269 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 270 #define R92C_APS_FSMCO_PDN_EN 0x00000010 271 #define R92C_APS_FSMCO_PDN_PL 0x00000020 272 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 273 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 274 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 275 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 276 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 277 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 278 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 279 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 280 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 281 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 282 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 283 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 284 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 285 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 286 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 287 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 288 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 289 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 290 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 291 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 292 293 /* Bits for R92C_SYS_CLKR. */ 294 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 295 #define R92C_SYS_CLKR_ANA8M 0x00000002 296 #define R92C_SYS_CLKR_MACSLP 0x00000010 297 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 298 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 299 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 300 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 301 #define R92C_SYS_CLKR_SEC_EN 0x00000400 302 #define R92C_SYS_CLKR_MAC_EN 0x00000800 303 #define R92C_SYS_CLKR_SYS_EN 0x00001000 304 #define R92C_SYS_CLKR_RING_EN 0x00002000 305 306 /* Bits for R92C_RF_CTRL. */ 307 #define R92C_RF_CTRL_EN 0x01 308 #define R92C_RF_CTRL_RSTB 0x02 309 #define R92C_RF_CTRL_SDMRSTB 0x04 310 311 /* Bits for R92C_LDOV12D_CTRL. */ 312 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 313 314 /* Bits for R92C_AFE_XTAL_CTRL. */ 315 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 316 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 317 318 /* Bits for R92C_EFUSE_CTRL. */ 319 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 320 #define R92C_EFUSE_CTRL_DATA_S 0 321 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 322 #define R92C_EFUSE_CTRL_ADDR_S 8 323 #define R92C_EFUSE_CTRL_VALID 0x80000000 324 325 /* Bits for R92C_GPIO_MUXCFG. */ 326 #define R92C_GPIO_MUXCFG_RFKILL 0x0008 327 #define R92C_GPIO_MUXCFG_ENBT 0x0020 328 329 /* Bits for R92C_GPIO_IO_SEL. */ 330 #define R92C_GPIO_IO_SEL_RFKILL 0x0008 331 332 /* Bits for R92C_LEDCFG0. */ 333 #define R92C_LEDCFG0_DIS 0x08 334 335 /* Bits for R92C_LEDCFG2. */ 336 #define R92C_LEDCFG2_EN 0x60 337 #define R92C_LEDCFG2_DIS 0x68 338 339 /* Bits for R92C_MCUFWDL. */ 340 #define R92C_MCUFWDL_EN 0x00000001 341 #define R92C_MCUFWDL_RDY 0x00000002 342 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 343 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 344 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 345 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 346 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 347 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 348 #define R92C_MCUFWDL_PAGE_M 0x00070000 349 #define R92C_MCUFWDL_PAGE_S 16 350 #define R92C_MCUFWDL_CPRST 0x00800000 351 352 /* Bits for R88E_HIMR. */ 353 #define R88E_HIMR_CPWM 0x00000100 354 #define R88E_HIMR_CPWM2 0x00000200 355 #define R88E_HIMR_TBDER 0x04000000 356 #define R88E_HIMR_PSTIMEOUT 0x20000000 357 358 /* Bits for R88E_HIMRE.*/ 359 #define R88E_HIMRE_RXFOVW 0x00000100 360 #define R88E_HIMRE_TXFOVW 0x00000200 361 #define R88E_HIMRE_RXERR 0x00000400 362 #define R88E_HIMRE_TXERR 0x00000800 363 364 /* Bits for R92C_EFUSE_ACCESS. */ 365 #define R92C_EFUSE_ACCESS_OFF 0x00 366 #define R92C_EFUSE_ACCESS_ON 0x69 367 368 /* Bits for R92C_HPON_FSM. */ 369 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 370 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 371 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 372 373 /* Bits for R92C_SYS_CFG. */ 374 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 375 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 376 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 377 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 378 #define R92C_SYS_CFG_PCIRSTB 0x00000010 379 #define R92C_SYS_CFG_V15_VLD 0x00000020 380 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 381 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 382 #define R92C_SYS_CFG_BD_MAC2 0x00000200 383 #define R92C_SYS_CFG_BD_MAC1 0x00000400 384 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 385 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 386 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 387 #define R92C_SYS_CFG_BT_FUNC 0x00010000 388 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 389 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 390 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 391 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 392 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 393 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 394 #define R92C_SYS_CFG_TYPE_92C 0x08000000 395 396 /* Bits for R92C_CR. */ 397 #define R92C_CR_HCI_TXDMA_EN 0x00000001 398 #define R92C_CR_HCI_RXDMA_EN 0x00000002 399 #define R92C_CR_TXDMA_EN 0x00000004 400 #define R92C_CR_RXDMA_EN 0x00000008 401 #define R92C_CR_PROTOCOL_EN 0x00000010 402 #define R92C_CR_SCHEDULE_EN 0x00000020 403 #define R92C_CR_MACTXEN 0x00000040 404 #define R92C_CR_MACRXEN 0x00000080 405 #define R92C_CR_ENSEC 0x00000200 406 #define R92C_CR_CALTMR_EN 0x00000400 407 #define R92C_CR_NETTYPE_S 16 408 #define R92C_CR_NETTYPE_M 0x00030000 409 #define R92C_CR_NETTYPE_NOLINK 0 410 #define R92C_CR_NETTYPE_ADHOC 1 411 #define R92C_CR_NETTYPE_INFRA 2 412 #define R92C_CR_NETTYPE_AP 3 413 414 /* Bits for R92C_PBP. */ 415 #define R92C_PBP_PSRX_M 0x0f 416 #define R92C_PBP_PSRX_S 0 417 #define R92C_PBP_PSTX_M 0xf0 418 #define R92C_PBP_PSTX_S 4 419 #define R92C_PBP_64 0 420 #define R92C_PBP_128 1 421 #define R92C_PBP_256 2 422 #define R92C_PBP_512 3 423 #define R92C_PBP_1024 4 424 425 /* Bits for R92C_TRXDMA_CTRL. */ 426 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 427 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 428 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 429 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 430 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 431 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 432 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 433 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 434 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 435 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 436 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 437 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 438 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 439 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 440 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 441 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 442 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 443 #define R92C_TRXDMA_CTRL_QMAP_S 4 444 /* Shortcuts. */ 445 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 446 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 447 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 448 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 449 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 450 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 451 452 /* Bits for R92C_LLT_INIT. */ 453 #define R92C_LLT_INIT_DATA_M 0x000000ff 454 #define R92C_LLT_INIT_DATA_S 0 455 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 456 #define R92C_LLT_INIT_ADDR_S 8 457 #define R92C_LLT_INIT_OP_M 0xc0000000 458 #define R92C_LLT_INIT_OP_S 30 459 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 460 #define R92C_LLT_INIT_OP_WRITE 1 461 462 /* Bits for R92C_RQPN. */ 463 #define R92C_RQPN_HPQ_M 0x000000ff 464 #define R92C_RQPN_HPQ_S 0 465 #define R92C_RQPN_LPQ_M 0x0000ff00 466 #define R92C_RQPN_LPQ_S 8 467 #define R92C_RQPN_PUBQ_M 0x00ff0000 468 #define R92C_RQPN_PUBQ_S 16 469 #define R92C_RQPN_LD 0x80000000 470 471 /* Bits for R92C_TDECTRL. */ 472 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 473 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 474 475 /* Bits for R92C_FWHW_TXQ_CTRL. */ 476 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 477 478 /* Bits for R92C_SPEC_SIFS. */ 479 #define R92C_SPEC_SIFS_CCK_M 0x00ff 480 #define R92C_SPEC_SIFS_CCK_S 0 481 #define R92C_SPEC_SIFS_OFDM_M 0xff00 482 #define R92C_SPEC_SIFS_OFDM_S 8 483 484 /* Bits for R92C_RL. */ 485 #define R92C_RL_LRL_M 0x003f 486 #define R92C_RL_LRL_S 0 487 #define R92C_RL_SRL_M 0x3f00 488 #define R92C_RL_SRL_S 8 489 490 /* Bits for R92C_RRSR. */ 491 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 492 #define R92C_RRSR_RATE_BITMAP_S 0 493 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 494 #define R92C_RRSR_RATE_ALL 0xfffff 495 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 496 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 497 #define R92C_RRSR_SHORT 0x00800000 498 499 /* Bits for R92C_EDCA_XX_PARAM. */ 500 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 501 #define R92C_EDCA_PARAM_AIFS_S 0 502 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 503 #define R92C_EDCA_PARAM_ECWMIN_S 8 504 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 505 #define R92C_EDCA_PARAM_ECWMAX_S 12 506 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 507 #define R92C_EDCA_PARAM_TXOP_S 16 508 509 /* Bits for R92C_TXPAUSE. */ 510 #define R92C_TXPAUSE_AC_VO 0x01 511 #define R92C_TXPAUSE_AC_VI 0x02 512 #define R92C_TXPAUSE_AC_BE 0x04 513 #define R92C_TXPAUSE_AC_BK 0x08 514 515 /* Bits for R92C_BCN_CTRL. */ 516 #define R92C_BCN_CTRL_EN_MBSSID 0x02 517 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 518 #define R92C_BCN_CTRL_EN_BCN 0x08 519 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 520 521 /* Bits for R92C_APSD_CTRL. */ 522 #define R92C_APSD_CTRL_OFF 0x40 523 #define R92C_APSD_CTRL_OFF_STATUS 0x80 524 525 /* Bits for R92C_BWOPMODE. */ 526 #define R92C_BWOPMODE_11J 0x01 527 #define R92C_BWOPMODE_5G 0x02 528 #define R92C_BWOPMODE_20MHZ 0x04 529 530 /* Bits for R92C_TCR. */ 531 #define R92C_TCR_TSFRST 0x00000001 532 #define R92C_TCR_DIS_GCLK 0x00000002 533 #define R92C_TCR_PAD_SEL 0x00000004 534 #define R92C_TCR_PWR_ST 0x00000040 535 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 536 #define R92C_TCR_ACRC 0x00000100 537 #define R92C_TCR_CFENDFORM 0x00000200 538 #define R92C_TCR_ICV 0x00000400 539 540 /* Bits for R92C_RCR. */ 541 #define R92C_RCR_AAP 0x00000001 542 #define R92C_RCR_APM 0x00000002 543 #define R92C_RCR_AM 0x00000004 544 #define R92C_RCR_AB 0x00000008 545 #define R92C_RCR_ADD3 0x00000010 546 #define R92C_RCR_APWRMGT 0x00000020 547 #define R92C_RCR_CBSSID_DATA 0x00000040 548 #define R92C_RCR_CBSSID_BCN 0x00000080 549 #define R92C_RCR_ACRC32 0x00000100 550 #define R92C_RCR_AICV 0x00000200 551 #define R92C_RCR_ADF 0x00000800 552 #define R92C_RCR_ACF 0x00001000 553 #define R92C_RCR_AMF 0x00002000 554 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 555 #define R92C_RCR_MFBEN 0x00400000 556 #define R92C_RCR_LSIGEN 0x00800000 557 #define R92C_RCR_ENMBID 0x01000000 558 #define R92C_RCR_APP_BA_SSN 0x08000000 559 #define R92C_RCR_APP_PHYSTS 0x10000000 560 #define R92C_RCR_APP_ICV 0x20000000 561 #define R92C_RCR_APP_MIC 0x40000000 562 #define R92C_RCR_APPFCS 0x80000000 563 564 /* Bits for R92C_CAMCMD. */ 565 #define R92C_CAMCMD_ADDR_M 0x0000ffff 566 #define R92C_CAMCMD_ADDR_S 0 567 #define R92C_CAMCMD_WRITE 0x00010000 568 #define R92C_CAMCMD_CLR 0x40000000 569 #define R92C_CAMCMD_POLLING 0x80000000 570 571 /* IMR */ 572 573 /*Beacon DMA interrupt 6 */ 574 #define R92C_IMR_BCNDMAINT6 0x80000000 575 /*Beacon DMA interrupt 5 */ 576 #define R92C_IMR_BCNDMAINT5 0x40000000 577 /*Beacon DMA interrupt 4 */ 578 #define R92C_IMR_BCNDMAINT4 0x20000000 579 /*Beacon DMA interrupt 3 */ 580 #define R92C_IMR_BCNDMAINT3 0x10000000 581 /*Beacon DMA interrupt 2 */ 582 #define R92C_IMR_BCNDMAINT2 0x08000000 583 /*Beacon DMA interrupt 1 */ 584 #define R92C_IMR_BCNDMAINT1 0x04000000 585 /*Beacon Queue DMA OK interrupt 8 */ 586 #define R92C_IMR_BCNDOK8 0x02000000 587 /*Beacon Queue DMA OK interrupt 7 */ 588 #define R92C_IMR_BCNDOK7 0x01000000 589 /*Beacon Queue DMA OK interrupt 6 */ 590 #define R92C_IMR_BCNDOK6 0x00800000 591 /*Beacon Queue DMA OK interrupt 5 */ 592 #define R92C_IMR_BCNDOK5 0x00400000 593 /*Beacon Queue DMA OK interrupt 4 */ 594 #define R92C_IMR_BCNDOK4 0x00200000 595 /*Beacon Queue DMA OK interrupt 3 */ 596 #define R92C_IMR_BCNDOK3 0x00100000 597 /*Beacon Queue DMA OK interrupt 2 */ 598 #define R92C_IMR_BCNDOK2 0x00080000 599 /*Beacon Queue DMA OK interrupt 1 */ 600 #define R92C_IMR_BCNDOK1 0x00040000 601 /*Timeout interrupt 2 */ 602 #define R92C_IMR_TIMEOUT2 0x00020000 603 /*Timeout interrupt 1 */ 604 #define R92C_IMR_TIMEOUT1 0x00010000 605 /*Transmit FIFO Overflow */ 606 #define R92C_IMR_TXFOVW 0x00008000 607 /*Power save time out interrupt */ 608 #define R92C_IMR_PSTIMEOUT 0x00004000 609 /*Beacon DMA interrupt 0 */ 610 #define R92C_IMR_BCNINT 0x00002000 611 /*Receive FIFO Overflow */ 612 #define R92C_IMR_RXFOVW 0x00001000 613 /*Receive Descriptor Unavailable */ 614 #define R92C_IMR_RDU 0x00000800 615 /*For 92C,ATIM Window End interrupt */ 616 #define R92C_IMR_ATIMEND 0x00000400 617 /*Beacon Queue DMA OK interrupt */ 618 #define R92C_IMR_BDOK 0x00000200 619 /*High Queue DMA OK interrupt */ 620 #define R92C_IMR_HIGHDOK 0x00000100 621 /*Transmit Beacon OK interrupt */ 622 #define R92C_IMR_TBDOK 0x00000080 623 /*Management Queue DMA OK interrupt */ 624 #define R92C_IMR_MGNTDOK 0x00000040 625 /*For 92C,Transmit Beacon Error interrupt */ 626 #define R92C_IMR_TBDER 0x00000020 627 /*AC_BK DMA OK interrupt */ 628 #define R92C_IMR_BKDOK 0x00000010 629 /*AC_BE DMA OK interrupt */ 630 #define R92C_IMR_BEDOK 0x00000008 631 /*AC_VI DMA OK interrupt */ 632 #define R92C_IMR_VIDOK 0x00000004 633 /*AC_VO DMA interrupt */ 634 #define R92C_IMR_VODOK 0x00000002 635 /*Receive DMA OK interrupt */ 636 #define R92C_IMR_ROK 0x00000001 637 638 #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) 639 640 641 /* 642 * Baseband registers. 643 */ 644 #define R92C_FPGA0_RFMOD 0x800 645 #define R92C_FPGA0_TXINFO 0x804 646 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 647 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 648 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 649 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 650 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 651 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 652 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 653 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 654 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 655 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 656 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 657 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 658 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 659 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 660 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 661 #define R92C_FPGA0_ANAPARAM2 0x884 662 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 663 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 664 #define R92C_FPGA1_RFMOD 0x900 665 #define R92C_FPGA1_TXINFO 0x90c 666 #define R92C_CCK0_SYSTEM 0xa00 667 #define R92C_CCK0_AFESETTING 0xa04 668 #define R92C_OFDM0_TRXPATHENA 0xc04 669 #define R92C_OFDM0_TRMUXPAR 0xc08 670 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 671 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 672 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 673 #define R92C_OFDM0_AGCPARAM1 0xc70 674 #define R92C_OFDM0_AGCRSSITABLE 0xc78 675 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 676 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 677 #define R92C_OFDM0_RXIQEXTANTA 0xca0 678 #define R92C_OFDM1_LSTF 0xd00 679 680 /* Bits for R92C_FPGA[01]_RFMOD. */ 681 #define R92C_RFMOD_40MHZ 0x00000001 682 #define R92C_RFMOD_JAPAN 0x00000002 683 #define R92C_RFMOD_CCK_TXSC 0x00000030 684 #define R92C_RFMOD_CCK_EN 0x01000000 685 #define R92C_RFMOD_OFDM_EN 0x02000000 686 687 /* Bits for R92C_HSSI_PARAM1(i). */ 688 #define R92C_HSSI_PARAM1_PI 0x00000100 689 690 /* Bits for R92C_HSSI_PARAM2(i). */ 691 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 692 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 693 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 694 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 695 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 696 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 697 698 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 699 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 700 #define R92C_TXAGC_A_CCK1_S 8 701 702 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 703 #define R92C_TXAGC_B_CCK11_M 0x000000ff 704 #define R92C_TXAGC_B_CCK11_S 0 705 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 706 #define R92C_TXAGC_A_CCK2_S 8 707 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 708 #define R92C_TXAGC_A_CCK55_S 16 709 #define R92C_TXAGC_A_CCK11_M 0xff000000 710 #define R92C_TXAGC_A_CCK11_S 24 711 712 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 713 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 714 #define R92C_TXAGC_B_CCK1_S 8 715 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 716 #define R92C_TXAGC_B_CCK2_S 16 717 #define R92C_TXAGC_B_CCK55_M 0xff000000 718 #define R92C_TXAGC_B_CCK55_S 24 719 720 /* Bits for R92C_TXAGC_RATE18_06(x). */ 721 #define R92C_TXAGC_RATE06_M 0x000000ff 722 #define R92C_TXAGC_RATE06_S 0 723 #define R92C_TXAGC_RATE09_M 0x0000ff00 724 #define R92C_TXAGC_RATE09_S 8 725 #define R92C_TXAGC_RATE12_M 0x00ff0000 726 #define R92C_TXAGC_RATE12_S 16 727 #define R92C_TXAGC_RATE18_M 0xff000000 728 #define R92C_TXAGC_RATE18_S 24 729 730 /* Bits for R92C_TXAGC_RATE54_24(x). */ 731 #define R92C_TXAGC_RATE24_M 0x000000ff 732 #define R92C_TXAGC_RATE24_S 0 733 #define R92C_TXAGC_RATE36_M 0x0000ff00 734 #define R92C_TXAGC_RATE36_S 8 735 #define R92C_TXAGC_RATE48_M 0x00ff0000 736 #define R92C_TXAGC_RATE48_S 16 737 #define R92C_TXAGC_RATE54_M 0xff000000 738 #define R92C_TXAGC_RATE54_S 24 739 740 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 741 #define R92C_TXAGC_MCS00_M 0x000000ff 742 #define R92C_TXAGC_MCS00_S 0 743 #define R92C_TXAGC_MCS01_M 0x0000ff00 744 #define R92C_TXAGC_MCS01_S 8 745 #define R92C_TXAGC_MCS02_M 0x00ff0000 746 #define R92C_TXAGC_MCS02_S 16 747 #define R92C_TXAGC_MCS03_M 0xff000000 748 #define R92C_TXAGC_MCS03_S 24 749 750 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 751 #define R92C_TXAGC_MCS04_M 0x000000ff 752 #define R92C_TXAGC_MCS04_S 0 753 #define R92C_TXAGC_MCS05_M 0x0000ff00 754 #define R92C_TXAGC_MCS05_S 8 755 #define R92C_TXAGC_MCS06_M 0x00ff0000 756 #define R92C_TXAGC_MCS06_S 16 757 #define R92C_TXAGC_MCS07_M 0xff000000 758 #define R92C_TXAGC_MCS07_S 24 759 760 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 761 #define R92C_TXAGC_MCS08_M 0x000000ff 762 #define R92C_TXAGC_MCS08_S 0 763 #define R92C_TXAGC_MCS09_M 0x0000ff00 764 #define R92C_TXAGC_MCS09_S 8 765 #define R92C_TXAGC_MCS10_M 0x00ff0000 766 #define R92C_TXAGC_MCS10_S 16 767 #define R92C_TXAGC_MCS11_M 0xff000000 768 #define R92C_TXAGC_MCS11_S 24 769 770 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 771 #define R92C_TXAGC_MCS12_M 0x000000ff 772 #define R92C_TXAGC_MCS12_S 0 773 #define R92C_TXAGC_MCS13_M 0x0000ff00 774 #define R92C_TXAGC_MCS13_S 8 775 #define R92C_TXAGC_MCS14_M 0x00ff0000 776 #define R92C_TXAGC_MCS14_S 16 777 #define R92C_TXAGC_MCS15_M 0xff000000 778 #define R92C_TXAGC_MCS15_S 24 779 780 /* Bits for R92C_LSSI_PARAM(i). */ 781 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 782 #define R92C_LSSI_PARAM_DATA_S 0 783 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 784 #define R92C_LSSI_PARAM_ADDR_S 20 785 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 786 #define R88E_LSSI_PARAM_ADDR_S 20 787 788 /* Bits for R92C_FPGA0_ANAPARAM2. */ 789 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 790 791 /* Bits for R92C_LSSI_READBACK(i). */ 792 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 793 #define R92C_LSSI_READBACK_DATA_S 0 794 795 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 796 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 797 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 798 799 800 /* 801 * USB registers. 802 */ 803 #define R92C_USB_INFO 0xfe17 804 #define R92C_USB_SPECIAL_OPTION 0xfe55 805 #define R92C_USB_HCPWM 0xfe57 806 #define R92C_USB_HRPWM 0xfe58 807 #define R92C_USB_DMA_AGG_TO 0xfe5b 808 #define R92C_USB_AGG_TO 0xfe5c 809 #define R92C_USB_AGG_TH 0xfe5d 810 #define R92C_USB_VID 0xfe60 811 #define R92C_USB_PID 0xfe62 812 #define R92C_USB_OPTIONAL 0xfe64 813 #define R92C_USB_EP 0xfe65 814 #define R92C_USB_PHY 0xfe68 815 #define R92C_USB_MAC_ADDR 0xfe70 816 #define R92C_USB_STRING 0xfe80 817 818 /* Bits for R92C_USB_SPECIAL_OPTION. */ 819 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 820 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 821 822 /* Bits for R92C_USB_EP. */ 823 #define R92C_USB_EP_HQ_M 0x000f 824 #define R92C_USB_EP_HQ_S 0 825 #define R92C_USB_EP_NQ_M 0x00f0 826 #define R92C_USB_EP_NQ_S 4 827 #define R92C_USB_EP_LQ_M 0x0f00 828 #define R92C_USB_EP_LQ_S 8 829 830 831 /* 832 * Firmware base address. 833 */ 834 #define R92C_FW_START_ADDR 0x1000 835 #define R92C_FW_PAGE_SIZE 4096 836 837 838 /* 839 * RF (6052) registers. 840 */ 841 #define R92C_RF_AC 0x00 842 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 843 #define R92C_RF_POW_TRSW 0x05 844 #define R92C_RF_GAIN_RX 0x06 845 #define R92C_RF_GAIN_TX 0x07 846 #define R92C_RF_TXM_IDAC 0x08 847 #define R92C_RF_BS_IQGEN 0x0f 848 #define R92C_RF_MODE1 0x10 849 #define R92C_RF_MODE2 0x11 850 #define R92C_RF_RX_AGC_HP 0x12 851 #define R92C_RF_TX_AGC 0x13 852 #define R92C_RF_BIAS 0x14 853 #define R92C_RF_IPA 0x15 854 #define R92C_RF_POW_ABILITY 0x17 855 #define R92C_RF_CHNLBW 0x18 856 #define R92C_RF_RX_G1 0x1a 857 #define R92C_RF_RX_G2 0x1b 858 #define R92C_RF_RX_BB2 0x1c 859 #define R92C_RF_RX_BB1 0x1d 860 #define R92C_RF_RCK1 0x1e 861 #define R92C_RF_RCK2 0x1f 862 #define R92C_RF_TX_G(i) (0x20 + (i)) 863 #define R92C_RF_TX_BB1 0x23 864 #define R92C_RF_T_METER 0x24 865 #define R92C_RF_SYN_G(i) (0x25 + (i)) 866 #define R92C_RF_RCK_OS 0x30 867 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 868 869 /* Bits for R92C_RF_AC. */ 870 #define R92C_RF_AC_MODE_M 0x70000 871 #define R92C_RF_AC_MODE_S 16 872 #define R92C_RF_AC_MODE_STANDBY 1 873 874 /* Bits for R92C_RF_CHNLBW. */ 875 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 876 #define R92C_RF_CHNLBW_CHNL_S 0 877 #define R92C_RF_CHNLBW_BW20 0x00400 878 #define R88E_RF_CHNLBW_BW20 0x00c00 879 #define R92C_RF_CHNLBW_LCSTART 0x08000 880 881 882 /* 883 * CAM entries. 884 */ 885 #define R92C_CAM_ENTRY_COUNT 32 886 887 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 888 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 889 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 890 891 /* Bits for R92C_CAM_CTL0(i). */ 892 #define R92C_CAM_KEYID_M 0x00000003 893 #define R92C_CAM_KEYID_S 0 894 #define R92C_CAM_ALGO_M 0x0000001c 895 #define R92C_CAM_ALGO_S 2 896 #define R92C_CAM_ALGO_NONE 0 897 #define R92C_CAM_ALGO_WEP40 1 898 #define R92C_CAM_ALGO_TKIP 2 899 #define R92C_CAM_ALGO_AES 4 900 #define R92C_CAM_ALGO_WEP104 5 901 #define R92C_CAM_VALID 0x00008000 902 #define R92C_CAM_MACLO_M 0xffff0000 903 #define R92C_CAM_MACLO_S 16 904 905 /* Rate adaptation modes. */ 906 #define R92C_RAID_11GN 1 907 #define R92C_RAID_11N 3 908 #define R92C_RAID_11BG 4 909 #define R92C_RAID_11G 5 /* "pure" 11g */ 910 #define R92C_RAID_11B 6 911 912 913 /* Macros to access unaligned little-endian memory. */ 914 #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 915 #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 916 917 /* 918 * Macros to access subfields in registers. 919 */ 920 /* Mask and Shift (getter). */ 921 #define MS(val, field) \ 922 (((val) & field##_M) >> field##_S) 923 924 /* Shift and Mask (setter). */ 925 #define SM(field, val) \ 926 (((val) << field##_S) & field##_M) 927 928 /* Rewrite. */ 929 #define RW(var, field, val) \ 930 (((var) & ~field##_M) | SM(field, val)) 931 932 /* 933 * Firmware image header. 934 */ 935 struct r92c_fw_hdr { 936 /* QWORD0 */ 937 uint16_t signature; 938 uint8_t category; 939 uint8_t function; 940 uint16_t version; 941 uint16_t subversion; 942 /* QWORD1 */ 943 uint8_t month; 944 uint8_t date; 945 uint8_t hour; 946 uint8_t minute; 947 uint16_t ramcodesize; 948 uint16_t reserved2; 949 /* QWORD2 */ 950 uint32_t svnidx; 951 uint32_t reserved3; 952 /* QWORD3 */ 953 uint32_t reserved4; 954 uint32_t reserved5; 955 } __packed; 956 957 /* 958 * Host to firmware commands. 959 */ 960 struct r92c_fw_cmd { 961 uint8_t id; 962 #define R92C_CMD_AP_OFFLOAD 0 963 #define R92C_CMD_SET_PWRMODE 1 964 #define R92C_CMD_JOINBSS_RPT 2 965 #define R92C_CMD_RSVD_PAGE 3 966 #define R92C_CMD_RSSI 4 967 #define R92C_CMD_RSSI_SETTING 5 968 #define R92C_CMD_MACID_CONFIG 6 969 #define R92C_CMD_MACID_PS_MODE 7 970 #define R92C_CMD_P2P_PS_OFFLOAD 8 971 #define R92C_CMD_SELECTIVE_SUSPEND 9 972 #define R92C_CMD_FLAG_EXT 0x80 973 974 uint8_t msg[5]; 975 } __packed; 976 977 /* Structure for R92C_CMD_RSSI_SETTING. */ 978 struct r92c_fw_cmd_rssi { 979 uint8_t macid; 980 uint8_t reserved; 981 uint8_t pwdb; 982 } __packed; 983 984 /* Structure for R92C_CMD_MACID_CONFIG. */ 985 struct r92c_fw_cmd_macid_cfg { 986 uint32_t mask; 987 uint8_t macid; 988 #define R92C_MACID_BSS 0 989 #define R92C_MACID_BC 4 /* Broadcast. */ 990 #define R92C_MACID_VALID 0x80 991 } __packed; 992 993 /* 994 * RTL8192CU ROM image. 995 */ 996 struct r92c_rom { 997 uint16_t id; /* 0x8192 */ 998 uint8_t reserved1[5]; 999 uint8_t dbg_sel; 1000 uint16_t reserved2; 1001 uint16_t vid; 1002 uint16_t pid; 1003 uint8_t usb_opt; 1004 uint8_t ep_setting; 1005 uint16_t reserved3; 1006 uint8_t usb_phy; 1007 uint8_t reserved4[3]; 1008 uint8_t macaddr[6]; 1009 uint8_t string[61]; /* "Realtek" */ 1010 uint8_t subcustomer_id; 1011 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 1012 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 1013 uint8_t ht40_2s_tx_pwr_diff[3]; 1014 uint8_t ht20_tx_pwr_diff[3]; 1015 uint8_t ofdm_tx_pwr_diff[3]; 1016 uint8_t ht40_max_pwr[3]; 1017 uint8_t ht20_max_pwr[3]; 1018 uint8_t xtal_calib; 1019 uint8_t tssi[R92C_MAX_CHAINS]; 1020 uint8_t thermal_meter; 1021 uint8_t rf_opt1; 1022 #define R92C_ROM_RF1_REGULATORY_M 0x07 1023 #define R92C_ROM_RF1_REGULATORY_S 0 1024 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1025 #define R92C_ROM_RF1_BOARD_TYPE_S 5 1026 #define R92C_BOARD_TYPE_DONGLE 0 1027 #define R92C_BOARD_TYPE_HIGHPA 1 1028 #define R92C_BOARD_TYPE_MINICARD 2 1029 #define R92C_BOARD_TYPE_SOLO 3 1030 #define R92C_BOARD_TYPE_COMBO 4 1031 1032 uint8_t rf_opt2; 1033 uint8_t rf_opt3; 1034 uint8_t rf_opt4; 1035 uint8_t channel_plan; 1036 uint8_t version; 1037 uint8_t curstomer_id; 1038 } __packed; 1039 1040 /* Rx PHY descriptor. */ 1041 struct r92c_rx_phystat { 1042 uint32_t phydw0; 1043 uint32_t phydw1; 1044 uint32_t phydw2; 1045 uint32_t phydw3; 1046 uint32_t phydw4; 1047 uint32_t phydw5; 1048 uint32_t phydw6; 1049 uint32_t phydw7; 1050 } __packed __attribute__((aligned(4))); 1051 1052 /* Rx PHY CCK descriptor. */ 1053 struct r92c_rx_cck { 1054 uint8_t adc_pwdb[4]; 1055 uint8_t sq_rpt; 1056 uint8_t agc_rpt; 1057 } __packed; 1058 1059 struct r88e_rx_cck { 1060 uint8_t path_agc[2]; 1061 uint8_t sig_qual; 1062 uint8_t agc_rpt; 1063 uint8_t rpt_b; 1064 uint8_t reserved1; 1065 uint8_t noise_power; 1066 uint8_t path_cfotail[2]; 1067 uint8_t pcts_mask[2]; 1068 uint8_t stream_rxevm[2]; 1069 uint8_t path_rxsnr[2]; 1070 uint8_t noise_power_db_lsb; 1071 uint8_t reserved2[3]; 1072 uint8_t stream_csi[2]; 1073 uint8_t stream_target_csi[2]; 1074 uint8_t sig_evm; 1075 uint8_t reserved3; 1076 uint8_t reserved4; 1077 } __packed; 1078 1079 /* Rx MAC descriptor. */ 1080 1081 struct r92c_rx_desc_pci { 1082 uint32_t rxdw0; 1083 uint32_t rxdw1; 1084 uint32_t rxdw2; 1085 uint32_t rxdw3; 1086 uint32_t rxdw4; 1087 uint32_t rxdw5; 1088 uint32_t rxbufaddr; 1089 uint32_t rxbufaddr64; 1090 } __packed __attribute__((aligned(4))); 1091 1092 struct r92c_rx_desc_usb { 1093 uint32_t rxdw0; 1094 uint32_t rxdw1; 1095 uint32_t rxdw2; 1096 uint32_t rxdw3; 1097 uint32_t rxdw4; 1098 uint32_t rxdw5; 1099 } __packed __attribute__((aligned(4))); 1100 1101 #define R92C_RXDW0_PKTLEN_M 0x00003fff 1102 #define R92C_RXDW0_PKTLEN_S 0 1103 #define R92C_RXDW0_CRCERR 0x00004000 1104 #define R92C_RXDW0_ICVERR 0x00008000 1105 #define R92C_RXDW0_INFOSZ_M 0x000f0000 1106 #define R92C_RXDW0_INFOSZ_S 16 1107 #define R92C_RXDW0_QOS 0x00800000 1108 #define R92C_RXDW0_SHIFT_M 0x03000000 1109 #define R92C_RXDW0_SHIFT_S 24 1110 #define R92C_RXDW0_PHYST 0x04000000 1111 #define R92C_RXDW0_DECRYPTED 0x08000000 1112 #define R92C_RXDW0_LS 0x10000000 1113 #define R92C_RXDW0_FS 0x20000000 1114 #define R92C_RXDW0_EOR 0x40000000 1115 #define R92C_RXDW0_OWN 0x80000000 1116 1117 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1118 #define R92C_RXDW2_PKTCNT_S 16 1119 1120 #define R92C_RXDW3_RATE_M 0x0000003f 1121 #define R92C_RXDW3_RATE_S 0 1122 #define R92C_RXDW3_HT 0x00000040 1123 #define R92C_RXDW3_HTC 0x00000400 1124 1125 /* Tx MAC descriptor. */ 1126 1127 struct r92c_tx_desc_pci { 1128 uint32_t txdw0; 1129 uint32_t txdw1; 1130 uint32_t txdw2; 1131 uint16_t txdw3; 1132 uint16_t txdseq; 1133 uint32_t txdw4; 1134 uint32_t txdw5; 1135 uint32_t txdw6; 1136 uint16_t txbufsize; 1137 uint16_t pad; 1138 uint32_t txbufaddr; 1139 uint32_t txbufaddr64; 1140 uint32_t nextdescaddr; 1141 uint32_t nextdescaddr64; 1142 uint32_t reserved[4]; 1143 } __packed __attribute__((aligned(4))); 1144 1145 struct r92c_tx_desc_usb { 1146 uint32_t txdw0; 1147 uint32_t txdw1; 1148 uint32_t txdw2; 1149 uint16_t txdw3; 1150 uint16_t txdseq; 1151 uint32_t txdw4; 1152 uint32_t txdw5; 1153 uint32_t txdw6; 1154 uint16_t txdsum; 1155 uint16_t pad; 1156 } __packed __attribute__((aligned(4))); 1157 1158 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1159 #define R92C_TXDW0_PKTLEN_S 0 1160 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1161 #define R92C_TXDW0_OFFSET_S 16 1162 #define R92C_TXDW0_BMCAST 0x01000000 1163 #define R92C_TXDW0_LSG 0x04000000 1164 #define R92C_TXDW0_FSG 0x08000000 1165 #define R92C_TXDW0_OWN 0x80000000 1166 1167 #define R92C_TXDW1_MACID_M 0x0000001f 1168 #define R92C_TXDW1_MACID_S 0 1169 #define R88E_TXDW1_MACID_M 0x0000003f 1170 #define R88E_TXDW1_MACID_S 0 1171 #define R92C_TXDW1_AGGEN 0x00000020 1172 #define R92C_TXDW1_AGGBK 0x00000040 1173 #define R92C_TXDW1_QSEL_M 0x00001f00 1174 #define R92C_TXDW1_QSEL_S 8 1175 #define R92C_TXDW1_QSEL_BE 0x00 1176 #define R92C_TXDW1_QSEL_BK 0x02 1177 #define R92C_TXDW1_QSEL_VI 0x05 1178 #define R92C_TXDW1_QSEL_VO 0x07 1179 #define R92C_TXDW1_QSEL_BEACON 0x10 1180 #define R92C_TXDW1_QSEL_HIGH 0x11 1181 #define R92C_TXDW1_QSEL_MGNT 0x12 1182 #define R92C_TXDW1_QSEL_CMD 0x13 1183 #define R92C_TXDW1_RAID_M 0x000f0000 1184 #define R92C_TXDW1_RAID_S 16 1185 #define R92C_TXDW1_CIPHER_M 0x00c00000 1186 #define R92C_TXDW1_CIPHER_S 22 1187 #define R92C_TXDW1_CIPHER_NONE 0 1188 #define R92C_TXDW1_CIPHER_RC4 1 1189 #define R92C_TXDW1_CIPHER_AES 3 1190 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1191 #define R92C_TXDW1_PKTOFF_S 26 1192 1193 #define R88E_TXDW2_AGGBK 0x00010000 1194 1195 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1196 #define R92C_TXDW4_RTSRATE_S 0 1197 #define R92C_TXDW4_QOS 0x00000040 1198 #define R92C_TXDW4_HWSEQ 0x00000080 1199 #define R92C_TXDW4_DRVRATE 0x00000100 1200 #define R92C_TXDW4_CTS2SELF 0x00000800 1201 #define R92C_TXDW4_RTSEN 0x00001000 1202 #define R92C_TXDW4_HWRTSEN 0x00002000 1203 #define R92C_TXDW4_SCO_M 0x003f0000 1204 #define R92C_TXDW4_SCO_S 20 1205 #define R92C_TXDW4_SCO_SCA 1 1206 #define R92C_TXDW4_SCO_SCB 2 1207 #define R92C_TXDW4_40MHZ 0x02000000 1208 1209 #define R92C_TXDW5_DATARATE_M 0x0000003f 1210 #define R92C_TXDW5_DATARATE_S 0 1211 #define R92C_TXDW5_SGI 0x00000040 1212 #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1213 #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1214 #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1215 #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1216 #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1217 #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1218 #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1219 #define R92C_TXDW5_AGGNUM_M 0xff000000 1220 #define R92C_TXDW5_AGGNUM_S 24 1221 1222 /* 1223 * MAC initialization values. 1224 */ 1225 static const struct { 1226 uint16_t reg; 1227 uint8_t val; 1228 } rtl8192ce_mac[] = { 1229 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1230 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1231 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1232 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1233 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1234 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1235 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1236 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, 1237 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, 1238 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1239 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1240 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1241 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1242 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1243 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1244 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, 1245 { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, 1246 { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, 1247 { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, 1248 { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, 1249 { 0x70b, 0x87 } 1250 }, rtl8188eu_mac[] = { 1251 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1252 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1253 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1254 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1255 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1256 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1257 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1258 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1259 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1260 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1261 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1262 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1263 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1264 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1265 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1266 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1267 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1268 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1269 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1270 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1271 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1272 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1273 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1274 }, rtl8192cu_mac[] = { 1275 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1276 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1277 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1278 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1279 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1280 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1281 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1282 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1283 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1284 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1285 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1286 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1287 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1288 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1289 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1290 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1291 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1292 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1293 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1294 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1295 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1296 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1297 }; 1298 1299 /* 1300 * Baseband initialization values. 1301 */ 1302 struct r92c_bb_prog { 1303 int count; 1304 const uint16_t *regs; 1305 const uint32_t *vals; 1306 int agccount; 1307 const uint32_t *agcvals; 1308 }; 1309 1310 /* 1311 * RTL8192CU and RTL8192CE-VAU. 1312 */ 1313 static const uint32_t rtl8192ce_bb_vals_1t[] = { 1314 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1315 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1316 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1317 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1318 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1319 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1320 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1321 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1322 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1323 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1324 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1325 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1326 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1327 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1328 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1329 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1330 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1331 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1332 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1333 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1334 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1335 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1336 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1337 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1338 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1339 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1340 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1341 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1342 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1343 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1344 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1345 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1346 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1347 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, 1348 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1349 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1350 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1351 0x00000000, 0x00000300, 1352 }; 1353 1354 static const uint16_t rtl8192ce_bb_regs[] = { 1355 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1356 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1357 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1358 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1359 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1360 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1361 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1362 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1363 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1364 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1365 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1366 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1367 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1368 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1369 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1370 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1371 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1372 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1373 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1374 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1375 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1376 }; 1377 1378 static const uint32_t rtl8192ce_bb_vals[] = { 1379 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1380 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1381 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1382 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1383 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1384 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1385 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1386 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1387 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1388 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1389 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1390 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1391 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1392 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1393 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1394 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1395 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1396 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1397 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1398 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1399 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1400 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1401 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1402 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1403 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1404 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1405 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1406 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1407 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1408 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1409 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1410 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1411 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1412 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1413 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1414 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1415 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1416 0x00000000, 0x00000300 1417 }; 1418 1419 static const uint32_t rtl8192ce_bb_vals_2t[] = { 1420 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1421 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1422 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1423 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1424 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1425 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1426 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1427 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1428 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1429 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1430 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1431 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1432 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1433 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1434 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1435 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1436 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1437 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1438 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1439 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1440 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1441 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1442 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1443 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1444 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1445 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1446 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1447 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1448 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1449 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1450 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1451 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1452 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1453 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1454 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1455 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1456 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1457 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1458 0x00000000, 0x00000300 1459 }; 1460 static const uint32_t rtl8192ce_agc_vals[] = { 1461 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1462 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1463 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1464 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1465 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1466 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1467 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1468 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1469 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1470 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1471 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1472 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1473 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1474 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1475 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1476 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1477 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1478 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1479 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1480 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1481 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1482 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1483 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1484 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1485 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1486 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1487 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1488 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1489 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1490 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1491 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1492 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1493 }; 1494 1495 static const struct r92c_bb_prog rtl8192ce_bb_prog = { 1496 nitems(rtl8192ce_bb_regs), 1497 rtl8192ce_bb_regs, 1498 rtl8192ce_bb_vals, 1499 nitems(rtl8192ce_agc_vals), 1500 rtl8192ce_agc_vals 1501 }; 1502 1503 static const struct r92c_bb_prog rtl8192ce_bb_prog_2t = { 1504 nitems(rtl8192ce_bb_regs), 1505 rtl8192ce_bb_regs, 1506 rtl8192ce_bb_vals_2t, 1507 nitems(rtl8192ce_agc_vals), 1508 rtl8192ce_agc_vals 1509 }; 1510 1511 static const struct r92c_bb_prog rtl8192ce_bb_prog_1t = { 1512 nitems(rtl8192ce_bb_regs), 1513 rtl8192ce_bb_regs, 1514 rtl8192ce_bb_vals_1t, 1515 nitems(rtl8192ce_agc_vals), 1516 rtl8192ce_agc_vals 1517 }; 1518 1519 /* 1520 * RTL8188CU. 1521 */ 1522 static const uint32_t rtl8192cu_bb_vals[] = { 1523 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1524 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1525 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1526 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1527 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1528 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1529 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1530 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1531 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1532 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1533 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1534 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1535 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1536 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1537 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1538 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1539 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1540 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1541 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1542 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1543 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1544 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1545 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1546 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1547 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1548 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1549 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1550 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1551 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1552 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1553 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1554 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1555 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1556 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1557 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1558 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1559 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1560 0x00000000, 0x00000300 1561 }; 1562 1563 static const struct r92c_bb_prog rtl8192cu_bb_prog = { 1564 nitems(rtl8192ce_bb_regs), 1565 rtl8192ce_bb_regs, 1566 rtl8192cu_bb_vals, 1567 nitems(rtl8192ce_agc_vals), 1568 rtl8192ce_agc_vals 1569 }; 1570 1571 /* 1572 * RTL8188CE-VAU. 1573 */ 1574 static const uint32_t rtl8188ce_bb_vals[] = { 1575 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1576 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1577 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1578 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1579 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1580 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1581 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1582 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1583 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1584 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1585 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1586 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1587 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1588 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1589 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1590 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1591 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1592 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1593 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1594 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1595 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1596 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1597 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1598 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1599 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1600 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1601 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1602 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1603 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1604 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1605 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1606 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1607 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1608 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1609 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1610 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1611 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1612 0x00000000, 0x00000300 1613 }; 1614 1615 static const uint32_t rtl8188ce_agc_vals[] = { 1616 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1617 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1618 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1619 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1620 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1621 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1622 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1623 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1624 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1625 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1626 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1627 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1628 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1629 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1630 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1631 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1632 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1633 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1634 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1635 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1636 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1637 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1638 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1639 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1640 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1641 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1642 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1643 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1644 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1645 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1646 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1647 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1648 }; 1649 1650 static const struct r92c_bb_prog rtl8188ce_bb_prog = { 1651 nitems(rtl8192ce_bb_regs), 1652 rtl8192ce_bb_regs, 1653 rtl8188ce_bb_vals, 1654 nitems(rtl8188ce_agc_vals), 1655 rtl8188ce_agc_vals 1656 }; 1657 1658 static const uint32_t rtl8188cu_bb_vals[] = { 1659 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1660 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1661 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1662 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1663 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1664 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1665 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1666 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1667 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1668 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1669 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1670 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1671 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1672 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1673 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1674 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1675 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1676 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1677 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1678 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1679 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1680 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1681 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1682 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1683 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1684 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1685 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1686 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1687 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1688 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1689 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1690 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1691 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1692 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1693 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1694 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1695 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1696 0x00000000, 0x00000300 1697 }; 1698 1699 static const struct r92c_bb_prog rtl8188cu_bb_prog = { 1700 nitems(rtl8192ce_bb_regs), 1701 rtl8192ce_bb_regs, 1702 rtl8188cu_bb_vals, 1703 nitems(rtl8188ce_agc_vals), 1704 rtl8188ce_agc_vals 1705 }; 1706 1707 /* 1708 * RTL8188EU. 1709 */ 1710 static const uint16_t rtl8188eu_bb_regs[] = { 1711 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1712 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1713 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1714 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1715 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1716 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1717 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1718 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1719 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1720 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1721 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1722 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1723 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1724 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1725 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1726 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1727 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1728 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1729 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1730 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1731 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1732 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1733 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1734 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1735 }; 1736 1737 static const uint32_t rtl8188eu_bb_vals[] = { 1738 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1739 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1740 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1741 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1742 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1743 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1744 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1745 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1746 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1747 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1748 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1749 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1750 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1751 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1752 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1753 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1754 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1755 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1756 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1757 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1758 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1759 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1760 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1761 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1762 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1763 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1764 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1765 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1766 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1767 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1768 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1769 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1770 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1771 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1772 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1773 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1774 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1775 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1776 0x00000000, 0x00000300 1777 }; 1778 1779 static const uint32_t rtl8188eu_agc_vals[] = { 1780 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1781 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1782 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1783 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1784 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1785 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1786 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1787 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1788 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1789 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1790 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1791 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1792 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1793 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1794 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1795 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1796 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1797 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1798 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1799 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1800 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1801 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1802 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1803 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1804 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1805 0x407d0001, 0x407e0001, 0x407f0001 1806 }; 1807 1808 static const struct r92c_bb_prog rtl8188eu_bb_prog = { 1809 nitems(rtl8188eu_bb_regs), 1810 rtl8188eu_bb_regs, 1811 rtl8188eu_bb_vals, 1812 nitems(rtl8188eu_agc_vals), 1813 rtl8188eu_agc_vals 1814 }; 1815 1816 /* 1817 * RTL8188RU. 1818 */ 1819 static const uint16_t rtl8188ru_bb_regs[] = { 1820 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1821 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1822 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1823 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1824 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1825 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1826 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1827 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1828 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1829 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1830 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1831 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1832 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1833 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1834 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1835 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1836 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1837 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1838 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1839 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1840 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1841 }; 1842 1843 static const uint32_t rtl8188ru_bb_vals[] = { 1844 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1845 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1846 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1847 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1848 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1849 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1850 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1851 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1852 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1853 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1854 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1855 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1856 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1857 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1858 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1859 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1860 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1861 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1862 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1863 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1864 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1865 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1866 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1867 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1868 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1869 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1870 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1871 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1872 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1873 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1874 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1875 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1876 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1877 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1878 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1879 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1880 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1881 0x31555448, 0x00000003, 0x00000000, 0x00000300 1882 }; 1883 1884 static const uint32_t rtl8188ru_agc_vals[] = { 1885 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1886 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1887 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1888 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1889 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1890 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1891 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1892 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1893 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1894 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1895 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1896 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1897 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1898 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1899 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1900 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1901 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1902 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1903 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1904 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1905 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1906 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1907 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1908 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1909 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1910 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1911 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1912 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1913 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1914 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1915 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1916 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1917 }; 1918 1919 static const struct r92c_bb_prog rtl8188ru_bb_prog = { 1920 nitems(rtl8188ru_bb_regs), 1921 rtl8188ru_bb_regs, 1922 rtl8188ru_bb_vals, 1923 nitems(rtl8188ru_agc_vals), 1924 rtl8188ru_agc_vals 1925 }; 1926 1927 /* 1928 * RF initialization values. 1929 */ 1930 struct r92c_rf_prog { 1931 int count; 1932 const uint8_t *regs; 1933 const uint32_t *vals; 1934 }; 1935 1936 /* 1937 * RTL8192CU and RTL8192CE-VAU. 1938 */ 1939 static const uint8_t rtl8192ce_rf1_regs[] = { 1940 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1941 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1942 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1943 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1944 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1945 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1946 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1947 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1948 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1949 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1950 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1951 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1952 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1953 }; 1954 1955 static const uint32_t rtl8192ce_rf1_vals[] = { 1956 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1957 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1958 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1959 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1960 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1961 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1962 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1963 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1964 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1965 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1966 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1967 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1968 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1969 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1970 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1971 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1972 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1973 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1974 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1975 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1976 0x30159 1977 }; 1978 1979 static const uint8_t rtl8192ce_rf2_regs[] = { 1980 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1981 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1982 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1983 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1984 }; 1985 1986 static const uint32_t rtl8192ce_rf2_vals[] = { 1987 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1988 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1989 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1990 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1991 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1992 0xe0330, 0xa0330, 0x60330, 0x20330 1993 }; 1994 1995 static const struct r92c_rf_prog rtl8192ce_rf_prog[] = { 1996 { 1997 nitems(rtl8192ce_rf1_regs), 1998 rtl8192ce_rf1_regs, 1999 rtl8192ce_rf1_vals 2000 }, 2001 { 2002 nitems(rtl8192ce_rf2_regs), 2003 rtl8192ce_rf2_regs, 2004 rtl8192ce_rf2_vals 2005 } 2006 }; 2007 2008 /* 2009 * RTL8188CE-VAU. 2010 */ 2011 static const uint32_t rtl8188ce_rf_vals[] = { 2012 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2013 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2014 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2015 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 2016 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2017 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2018 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2019 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2020 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2021 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2022 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2023 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2024 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2025 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2026 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2027 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 2028 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 2029 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 2030 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2031 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2032 0x30159 2033 }; 2034 2035 static const struct r92c_rf_prog rtl8188ce_rf_prog[] = { 2036 { 2037 nitems(rtl8192ce_rf1_regs), 2038 rtl8192ce_rf1_regs, 2039 rtl8188ce_rf_vals 2040 } 2041 }; 2042 2043 2044 /* 2045 * RTL8188CU. 2046 */ 2047 static const uint32_t rtl8188cu_rf_vals[] = { 2048 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2049 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2050 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2051 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 2052 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2053 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2054 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2055 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2056 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2057 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2058 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2059 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2060 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2061 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2062 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2063 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 2064 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 2065 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2066 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2067 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2068 0x30159 2069 }; 2070 2071 static const struct r92c_rf_prog rtl8188cu_rf_prog[] = { 2072 { 2073 nitems(rtl8192ce_rf1_regs), 2074 rtl8192ce_rf1_regs, 2075 rtl8188cu_rf_vals 2076 } 2077 }; 2078 2079 /* 2080 * RTL8188EU. 2081 */ 2082 static const uint8_t rtl8188eu_rf_regs[] = { 2083 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 2084 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 2085 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 2086 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 2087 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 2088 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 2089 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 2090 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2091 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 2092 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2093 }; 2094 2095 static const uint32_t rtl8188eu_rf_vals[] = { 2096 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2097 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2098 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2099 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2100 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2101 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 2102 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 2103 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 2104 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 2105 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 2106 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 2107 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 2108 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 2109 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 2110 }; 2111 2112 static const struct r92c_rf_prog rtl8188eu_rf_prog[] = { 2113 { 2114 nitems(rtl8188eu_rf_regs), 2115 rtl8188eu_rf_regs, 2116 rtl8188eu_rf_vals 2117 } 2118 }; 2119 2120 /* 2121 * RTL8188RU. 2122 */ 2123 static const uint32_t rtl8188ru_rf_vals[] = { 2124 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2125 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2126 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2127 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2128 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2129 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2130 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2131 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2132 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2133 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2134 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2135 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2136 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2137 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2138 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2139 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2140 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2141 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2142 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2143 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2144 0x30159 2145 }; 2146 2147 static const struct r92c_rf_prog rtl8188ru_rf_prog[] = { 2148 { 2149 nitems(rtl8192ce_rf1_regs), 2150 rtl8192ce_rf1_regs, 2151 rtl8188ru_rf_vals 2152 } 2153 }; 2154 2155 struct r92c_txpwr { 2156 uint8_t pwr[3][28]; 2157 }; 2158 2159 struct r88e_txpwr { 2160 uint8_t pwr[6][28]; 2161 }; 2162 2163 /* 2164 * Per RF chain/group/rate Tx gain values. 2165 */ 2166 static const struct r92c_txpwr rtl8192cu_txagc[] = { 2167 { { /* Chain 0. */ 2168 { /* Group 0. */ 2169 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2170 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2171 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2172 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2173 }, 2174 { /* Group 1. */ 2175 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2179 }, 2180 { /* Group 2. */ 2181 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2182 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2185 } 2186 } }, 2187 { { /* Chain 1. */ 2188 { /* Group 0. */ 2189 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2193 }, 2194 { /* Group 1. */ 2195 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2199 }, 2200 { /* Group 2. */ 2201 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2202 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2204 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2205 } 2206 } } 2207 }; 2208 2209 static const struct r92c_txpwr rtl8188ru_txagc[] = { 2210 { { /* Chain 0. */ 2211 { /* Group 0. */ 2212 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2213 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2214 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2215 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2216 }, 2217 { /* Group 1. */ 2218 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2219 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2220 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2221 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2222 }, 2223 { /* Group 2. */ 2224 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2226 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2227 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2228 } 2229 } } 2230 }; 2231 2232 static const struct r88e_txpwr rtl8188eu_txagc[] = { 2233 { { /* Chain 0. */ 2234 { /* Group 0. */ 2235 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2236 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2237 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2238 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2239 }, 2240 { /* Group 1. */ 2241 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2243 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2244 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2245 }, 2246 { /* Group 2. */ 2247 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2251 }, 2252 { /* Group 3. */ 2253 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2254 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2256 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2257 }, 2258 { /* Group 4. */ 2259 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2263 }, 2264 { /* Group 5. */ 2265 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2269 } 2270 } } 2271 }; 2272