1 /* $OpenBSD: r92creg.h,v 1.14 2017/08/23 09:25:17 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define R92C_MAX_CHAINS 2 21 #define R92C_MAX_TX_PWR 0x3f 22 #define R92C_H2C_NBOX 4 23 24 /* 25 * MAC registers. 26 */ 27 /* System Configuration. */ 28 #define R92C_SYS_ISO_CTRL 0x000 29 #define R92C_SYS_FUNC_EN 0x002 30 #define R92C_APS_FSMCO 0x004 31 #define R92C_SYS_CLKR 0x008 32 #define R92C_AFE_MISC 0x010 33 #define R92C_SPS0_CTRL 0x011 34 #define R92C_SPS_OCP_CFG 0x018 35 #define R92C_RSV_CTRL 0x01c 36 #define R92C_RF_CTRL 0x01f 37 #define R92C_LDOA15_CTRL 0x020 38 #define R92C_LDOV12D_CTRL 0x021 39 #define R92C_LDOHCI12_CTRL 0x022 40 #define R92C_LPLDO_CTRL 0x023 41 #define R92C_AFE_XTAL_CTRL 0x024 42 #define R92C_AFE_PLL_CTRL 0x028 43 #define R92C_EFUSE_CTRL 0x030 44 #define R92C_EFUSE_TEST 0x034 45 #define R92C_PWR_DATA 0x038 46 #define R92C_CAL_TIMER 0x03c 47 #define R92C_ACLK_MON 0x03e 48 #define R92C_GPIO_MUXCFG 0x040 49 #define R92C_GPIO_IO_SEL 0x042 50 #define R92C_MAC_PINMUX_CFG 0x043 51 #define R92C_GPIO_PIN_CTRL 0x044 52 #define R92C_GPIO_INTM 0x048 53 #define R92C_LEDCFG0 0x04c 54 #define R92C_LEDCFG1 0x04d 55 #define R92C_LEDCFG2 0x04e 56 #define R92C_LEDCFG3 0x04f 57 #define R92C_FSIMR 0x050 58 #define R92C_FSISR 0x054 59 #define R92C_HSIMR 0x058 60 #define R92C_HSISR 0x05c 61 #define R92C_MCUFWDL 0x080 62 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 63 #define R88E_HIMR 0x0b0 64 #define R88E_HISR 0x0b4 65 #define R88E_HIMRE 0x0b8 66 #define R88E_HISRE 0x0bc 67 #define R92C_EFUSE_ACCESS 0x0cf 68 #define R92C_BIST_SCAN 0x0d0 69 #define R92C_BIST_RPT 0x0d4 70 #define R92C_BIST_ROM_RPT 0x0d8 71 #define R92C_USB_SIE_INTF 0x0e0 72 #define R92C_PCIE_MIO_INTF 0x0e4 73 #define R92C_PCIE_MIO_INTD 0x0e8 74 #define R92C_HPON_FSM 0x0ec 75 #define R92C_SYS_CFG 0x0f0 76 /* MAC General Configuration. */ 77 #define R92C_CR 0x100 78 #define R92C_PBP 0x104 79 #define R92C_TRXDMA_CTRL 0x10c 80 #define R92C_TRXFF_BNDY 0x114 81 #define R92C_TRXFF_STATUS 0x118 82 #define R92C_RXFF_PTR 0x11c 83 #define R92C_HIMR 0x120 84 #define R92C_HISR 0x124 85 #define R92C_HIMRE 0x128 86 #define R92C_HISRE 0x12c 87 #define R92C_CPWM 0x12f 88 #define R92C_FWIMR 0x130 89 #define R92C_FWISR 0x134 90 #define R92C_PKTBUF_DBG_CTRL 0x140 91 #define R92C_PKTBUF_DBG_DATA_L 0x144 92 #define R92C_PKTBUF_DBG_DATA_H 0x148 93 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 94 #define R92C_TCUNIT_BASE 0x164 95 #define R92C_MBIST_START 0x174 96 #define R92C_MBIST_DONE 0x178 97 #define R92C_MBIST_FAIL 0x17c 98 #define R92C_C2HEVT_MSG 0x1a0 99 #define R92C_C2HEVT_CLEAR 0x1af 100 #define R92C_C2HEVT_MSG_TEST 0x1b8 101 #define R92C_MCUTST_1 0x1c0 102 #define R92C_FMETHR 0x1c8 103 #define R92C_HMETFR 0x1cc 104 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 105 #define R92C_LLT_INIT 0x1e0 106 #define R92C_BB_ACCESS_CTRL 0x1e8 107 #define R92C_BB_ACCESS_DATA 0x1ec 108 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 109 /* Tx DMA Configuration. */ 110 #define R92C_RQPN 0x200 111 #define R92C_FIFOPAGE 0x204 112 #define R92C_TDECTRL 0x208 113 #define R92C_TXDMA_OFFSET_CHK 0x20c 114 #define R92C_TXDMA_STATUS 0x210 115 #define R92C_RQPN_NPQ 0x214 116 /* Rx DMA Configuration. */ 117 #define R92C_RXDMA_AGG_PG_TH 0x280 118 #define R92C_RXPKT_NUM 0x284 119 #define R92C_RXDMA_STATUS 0x288 120 121 #define R92C_PCIE_CTRL_REG 0x300 122 #define R92C_INT_MIG 0x304 123 #define R92C_BCNQ_DESA 0x308 124 #define R92C_HQ_DESA 0x310 125 #define R92C_MGQ_DESA 0x318 126 #define R92C_VOQ_DESA 0x320 127 #define R92C_VIQ_DESA 0x328 128 #define R92C_BEQ_DESA 0x330 129 #define R92C_BKQ_DESA 0x338 130 #define R92C_RX_DESA 0x340 131 #define R92C_DBI 0x348 132 #define R92C_MDIO 0x354 133 #define R92C_DBG_SEL 0x360 134 #define R92C_PCIE_HRPWM 0x361 135 #define R92C_PCIE_HCPWM 0x363 136 #define R92C_UART_CTRL 0x364 137 #define R92C_UART_TX_DES 0x370 138 #define R92C_UART_RX_DES 0x378 139 140 #define R92C_VOQ_INFORMATION 0x0400 141 #define R92C_VIQ_INFORMATION 0x0404 142 #define R92C_BEQ_INFORMATION 0x0408 143 #define R92C_BKQ_INFORMATION 0x040C 144 #define R92C_MGQ_INFORMATION 0x0410 145 #define R92C_HGQ_INFORMATION 0x0414 146 #define R92C_BCNQ_INFORMATION 0x0418 147 #define R92C_CPU_MGQ_INFORMATION 0x041C 148 149 /* Protocol Configuration. */ 150 #define R92C_FWHW_TXQ_CTRL 0x420 151 #define R92C_HWSEQ_CTRL 0x423 152 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 153 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 154 #define R92C_SPEC_SIFS 0x428 155 #define R92C_RL 0x42a 156 #define R92C_DARFRC 0x430 157 #define R92C_RARFRC 0x438 158 #define R92C_RRSR 0x440 159 #define R92C_ARFR(i) (0x444 + (i) * 4) 160 #define R92C_AGGLEN_LMT 0x458 161 #define R92C_AMPDU_MIN_SPACE 0x45c 162 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 163 #define R92C_FAST_EDCA_CTRL 0x460 164 #define R92C_RD_RESP_PKT_TH 0x463 165 #define R92C_INIRTS_RATE_SEL 0x480 166 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 167 #define R88E_TX_RPT_CTRL 0x4ec 168 #define R92C_MAX_AGGR_NUM 0x4ca 169 /* EDCA Configuration. */ 170 #define R92C_EDCA_VO_PARAM 0x500 171 #define R92C_EDCA_VI_PARAM 0x504 172 #define R92C_EDCA_BE_PARAM 0x508 173 #define R92C_EDCA_BK_PARAM 0x50c 174 #define R92C_BCNTCFG 0x510 175 #define R92C_PIFS 0x512 176 #define R92C_RDG_PIFS 0x513 177 #define R92C_SIFS_CCK 0x514 178 #define R92C_SIFS_OFDM 0x516 179 #define R92C_AGGR_BREAK_TIME 0x51a 180 #define R92C_SLOT 0x51b 181 #define R92C_TX_PTCL_CTRL 0x520 182 #define R92C_TXPAUSE 0x522 183 #define R92C_DIS_TXREQ_CLR 0x523 184 #define R92C_RD_CTRL 0x524 185 #define R92C_TBTT_PROHIBIT 0x540 186 #define R92C_RD_NAV_NXT 0x544 187 #define R92C_NAV_PROT_LEN 0x546 188 #define R92C_BCN_CTRL 0x550 189 #define R92C_BCN_CTRL1 0x551 190 #define R92C_MBID_NUM 0x552 191 #define R92C_DUAL_TSF_RST 0x553 192 #define R92C_BCN_INTERVAL 0x554 193 #define R92C_DRVERLYINT 0x558 194 #define R92C_BCNDMATIM 0x559 195 #define R92C_ATIMWND 0x55a 196 #define R92C_USTIME_TSF 0x55c 197 #define R92C_BCN_MAX_ERR 0x55d 198 #define R92C_RXTSF_OFFSET_CCK 0x55e 199 #define R92C_RXTSF_OFFSET_OFDM 0x55f 200 #define R92C_TSFTR 0x560 201 #define R92C_INIT_TSFTR 0x564 202 #define R92C_PSTIMER 0x580 203 #define R92C_TIMER0 0x584 204 #define R92C_TIMER1 0x588 205 #define R92C_ACMHWCTRL 0x5c0 206 #define R92C_ACMRSTCTRL 0x5c1 207 #define R92C_ACMAVG 0x5c2 208 #define R92C_VO_ADMTIME 0x5c4 209 #define R92C_VI_ADMTIME 0x5c6 210 #define R92C_BE_ADMTIME 0x5c8 211 #define R92C_EDCA_RANDOM_GEN 0x5cc 212 #define R92C_SCH_TXCMD 0x5d0 213 /* WMAC Configuration. */ 214 #define R92C_APSD_CTRL 0x600 215 #define R92C_BWOPMODE 0x603 216 #define R92C_TCR 0x604 217 #define R92C_RCR 0x608 218 #define R92C_RX_DRVINFO_SZ 0x60f 219 #define R92C_MACID 0x610 220 #define R92C_BSSID 0x618 221 #define R92C_MAR 0x620 222 #define R92C_MAC_SPEC_SIFS 0x63a 223 #define R92C_RESP_SIFS_CCK 0x63c 224 #define R92C_RESP_SIFS_OFDM 0x63e 225 #define R92C_ACKTO 0x640 226 #define R92C_CAMCMD 0x670 227 #define R92C_CAMWRITE 0x674 228 #define R92C_CAMREAD 0x678 229 #define R92C_CAMDBG 0x67c 230 #define R92C_SECCFG 0x680 231 #define R92C_RXFLTMAP0 0x6a0 232 #define R92C_RXFLTMAP1 0x6a2 233 #define R92C_RXFLTMAP2 0x6a4 234 235 /* Bits for R92C_SYS_ISO_CTRL. */ 236 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 237 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 238 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 239 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 240 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 241 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 242 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 243 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 244 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 245 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 246 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 247 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 248 249 /* Bits for R92C_SYS_FUNC_EN. */ 250 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 251 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 252 #define R92C_SYS_FUNC_EN_USBA 0x0004 253 #define R92C_SYS_FUNC_EN_UPLL 0x0008 254 #define R92C_SYS_FUNC_EN_USBD 0x0010 255 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 256 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 257 #define R92C_SYS_FUNC_EN_PPLL 0x0080 258 #define R92C_SYS_FUNC_EN_PCIED 0x0100 259 #define R92C_SYS_FUNC_EN_DIOE 0x0200 260 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 261 #define R92C_SYS_FUNC_EN_DCORE 0x0800 262 #define R92C_SYS_FUNC_EN_ELDR 0x1000 263 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 264 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 265 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 266 267 /* Bits for R92C_APS_FSMCO. */ 268 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 269 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 270 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 271 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 272 #define R92C_APS_FSMCO_PDN_EN 0x00000010 273 #define R92C_APS_FSMCO_PDN_PL 0x00000020 274 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 275 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 276 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 277 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 278 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 279 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 280 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 281 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 282 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 283 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 284 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 285 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 286 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 287 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 288 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 289 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 290 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 291 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 292 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 293 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 294 295 /* Bits for R92C_SYS_CLKR. */ 296 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 297 #define R92C_SYS_CLKR_ANA8M 0x00000002 298 #define R92C_SYS_CLKR_MACSLP 0x00000010 299 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 300 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 301 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 302 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 303 #define R92C_SYS_CLKR_SEC_EN 0x00000400 304 #define R92C_SYS_CLKR_MAC_EN 0x00000800 305 #define R92C_SYS_CLKR_SYS_EN 0x00001000 306 #define R92C_SYS_CLKR_RING_EN 0x00002000 307 308 /* Bits for R92C_RSV_CTRL. */ 309 #define R92C_RSV_CTRL_WLOCK_ALL 0x01 310 #define R92C_RSV_CTRL_WLOCK_00 0x02 311 #define R92C_RSV_CTRL_WLOCK_04 0x04 312 #define R92C_RSV_CTRL_WLOCK_08 0x08 313 #define R92C_RSV_CTRL_WLOCK_40 0x10 314 #define R92C_RSV_CTRL_R_DIS_PRST_0 0x20 315 #define R92C_RSV_CTRL_R_DIS_PRST_1 0x40 316 #define R92C_RSV_CTRL_LOCK_ALL_EN 0x80 317 318 /* Bits for R92C_RF_CTRL. */ 319 #define R92C_RF_CTRL_EN 0x01 320 #define R92C_RF_CTRL_RSTB 0x02 321 #define R92C_RF_CTRL_SDMRSTB 0x04 322 323 /* Bits for R92C_LDOV12D_CTRL. */ 324 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 325 326 /* Bits for R92C_AFE_XTAL_CTRL. */ 327 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 328 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 329 330 /* Bits for R92C_EFUSE_CTRL. */ 331 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 332 #define R92C_EFUSE_CTRL_DATA_S 0 333 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 334 #define R92C_EFUSE_CTRL_ADDR_S 8 335 #define R92C_EFUSE_CTRL_VALID 0x80000000 336 337 /* Bits for R92C_GPIO_MUXCFG. */ 338 #define R92C_GPIO_MUXCFG_RFKILL 0x0008 339 #define R92C_GPIO_MUXCFG_ENBT 0x0020 340 341 /* Bits for R92C_GPIO_IO_SEL. */ 342 #define R92C_GPIO_IO_SEL_RFKILL 0x0008 343 344 /* Bits for R92C_LEDCFG0. */ 345 #define R92C_LEDCFG0_DIS 0x08 346 347 /* Bits for R92C_LEDCFG2. */ 348 #define R92C_LEDCFG2_EN 0x60 349 #define R92C_LEDCFG2_DIS 0x68 350 351 /* Bits for R92C_MCUFWDL. */ 352 #define R92C_MCUFWDL_EN 0x00000001 353 #define R92C_MCUFWDL_RDY 0x00000002 354 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 355 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 356 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 357 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 358 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 359 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 360 #define R92C_MCUFWDL_PAGE_M 0x00070000 361 #define R92C_MCUFWDL_PAGE_S 16 362 #define R92C_MCUFWDL_ROM_DLEN 0x00080000 363 #define R92C_MCUFWDL_CPRST 0x00800000 364 365 /* Bits for R88E_HIMR. */ 366 #define R88E_HIMR_CPWM 0x00000100 367 #define R88E_HIMR_CPWM2 0x00000200 368 #define R88E_HIMR_TBDER 0x04000000 369 #define R88E_HIMR_PSTIMEOUT 0x20000000 370 371 /* Bits for R88E_HIMRE.*/ 372 #define R88E_HIMRE_RXFOVW 0x00000100 373 #define R88E_HIMRE_TXFOVW 0x00000200 374 #define R88E_HIMRE_RXERR 0x00000400 375 #define R88E_HIMRE_TXERR 0x00000800 376 377 /* Bits for R92C_EFUSE_ACCESS. */ 378 #define R92C_EFUSE_ACCESS_OFF 0x00 379 #define R92C_EFUSE_ACCESS_ON 0x69 380 381 /* Bits for R92C_HPON_FSM. */ 382 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 383 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 384 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 385 386 /* Bits for R92C_SYS_CFG. */ 387 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 388 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 389 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 390 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 391 #define R92C_SYS_CFG_PCIRSTB 0x00000010 392 #define R92C_SYS_CFG_V15_VLD 0x00000020 393 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 394 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 395 #define R92C_SYS_CFG_BD_MAC2 0x00000200 396 #define R92C_SYS_CFG_BD_MAC1 0x00000400 397 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 398 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 399 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 400 #define R92C_SYS_CFG_BT_FUNC 0x00010000 401 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 402 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 403 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 404 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 405 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 406 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 407 #define R92C_SYS_CFG_TYPE_92C 0x08000000 408 409 /* Bits for R92C_CR. */ 410 #define R92C_CR_HCI_TXDMA_EN 0x00000001 411 #define R92C_CR_HCI_RXDMA_EN 0x00000002 412 #define R92C_CR_TXDMA_EN 0x00000004 413 #define R92C_CR_RXDMA_EN 0x00000008 414 #define R92C_CR_PROTOCOL_EN 0x00000010 415 #define R92C_CR_SCHEDULE_EN 0x00000020 416 #define R92C_CR_MACTXEN 0x00000040 417 #define R92C_CR_MACRXEN 0x00000080 418 #define R92C_CR_ENSEC 0x00000200 419 #define R92C_CR_CALTMR_EN 0x00000400 420 #define R92C_CR_NETTYPE_S 16 421 #define R92C_CR_NETTYPE_M 0x00030000 422 #define R92C_CR_NETTYPE_NOLINK 0 423 #define R92C_CR_NETTYPE_ADHOC 1 424 #define R92C_CR_NETTYPE_INFRA 2 425 #define R92C_CR_NETTYPE_AP 3 426 427 /* Bits for R92C_PBP. */ 428 #define R92C_PBP_PSRX_M 0x0f 429 #define R92C_PBP_PSRX_S 0 430 #define R92C_PBP_PSTX_M 0xf0 431 #define R92C_PBP_PSTX_S 4 432 #define R92C_PBP_64 0 433 #define R92C_PBP_128 1 434 #define R92C_PBP_256 2 435 #define R92C_PBP_512 3 436 #define R92C_PBP_1024 4 437 438 /* Bits for R92C_TRXDMA_CTRL. */ 439 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 440 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 441 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 442 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 443 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 444 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 445 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 446 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 447 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 448 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 449 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 450 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 451 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 452 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 453 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 454 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 455 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 456 #define R92C_TRXDMA_CTRL_QMAP_S 4 457 /* Shortcuts. */ 458 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 459 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 460 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 461 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 462 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 463 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 464 465 /* Bits for R92C_LLT_INIT. */ 466 #define R92C_LLT_INIT_DATA_M 0x000000ff 467 #define R92C_LLT_INIT_DATA_S 0 468 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 469 #define R92C_LLT_INIT_ADDR_S 8 470 #define R92C_LLT_INIT_OP_M 0xc0000000 471 #define R92C_LLT_INIT_OP_S 30 472 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 473 #define R92C_LLT_INIT_OP_WRITE 1 474 475 /* Bits for R92C_RQPN. */ 476 #define R92C_RQPN_HPQ_M 0x000000ff 477 #define R92C_RQPN_HPQ_S 0 478 #define R92C_RQPN_LPQ_M 0x0000ff00 479 #define R92C_RQPN_LPQ_S 8 480 #define R92C_RQPN_PUBQ_M 0x00ff0000 481 #define R92C_RQPN_PUBQ_S 16 482 #define R92C_RQPN_LD 0x80000000 483 484 /* Bits for R92C_TDECTRL. */ 485 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 486 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 487 488 /* Bits for R92C_FWHW_TXQ_CTRL. */ 489 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 490 491 /* Bits for R92C_SPEC_SIFS. */ 492 #define R92C_SPEC_SIFS_CCK_M 0x00ff 493 #define R92C_SPEC_SIFS_CCK_S 0 494 #define R92C_SPEC_SIFS_OFDM_M 0xff00 495 #define R92C_SPEC_SIFS_OFDM_S 8 496 497 /* Bits for R92C_RL. */ 498 #define R92C_RL_LRL_M 0x003f 499 #define R92C_RL_LRL_S 0 500 #define R92C_RL_SRL_M 0x3f00 501 #define R92C_RL_SRL_S 8 502 503 /* Bits for R92C_RRSR. */ 504 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 505 #define R92C_RRSR_RATE_BITMAP_S 0 506 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 507 #define R92C_RRSR_RATE_ALL 0xfffff 508 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 509 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 510 #define R92C_RRSR_SHORT 0x00800000 511 512 /* Bits for R88E_TX_RPT_CTRL. */ 513 #define R88E_TX_RPT_CTRL_EN 0x01 514 #define R88E_TX_RPT_CTRL_TIMER_EN 0x02 515 516 /* Bits for R92C_EDCA_XX_PARAM. */ 517 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 518 #define R92C_EDCA_PARAM_AIFS_S 0 519 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 520 #define R92C_EDCA_PARAM_ECWMIN_S 8 521 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 522 #define R92C_EDCA_PARAM_ECWMAX_S 12 523 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 524 #define R92C_EDCA_PARAM_TXOP_S 16 525 526 /* Bits for R92C_ACMHWCTRL */ 527 #define R92C_ACMHW_HWEN 0x01 528 #define R92C_ACMHW_BEQEN 0x02 529 #define R92C_ACMHW_VIQEN 0x04 530 #define R92C_ACMHW_VOQEN 0x08 531 #define R92C_ACMHW_BEQSTATUS 0x10 532 #define R92C_ACMHW_VIQSTATUS 0x20 533 #define R92C_ACMHW_VOQSTATUS 0x40 534 535 /* Bits for R92C_TXPAUSE. */ 536 #define R92C_TXPAUSE_AC_VO 0x01 537 #define R92C_TXPAUSE_AC_VI 0x02 538 #define R92C_TXPAUSE_AC_BE 0x04 539 #define R92C_TXPAUSE_AC_BK 0x08 540 541 /* Bits for R92C_BCN_CTRL. */ 542 #define R92C_BCN_CTRL_EN_MBSSID 0x02 543 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 544 #define R92C_BCN_CTRL_EN_BCN 0x08 545 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 546 547 /* Bits for R92C_DRVERLYINT. */ 548 #define R92C_DRVERLYINT_INIT_TIME 0x05 549 550 /* Bits for R92C_BCNDMATIM. */ 551 #define R92C_BCNDMATIM_INIT_TIME 0x02 552 553 /* Bits for R92C_APSD_CTRL. */ 554 #define R92C_APSD_CTRL_OFF 0x40 555 #define R92C_APSD_CTRL_OFF_STATUS 0x80 556 557 /* Bits for R92C_BWOPMODE. */ 558 #define R92C_BWOPMODE_11J 0x01 559 #define R92C_BWOPMODE_5G 0x02 560 #define R92C_BWOPMODE_20MHZ 0x04 561 562 /* Bits for R92C_TCR. */ 563 #define R92C_TCR_TSFRST 0x00000001 564 #define R92C_TCR_DIS_GCLK 0x00000002 565 #define R92C_TCR_PAD_SEL 0x00000004 566 #define R92C_TCR_PWR_ST 0x00000040 567 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 568 #define R92C_TCR_ACRC 0x00000100 569 #define R92C_TCR_CFENDFORM 0x00000200 570 #define R92C_TCR_ICV 0x00000400 571 572 /* Bits for R92C_RCR. */ 573 #define R92C_RCR_AAP 0x00000001 574 #define R92C_RCR_APM 0x00000002 575 #define R92C_RCR_AM 0x00000004 576 #define R92C_RCR_AB 0x00000008 577 #define R92C_RCR_ADD3 0x00000010 578 #define R92C_RCR_APWRMGT 0x00000020 579 #define R92C_RCR_CBSSID_DATA 0x00000040 580 #define R92C_RCR_CBSSID_BCN 0x00000080 581 #define R92C_RCR_ACRC32 0x00000100 582 #define R92C_RCR_AICV 0x00000200 583 #define R92C_RCR_ADF 0x00000800 584 #define R92C_RCR_ACF 0x00001000 585 #define R92C_RCR_AMF 0x00002000 586 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 587 #define R92C_RCR_MFBEN 0x00400000 588 #define R92C_RCR_LSIGEN 0x00800000 589 #define R92C_RCR_ENMBID 0x01000000 590 #define R92C_RCR_APP_BA_SSN 0x08000000 591 #define R92C_RCR_APP_PHYSTS 0x10000000 592 #define R92C_RCR_APP_ICV 0x20000000 593 #define R92C_RCR_APP_MIC 0x40000000 594 #define R92C_RCR_APPFCS 0x80000000 595 596 /* Bits for R92C_CAMCMD. */ 597 #define R92C_CAMCMD_ADDR_M 0x0000ffff 598 #define R92C_CAMCMD_ADDR_S 0 599 #define R92C_CAMCMD_WRITE 0x00010000 600 #define R92C_CAMCMD_CLR 0x40000000 601 #define R92C_CAMCMD_POLLING 0x80000000 602 603 /* IMR */ 604 605 /*Beacon DMA interrupt 6 */ 606 #define R92C_IMR_BCNDMAINT6 0x80000000 607 /*Beacon DMA interrupt 5 */ 608 #define R92C_IMR_BCNDMAINT5 0x40000000 609 /*Beacon DMA interrupt 4 */ 610 #define R92C_IMR_BCNDMAINT4 0x20000000 611 /*Beacon DMA interrupt 3 */ 612 #define R92C_IMR_BCNDMAINT3 0x10000000 613 /*Beacon DMA interrupt 2 */ 614 #define R92C_IMR_BCNDMAINT2 0x08000000 615 /*Beacon DMA interrupt 1 */ 616 #define R92C_IMR_BCNDMAINT1 0x04000000 617 /*Beacon Queue DMA OK interrupt 8 */ 618 #define R92C_IMR_BCNDOK8 0x02000000 619 /*Beacon Queue DMA OK interrupt 7 */ 620 #define R92C_IMR_BCNDOK7 0x01000000 621 /*Beacon Queue DMA OK interrupt 6 */ 622 #define R92C_IMR_BCNDOK6 0x00800000 623 /*Beacon Queue DMA OK interrupt 5 */ 624 #define R92C_IMR_BCNDOK5 0x00400000 625 /*Beacon Queue DMA OK interrupt 4 */ 626 #define R92C_IMR_BCNDOK4 0x00200000 627 /*Beacon Queue DMA OK interrupt 3 */ 628 #define R92C_IMR_BCNDOK3 0x00100000 629 /*Beacon Queue DMA OK interrupt 2 */ 630 #define R92C_IMR_BCNDOK2 0x00080000 631 /*Beacon Queue DMA OK interrupt 1 */ 632 #define R92C_IMR_BCNDOK1 0x00040000 633 /*Timeout interrupt 2 */ 634 #define R92C_IMR_TIMEOUT2 0x00020000 635 /*Timeout interrupt 1 */ 636 #define R92C_IMR_TIMEOUT1 0x00010000 637 /*Transmit FIFO Overflow */ 638 #define R92C_IMR_TXFOVW 0x00008000 639 /*Power save time out interrupt */ 640 #define R92C_IMR_PSTIMEOUT 0x00004000 641 /*Beacon DMA interrupt 0 */ 642 #define R92C_IMR_BCNINT 0x00002000 643 /*Receive FIFO Overflow */ 644 #define R92C_IMR_RXFOVW 0x00001000 645 /*Receive Descriptor Unavailable */ 646 #define R92C_IMR_RDU 0x00000800 647 /*For 92C,ATIM Window End interrupt */ 648 #define R92C_IMR_ATIMEND 0x00000400 649 /*Beacon Queue DMA OK interrupt */ 650 #define R92C_IMR_BDOK 0x00000200 651 /*High Queue DMA OK interrupt */ 652 #define R92C_IMR_HIGHDOK 0x00000100 653 /*Transmit Beacon OK interrupt */ 654 #define R92C_IMR_TBDOK 0x00000080 655 /*Management Queue DMA OK interrupt */ 656 #define R92C_IMR_MGNTDOK 0x00000040 657 /*For 92C,Transmit Beacon Error interrupt */ 658 #define R92C_IMR_TBDER 0x00000020 659 /*AC_BK DMA OK interrupt */ 660 #define R92C_IMR_BKDOK 0x00000010 661 /*AC_BE DMA OK interrupt */ 662 #define R92C_IMR_BEDOK 0x00000008 663 /*AC_VI DMA OK interrupt */ 664 #define R92C_IMR_VIDOK 0x00000004 665 /*AC_VO DMA interrupt */ 666 #define R92C_IMR_VODOK 0x00000002 667 /*Receive DMA OK interrupt */ 668 #define R92C_IMR_ROK 0x00000001 669 670 #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) 671 672 673 /* 674 * Baseband registers. 675 */ 676 #define R92C_FPGA0_RFMOD 0x800 677 #define R92C_FPGA0_TXINFO 0x804 678 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 679 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 680 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 681 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 682 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 683 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 684 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 685 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 686 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 687 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 688 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 689 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 690 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 691 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 692 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 693 #define R92C_FPGA0_ANAPARAM2 0x884 694 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 695 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 696 #define R92C_FPGA1_RFMOD 0x900 697 #define R92C_FPGA1_TXINFO 0x90c 698 #define R92C_CCK0_SYSTEM 0xa00 699 #define R92C_CCK0_AFESETTING 0xa04 700 #define R92C_OFDM0_TRXPATHENA 0xc04 701 #define R92C_OFDM0_TRMUXPAR 0xc08 702 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 703 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 704 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 705 #define R92C_OFDM0_AGCPARAM1 0xc70 706 #define R92C_OFDM0_AGCRSSITABLE 0xc78 707 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 708 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 709 #define R92C_OFDM0_RXIQEXTANTA 0xca0 710 #define R92C_OFDM1_LSTF 0xd00 711 712 /* Bits for R92C_FPGA[01]_RFMOD. */ 713 #define R92C_RFMOD_40MHZ 0x00000001 714 #define R92C_RFMOD_JAPAN 0x00000002 715 #define R92C_RFMOD_CCK_TXSC 0x00000030 716 #define R92C_RFMOD_CCK_EN 0x01000000 717 #define R92C_RFMOD_OFDM_EN 0x02000000 718 719 /* Bits for R92C_HSSI_PARAM1(i). */ 720 #define R92C_HSSI_PARAM1_PI 0x00000100 721 722 /* Bits for R92C_HSSI_PARAM2(i). */ 723 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 724 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 725 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 726 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 727 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 728 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 729 730 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 731 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 732 #define R92C_TXAGC_A_CCK1_S 8 733 734 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 735 #define R92C_TXAGC_B_CCK11_M 0x000000ff 736 #define R92C_TXAGC_B_CCK11_S 0 737 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 738 #define R92C_TXAGC_A_CCK2_S 8 739 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 740 #define R92C_TXAGC_A_CCK55_S 16 741 #define R92C_TXAGC_A_CCK11_M 0xff000000 742 #define R92C_TXAGC_A_CCK11_S 24 743 744 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 745 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 746 #define R92C_TXAGC_B_CCK1_S 8 747 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 748 #define R92C_TXAGC_B_CCK2_S 16 749 #define R92C_TXAGC_B_CCK55_M 0xff000000 750 #define R92C_TXAGC_B_CCK55_S 24 751 752 /* Bits for R92C_TXAGC_RATE18_06(x). */ 753 #define R92C_TXAGC_RATE06_M 0x000000ff 754 #define R92C_TXAGC_RATE06_S 0 755 #define R92C_TXAGC_RATE09_M 0x0000ff00 756 #define R92C_TXAGC_RATE09_S 8 757 #define R92C_TXAGC_RATE12_M 0x00ff0000 758 #define R92C_TXAGC_RATE12_S 16 759 #define R92C_TXAGC_RATE18_M 0xff000000 760 #define R92C_TXAGC_RATE18_S 24 761 762 /* Bits for R92C_TXAGC_RATE54_24(x). */ 763 #define R92C_TXAGC_RATE24_M 0x000000ff 764 #define R92C_TXAGC_RATE24_S 0 765 #define R92C_TXAGC_RATE36_M 0x0000ff00 766 #define R92C_TXAGC_RATE36_S 8 767 #define R92C_TXAGC_RATE48_M 0x00ff0000 768 #define R92C_TXAGC_RATE48_S 16 769 #define R92C_TXAGC_RATE54_M 0xff000000 770 #define R92C_TXAGC_RATE54_S 24 771 772 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 773 #define R92C_TXAGC_MCS00_M 0x000000ff 774 #define R92C_TXAGC_MCS00_S 0 775 #define R92C_TXAGC_MCS01_M 0x0000ff00 776 #define R92C_TXAGC_MCS01_S 8 777 #define R92C_TXAGC_MCS02_M 0x00ff0000 778 #define R92C_TXAGC_MCS02_S 16 779 #define R92C_TXAGC_MCS03_M 0xff000000 780 #define R92C_TXAGC_MCS03_S 24 781 782 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 783 #define R92C_TXAGC_MCS04_M 0x000000ff 784 #define R92C_TXAGC_MCS04_S 0 785 #define R92C_TXAGC_MCS05_M 0x0000ff00 786 #define R92C_TXAGC_MCS05_S 8 787 #define R92C_TXAGC_MCS06_M 0x00ff0000 788 #define R92C_TXAGC_MCS06_S 16 789 #define R92C_TXAGC_MCS07_M 0xff000000 790 #define R92C_TXAGC_MCS07_S 24 791 792 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 793 #define R92C_TXAGC_MCS08_M 0x000000ff 794 #define R92C_TXAGC_MCS08_S 0 795 #define R92C_TXAGC_MCS09_M 0x0000ff00 796 #define R92C_TXAGC_MCS09_S 8 797 #define R92C_TXAGC_MCS10_M 0x00ff0000 798 #define R92C_TXAGC_MCS10_S 16 799 #define R92C_TXAGC_MCS11_M 0xff000000 800 #define R92C_TXAGC_MCS11_S 24 801 802 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 803 #define R92C_TXAGC_MCS12_M 0x000000ff 804 #define R92C_TXAGC_MCS12_S 0 805 #define R92C_TXAGC_MCS13_M 0x0000ff00 806 #define R92C_TXAGC_MCS13_S 8 807 #define R92C_TXAGC_MCS14_M 0x00ff0000 808 #define R92C_TXAGC_MCS14_S 16 809 #define R92C_TXAGC_MCS15_M 0xff000000 810 #define R92C_TXAGC_MCS15_S 24 811 812 /* Bits for R92C_LSSI_PARAM(i). */ 813 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 814 #define R92C_LSSI_PARAM_DATA_S 0 815 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 816 #define R92C_LSSI_PARAM_ADDR_S 20 817 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 818 #define R88E_LSSI_PARAM_ADDR_S 20 819 820 /* Bits for R92C_FPGA0_ANAPARAM2. */ 821 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 822 823 /* Bits for R92C_LSSI_READBACK(i). */ 824 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 825 #define R92C_LSSI_READBACK_DATA_S 0 826 827 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 828 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 829 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 830 831 832 /* 833 * USB registers. 834 */ 835 #define R92C_USB_INFO 0xfe17 836 #define R92C_USB_SPECIAL_OPTION 0xfe55 837 #define R92C_USB_HCPWM 0xfe57 838 #define R92C_USB_HRPWM 0xfe58 839 #define R92C_USB_DMA_AGG_TO 0xfe5b 840 #define R92C_USB_AGG_TO 0xfe5c 841 #define R92C_USB_AGG_TH 0xfe5d 842 #define R92C_USB_VID 0xfe60 843 #define R92C_USB_PID 0xfe62 844 #define R92C_USB_OPTIONAL 0xfe64 845 #define R92C_USB_EP 0xfe65 846 #define R92C_USB_PHY 0xfe68 847 #define R92C_USB_MAC_ADDR 0xfe70 848 #define R92C_USB_STRING 0xfe80 849 850 /* Bits for R92C_USB_SPECIAL_OPTION. */ 851 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 852 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 853 854 /* Bits for R92C_USB_EP. */ 855 #define R92C_USB_EP_HQ_M 0x000f 856 #define R92C_USB_EP_HQ_S 0 857 #define R92C_USB_EP_NQ_M 0x00f0 858 #define R92C_USB_EP_NQ_S 4 859 #define R92C_USB_EP_LQ_M 0x0f00 860 #define R92C_USB_EP_LQ_S 8 861 862 863 /* 864 * Firmware base address. 865 */ 866 #define R92C_FW_START_ADDR 0x1000 867 #define R92C_FW_PAGE_SIZE 4096 868 869 870 /* 871 * RF (6052) registers. 872 */ 873 #define R92C_RF_AC 0x00 874 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 875 #define R92C_RF_POW_TRSW 0x05 876 #define R92C_RF_GAIN_RX 0x06 877 #define R92C_RF_GAIN_TX 0x07 878 #define R92C_RF_TXM_IDAC 0x08 879 #define R92C_RF_BS_IQGEN 0x0f 880 #define R92C_RF_MODE1 0x10 881 #define R92C_RF_MODE2 0x11 882 #define R92C_RF_RX_AGC_HP 0x12 883 #define R92C_RF_TX_AGC 0x13 884 #define R92C_RF_BIAS 0x14 885 #define R92C_RF_IPA 0x15 886 #define R92C_RF_POW_ABILITY 0x17 887 #define R92C_RF_CHNLBW 0x18 888 #define R92C_RF_RX_G1 0x1a 889 #define R92C_RF_RX_G2 0x1b 890 #define R92C_RF_RX_BB2 0x1c 891 #define R92C_RF_RX_BB1 0x1d 892 #define R92C_RF_RCK1 0x1e 893 #define R92C_RF_RCK2 0x1f 894 #define R92C_RF_TX_G(i) (0x20 + (i)) 895 #define R92C_RF_TX_BB1 0x23 896 #define R92C_RF_T_METER 0x24 897 #define R92C_RF_SYN_G(i) (0x25 + (i)) 898 #define R92C_RF_RCK_OS 0x30 899 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 900 901 /* Bits for R92C_RF_AC. */ 902 #define R92C_RF_AC_MODE_M 0x70000 903 #define R92C_RF_AC_MODE_S 16 904 #define R92C_RF_AC_MODE_STANDBY 1 905 906 /* Bits for R92C_RF_CHNLBW. */ 907 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 908 #define R92C_RF_CHNLBW_CHNL_S 0 909 #define R92C_RF_CHNLBW_BW20 0x00400 910 #define R88E_RF_CHNLBW_BW20 0x00c00 911 #define R92C_RF_CHNLBW_LCSTART 0x08000 912 913 914 /* 915 * CAM entries. 916 */ 917 #define R92C_CAM_ENTRY_COUNT 32 918 919 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 920 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 921 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 922 923 /* Bits for R92C_CAM_CTL0(i). */ 924 #define R92C_CAM_KEYID_M 0x00000003 925 #define R92C_CAM_KEYID_S 0 926 #define R92C_CAM_ALGO_M 0x0000001c 927 #define R92C_CAM_ALGO_S 2 928 #define R92C_CAM_ALGO_NONE 0 929 #define R92C_CAM_ALGO_WEP40 1 930 #define R92C_CAM_ALGO_TKIP 2 931 #define R92C_CAM_ALGO_AES 4 932 #define R92C_CAM_ALGO_WEP104 5 933 #define R92C_CAM_VALID 0x00008000 934 #define R92C_CAM_MACLO_M 0xffff0000 935 #define R92C_CAM_MACLO_S 16 936 937 /* Rate adaptation modes. */ 938 #define R92C_RAID_11GN 1 939 #define R92C_RAID_11N 3 940 #define R92C_RAID_11BG 4 941 #define R92C_RAID_11G 5 /* "pure" 11g */ 942 #define R92C_RAID_11B 6 943 944 945 /* Macros to access unaligned little-endian memory. */ 946 #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 947 #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 948 949 /* 950 * Macros to access subfields in registers. 951 */ 952 /* Mask and Shift (getter). */ 953 #define MS(val, field) \ 954 (((val) & field##_M) >> field##_S) 955 956 /* Shift and Mask (setter). */ 957 #define SM(field, val) \ 958 (((val) << field##_S) & field##_M) 959 960 /* Rewrite. */ 961 #define RW(var, field, val) \ 962 (((var) & ~field##_M) | SM(field, val)) 963 964 /* 965 * Firmware image header. 966 */ 967 struct r92c_fw_hdr { 968 /* QWORD0 */ 969 uint16_t signature; 970 uint8_t category; 971 uint8_t function; 972 uint16_t version; 973 uint16_t subversion; 974 /* QWORD1 */ 975 uint8_t month; 976 uint8_t date; 977 uint8_t hour; 978 uint8_t minute; 979 uint16_t ramcodesize; 980 uint16_t reserved2; 981 /* QWORD2 */ 982 uint32_t svnidx; 983 uint32_t reserved3; 984 /* QWORD3 */ 985 uint32_t reserved4; 986 uint32_t reserved5; 987 } __packed; 988 989 /* 990 * Host to firmware commands. 991 */ 992 struct r92c_fw_cmd { 993 uint8_t id; 994 #define R92C_CMD_AP_OFFLOAD 0 995 #define R92C_CMD_SET_PWRMODE 1 996 #define R92C_CMD_JOINBSS_RPT 2 997 #define R92C_CMD_RSVD_PAGE 3 998 #define R92C_CMD_RSSI 4 999 #define R92C_CMD_RSSI_SETTING 5 1000 #define R92C_CMD_MACID_CONFIG 6 1001 #define R92C_CMD_MACID_PS_MODE 7 1002 #define R92C_CMD_P2P_PS_OFFLOAD 8 1003 #define R92C_CMD_SELECTIVE_SUSPEND 9 1004 #define R92C_CMD_FLAG_EXT 0x80 1005 1006 uint8_t msg[5]; 1007 } __packed; 1008 1009 /* Structure for R92C_CMD_RSSI_SETTING. */ 1010 struct r92c_fw_cmd_rssi { 1011 uint8_t macid; 1012 uint8_t reserved; 1013 uint8_t pwdb; 1014 } __packed; 1015 1016 /* Structure for R92C_CMD_MACID_CONFIG. */ 1017 struct r92c_fw_cmd_macid_cfg { 1018 uint32_t mask; 1019 uint8_t macid; 1020 #define R92C_MACID_BSS 0 1021 #define R92C_MACID_BC 4 /* Broadcast. */ 1022 #define R92C_MACID_VALID 0x80 1023 } __packed; 1024 1025 /* 1026 * RTL8192CU ROM image. 1027 */ 1028 struct r92c_rom { 1029 uint16_t id; /* 0x8192 */ 1030 uint8_t reserved1[5]; 1031 uint8_t dbg_sel; 1032 uint16_t reserved2; 1033 uint16_t vid; 1034 uint16_t pid; 1035 uint8_t usb_opt; 1036 uint8_t ep_setting; 1037 uint16_t reserved3; 1038 uint8_t usb_phy; 1039 uint8_t reserved4[3]; 1040 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1041 uint8_t string[61]; /* "Realtek" */ 1042 uint8_t subcustomer_id; 1043 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 1044 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 1045 uint8_t ht40_2s_tx_pwr_diff[3]; 1046 uint8_t ht20_tx_pwr_diff[3]; 1047 uint8_t ofdm_tx_pwr_diff[3]; 1048 uint8_t ht40_max_pwr[3]; 1049 uint8_t ht20_max_pwr[3]; 1050 uint8_t channel_plan; 1051 uint8_t tssi[R92C_MAX_CHAINS]; 1052 uint8_t thermal_meter; 1053 uint8_t rf_opt1; 1054 #define R92C_ROM_RF1_REGULATORY_M 0x07 1055 #define R92C_ROM_RF1_REGULATORY_S 0 1056 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1057 #define R92C_ROM_RF1_BOARD_TYPE_S 5 1058 #define R92C_BOARD_TYPE_DONGLE 0 1059 #define R92C_BOARD_TYPE_HIGHPA 1 1060 #define R92C_BOARD_TYPE_MINICARD 2 1061 #define R92C_BOARD_TYPE_SOLO 3 1062 #define R92C_BOARD_TYPE_COMBO 4 1063 1064 uint8_t rf_opt2; 1065 uint8_t rf_opt3; 1066 uint8_t rf_opt4; 1067 uint8_t reserved5; 1068 uint8_t version; 1069 uint8_t curstomer_id; 1070 } __packed; 1071 1072 struct r88e_tx_pwr { 1073 uint8_t cck_tx_pwr[6]; 1074 uint8_t ht40_tx_pwr[5]; 1075 uint8_t ht20_ofdm_tx_pwr_diff; 1076 #define R88E_ROM_TXPWR_HT20_DIFF_M 0xf0 1077 #define R88E_ROM_TXPWR_HT20_DIFF_S 4 1078 #define R88E_ROM_TXPWR_OFDM_DIFF_M 0x0f 1079 #define R88E_ROM_TXPWR_OFDM_DIFF_S 0 1080 1081 } __packed; 1082 1083 /* 1084 * RTL8188EU ROM image. 1085 */ 1086 struct r88e_rom { 1087 uint8_t reserved1[16]; 1088 struct r88e_tx_pwr txpwr; 1089 uint8_t reserved2[156]; 1090 uint8_t channel_plan; 1091 uint8_t xtal; 1092 uint8_t thermal_meter; 1093 uint8_t reserved3[6]; 1094 uint8_t rf_board_opt; 1095 uint8_t rf_feature_opt; 1096 uint8_t rf_bt_opt; 1097 uint8_t version; 1098 uint8_t customer_id; 1099 uint8_t reserved4[3]; 1100 uint8_t rf_ant_opt; 1101 uint8_t reserved5[6]; 1102 uint16_t vid; 1103 uint16_t pid; 1104 uint8_t usb_opt; 1105 uint8_t reserved6[2]; 1106 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1107 uint8_t reserved7[2]; 1108 uint8_t string[33]; /* "Realtek" */ 1109 uint8_t reserved8[256]; 1110 } __packed; 1111 1112 /* Rx PHY descriptor. */ 1113 struct r92c_rx_phystat { 1114 uint32_t phydw0; 1115 uint32_t phydw1; 1116 uint32_t phydw2; 1117 uint32_t phydw3; 1118 uint32_t phydw4; 1119 uint32_t phydw5; 1120 uint32_t phydw6; 1121 uint32_t phydw7; 1122 } __packed __attribute__((aligned(4))); 1123 1124 /* Rx PHY CCK descriptor. */ 1125 struct r92c_rx_cck { 1126 uint8_t adc_pwdb[4]; 1127 uint8_t sq_rpt; 1128 uint8_t agc_rpt; 1129 } __packed; 1130 1131 /* Tx report (type 1). */ 1132 struct r88e_tx_rpt_ccx { 1133 uint8_t rptb0; 1134 #define R88E_RPTB6_PKT_NUM_M 0x0e 1135 #define R88E_RPTB6_PKT_NUM_S 1 1136 #define R88E_RPTB0_INT_CCX 0x80 1137 1138 uint8_t rptb1; 1139 #define R88E_RPTB1_MACID_M 0x3f 1140 #define R88E_RPTB1_MACID_S 0 1141 #define R88E_RPTB1_PKT_OK 0x40 1142 #define R88E_RPTB1_BMC 0x80 1143 1144 uint8_t rptb2; 1145 #define R88E_RPTB2_RETRY_CNT_M 0x3f 1146 #define R88E_RPTB2_RETRY_CNT_S 0 1147 #define R88E_RPTB2_LIFE_EXPIRE 0x40 1148 #define R88E_RPTB2_RETRY_OVER 0x80 1149 1150 uint8_t queue_time_low; 1151 uint8_t queue_time_high; 1152 uint8_t final_rate; 1153 uint8_t rptb6; 1154 #define R88E_RPTB6_QSEL_M 0xf0 1155 #define R88E_RPTB6_QSEL_S 4 1156 1157 uint8_t rptb7; 1158 } __packed; 1159 1160 struct r88e_rx_phystat { 1161 uint8_t path_agc[2]; 1162 uint8_t ch_corr[2]; 1163 uint8_t sq_rpt; 1164 uint8_t agc_rpt; 1165 uint8_t rpt_b; 1166 uint8_t reserved1; 1167 uint8_t noise_power; 1168 int8_t path_cfotail[2]; 1169 uint8_t pcts_mask[2]; 1170 int8_t stream_rxevm[2]; 1171 uint8_t path_rxsnr[2]; 1172 uint8_t noise_power_db_lsb; 1173 uint8_t reserved2[3]; 1174 uint8_t stream_csi[2]; 1175 uint8_t stream_target_csi[2]; 1176 int8_t sig_evm; 1177 uint8_t reserved3; 1178 uint8_t reserved4; 1179 } __packed; 1180 1181 /* Rx MAC descriptor. */ 1182 1183 struct r92c_rx_desc_pci { 1184 uint32_t rxdw0; 1185 uint32_t rxdw1; 1186 uint32_t rxdw2; 1187 uint32_t rxdw3; 1188 uint32_t rxdw4; 1189 uint32_t rxdw5; 1190 uint32_t rxbufaddr; 1191 uint32_t rxbufaddr64; 1192 } __packed __attribute__((aligned(4))); 1193 1194 struct r92c_rx_desc_usb { 1195 uint32_t rxdw0; 1196 uint32_t rxdw1; 1197 uint32_t rxdw2; 1198 uint32_t rxdw3; 1199 uint32_t rxdw4; 1200 uint32_t rxdw5; 1201 } __packed __attribute__((aligned(4))); 1202 1203 #define R92C_RXDW0_PKTLEN_M 0x00003fff 1204 #define R92C_RXDW0_PKTLEN_S 0 1205 #define R92C_RXDW0_CRCERR 0x00004000 1206 #define R92C_RXDW0_ICVERR 0x00008000 1207 #define R92C_RXDW0_INFOSZ_M 0x000f0000 1208 #define R92C_RXDW0_INFOSZ_S 16 1209 #define R92C_RXDW0_QOS 0x00800000 1210 #define R92C_RXDW0_SHIFT_M 0x03000000 1211 #define R92C_RXDW0_SHIFT_S 24 1212 #define R92C_RXDW0_PHYST 0x04000000 1213 #define R92C_RXDW0_DECRYPTED 0x08000000 1214 #define R92C_RXDW0_LS 0x10000000 1215 #define R92C_RXDW0_FS 0x20000000 1216 #define R92C_RXDW0_EOR 0x40000000 1217 #define R92C_RXDW0_OWN 0x80000000 1218 1219 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1220 #define R92C_RXDW2_PKTCNT_S 16 1221 1222 #define R92C_RXDW3_RATE_M 0x0000003f 1223 #define R92C_RXDW3_RATE_S 0 1224 #define R92C_RXDW3_HT 0x00000040 1225 #define R92C_RXDW3_HTC 0x00000400 1226 #define R88E_RXDW3_RPT_M 0x0000c000 1227 #define R88E_RXDW3_RPT_S 14 1228 #define R88E_RXDW3_RPT_RX 0 1229 #define R88E_RXDW3_RPT_TX1 1 1230 #define R88E_RXDW3_RPT_TX2 2 1231 #define R88E_RXDW3_RPT_HIS 3 1232 1233 /* Tx MAC descriptor. */ 1234 1235 struct r92c_tx_desc_pci { 1236 uint32_t txdw0; 1237 uint32_t txdw1; 1238 uint32_t txdw2; 1239 uint16_t txdw3; 1240 uint16_t txdseq; 1241 uint32_t txdw4; 1242 uint32_t txdw5; 1243 uint32_t txdw6; 1244 uint16_t txbufsize; 1245 uint16_t pad; 1246 uint32_t txbufaddr; 1247 uint32_t txbufaddr64; 1248 uint32_t nextdescaddr; 1249 uint32_t nextdescaddr64; 1250 uint32_t reserved[4]; 1251 } __packed __attribute__((aligned(4))); 1252 1253 struct r92c_tx_desc_usb { 1254 uint32_t txdw0; 1255 uint32_t txdw1; 1256 uint32_t txdw2; 1257 uint16_t txdw3; 1258 uint16_t txdseq; 1259 uint32_t txdw4; 1260 uint32_t txdw5; 1261 uint32_t txdw6; 1262 uint16_t txdsum; 1263 uint16_t pad; 1264 } __packed __attribute__((aligned(4))); 1265 1266 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1267 #define R92C_TXDW0_PKTLEN_S 0 1268 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1269 #define R92C_TXDW0_OFFSET_S 16 1270 #define R92C_TXDW0_BMCAST 0x01000000 1271 #define R92C_TXDW0_LSG 0x04000000 1272 #define R92C_TXDW0_FSG 0x08000000 1273 #define R92C_TXDW0_OWN 0x80000000 1274 1275 #define R92C_TXDW1_MACID_M 0x0000001f 1276 #define R92C_TXDW1_MACID_S 0 1277 #define R88E_TXDW1_MACID_M 0x0000003f 1278 #define R88E_TXDW1_MACID_S 0 1279 #define R92C_TXDW1_AGGEN 0x00000020 1280 #define R92C_TXDW1_AGGBK 0x00000040 1281 #define R92C_TXDW1_QSEL_M 0x00001f00 1282 #define R92C_TXDW1_QSEL_S 8 1283 #define R92C_TXDW1_QSEL_BE 0x00 1284 #define R92C_TXDW1_QSEL_BK 0x02 1285 #define R92C_TXDW1_QSEL_VI 0x05 1286 #define R92C_TXDW1_QSEL_VO 0x07 1287 #define R92C_TXDW1_QSEL_BEACON 0x10 1288 #define R92C_TXDW1_QSEL_HIGH 0x11 1289 #define R92C_TXDW1_QSEL_MGNT 0x12 1290 #define R92C_TXDW1_QSEL_CMD 0x13 1291 #define R92C_TXDW1_RAID_M 0x000f0000 1292 #define R92C_TXDW1_RAID_S 16 1293 #define R92C_TXDW1_CIPHER_M 0x00c00000 1294 #define R92C_TXDW1_CIPHER_S 22 1295 #define R92C_TXDW1_CIPHER_NONE 0 1296 #define R92C_TXDW1_CIPHER_RC4 1 1297 #define R92C_TXDW1_CIPHER_AES 3 1298 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1299 #define R92C_TXDW1_PKTOFF_S 26 1300 1301 #define R88E_TXDW2_AGGBK 0x00010000 1302 #define R92C_TXDW2_CCX_RPT 0x00080000 1303 1304 #define R92C_TXDW4_RTSRATE_M 0x0000001f 1305 #define R92C_TXDW4_RTSRATE_S 0 1306 #define R92C_TXDW4_QOS 0x00000040 1307 #define R92C_TXDW4_HWSEQ 0x00000080 1308 #define R92C_TXDW4_DRVRATE 0x00000100 1309 #define R92C_TXDW4_CTS2SELF 0x00000800 1310 #define R92C_TXDW4_RTSEN 0x00001000 1311 #define R92C_TXDW4_HWRTSEN 0x00002000 1312 #define R92C_TXDW4_SCO_M 0x003f0000 1313 #define R92C_TXDW4_SCO_S 20 1314 #define R92C_TXDW4_SCO_SCA 1 1315 #define R92C_TXDW4_SCO_SCB 2 1316 #define R92C_TXDW4_40MHZ 0x02000000 1317 #define R92C_TXDW4_RTS_SHORT 0x04000000 1318 1319 #define R92C_TXDW5_DATARATE_M 0x0000003f 1320 #define R92C_TXDW5_DATARATE_S 0 1321 #define R92C_TXDW5_SGI 0x00000040 1322 #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1323 #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1324 #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1325 #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1326 #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1327 #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1328 #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1329 #define R92C_TXDW5_AGGNUM_M 0xff000000 1330 #define R92C_TXDW5_AGGNUM_S 24 1331 1332 /* 1333 * C2H event structure. 1334 */ 1335 #define R92C_C2H_MSG_MAX_LEN 16 1336 1337 struct r92c_c2h_evt { 1338 uint8_t evtb0; 1339 #define R92C_C2H_EVTB0_ID_M 0x0f 1340 #define R92C_C2H_EVTB0_ID_S 0 1341 #define R92C_C2H_EVTB0_LEN_M 0xf0 1342 #define R92C_C2H_EVTB0_LEN_S 4 1343 1344 uint8_t seq; 1345 1346 /* Followed by payload (see below). */ 1347 } __packed; 1348 1349 /* Bits for R92C_C2HEVT_CLEAR. */ 1350 #define R92C_C2HEVT_HOST_CLOSE 0x00 1351 #define R92C_C2HEVT_FW_CLOSE 0xff 1352 1353 /* 1354 * C2H event types. 1355 */ 1356 #define R92C_C2HEVT_DEBUG 0 1357 #define R92C_C2HEVT_TX_REPORT 3 1358 #define R92C_C2HEVT_EXT_RA_RPT 6 1359 1360 /* Structure for R92C_C2H_EVT_TX_REPORT event. */ 1361 struct r92c_c2h_tx_rpt { 1362 uint8_t rptb0; 1363 #define R92C_RPTB0_RETRY_CNT_M 0x3f 1364 #define R92C_RPTB0_RETRY_CNT_S 0 1365 1366 uint8_t rptb1; /* XXX junk */ 1367 #define R92C_RPTB1_RTS_RETRY_CNT_M 0x3f 1368 #define R92C_RPTB1_RTS_RETRY_CNT_S 0 1369 1370 uint8_t queue_time_low; 1371 uint8_t queue_time_high; 1372 uint8_t rptb4; 1373 #define R92C_RPTB4_MISSED_PKT_NUM_M 0x1f 1374 #define R92C_RPTB4_MISSED_PKT_NUM_S 0 1375 1376 uint8_t rptb5; 1377 #define R92C_RPTB5_MACID_M 0x1f 1378 #define R92C_RPTB5_MACID_S 0 1379 #define R92C_RPTB5_DES1_FRAGSSN_M 0xe0 1380 #define R92C_RPTB5_DES1_FRAGSSN_S 5 1381 1382 uint8_t rptb6; 1383 #define R92C_RPTB6_RPT_PKT_NUM_M 0x1f 1384 #define R92C_RPTB6_RPT_PKT_NUM_S 0 1385 #define R92C_RPTB6_PKT_DROP 0x20 1386 #define R92C_RPTB6_LIFE_EXPIRE 0x40 1387 #define R92C_RPTB6_RETRY_OVER 0x80 1388 1389 uint8_t rptb7; 1390 #define R92C_RPTB7_EDCA_M 0x0f 1391 #define R92C_RPTB7_EDCA_S 0 1392 #define R92C_RPTB7_BMC 0x20 1393 #define R92C_RPTB7_PKT_OK 0x40 1394 #define R92C_RPTB7_INT_CCX 0x80 1395 } __packed; 1396 1397 /* 1398 * MAC initialization values. 1399 */ 1400 static const struct { 1401 uint16_t reg; 1402 uint8_t val; 1403 } rtl8192ce_mac[] = { 1404 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1405 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1406 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1407 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1408 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1409 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1410 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1411 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, 1412 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, 1413 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1414 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1415 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1416 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1417 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1418 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1419 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, 1420 { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, 1421 { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, 1422 { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, 1423 { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, 1424 { 0x70b, 0x87 } 1425 }, rtl8188eu_mac[] = { 1426 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1427 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1428 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1429 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1430 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1431 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1432 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1433 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1434 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1435 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1436 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1437 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1438 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1439 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1440 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1441 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1442 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1443 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1444 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1445 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1446 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1447 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1448 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1449 }, rtl8192cu_mac[] = { 1450 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1451 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1452 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1453 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1454 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1455 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1456 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1457 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1458 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1459 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1460 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1461 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1462 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1463 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1464 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1465 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1466 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1467 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1468 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1469 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1470 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1471 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1472 }; 1473 1474 /* 1475 * Baseband initialization values. 1476 */ 1477 struct r92c_bb_prog { 1478 int count; 1479 const uint16_t *regs; 1480 const uint32_t *vals; 1481 int agccount; 1482 const uint32_t *agcvals; 1483 }; 1484 1485 /* 1486 * RTL8192CU and RTL8192CE-VAU. 1487 */ 1488 static const uint32_t rtl8192ce_bb_vals_1t[] = { 1489 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1490 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1491 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1492 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1493 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1494 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1495 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1496 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1497 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1498 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1499 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1500 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1501 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1502 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1503 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1504 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1505 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1506 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1507 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1508 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1509 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1510 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1511 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1512 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1513 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1514 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1515 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1516 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1517 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1518 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1519 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1520 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1521 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1522 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, 1523 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1524 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1525 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1526 0x00000000, 0x00000300, 1527 }; 1528 1529 static const uint16_t rtl8192ce_bb_regs[] = { 1530 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1531 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1532 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1533 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1534 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1535 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1536 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1537 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1538 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1539 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1540 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1541 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1542 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1543 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1544 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1545 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1546 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1547 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1548 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1549 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1550 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1551 }; 1552 1553 static const uint32_t rtl8192ce_bb_vals[] = { 1554 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1555 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1556 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1557 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1558 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1559 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1560 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1561 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1562 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1563 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1564 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1565 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1566 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1567 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1568 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1569 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1570 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1571 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1572 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1573 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1574 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1575 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1576 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1577 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1578 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1579 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1580 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1581 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1582 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1583 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1584 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1585 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1586 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1587 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1588 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1589 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1590 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1591 0x00000000, 0x00000300 1592 }; 1593 1594 static const uint32_t rtl8192ce_bb_vals_2t[] = { 1595 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1596 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1597 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1598 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1599 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1600 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1601 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1602 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1603 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1604 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1605 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1606 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1607 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1608 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1609 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1610 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1611 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1612 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1613 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1614 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1615 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1616 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1617 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1618 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1619 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1620 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1621 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1622 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1623 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1624 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1625 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1626 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1627 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1628 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1629 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1630 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1631 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1632 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1633 0x00000000, 0x00000300 1634 }; 1635 static const uint32_t rtl8192ce_agc_vals[] = { 1636 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1637 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1638 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1639 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1640 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1641 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1642 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1643 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1644 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1645 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1646 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1647 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1648 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1649 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1650 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1651 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1652 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1653 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1654 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1655 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1656 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1657 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1658 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1659 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1660 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1661 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1662 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1663 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1664 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1665 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1666 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1667 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1668 }; 1669 1670 static const struct r92c_bb_prog rtl8192ce_bb_prog = { 1671 nitems(rtl8192ce_bb_regs), 1672 rtl8192ce_bb_regs, 1673 rtl8192ce_bb_vals, 1674 nitems(rtl8192ce_agc_vals), 1675 rtl8192ce_agc_vals 1676 }; 1677 1678 static const struct r92c_bb_prog rtl8192ce_bb_prog_2t = { 1679 nitems(rtl8192ce_bb_regs), 1680 rtl8192ce_bb_regs, 1681 rtl8192ce_bb_vals_2t, 1682 nitems(rtl8192ce_agc_vals), 1683 rtl8192ce_agc_vals 1684 }; 1685 1686 static const struct r92c_bb_prog rtl8192ce_bb_prog_1t = { 1687 nitems(rtl8192ce_bb_regs), 1688 rtl8192ce_bb_regs, 1689 rtl8192ce_bb_vals_1t, 1690 nitems(rtl8192ce_agc_vals), 1691 rtl8192ce_agc_vals 1692 }; 1693 1694 /* 1695 * RTL8188CU. 1696 */ 1697 static const uint32_t rtl8192cu_bb_vals[] = { 1698 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1699 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1700 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1701 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1702 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1703 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1704 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1705 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1706 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1707 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1708 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1709 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1710 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1711 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1712 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1713 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1714 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1715 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1716 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1717 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1718 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1719 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1720 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1721 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1722 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1723 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1724 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1725 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1726 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1727 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1728 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1729 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1730 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1731 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1732 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1733 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1734 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1735 0x00000000, 0x00000300 1736 }; 1737 1738 static const struct r92c_bb_prog rtl8192cu_bb_prog = { 1739 nitems(rtl8192ce_bb_regs), 1740 rtl8192ce_bb_regs, 1741 rtl8192cu_bb_vals, 1742 nitems(rtl8192ce_agc_vals), 1743 rtl8192ce_agc_vals 1744 }; 1745 1746 /* 1747 * RTL8188CE-VAU. 1748 */ 1749 static const uint32_t rtl8188ce_bb_vals[] = { 1750 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1751 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1752 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1753 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1754 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1755 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1756 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1757 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1758 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1759 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1760 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1761 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1762 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1763 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1764 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1765 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1766 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1767 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1768 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1769 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1770 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1771 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1772 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1773 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1774 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1775 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1776 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1777 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1778 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1779 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1780 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1781 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1782 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1783 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1784 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1785 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1786 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1787 0x00000000, 0x00000300 1788 }; 1789 1790 static const uint32_t rtl8188ce_agc_vals[] = { 1791 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1792 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1793 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1794 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1795 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1796 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1797 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1798 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1799 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1800 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1801 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1802 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1803 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1804 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1805 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1806 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1807 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1808 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1809 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1810 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1811 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1812 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1813 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1814 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1815 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1816 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1817 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1818 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1819 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1820 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1821 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1822 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1823 }; 1824 1825 static const struct r92c_bb_prog rtl8188ce_bb_prog = { 1826 nitems(rtl8192ce_bb_regs), 1827 rtl8192ce_bb_regs, 1828 rtl8188ce_bb_vals, 1829 nitems(rtl8188ce_agc_vals), 1830 rtl8188ce_agc_vals 1831 }; 1832 1833 static const uint32_t rtl8188cu_bb_vals[] = { 1834 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1835 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1836 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1837 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1838 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1839 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1840 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1841 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1842 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1843 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1844 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1845 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1846 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1847 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1848 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1849 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1850 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1851 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1852 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1853 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1854 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1855 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1856 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1857 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1858 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1859 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1860 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1861 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1862 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1863 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1864 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1865 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1866 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1867 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1868 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1869 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1870 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1871 0x00000000, 0x00000300 1872 }; 1873 1874 static const struct r92c_bb_prog rtl8188cu_bb_prog = { 1875 nitems(rtl8192ce_bb_regs), 1876 rtl8192ce_bb_regs, 1877 rtl8188cu_bb_vals, 1878 nitems(rtl8188ce_agc_vals), 1879 rtl8188ce_agc_vals 1880 }; 1881 1882 /* 1883 * RTL8188EU. 1884 */ 1885 static const uint16_t rtl8188eu_bb_regs[] = { 1886 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 0x820, 1887 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840, 0x844, 1888 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868, 1889 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 1890 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 0x90c, 0x910, 1891 0x914, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1892 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 1893 0xb2c, 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1894 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 1895 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 1896 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 1897 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 1898 0xcb0, 0xcb4, 0xcb8, 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 1899 0xcd4, 0xcd8, 0xcdc, 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 1900 0xd08, 0xd0c, 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 1901 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1902 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 1903 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 1904 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 1905 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 1906 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 1907 0xf14, 0xf4c, 0xf00 1908 }; 1909 1910 static const uint32_t rtl8188eu_bb_vals[] = { 1911 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1912 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1913 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1914 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1915 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1916 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1917 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1918 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1919 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1920 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1921 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1922 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1923 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1924 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1925 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1926 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1927 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1928 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1929 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1930 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1931 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1932 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1933 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1934 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1935 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1936 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1937 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1938 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1939 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1940 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1941 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1942 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1943 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1944 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1945 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1946 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1947 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1948 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1949 0x00000000, 0x00000300 1950 }; 1951 1952 static const uint32_t rtl8188eu_agc_vals[] = { 1953 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1954 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1955 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1956 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1957 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1958 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1959 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1960 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1961 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1962 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1963 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1964 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1965 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1966 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1967 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1968 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1969 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1970 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1971 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1972 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1973 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1974 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1975 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1976 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1977 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1978 0x407d0001, 0x407e0001, 0x407f0001 1979 }; 1980 1981 static const struct r92c_bb_prog rtl8188eu_bb_prog = { 1982 nitems(rtl8188eu_bb_regs), 1983 rtl8188eu_bb_regs, 1984 rtl8188eu_bb_vals, 1985 nitems(rtl8188eu_agc_vals), 1986 rtl8188eu_agc_vals 1987 }; 1988 1989 /* 1990 * RTL8188RU. 1991 */ 1992 static const uint16_t rtl8188ru_bb_regs[] = { 1993 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1994 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1995 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1996 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1997 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1998 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1999 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 2000 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 2001 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 2002 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 2003 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 2004 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 2005 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 2006 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 2007 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 2008 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 2009 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 2010 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 2011 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 2012 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 2013 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 2014 }; 2015 2016 static const uint32_t rtl8188ru_bb_vals[] = { 2017 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 2018 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 2019 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 2020 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 2021 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2022 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 2023 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 2024 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 2025 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 2026 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 2027 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 2028 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 2029 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 2030 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 2031 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 2032 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 2033 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 2034 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 2035 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 2036 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 2037 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 2038 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 2039 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2040 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 2041 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 2042 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 2043 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 2044 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 2045 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 2046 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 2047 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 2048 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 2049 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 2050 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 2051 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 2052 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 2053 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 2054 0x31555448, 0x00000003, 0x00000000, 0x00000300 2055 }; 2056 2057 static const uint32_t rtl8188ru_agc_vals[] = { 2058 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 2059 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 2060 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 2061 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 2062 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 2063 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 2064 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 2065 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 2066 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 2067 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 2068 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 2069 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 2070 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 2071 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 2072 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 2073 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 2074 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 2075 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 2076 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 2077 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 2078 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 2079 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 2080 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 2081 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 2082 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 2083 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 2084 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 2085 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 2086 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 2087 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 2088 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 2089 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 2090 }; 2091 2092 static const struct r92c_bb_prog rtl8188ru_bb_prog = { 2093 nitems(rtl8188ru_bb_regs), 2094 rtl8188ru_bb_regs, 2095 rtl8188ru_bb_vals, 2096 nitems(rtl8188ru_agc_vals), 2097 rtl8188ru_agc_vals 2098 }; 2099 2100 /* 2101 * RF initialization values. 2102 */ 2103 struct r92c_rf_prog { 2104 int count; 2105 const uint8_t *regs; 2106 const uint32_t *vals; 2107 }; 2108 2109 /* 2110 * RTL8192CU and RTL8192CE-VAU. 2111 */ 2112 static const uint8_t rtl8192ce_rf1_regs[] = { 2113 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 2114 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 2115 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 2116 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 2117 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 2118 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 2119 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 2120 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 2121 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 2122 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 2123 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 2124 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 2125 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2126 }; 2127 2128 static const uint32_t rtl8192ce_rf1_vals[] = { 2129 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2130 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2131 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2132 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 2133 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2134 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2135 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2136 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2137 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2138 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2139 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2140 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2141 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2142 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2143 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2144 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 2145 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 2146 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 2147 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2148 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2149 0x30159 2150 }; 2151 2152 static const uint8_t rtl8192ce_rf2_regs[] = { 2153 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 2154 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 2155 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 2156 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 2157 }; 2158 2159 static const uint32_t rtl8192ce_rf2_vals[] = { 2160 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2161 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 2162 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 2163 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 2164 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 2165 0xe0330, 0xa0330, 0x60330, 0x20330 2166 }; 2167 2168 static const struct r92c_rf_prog rtl8192ce_rf_prog[] = { 2169 { 2170 nitems(rtl8192ce_rf1_regs), 2171 rtl8192ce_rf1_regs, 2172 rtl8192ce_rf1_vals 2173 }, 2174 { 2175 nitems(rtl8192ce_rf2_regs), 2176 rtl8192ce_rf2_regs, 2177 rtl8192ce_rf2_vals 2178 } 2179 }; 2180 2181 /* 2182 * RTL8188CE-VAU. 2183 */ 2184 static const uint32_t rtl8188ce_rf_vals[] = { 2185 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2186 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2187 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2188 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 2189 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2190 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2191 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2192 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2193 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2194 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2195 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2196 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2197 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2198 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2199 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2200 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 2201 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 2202 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 2203 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2204 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2205 0x30159 2206 }; 2207 2208 static const struct r92c_rf_prog rtl8188ce_rf_prog[] = { 2209 { 2210 nitems(rtl8192ce_rf1_regs), 2211 rtl8192ce_rf1_regs, 2212 rtl8188ce_rf_vals 2213 } 2214 }; 2215 2216 2217 /* 2218 * RTL8188CU. 2219 */ 2220 static const uint32_t rtl8188cu_rf_vals[] = { 2221 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2222 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2223 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2224 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 2225 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2226 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2227 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2228 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2229 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2230 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2231 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2232 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2233 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2234 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2235 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2236 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 2237 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 2238 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2239 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2240 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2241 0x30159 2242 }; 2243 2244 static const struct r92c_rf_prog rtl8188cu_rf_prog[] = { 2245 { 2246 nitems(rtl8192ce_rf1_regs), 2247 rtl8192ce_rf1_regs, 2248 rtl8188cu_rf_vals 2249 } 2250 }; 2251 2252 /* 2253 * RTL8188EU. 2254 */ 2255 static const uint8_t rtl8188eu_rf_regs[] = { 2256 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 0x58, 2257 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 2258 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 2259 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 0x35, 0x35, 0x35, 0x36, 0x36, 2260 0x36, 0x36, 0xb6, 0x18, 0x5a, 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 2261 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 2262 0x8f, 0xef, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2263 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 2264 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2265 }; 2266 2267 static const uint32_t rtl8188eu_rf_vals[] = { 2268 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2269 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2270 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2271 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2272 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2273 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 0x00286, 2274 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 0x4bd00, 2275 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 0x054ee, 2276 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 0x68200, 2277 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 0xef7b0, 2278 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 0x722b0, 2279 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 0x0f780, 2280 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 0x00000, 2281 0x00000, 0x00001, 0x80000, 0x33e60 2282 }; 2283 2284 static const struct r92c_rf_prog rtl8188eu_rf_prog[] = { 2285 { 2286 nitems(rtl8188eu_rf_regs), 2287 rtl8188eu_rf_regs, 2288 rtl8188eu_rf_vals 2289 } 2290 }; 2291 2292 /* 2293 * RTL8188RU. 2294 */ 2295 static const uint32_t rtl8188ru_rf_vals[] = { 2296 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2297 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2298 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2299 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2300 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2301 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2302 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2303 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2304 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2305 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2306 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2307 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2308 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2309 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2310 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2311 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2312 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2313 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2314 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2315 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2316 0x30159 2317 }; 2318 2319 static const struct r92c_rf_prog rtl8188ru_rf_prog[] = { 2320 { 2321 nitems(rtl8192ce_rf1_regs), 2322 rtl8192ce_rf1_regs, 2323 rtl8188ru_rf_vals 2324 } 2325 }; 2326 2327 struct r92c_txpwr { 2328 uint8_t pwr[3][28]; 2329 }; 2330 2331 /* 2332 * Per RF chain/group/rate Tx gain values. 2333 */ 2334 static const struct r92c_txpwr rtl8192cu_txagc[] = { 2335 { { /* Chain 0. */ 2336 { /* Group 0. */ 2337 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2338 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2339 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2340 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2341 }, 2342 { /* Group 1. */ 2343 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2344 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2346 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2347 }, 2348 { /* Group 2. */ 2349 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2350 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2351 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2352 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2353 } 2354 } }, 2355 { { /* Chain 1. */ 2356 { /* Group 0. */ 2357 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2359 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2360 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2361 }, 2362 { /* Group 1. */ 2363 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2364 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2366 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2367 }, 2368 { /* Group 2. */ 2369 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2370 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2372 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2373 } 2374 } } 2375 }; 2376 2377 static const struct r92c_txpwr rtl8188ru_txagc[] = { 2378 { { /* Chain 0. */ 2379 { /* Group 0. */ 2380 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2381 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2382 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2383 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2384 }, 2385 { /* Group 1. */ 2386 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2388 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2389 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2390 }, 2391 { /* Group 2. */ 2392 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2393 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2394 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2396 } 2397 } } 2398 }; 2399