1 /* $OpenBSD: nvmereg.h,v 1.10 2016/04/14 11:18:32 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define NVME_CAP 0x0000 /* Controller Capabilities */ 20 #define NVME_CAP_MPSMAX(_r) (12 + (((_r) >> 52) & 0xf)) /* shift */ 21 #define NVME_CAP_MPSMIN(_r) (12 + (((_r) >> 48) & 0xf)) /* shift */ 22 #define NVME_CAP_CSS(_r) (((_r) >> 37) & 0x7f) 23 #define NVME_CAP_CSS_NVM (1 << 0) 24 #define NVME_CAP_NSSRS(_r) ISSET((_r), (1ULL << 36)) 25 #define NVME_CAP_DSTRD(_r) (1 << (2 + (((_r) >> 32) & 0xf))) /* bytes */ 26 #define NVME_CAP_TO(_r) (500 * (((_r) >> 24) & 0xff)) /* ms */ 27 #define NVME_CAP_AMS(_r) (((_r) >> 17) & 0x3) 28 #define NVME_CAP_AMS_WRR (1 << 0) 29 #define NVME_CAP_AMS_VENDOR (1 << 1) 30 #define NVME_CAP_CQR(_r) ISSET((_r), (1 << 16)) 31 #define NVME_CAP_MQES(_r) (((_r) & 0xffff) + 1) 32 #define NVME_CAP_LO 0x0000 33 #define NVME_CAP_HI 0x0004 34 #define NVME_VS 0x0008 /* Version */ 35 #define NVME_VS_MJR(_r) (((_r) >> 16) & 0xffff) 36 #define NVME_VS_MNR(_r) ((_r) & 0xffff) 37 #define NVME_VS_1_0 0x00010000 38 #define NVME_VS_1_1 0x00010100 39 #define NVME_VS_1_2 0x00010200 40 #define NVME_INTMS 0x000c /* Interrupt Mask Set */ 41 #define NVME_INTMC 0x0010 /* Interrupt Mask Clear */ 42 #define NVME_CC 0x0014 /* Controller Configuration */ 43 #define NVME_CC_IOCQES(_v) (((_v) & 0xf) << 20) 44 #define NVME_CC_IOCQES_MASK NVME_CC_IOCQES(0xf) 45 #define NVME_CC_IOCQES_R(_v) (((_v) >> 20) & 0xf) 46 #define NVME_CC_IOSQES(_v) (((_v) & 0xf) << 16) 47 #define NVME_CC_IOSQES_MASK NVME_CC_IOSQES(0xf) 48 #define NVME_CC_IOSQES_R(_v) (((_v) >> 16) & 0xf) 49 #define NVME_CC_SHN(_v) (((_v) & 0x3) << 14) 50 #define NVME_CC_SHN_MASK NVME_CC_SHN(0x3) 51 #define NVME_CC_SHN_R(_v) (((_v) >> 15) & 0x3) 52 #define NVME_CC_SHN_NONE 0 53 #define NVME_CC_SHN_NORMAL 1 54 #define NVME_CC_SHN_ABRUPT 2 55 #define NVME_CC_AMS(_v) (((_v) & 0x7) << 11) 56 #define NVME_CC_AMS_MASK NVME_CC_AMS(0x7) 57 #define NVME_CC_AMS_R(_v) (((_v) >> 11) & 0xf) 58 #define NVME_CC_AMS_RR 0 /* round-robin */ 59 #define NVME_CC_AMS_WRR_U 1 /* weighted round-robin w/ urgent */ 60 #define NVME_CC_AMS_VENDOR 7 /* vendor */ 61 #define NVME_CC_MPS(_v) ((((_v) - 12) & 0xf) << 7) 62 #define NVME_CC_MPS_MASK (0xf << 7) 63 #define NVME_CC_MPS_R(_v) (12 + (((_v) >> 7) & 0xf)) 64 #define NVME_CC_CSS(_v) (((_v) & 0x7) << 4) 65 #define NVME_CC_CSS_MASK NVME_CC_CSS(0x7) 66 #define NVME_CC_CSS_R(_v) (((_v) >> 4) & 0x7) 67 #define NVME_CC_CSS_NVM 0 68 #define NVME_CC_EN (1 << 0) 69 #define NVME_CSTS 0x001c /* Controller Status */ 70 #define NVME_CSTS_SHST_MASK (0x3 << 2) 71 #define NVME_CSTS_SHST_NONE (0x0 << 2) /* normal operation */ 72 #define NVME_CSTS_SHST_WAIT (0x1 << 2) /* shutdown processing occurring */ 73 #define NVME_CSTS_SHST_DONE (0x2 << 2) /* shutdown processing complete */ 74 #define NVME_CSTS_CFS (1 << 1) 75 #define NVME_CSTS_RDY (1 << 0) 76 #define NVME_NSSR 0x0020 /* NVM Subsystem Reset (Optional) */ 77 #define NVME_AQA 0x0024 /* Admin Queue Attributes */ 78 /* Admin Completion Queue Size */ 79 #define NVME_AQA_ACQS(_v) (((_v) - 1) << 16) 80 /* Admin Submission Queue Size */ 81 #define NVME_AQA_ASQS(_v) (((_v) - 1) << 0) 82 #define NVME_ASQ 0x0028 /* Admin Submission Queue Base Address */ 83 #define NVME_ACQ 0x0030 /* Admin Completion Queue Base Address */ 84 85 #define NVME_ADMIN_Q 0 86 /* Submission Queue Tail Doorbell */ 87 #define NVME_SQTDBL(_q, _s) (0x1000 + (2 * (_q) + 0) * (_s)) 88 /* Completion Queue Head Doorbell */ 89 #define NVME_CQHDBL(_q, _s) (0x1000 + (2 * (_q) + 1) * (_s)) 90 91 struct nvme_sge { 92 u_int8_t id; 93 u_int8_t _reserved[15]; 94 } __packed __aligned(8); 95 96 struct nvme_sge_data { 97 u_int8_t id; 98 u_int8_t _reserved[3]; 99 100 u_int32_t length; 101 102 u_int64_t address; 103 } __packed __aligned(8); 104 105 struct nvme_sge_bit_bucket { 106 u_int8_t id; 107 u_int8_t _reserved[3]; 108 109 u_int32_t length; 110 111 u_int64_t address; 112 } __packed __aligned(8); 113 114 struct nvme_sqe { 115 u_int8_t opcode; 116 u_int8_t flags; 117 u_int16_t cid; 118 119 u_int32_t nsid; 120 121 u_int8_t _reserved[8]; 122 123 u_int64_t mptr; 124 125 union { 126 u_int64_t prp[2]; 127 struct nvme_sge sge; 128 } __packed entry; 129 130 u_int32_t cdw10; 131 u_int32_t cdw11; 132 u_int32_t cdw12; 133 u_int32_t cdw13; 134 u_int32_t cdw14; 135 u_int32_t cdw15; 136 } __packed __aligned(8); 137 138 struct nvme_sqe_q { 139 u_int8_t opcode; 140 u_int8_t flags; 141 u_int16_t cid; 142 143 u_int8_t _reserved1[20]; 144 145 u_int64_t prp1; 146 147 u_int8_t _reserved2[8]; 148 149 u_int16_t qid; 150 u_int16_t qsize; 151 152 u_int8_t qflags; 153 #define NVM_SQE_SQ_QPRIO_URG (0x0 << 1) 154 #define NVM_SQE_SQ_QPRIO_HI (0x1 << 1) 155 #define NVM_SQE_SQ_QPRIO_MED (0x2 << 1) 156 #define NVM_SQE_SQ_QPRIO_LOW (0x3 << 1) 157 #define NVM_SQE_CQ_IEN (1 << 1) 158 #define NVM_SQE_Q_PC (1 << 0) 159 u_int8_t _reserved3; 160 u_int16_t cqid; /* XXX interrupt vector for cq */ 161 162 u_int8_t _reserved4[16]; 163 } __packed __aligned(8); 164 165 struct nvme_sqe_io { 166 u_int8_t opcode; 167 u_int8_t flags; 168 u_int16_t cid; 169 170 u_int32_t nsid; 171 172 u_int8_t _reserved[8]; 173 174 u_int64_t mptr; 175 176 union { 177 u_int64_t prp[2]; 178 struct nvme_sge sge; 179 } __packed entry; 180 181 u_int64_t slba; /* Starting LBA */ 182 183 u_int16_t nlb; /* Number of Logical Blocks */ 184 u_int16_t ioflags; 185 186 u_int8_t dsm; /* Dataset Management */ 187 u_int8_t _reserved2[3]; 188 189 u_int32_t eilbrt; /* Expected Initial Logical Block 190 Reference Tag */ 191 192 u_int16_t elbat; /* Expected Logical Block 193 Application Tag */ 194 u_int16_t elbatm; /* Expected Logical Block 195 Application Tag Mask */ 196 } __packed __aligned(8); 197 198 struct nvme_cqe { 199 u_int32_t cdw0; 200 201 u_int32_t _reserved; 202 203 u_int16_t sqhd; /* SQ Head Pointer */ 204 u_int16_t sqid; /* SQ Identifier */ 205 206 u_int16_t cid; /* Command Identifier */ 207 u_int16_t flags; 208 #define NVME_CQE_DNR (1 << 15) 209 #define NVME_CQE_M (1 << 14) 210 #define NVME_CQE_SCT(_f) ((_f) & (0x07 << 8)) 211 #define NVME_CQE_SCT_GENERIC (0x00 << 8) 212 #define NVME_CQE_SCT_COMMAND (0x01 << 8) 213 #define NVME_CQE_SCT_MEDIAERR (0x02 << 8) 214 #define NVME_CQE_SCT_VENDOR (0x07 << 8) 215 #define NVME_CQE_SC(_f) ((_f) & (0x7f << 1)) 216 #define NVME_CQE_SC_SUCCESS (0x00 << 1) 217 #define NVME_CQE_SC_INVALID_OPCODE (0x01 << 1) 218 #define NVME_CQE_SC_INVALID_FIELD (0x02 << 1) 219 #define NVME_CQE_SC_CID_CONFLICT (0x03 << 1) 220 #define NVME_CQE_SC_DATA_XFER_ERR (0x04 << 1) 221 #define NVME_CQE_SC_ABRT_BY_NO_PWR (0x05 << 1) 222 #define NVME_CQE_SC_INTERNAL_DEV_ERR (0x06 << 1) 223 #define NVME_CQE_SC_CMD_ABRT_REQD (0x07 << 1) 224 #define NVME_CQE_SC_CMD_ABDR_SQ_DEL (0x08 << 1) 225 #define NVME_CQE_SC_CMD_ABDR_FUSE_ERR (0x09 << 1) 226 #define NVME_CQE_SC_CMD_ABDR_FUSE_MISS (0x0a << 1) 227 #define NVME_CQE_SC_INVALID_NS (0x0b << 1) 228 #define NVME_CQE_SC_CMD_SEQ_ERR (0x0c << 1) 229 #define NVME_CQE_SC_INVALID_LAST_SGL (0x0d << 1) 230 #define NVME_CQE_SC_INVALID_NUM_SGL (0x0e << 1) 231 #define NVME_CQE_SC_DATA_SGL_LEN (0x0f << 1) 232 #define NVME_CQE_SC_MDATA_SGL_LEN (0x10 << 1) 233 #define NVME_CQE_SC_SGL_TYPE_INVALID (0x11 << 1) 234 #define NVME_CQE_SC_LBA_RANGE (0x80 << 1) 235 #define NVME_CQE_SC_CAP_EXCEEDED (0x81 << 1) 236 #define NVME_CQE_NS_NOT_RDY (0x82 << 1) 237 #define NVME_CQE_RSV_CONFLICT (0x83 << 1) 238 #define NVME_CQE_PHASE (1 << 0) 239 } __packed __aligned(8); 240 241 #define NVM_ADMIN_DEL_IOSQ 0x00 /* Delete I/O Submission Queue */ 242 #define NVM_ADMIN_ADD_IOSQ 0x01 /* Create I/O Submission Queue */ 243 #define NVM_ADMIN_GET_LOG_PG 0x02 /* Get Log Page */ 244 #define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */ 245 #define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */ 246 #define NVM_ADMIN_IDENTIFY 0x06 /* Identify */ 247 #define NVM_ADMIN_ABORT 0x08 /* Abort */ 248 #define NVM_ADMIN_SET_FEATURES 0x09 /* Set Features */ 249 #define NVM_ADMIN_GET_FEATURES 0x0a /* Get Features */ 250 #define NVM_ADMIN_ASYNC_EV_REQ 0x0c /* Asynchronous Event Request */ 251 #define NVM_ADMIN_FW_ACTIVATE 0x10 /* Firmware Activate */ 252 #define NVM_ADMIN_FW_DOWNLOAD 0x11 /* Firmware Image Download */ 253 254 #define NVM_CMD_FLUSH 0x00 /* Flush */ 255 #define NVM_CMD_WRITE 0x01 /* Write */ 256 #define NVM_CMD_READ 0x02 /* Read */ 257 #define NVM_CMD_WR_UNCOR 0x04 /* Write Uncorrectable */ 258 #define NVM_CMD_COMPARE 0x05 /* Compare */ 259 #define NVM_CMD_DSM 0x09 /* Dataset Management */ 260 261 /* Power State Descriptor Data */ 262 struct nvm_identify_psd { 263 u_int16_t mp; /* Max Power */ 264 u_int16_t flags; 265 266 u_int32_t enlat; /* Entry Latency */ 267 268 u_int32_t exlat; /* Exit Latency */ 269 270 u_int8_t rrt; /* Relative Read Throughput */ 271 u_int8_t rrl; /* Relative Read Latency */ 272 u_int8_t rwt; /* Relative Write Throughput */ 273 u_int8_t rwl; /* Relative Write Latency */ 274 275 u_int8_t _reserved[16]; 276 } __packed __aligned(8); 277 278 struct nvm_identify_controller { 279 /* Controller Capabilities and Features */ 280 281 u_int16_t vid; /* PCI Vendor ID */ 282 u_int16_t ssvid; /* PCI Subsystem Vendor ID */ 283 284 u_int8_t sn[20]; /* Serial Number */ 285 u_int8_t mn[40]; /* Model Number */ 286 u_int8_t fr[8]; /* Firmware Revision */ 287 288 u_int8_t rab; /* Recommended Arbitration Burst */ 289 u_int8_t ieee[3]; /* IEEE OUI Identifier */ 290 291 u_int8_t cmic; /* Controller Multi-Path I/O and 292 Namespace Sharing Capabilities */ 293 u_int8_t mdts; /* Maximum Data Transfer Size */ 294 u_int16_t cntlid; /* Controller ID */ 295 296 u_int8_t _reserved1[176]; 297 298 /* Admin Command Set Attributes & Optional Controller Capabilities */ 299 300 u_int16_t oacs; /* Optional Admin Command Support */ 301 u_int8_t acl; /* Abort Command Limit */ 302 u_int8_t aerl; /* Asynchronous Event Request Limit */ 303 304 u_int8_t frmw; /* Firmware Updates */ 305 u_int8_t lpa; /* Log Page Attributes */ 306 u_int8_t elpe; /* Error Log Page Entries */ 307 u_int8_t npss; /* Number of Power States Support */ 308 309 u_int8_t avscc; /* Admin Vendor Specific Command 310 Configuration */ 311 u_int8_t apsta; /* Autonomous Power State Transition 312 Attributes */ 313 314 u_int8_t _reserved2[246]; 315 316 /* NVM Command Set Attributes */ 317 318 u_int8_t sqes; /* Submission Queue Entry Size */ 319 u_int8_t cqes; /* Completion Queue Entry Size */ 320 u_int8_t _reserved3[2]; 321 322 u_int32_t nn; /* Number of Namespaces */ 323 324 u_int16_t oncs; /* Optional NVM Command Support */ 325 u_int16_t fuses; /* Fused Operation Support */ 326 327 u_int8_t fna; /* Format NVM Attributes */ 328 u_int8_t vwc; /* Volatile Write Cache */ 329 u_int16_t awun; /* Atomic Write Unit Normal */ 330 331 u_int16_t awupf; /* Atomic Write Unit Power Fail */ 332 u_int8_t nvscc; /* NVM Vendor Specific Command */ 333 u_int8_t _reserved4[1]; 334 335 u_int16_t acwu; /* Atomic Compare & Write Unit */ 336 u_int8_t _reserved5[2]; 337 338 u_int32_t sgls; /* SGL Support */ 339 340 u_int8_t _reserved6[164]; 341 342 /* I/O Command Set Attributes */ 343 344 u_int8_t _reserved7[1344]; 345 346 /* Power State Descriptors */ 347 348 struct nvm_identify_psd psd[32]; /* Power State Descriptors */ 349 350 /* Vendor Specific */ 351 352 u_int8_t _reserved8[1024]; 353 } __packed __aligned(8); 354 355 struct nvm_namespace_format { 356 u_int16_t ms; /* Metadata Size */ 357 u_int8_t lbads; /* LBA Data Size */ 358 u_int8_t rp; /* Relative Performance */ 359 } __packed __aligned(4); 360 361 struct nvm_identify_namespace { 362 u_int64_t nsze; /* Namespace Size */ 363 364 u_int64_t ncap; /* Namespace Capacity */ 365 366 u_int64_t nuse; /* Namespace Utilization */ 367 368 u_int8_t nsfeat; /* Namespace Features */ 369 u_int8_t nlbaf; /* Number of LBA Formats */ 370 u_int8_t flbas; /* Formatted LBA Size */ 371 #define NVME_ID_NS_FLBAS(_f) ((_f) & 0x0f) 372 #define NVME_ID_NS_FLBAS_MD 0x10 373 u_int8_t mc; /* Metadata Capabilities */ 374 u_int8_t dpc; /* End-to-end Data Protection 375 Capabilities */ 376 u_int8_t dps; /* End-to-end Data Protection Type Settings */ 377 378 u_int8_t _reserved1[98]; 379 380 struct nvm_namespace_format 381 lbaf[16]; /* LBA Format Support */ 382 383 u_int8_t _reserved2[192]; 384 385 u_int8_t vs[3712]; 386 } __packed __aligned(8); 387