1 /* $OpenBSD: mfireg.h,v 1.45 2016/08/14 04:08:03 dlg Exp $ */ 2 /* 3 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* management interface constants */ 19 #define MFI_MGMT_VD 0x01 20 #define MFI_MGMT_SD 0x02 21 22 /* generic constants */ 23 #define MFI_FRAME_SIZE 64 24 #define MFI_SENSE_SIZE 128 25 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 26 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 27 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 28 #define MFI_INVALID_CTX 0xffffffff 29 #define MFI_ENABLE_INTR 0x01 30 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 31 32 /* register offsets */ 33 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 34 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 35 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 36 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 37 #define MFI_IDB 0x20 /* inbound doorbell */ 38 #define MFI_ISTS 0x24 /* inbound intr stat */ 39 #define MFI_IMSK 0x28 /* inbound intr mask */ 40 #define MFI_ODB 0x2c /* outbound doorbell */ 41 #define MFI_OSTS 0x30 /* outbound intr stat */ 42 #define MFI_OMSK 0x34 /* outbound inter mask */ 43 #define MFI_IQP 0x40 /* inbound queue port */ 44 #define MFI_OQP 0x44 /* outbound queue port */ 45 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 46 #define MFI_OSP 0xb0 /* outbound scratch pad */ 47 48 /* 49 * skinny specific changes 50 */ 51 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 52 #define MFI_IQPL 0x000000c0 53 #define MFI_IQPH 0x000000c4 54 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 55 56 /* * firmware states */ 57 #define MFI_STATE_MASK 0xf0000000 58 #define MFI_STATE_UNDEFINED 0x00000000 59 #define MFI_STATE_BB_INIT 0x10000000 60 #define MFI_STATE_FW_INIT 0x40000000 61 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 62 #define MFI_STATE_FW_INIT_2 0x70000000 63 #define MFI_STATE_DEVICE_SCAN 0x80000000 64 #define MFI_STATE_FLUSH_CACHE 0xa0000000 65 #define MFI_STATE_READY 0xb0000000 66 #define MFI_STATE_OPERATIONAL 0xc0000000 67 #define MFI_STATE_FAULT 0xf0000000 68 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 69 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 70 71 /* command reset register */ 72 #define MFI_INIT_ABORT 0x00000000 73 #define MFI_INIT_READY 0x00000002 74 #define MFI_INIT_MFIMODE 0x00000004 75 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 76 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 77 78 /* mfi Frame flags */ 79 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 80 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 81 #define MFI_FRAME_SGL32 0x0000 82 #define MFI_FRAME_SGL64 0x0002 83 #define MFI_FRAME_SENSE32 0x0000 84 #define MFI_FRAME_SENSE64 0x0004 85 #define MFI_FRAME_DIR_NONE 0x0000 86 #define MFI_FRAME_DIR_WRITE 0x0008 87 #define MFI_FRAME_DIR_READ 0x0010 88 #define MFI_FRAME_DIR_BOTH 0x0018 89 #define MFI_FRAME_IEEE 0x0020 90 91 /* mfi command opcodes */ 92 #define MFI_CMD_INIT 0x00 93 #define MFI_CMD_LD_READ 0x01 94 #define MFI_CMD_LD_WRITE 0x02 95 #define MFI_CMD_LD_SCSI_IO 0x03 96 #define MFI_CMD_PD_SCSI_IO 0x04 97 #define MFI_CMD_DCMD 0x05 98 #define MFI_CMD_ABORT 0x06 99 #define MFI_CMD_SMP 0x07 100 #define MFI_CMD_STP 0x08 101 102 #define MFI_PR_STATE_STOPPED 0 103 #define MFI_PR_STATE_READY 1 104 #define MFI_PR_STATE_ACTIVE 2 105 #define MFI_PR_STATE_ABORTED 0xff 106 107 #define MFI_PR_OPMODE_AUTO 0x00 108 #define MFI_PR_OPMODE_MANUAL 0x01 109 #define MFI_PR_OPMODE_DISABLED 0x02 110 111 /* direct commands */ 112 #define MR_DCMD_CTRL_GET_INFO 0x01010000 113 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 114 #define MR_FLUSH_CTRL_CACHE 0x01 115 #define MR_FLUSH_DISK_CACHE 0x02 116 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 117 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 118 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 119 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 120 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 121 #define MR_DCMD_PR_GET_STATUS 0x01070100 122 #define MR_DCMD_PR_GET_PROPERTIES 0x01070200 123 #define MR_DCMD_PR_SET_PROPERTIES 0x01070300 124 #define MR_DCMD_PR_START 0x01070400 125 #define MR_DCMD_PR_STOP 0x01070500 126 #define MR_DCMD_TIME_SECS_GET 0x01080201 127 #define MR_DCMD_PD_GET_LIST 0x02010000 128 #define MR_DCMD_PD_GET_INFO 0x02020000 129 #define MR_DCMD_PD_SET_STATE 0x02030100 130 #define MR_DCMD_PD_REBUILD 0x02040100 131 #define MR_DCMD_PD_BLINK 0x02070100 132 #define MR_DCMD_PD_UNBLINK 0x02070200 133 #define MR_DCMD_PD_GET_ALLOWED_OPS_LIST 0x020a0100 134 #define MR_DCMD_LD_GET_LIST 0x03010000 135 #define MR_DCMD_LD_GET_INFO 0x03020000 136 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 137 #define MR_DCMD_LD_SET_PROPERTIES 0x03040000 138 #define MR_DCMD_LD_DELETE 0x03090000 139 #define MR_DCMD_CONF_GET 0x04010000 140 #define MR_DCMD_CFG_ADD 0x04020000 141 #define MR_DCMD_CFG_CLEAR 0x04030000 142 #define MR_DCMD_BBU_GET_STATUS 0x05010000 143 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 144 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 145 #define MR_DCMD_BBU_START_LEARN 0x05040000 146 #define MR_DCMD_BBU_GET_PROP 0x05050100 147 #define MR_DCMD_BBU_SET_PROP 0x05050200 148 #define MR_DCMD_CLUSTER 0x08000000 149 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 150 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 151 152 #define MR_DCMD_SPEAKER_GET 0x01030100 153 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 154 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 155 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 156 #define MR_DCMD_SPEAKER_TEST 0x01030500 157 158 #define MR_LD_CACHE_WRITE_BACK 0x01 159 #define MR_LD_CACHE_WRITE_ADAPTIVE 0x02 160 #define MR_LD_CACHE_READ_AHEAD 0x04 161 #define MR_LD_CACHE_READ_ADAPTIVE 0x08 162 #define MR_LD_CACHE_WRITE_CACHE_BAD_BBU 0x10 163 #define MR_LD_CACHE_ALLOW_WRITE_CACHE 0x20 164 #define MR_LD_CACHE_ALLOW_READ_CACHE 0x40 165 166 #define MR_LD_DISK_CACHE_ENABLE 0x01 167 #define MR_LD_DISK_CACHE_DISABLE 0x02 168 169 /* mailbox bytes in direct command */ 170 #define MFI_MBOX_SIZE 12 171 172 /* mfi completion codes */ 173 typedef enum { 174 MFI_STAT_OK = 0x00, 175 MFI_STAT_INVALID_CMD = 0x01, 176 MFI_STAT_INVALID_DCMD = 0x02, 177 MFI_STAT_INVALID_PARAMETER = 0x03, 178 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 179 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 180 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 181 MFI_STAT_APP_IN_USE = 0x07, 182 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 183 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 184 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 185 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 186 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 187 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 188 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 189 MFI_STAT_FLASH_BUSY = 0x0f, 190 MFI_STAT_FLASH_ERROR = 0x10, 191 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 192 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 193 MFI_STAT_FLASH_NOT_OPEN = 0x13, 194 MFI_STAT_FLASH_NOT_STARTED = 0x14, 195 MFI_STAT_FLUSH_FAILED = 0x15, 196 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 197 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 198 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 199 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 200 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 201 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 202 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 203 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 204 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 205 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 206 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 207 MFI_STAT_MFC_HW_ERROR = 0x21, 208 MFI_STAT_NO_HW_PRESENT = 0x22, 209 MFI_STAT_NOT_FOUND = 0x23, 210 MFI_STAT_NOT_IN_ENCL = 0x24, 211 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 212 MFI_STAT_PD_TYPE_WRONG = 0x26, 213 MFI_STAT_PR_DISABLED = 0x27, 214 MFI_STAT_ROW_INDEX_INVALID = 0x28, 215 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 216 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 217 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 218 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 219 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 220 MFI_STAT_SCSI_IO_FAILED = 0x2e, 221 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 222 MFI_STAT_SHUTDOWN_FAILED = 0x30, 223 MFI_STAT_TIME_NOT_SET = 0x31, 224 MFI_STAT_WRONG_STATE = 0x32, 225 MFI_STAT_LD_OFFLINE = 0x33, 226 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 227 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 228 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 229 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 230 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 231 MFI_STAT_INVALID_STATUS = 0xff 232 } mfi_status_t; 233 234 typedef enum { 235 MFI_EVT_CLASS_DEBUG = -2, 236 MFI_EVT_CLASS_PROGRESS = -1, 237 MFI_EVT_CLASS_INFO = 0, 238 MFI_EVT_CLASS_WARNING = 1, 239 MFI_EVT_CLASS_CRITICAL = 2, 240 MFI_EVT_CLASS_FATAL = 3, 241 MFI_EVT_CLASS_DEAD = 4 242 } mfi_evt_class_t; 243 244 typedef enum { 245 MFI_EVT_LOCALE_LD = 0x0001, 246 MFI_EVT_LOCALE_PD = 0x0002, 247 MFI_EVT_LOCALE_ENCL = 0x0004, 248 MFI_EVT_LOCALE_BBU = 0x0008, 249 MFI_EVT_LOCALE_SAS = 0x0010, 250 MFI_EVT_LOCALE_CTRL = 0x0020, 251 MFI_EVT_LOCALE_CONFIG = 0x0040, 252 MFI_EVT_LOCALE_CLUSTER = 0x0080, 253 MFI_EVT_LOCALE_ALL = 0xffff 254 } mfi_evt_locale_t; 255 256 typedef enum { 257 MR_EVT_ARGS_NONE = 0x00, 258 MR_EVT_ARGS_CDB_SENSE, 259 MR_EVT_ARGS_LD, 260 MR_EVT_ARGS_LD_COUNT, 261 MR_EVT_ARGS_LD_LBA, 262 MR_EVT_ARGS_LD_OWNER, 263 MR_EVT_ARGS_LD_LBA_PD_LBA, 264 MR_EVT_ARGS_LD_PROG, 265 MR_EVT_ARGS_LD_STATE, 266 MR_EVT_ARGS_LD_STRIP, 267 MR_EVT_ARGS_PD, 268 MR_EVT_ARGS_PD_ERR, 269 MR_EVT_ARGS_PD_LBA, 270 MR_EVT_ARGS_PD_LBA_LD, 271 MR_EVT_ARGS_PD_PROG, 272 MR_EVT_ARGS_PD_STATE, 273 MR_EVT_ARGS_PCI, 274 MR_EVT_ARGS_RATE, 275 MR_EVT_ARGS_STR, 276 MR_EVT_ARGS_TIME, 277 MR_EVT_ARGS_ECC 278 } mfi_evt_args; 279 280 /* driver definitions */ 281 #define MFI_MAX_PD_CHANNELS 2 282 #define MFI_MAX_PD_ARRAY 32 283 #define MFI_MAX_LD_CHANNELS 2 284 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 285 #define MFI_MAX_CHANNEL_DEVS 128 286 #define MFI_DEFAULT_ID -1 287 #define MFI_MAX_LUN 8 288 #define MFI_MAX_LD 64 289 #define MFI_MAX_SPAN 8 290 #define MFI_MAX_ARRAY_DEDICATED 16 291 #define MFI_MAX_PD 256 292 293 /* sense buffer */ 294 struct mfi_sense { 295 uint8_t mse_data[MFI_SENSE_SIZE]; 296 } __packed; 297 298 /* scatter gather elements */ 299 struct mfi_sg32 { 300 uint32_t addr; 301 uint32_t len; 302 } __packed; 303 304 struct mfi_sg64 { 305 uint64_t addr; 306 uint32_t len; 307 } __packed; 308 309 struct mfi_sg_skinny { 310 uint64_t addr; 311 uint32_t len; 312 uint32_t flag; 313 } __packed; 314 315 union mfi_sgl { 316 struct mfi_sg32 sg32[1]; 317 struct mfi_sg64 sg64[1]; 318 struct mfi_sg_skinny sg_skinny[1]; 319 } __packed; 320 321 /* message frame */ 322 struct mfi_frame_header { 323 uint8_t mfh_cmd; 324 uint8_t mfh_sense_len; 325 uint8_t mfh_cmd_status; 326 uint8_t mfh_scsi_status; 327 uint8_t mfh_target_id; 328 uint8_t mfh_lun_id; 329 uint8_t mfh_cdb_len; 330 uint8_t mfh_sg_count; 331 uint32_t mfh_context; 332 uint32_t mfh_pad0; 333 uint16_t mfh_flags; 334 uint16_t mfh_timeout; 335 uint32_t mfh_data_len; 336 } __packed; 337 338 union mfi_sgl_frame { 339 struct mfi_sg32 sge32[8]; 340 struct mfi_sg64 sge64[5]; 341 342 } __packed; 343 344 struct mfi_init_frame { 345 struct mfi_frame_header mif_header; 346 uint64_t mif_qinfo_new_addr; 347 uint64_t mif_qinfo_old_addr; 348 uint32_t mif_reserved[6]; 349 } __packed; 350 351 /* queue init structure */ 352 struct mfi_init_qinfo { 353 uint32_t miq_flags; 354 uint32_t miq_rq_entries; 355 uint64_t miq_rq_addr; 356 uint64_t miq_pi_addr; 357 uint64_t miq_ci_addr; 358 } __packed; 359 360 #define MFI_IO_FRAME_SIZE 40 361 struct mfi_io_frame { 362 struct mfi_frame_header mif_header; 363 uint64_t mif_sense_addr; 364 uint64_t mif_lba; 365 union mfi_sgl mif_sgl; 366 } __packed; 367 368 #define MFI_PASS_FRAME_SIZE 48 369 struct mfi_pass_frame { 370 struct mfi_frame_header mpf_header; 371 uint64_t mpf_sense_addr; 372 uint8_t mpf_cdb[16]; 373 union mfi_sgl mpf_sgl; 374 } __packed; 375 376 #define MFI_DCMD_FRAME_SIZE 40 377 struct mfi_dcmd_frame { 378 struct mfi_frame_header mdf_header; 379 uint32_t mdf_opcode; 380 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 381 union mfi_sgl mdf_sgl; 382 } __packed; 383 384 struct mfi_abort_frame { 385 struct mfi_frame_header maf_header; 386 uint32_t maf_abort_context; 387 uint32_t maf_pad; 388 uint64_t maf_abort_mfi_addr; 389 uint32_t maf_reserved[6]; 390 } __packed; 391 392 struct mfi_smp_frame { 393 struct mfi_frame_header msf_header; 394 uint64_t msf_sas_addr; 395 union { 396 struct mfi_sg32 sg32[2]; 397 struct mfi_sg64 sg64[2]; 398 } msf_sgl; 399 } __packed; 400 401 struct mfi_stp_frame { 402 struct mfi_frame_header msf_header; 403 uint16_t msf_fis[10]; 404 uint32_t msf_stp_flags; 405 union { 406 struct mfi_sg32 sg32[2]; 407 struct mfi_sg64 sg64[2]; 408 } msf_sgl; 409 } __packed; 410 411 union mfi_frame { 412 struct mfi_frame_header mfr_header; 413 struct mfi_init_frame mfr_init; 414 struct mfi_io_frame mfr_io; 415 struct mfi_pass_frame mfr_pass; 416 struct mfi_dcmd_frame mfr_dcmd; 417 struct mfi_abort_frame mfr_abort; 418 struct mfi_smp_frame mfr_smp; 419 struct mfi_stp_frame mfr_stp; 420 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 421 }; 422 423 union mfi_evt_class_locale { 424 struct { 425 uint16_t locale; 426 uint8_t reserved; 427 int8_t class; 428 } __packed mec_members; 429 430 uint32_t mec_word; 431 } __packed; 432 433 struct mfi_evt_log_info { 434 uint32_t mel_newest_seq_num; 435 uint32_t mel_oldest_seq_num; 436 uint32_t mel_clear_seq_num; 437 uint32_t mel_shutdown_seq_num; 438 uint32_t mel_boot_seq_num; 439 } __packed; 440 441 struct mfi_progress { 442 uint16_t mp_progress; 443 uint16_t mp_elapsed_seconds; 444 } __packed; 445 446 struct mfi_evtarg_ld { 447 uint16_t mel_target_id; 448 uint8_t mel_ld_index; 449 uint8_t mel_reserved; 450 } __packed; 451 452 struct mfi_evtarg_pd { 453 uint16_t mep_device_id; 454 uint8_t mep_encl_index; 455 uint8_t mep_slot_number; 456 } __packed; 457 458 struct mfi_evt_detail { 459 uint32_t med_seq_num; 460 uint32_t med_time_stamp; 461 uint32_t med_code; 462 union mfi_evt_class_locale med_cl; 463 uint8_t med_arg_type; 464 uint8_t med_reserved1[15]; 465 466 union { 467 struct { 468 struct mfi_evtarg_pd pd; 469 uint8_t cdb_length; 470 uint8_t sense_length; 471 uint8_t reserved[2]; 472 uint8_t cdb[16]; 473 uint8_t sense[64]; 474 } __packed cdb_sense; 475 476 struct mfi_evtarg_ld ld; 477 478 struct { 479 struct mfi_evtarg_ld ld; 480 uint64_t count; 481 } __packed ld_count; 482 483 struct { 484 uint64_t lba; 485 struct mfi_evtarg_ld ld; 486 } __packed ld_lba; 487 488 struct { 489 struct mfi_evtarg_ld ld; 490 uint32_t prev_owner; 491 uint32_t new_owner; 492 } __packed ld_owner; 493 494 struct { 495 uint64_t ld_lba; 496 uint64_t pd_lba; 497 struct mfi_evtarg_ld ld; 498 struct mfi_evtarg_pd pd; 499 } __packed ld_lba_pd_lba; 500 501 struct { 502 struct mfi_evtarg_ld ld; 503 struct mfi_progress prog; 504 } __packed ld_prog; 505 506 struct { 507 struct mfi_evtarg_ld ld; 508 uint32_t prev_state; 509 uint32_t new_state; 510 } __packed ld_state; 511 512 struct { 513 uint64_t strip; 514 struct mfi_evtarg_ld ld; 515 } __packed ld_strip; 516 517 struct mfi_evtarg_pd pd; 518 519 struct { 520 struct mfi_evtarg_pd pd; 521 uint32_t err; 522 } __packed pd_err; 523 524 struct { 525 uint64_t lba; 526 struct mfi_evtarg_pd pd; 527 } __packed pd_lba; 528 529 struct { 530 uint64_t lba; 531 struct mfi_evtarg_pd pd; 532 struct mfi_evtarg_ld ld; 533 } __packed pd_lba_ld; 534 535 struct { 536 struct mfi_evtarg_pd pd; 537 struct mfi_progress prog; 538 } __packed pd_prog; 539 540 struct { 541 struct mfi_evtarg_pd pd; 542 uint32_t prev_state; 543 uint32_t new_state; 544 } __packed pd_state; 545 546 struct { 547 uint16_t vendor_id; 548 uint16_t device_id; 549 uint16_t subvendor_id; 550 uint16_t subdevice_id; 551 } __packed pci; 552 553 uint32_t rate; 554 char str[96]; 555 556 struct { 557 uint32_t rtc; 558 uint32_t elapsed_seconds; 559 } __packed time; 560 561 struct { 562 uint32_t ecar; 563 uint32_t elog; 564 char str[64]; 565 } __packed ecc; 566 567 uint8_t b[96]; 568 uint16_t s[48]; 569 uint32_t w[24]; 570 uint64_t d[12]; 571 } args; 572 573 char med_description[128]; 574 } __packed; 575 576 /* controller properties from mfi_ctrl_info */ 577 struct mfi_ctrl_props { 578 uint16_t mcp_seq_num; 579 uint16_t mcp_pred_fail_poll_interval; 580 uint16_t mcp_intr_throttle_cnt; 581 uint16_t mcp_intr_throttle_timeout; 582 uint8_t mcp_rebuild_rate; 583 uint8_t mcp_patrol_read_rate; 584 uint8_t mcp_bgi_rate; 585 uint8_t mcp_cc_rate; 586 uint8_t mcp_recon_rate; 587 uint8_t mcp_cache_flush_interval; 588 uint8_t mcp_spinup_drv_cnt; 589 uint8_t mcp_spinup_delay; 590 uint8_t mcp_cluster_enable; 591 uint8_t mcp_coercion_mode; 592 uint8_t mcp_alarm_enable; 593 uint8_t mcp_disable_auto_rebuild; 594 uint8_t mcp_disable_battery_warn; 595 uint8_t mcp_ecc_bucket_size; 596 uint16_t mcp_ecc_bucket_leak_rate; 597 uint8_t mcp_restore_hotspare_on_insertion; 598 uint8_t mcp_expose_encl_devices; 599 uint8_t mcp_reserved[38]; 600 } __packed; 601 602 /* pci info */ 603 struct mfi_info_pci { 604 uint16_t mip_vendor; 605 uint16_t mip_device; 606 uint16_t mip_subvendor; 607 uint16_t mip_subdevice; 608 uint8_t mip_reserved[24]; 609 } __packed; 610 611 /* host interface infor */ 612 struct mfi_info_host { 613 uint8_t mih_type; 614 #define MFI_INFO_HOST_PCIX 0x01 615 #define MFI_INFO_HOST_PCIE 0x02 616 #define MFI_INFO_HOST_ISCSI 0x04 617 #define MFI_INFO_HOST_SAS3G 0x08 618 uint8_t mih_reserved[6]; 619 uint8_t mih_port_count; 620 uint64_t mih_port_addr[8]; 621 } __packed; 622 623 /* device interface info */ 624 struct mfi_info_device { 625 uint8_t mid_type; 626 #define MFI_INFO_DEV_SPI 0x01 627 #define MFI_INFO_DEV_SAS3G 0x02 628 #define MFI_INFO_DEV_SATA1 0x04 629 #define MFI_INFO_DEV_SATA3G 0x08 630 uint8_t mid_reserved[6]; 631 uint8_t mid_port_count; 632 uint64_t mid_port_addr[8]; 633 } __packed; 634 635 /* firmware component info */ 636 struct mfi_info_component { 637 char mic_name[8]; 638 char mic_version[32]; 639 char mic_build_date[16]; 640 char mic_build_time[16]; 641 } __packed; 642 643 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 644 struct mfi_ctrl_info { 645 struct mfi_info_pci mci_pci; 646 struct mfi_info_host mci_host; 647 struct mfi_info_device mci_device; 648 649 /* Firmware components that are present and active. */ 650 uint32_t mci_image_check_word; 651 uint32_t mci_image_component_count; 652 struct mfi_info_component mci_image_component[8]; 653 654 /* Firmware components that have been flashed but are inactive */ 655 uint32_t mci_pending_image_component_count; 656 struct mfi_info_component mci_pending_image_component[8]; 657 658 uint8_t mci_max_arms; 659 uint8_t mci_max_spans; 660 uint8_t mci_max_arrays; 661 uint8_t mci_max_lds; 662 char mci_product_name[80]; 663 char mci_serial_number[32]; 664 uint32_t mci_hw_present; 665 #define MFI_INFO_HW_BBU 0x01 666 #define MFI_INFO_HW_ALARM 0x02 667 #define MFI_INFO_HW_NVRAM 0x04 668 #define MFI_INFO_HW_UART 0x08 669 #define MFI_INFO_HW_FMT "\020" "\001BBU" "\002ALARM" "\003NVRAM" \ 670 "\004UART" 671 672 uint32_t mci_current_fw_time; 673 uint16_t mci_max_cmds; 674 uint16_t mci_max_sg_elements; 675 uint32_t mci_max_request_size; 676 uint16_t mci_lds_present; 677 uint16_t mci_lds_degraded; 678 uint16_t mci_lds_offline; 679 uint16_t mci_pd_present; 680 uint16_t mci_pd_disks_present; 681 uint16_t mci_pd_disks_pred_failure; 682 uint16_t mci_pd_disks_failed; 683 uint16_t mci_nvram_size; 684 uint16_t mci_memory_size; 685 uint16_t mci_flash_size; 686 uint16_t mci_ram_correctable_errors; 687 uint16_t mci_ram_uncorrectable_errors; 688 uint8_t mci_cluster_allowed; 689 uint8_t mci_cluster_active; 690 uint16_t mci_max_strips_per_io; 691 692 uint32_t mci_raid_levels; 693 #define MFI_INFO_RAID_0 0x01 694 #define MFI_INFO_RAID_1 0x02 695 #define MFI_INFO_RAID_5 0x04 696 #define MFI_INFO_RAID_1E 0x08 697 #define MFI_INFO_RAID_6 0x10 698 699 uint32_t mci_adapter_ops; 700 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 701 #define MFI_INFO_AOPS_CC_RATE 0x0002 702 #define MFI_INFO_AOPS_BGI_RATE 0x0004 703 #define MFI_INFO_AOPS_RECON_RATE 0x0008 704 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 705 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 706 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 707 #define MFI_INFO_AOPS_BBU 0x0080 708 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 709 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 710 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 711 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 712 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 713 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 714 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 715 #define MFI_INFO_AOPS_FMT "\020" "\001RBLD_RATE" "\002CC_RATE" \ 716 "\003BGI_RATE" "\004RECON_RATE" \ 717 "\005PATROL_RATE" "\006ALARM_CONTROL" \ 718 "\007CLUSTER_SUPPORT" "\010BBU" \ 719 "\011SPANNING_ALLOWED" \ 720 "\012DEDICATED_SPARES" \ 721 "\013REVERTIBLE_SPARES" \ 722 "\014FOREIGN_IMPORT" "\015SELF_DIAGNOSTIC" \ 723 "\016MIXED_ARRAY" "\017GLOBAL_SPARES" 724 725 uint32_t mci_ld_ops; 726 #define MFI_INFO_LDOPS_READ_POLICY 0x01 727 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 728 #define MFI_INFO_LDOPS_IO_POLICY 0x04 729 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 730 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 731 732 struct { 733 uint8_t min; 734 uint8_t max; 735 uint8_t reserved[2]; 736 } __packed mci_stripe_sz_ops; 737 738 uint32_t mci_pd_ops; 739 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 740 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 741 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 742 743 uint32_t mci_pd_mix_support; 744 #define MFI_INFO_PDMIX_SAS 0x01 745 #define MFI_INFO_PDMIX_SATA 0x02 746 #define MFI_INFO_PDMIX_ENCL 0x04 747 #define MFI_INFO_PDMIX_LD 0x08 748 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 749 750 uint8_t mci_ecc_bucket_count; 751 uint8_t mci_reserved2[11]; 752 struct mfi_ctrl_props mci_properties; 753 char mci_package_version[0x60]; 754 uint8_t mci_pad[0x800 - 0x6a0]; 755 } __packed; 756 757 /* logical disk info from MR_DCMD_LD_GET_LIST */ 758 struct mfi_ld { 759 uint8_t mld_target; 760 uint8_t mld_res; 761 uint16_t mld_seq; 762 } __packed; 763 764 struct mfi_ld_list { 765 uint32_t mll_no_ld; 766 uint32_t mll_res; 767 struct { 768 struct mfi_ld mll_ld; 769 uint8_t mll_state; 770 #define MFI_LD_OFFLINE 0x00 771 #define MFI_LD_PART_DEGRADED 0x01 772 #define MFI_LD_DEGRADED 0x02 773 #define MFI_LD_ONLINE 0x03 774 uint8_t mll_res2; 775 uint8_t mll_res3; 776 uint8_t mll_res4; 777 uint64_t mll_size; 778 } mll_list[MFI_MAX_LD]; 779 } __packed; 780 781 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 782 struct mfi_ld_prop { 783 struct mfi_ld mlp_ld; 784 char mlp_name[16]; 785 uint8_t mlp_cache_policy; 786 uint8_t mlp_acces_policy; 787 uint8_t mlp_diskcache_policy; 788 uint8_t mlp_cur_cache_policy; 789 uint8_t mlp_disable_bgi; 790 uint8_t mlp_res[7]; 791 } __packed; 792 793 struct mfi_ld_parm { 794 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 795 #define MFI_DDF_PRL_RAID0 0x00 796 #define MFI_DDF_PRL_RAID1 0x01 797 #define MFI_DDF_PRL_RAID3 0x03 798 #define MFI_DDF_PRL_RAID4 0x04 799 #define MFI_DDF_PRL_RAID5 0x05 800 #define MFI_DDF_PRL_RAID1E 0x11 801 #define MFI_DDF_PRL_JBOD 0x0f 802 #define MFI_DDF_PRL_CONCAT 0x1f 803 #define MFI_DDF_PRL_RAID5E 0x15 804 #define MFI_DDF_PRL_RAID5EE 0x25 805 #define MFI_DDF_PRL_RAID6 0x16 806 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 807 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 808 #define MFI_DDF_SRL_STRIPED 0x00 809 #define MFI_DDF_SRL_MIRRORED 0x01 810 #define MFI_DDF_SRL_CONCAT 0x02 811 #define MFI_DDF_SRL_SPANNED 0x03 812 uint8_t mpa_stripe_size; 813 uint8_t mpa_no_drv_per_span; 814 uint8_t mpa_span_depth; 815 uint8_t mpa_state; 816 uint8_t mpa_init_state; 817 uint8_t mpa_res[24]; 818 } __packed; 819 820 struct mfi_ld_span { 821 uint64_t mls_start_block; 822 uint64_t mls_no_blocks; 823 uint16_t mls_index; 824 uint8_t mls_res[6]; 825 } __packed; 826 827 struct mfi_ld_cfg { 828 struct mfi_ld_prop mlc_prop; 829 struct mfi_ld_parm mlc_parm; 830 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 831 } __packed; 832 833 struct mfi_ld_progress { 834 uint32_t mlp_in_prog; 835 #define MFI_LD_PROG_CC 0x01 836 #define MFI_LD_PROG_BGI 0x02 837 #define MFI_LD_PROG_FGI 0x04 838 #define MFI_LD_PROG_RECONSTRUCT 0x08 839 struct mfi_progress mlp_cc; 840 struct mfi_progress mlp_bgi; 841 struct mfi_progress mlp_fgi; 842 struct mfi_progress mlp_reconstruct; 843 struct mfi_progress mlp_res[4]; 844 } __packed; 845 846 struct mfi_ld_details { 847 struct mfi_ld_cfg mld_cfg; 848 uint64_t mld_size; 849 struct mfi_ld_progress mld_progress; 850 uint16_t mld_clust_own_id; 851 uint8_t mld_res1; 852 uint8_t mld_res2; 853 uint8_t mld_inq_page83[64]; 854 uint8_t mld_res[16]; 855 } __packed; 856 857 /* physical disk info from MR_DCMD_PD_GET_LIST */ 858 struct mfi_pd_address { 859 uint16_t mpa_pd_id; 860 uint16_t mpa_enc_id; 861 uint8_t mpa_enc_index; 862 uint8_t mpa_enc_slot; 863 uint8_t mpa_scsi_type; 864 uint8_t mpa_port; 865 uint64_t mpa_sas_address[2]; 866 } __packed; 867 868 struct mfi_pd_list { 869 uint32_t mpl_size; 870 uint32_t mpl_no_pd; 871 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 872 } __packed; 873 874 struct mfi_pd { 875 uint16_t mfp_id; 876 uint16_t mfp_seq; 877 } __packed; 878 879 struct mfi_pd_progress { 880 uint32_t mfp_in_prog; 881 #define MFI_PD_PROG_RBLD 0x01 882 #define MFI_PD_PROG_PR 0x02 883 #define MFI_PD_PROG_CLEAR 0x04 884 struct mfi_progress mfp_rebuild; 885 struct mfi_progress mfp_patrol_read; 886 struct mfi_progress mfp_clear; 887 struct mfi_progress mfp_res[4]; 888 } __packed; 889 890 struct mfi_pd_details { 891 struct mfi_pd mpd_pd; 892 uint8_t mpd_inq_data[96]; 893 uint8_t mpd_inq_page83[64]; 894 uint8_t mpd_no_support; 895 uint8_t mpd_scsi_type; 896 uint8_t mpd_port; 897 uint8_t mpd_speed; 898 uint32_t mpd_mediaerr_cnt; 899 uint32_t mpd_othererr_cnt; 900 uint32_t mpd_predfail_cnt; 901 uint32_t mpd_last_pred_event; 902 uint16_t mpd_fw_state; 903 uint8_t mpd_rdy_for_remove; 904 uint8_t mpd_link_speed; 905 uint32_t mpd_ddf_state; 906 #define MFI_DDF_GUID_FORCED 0x01 907 #define MFI_DDF_PART_OF_VD 0x02 908 #define MFI_DDF_GLOB_HOTSPARE 0x04 909 #define MFI_DDF_HOTSPARE 0x08 910 #define MFI_DDF_FOREIGN 0x10 911 #define MFI_DDF_TYPE_MASK 0xf000 912 #define MFI_DDF_TYPE_UNKNOWN 0x0000 913 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 914 #define MFI_DDF_TYPE_SAS 0x2000 915 #define MFI_DDF_TYPE_SATA 0x3000 916 #define MFI_DDF_TYPE_FC 0x4000 917 struct { 918 uint8_t mpp_cnt; 919 uint8_t mpp_severed; 920 uint8_t mpp_connector_idx[2]; 921 uint8_t mpp_res[4]; 922 uint64_t mpp_sas_addr[2]; 923 uint8_t mpp_res2[16]; 924 } __packed mpd_path; 925 uint64_t mpd_size; 926 uint64_t mpd_no_coerce_size; 927 uint64_t mpd_coerce_size; 928 uint16_t mpd_enc_id; 929 uint8_t mpd_enc_idx; 930 uint8_t mpd_enc_slot; 931 struct mfi_pd_progress mpd_progress; 932 uint8_t mpd_bblock_full; 933 uint8_t mpd_unusable; 934 uint8_t mpd_inq_page83_ext[64]; 935 uint8_t mpd_power_state; /* XXX */ 936 uint8_t mpd_enc_pos; 937 uint32_t mpd_allowed_ops; 938 #define MFI_PD_A_ONLINE (1<<0) 939 #define MFI_PD_A_OFFLINE (1<<1) 940 #define MFI_PD_A_FAILED (1<<2) 941 #define MFI_PD_A_BAD (1<<3) 942 #define MFI_PD_A_UNCONFIG (1<<4) 943 #define MFI_PD_A_HOTSPARE (1<<5) 944 #define MFI_PD_A_REMOVEHOTSPARE (1<<6) 945 #define MFI_PD_A_REPLACEMISSING (1<<7) 946 #define MFI_PD_A_MARKMISSING (1<<8) 947 #define MFI_PD_A_STARTREBUILD (1<<9) 948 #define MFI_PD_A_STOPREBUILD (1<<10) 949 #define MFI_PD_A_BLINK (1<<11) 950 #define MFI_PD_A_CLEAR (1<<12) 951 #define MFI_PD_A_FOREIGNIMPORNOTALLOWED (1<<13) 952 #define MFI_PD_A_STARTCOPYBACK (1<<14) 953 #define MFI_PD_A_STOPCOPYBACK (1<<15) 954 #define MFI_PD_A_FWDOWNLOADDNOTALLOWED (1<<16) 955 #define MFI_PD_A_REPROVISION (1<<17) 956 uint16_t mpd_copyback_partner_id; 957 uint16_t mpd_enc_partner_devid; 958 uint16_t mpd_security; 959 #define MFI_PD_FDE_CAPABLE (1<<0) 960 #define MFI_PD_FDE_ENABLED (1<<1) 961 #define MFI_PD_FDE_SECURED (1<<2) 962 #define MFI_PD_FDE_LOCKED (1<<3) 963 #define MFI_PD_FDE_FOREIGNLOCK (1<<4) 964 uint8_t mpd_media; 965 uint8_t mpd_res[141]; /* size is 512 */ 966 } __packed; 967 968 struct mfi_pd_allowedops_list { 969 uint32_t mpo_no_entries; 970 uint32_t mpo_res; 971 uint32_t mpo_allowedops_list[MFI_MAX_PD]; 972 } __packed; 973 974 /* array configuration from MR_DCMD_CONF_GET */ 975 struct mfi_array { 976 uint64_t mar_smallest_pd; 977 uint8_t mar_no_disk; 978 uint8_t mar_res1; 979 uint16_t mar_array_ref; 980 uint8_t mar_res2[20]; 981 struct { 982 struct mfi_pd mar_pd; 983 uint16_t mar_pd_state; 984 #define MFI_PD_UNCONFIG_GOOD 0x00 985 #define MFI_PD_UNCONFIG_BAD 0x01 986 #define MFI_PD_HOTSPARE 0x02 987 #define MFI_PD_OFFLINE 0x10 988 #define MFI_PD_FAILED 0x11 989 #define MFI_PD_REBUILD 0x14 990 #define MFI_PD_ONLINE 0x18 991 #define MFI_PD_COPYBACK 0x20 992 #define MFI_PD_SYSTEM 0x40 993 uint8_t mar_enc_pd; 994 uint8_t mar_enc_slot; 995 } pd[MFI_MAX_PD_ARRAY]; 996 } __packed; 997 998 struct mfi_hotspare { 999 struct mfi_pd mhs_pd; 1000 uint8_t mhs_type; 1001 #define MFI_PD_HS_DEDICATED 0x01 1002 #define MFI_PD_HS_REVERTIBLE 0x02 1003 #define MFI_PD_HS_ENC_AFFINITY 0x04 1004 uint8_t mhs_res[2]; 1005 uint8_t mhs_array_max; 1006 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1007 } __packed; 1008 1009 struct mfi_conf { 1010 uint32_t mfc_size; 1011 uint16_t mfc_no_array; 1012 uint16_t mfc_array_size; 1013 uint16_t mfc_no_ld; 1014 uint16_t mfc_ld_size; 1015 uint16_t mfc_no_hs; 1016 uint16_t mfc_hs_size; 1017 uint8_t mfc_res[16]; 1018 /* 1019 * XXX this is a ridiculous hack and does not reflect reality 1020 * Structures are actually indexed and therefore need pointer 1021 * math to reach. We need the size of this structure first so 1022 * call it with the size of this structure and then use the returned 1023 * values to allocate memory and do the transfer of the whole structure 1024 * then calculate pointers to each of these structures. 1025 */ 1026 struct mfi_array mfc_array[1]; 1027 struct mfi_ld_cfg mfc_ld[1]; 1028 struct mfi_hotspare mfc_hs[1]; 1029 } __packed; 1030 1031 struct mfi_bbu_capacity_info { 1032 uint16_t relative_charge; 1033 uint16_t absolute_charge; 1034 uint16_t remaining_capacity; 1035 uint16_t full_charge_capacity; 1036 uint16_t run_time_to_empty; 1037 uint16_t average_time_to_empty; 1038 uint16_t average_time_to_full; 1039 uint16_t cycle_count; 1040 uint16_t max_error; 1041 uint16_t remaining_capacity_alarm; 1042 uint16_t remaining_time_alarm; 1043 uint8_t reserved[26]; 1044 } __packed; 1045 1046 struct mfi_bbu_design_info { 1047 uint32_t mfg_date; 1048 uint16_t design_capacity; 1049 uint16_t design_voltage; 1050 uint16_t spec_info; 1051 uint16_t serial_number; 1052 uint16_t pack_stat_config; 1053 uint8_t mfg_name[12]; 1054 uint8_t device_name[8]; 1055 uint8_t device_chemistry[8]; 1056 uint8_t mfg_data[8]; 1057 uint8_t reserved[17]; 1058 } __packed; 1059 1060 struct mfi_ibbu_state { 1061 uint16_t gas_guage_status; 1062 uint16_t relative_charge; 1063 uint16_t charger_system_state; 1064 uint16_t charger_system_ctrl; 1065 uint16_t charging_current; 1066 uint16_t absolute_charge; 1067 uint16_t max_error; 1068 uint8_t reserved[18]; 1069 } __packed; 1070 1071 struct mfi_bbu_state { 1072 uint16_t gas_guage_status; 1073 uint16_t relative_charge; 1074 uint16_t charger_status; 1075 uint16_t remaining_capacity; 1076 uint16_t full_charge_capacity; 1077 uint8_t is_SOH_good; 1078 uint8_t reserved[21]; 1079 } __packed; 1080 1081 struct mfi_bbu_properties { 1082 uint32_t auto_learn_period; 1083 uint32_t next_learn_time; 1084 uint8_t learn_delay_interval; 1085 uint8_t auto_learn_mode; 1086 uint8_t bbu_mode; 1087 uint8_t reserved[21]; 1088 } __packed; 1089 1090 union mfi_bbu_status_detail { 1091 struct mfi_ibbu_state ibbu; 1092 struct mfi_bbu_state bbu; 1093 }; 1094 1095 struct mfi_bbu_status { 1096 uint8_t battery_type; 1097 #define MFI_BBU_TYPE_NONE 0 1098 #define MFI_BBU_TYPE_IBBU 1 1099 #define MFI_BBU_TYPE_BBU 2 1100 uint8_t reserved; 1101 uint16_t voltage; /* mV */ 1102 int16_t current; /* mA */ 1103 uint16_t temperature; /* degC */ 1104 uint32_t fw_status; 1105 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1106 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1107 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1108 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1109 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1110 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1111 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1112 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1113 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1114 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1115 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1116 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1117 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1118 #define MFI_BBU_STATE_FMT "\020" \ 1119 "\001PACK_MISSING" \ 1120 "\002VOLTAGE_LOW" \ 1121 "\003TEMP_HIGH" \ 1122 "\004CHARGE_ACTIVE" \ 1123 "\005DISCHARGE_ACTIVE" \ 1124 "\006LEARN_CYC_REQ" \ 1125 "\007LEARN_CYC_ACTIVE" \ 1126 "\010LEARN_CYC_FAIL" \ 1127 "\011LEARN_CYC_TIMEOUT" \ 1128 "\012I2C_ERR_DETECT" \ 1129 "\013REPLACE_PACK" \ 1130 "\014CAPACITY_LOW" \ 1131 "\015LEARN_REQUIRED" 1132 #define MFI_BBU_STATE_BAD_IBBU ( \ 1133 MFI_BBU_STATE_PACK_MISSING | \ 1134 MFI_BBU_STATE_VOLTAGE_LOW | \ 1135 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1136 MFI_BBU_STATE_LEARN_CYC_REQ | \ 1137 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1138 MFI_BBU_STATE_REPLACE_PACK | \ 1139 MFI_BBU_STATE_CAPACITY_LOW) 1140 #define MFI_BBU_STATE_BAD_BBU ( \ 1141 MFI_BBU_STATE_PACK_MISSING | \ 1142 MFI_BBU_STATE_REPLACE_PACK | \ 1143 MFI_BBU_STATE_CAPACITY_LOW) 1144 1145 uint8_t pad[20]; 1146 union mfi_bbu_status_detail detail; 1147 } __packed; 1148 1149 struct mfi_pr_status { 1150 uint32_t num_iteration; 1151 uint8_t state; 1152 uint8_t num_pd_done; 1153 uint8_t reserved[10]; 1154 } __packed; 1155 1156 struct mfi_pr_properties { 1157 uint8_t op_mode; 1158 uint8_t max_pd; 1159 uint8_t reserved; 1160 uint8_t exclude_ld_count; 1161 uint16_t excluded_ld[MFI_MAX_LD]; 1162 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1163 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1164 uint32_t next_exec; 1165 uint32_t exec_freq; 1166 uint32_t clear_freq; 1167 } __packed; 1168