1 /* $OpenBSD: gem.c,v 1.106 2014/08/27 05:54:15 dlg Exp $ */ 2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/timeout.h> 42 #include <sys/mbuf.h> 43 #include <sys/syslog.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 60 #if NBPFILTER > 0 61 #include <net/bpf.h> 62 #endif 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <dev/mii/mii_bitbang.h> 70 71 #include <dev/ic/gemreg.h> 72 #include <dev/ic/gemvar.h> 73 74 #define TRIES 10000 75 76 struct cfdriver gem_cd = { 77 NULL, "gem", DV_IFNET 78 }; 79 80 void gem_start(struct ifnet *); 81 void gem_stop(struct ifnet *, int); 82 int gem_ioctl(struct ifnet *, u_long, caddr_t); 83 void gem_tick(void *); 84 void gem_watchdog(struct ifnet *); 85 int gem_init(struct ifnet *); 86 void gem_init_regs(struct gem_softc *); 87 int gem_ringsize(int); 88 int gem_meminit(struct gem_softc *); 89 void gem_mifinit(struct gem_softc *); 90 int gem_bitwait(struct gem_softc *, bus_space_handle_t, int, 91 u_int32_t, u_int32_t); 92 void gem_reset(struct gem_softc *); 93 int gem_reset_rx(struct gem_softc *); 94 int gem_reset_tx(struct gem_softc *); 95 int gem_disable_rx(struct gem_softc *); 96 int gem_disable_tx(struct gem_softc *); 97 void gem_rx_watchdog(void *); 98 void gem_rxdrain(struct gem_softc *); 99 void gem_fill_rx_ring(struct gem_softc *); 100 int gem_add_rxbuf(struct gem_softc *, int idx); 101 void gem_iff(struct gem_softc *); 102 103 /* MII methods & callbacks */ 104 int gem_mii_readreg(struct device *, int, int); 105 void gem_mii_writereg(struct device *, int, int, int); 106 void gem_mii_statchg(struct device *); 107 int gem_pcs_readreg(struct device *, int, int); 108 void gem_pcs_writereg(struct device *, int, int, int); 109 110 int gem_mediachange(struct ifnet *); 111 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 112 113 int gem_eint(struct gem_softc *, u_int); 114 int gem_rint(struct gem_softc *); 115 int gem_tint(struct gem_softc *, u_int32_t); 116 int gem_pint(struct gem_softc *); 117 118 #ifdef GEM_DEBUG 119 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 120 printf x 121 #else 122 #define DPRINTF(sc, x) /* nothing */ 123 #endif 124 125 /* 126 * Attach a Gem interface to the system. 127 */ 128 void 129 gem_config(struct gem_softc *sc) 130 { 131 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 132 struct mii_data *mii = &sc->sc_mii; 133 struct mii_softc *child; 134 int i, error, mii_flags, phyad; 135 struct ifmedia_entry *ifm; 136 137 /* Make sure the chip is stopped. */ 138 ifp->if_softc = sc; 139 gem_reset(sc); 140 141 /* 142 * Allocate the control data structures, and create and load the 143 * DMA map for it. 144 */ 145 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 146 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 147 1, &sc->sc_cdnseg, 0)) != 0) { 148 printf("\n%s: unable to allocate control data, error = %d\n", 149 sc->sc_dev.dv_xname, error); 150 goto fail_0; 151 } 152 153 /* XXX should map this in with correct endianness */ 154 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 155 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 156 BUS_DMA_COHERENT)) != 0) { 157 printf("\n%s: unable to map control data, error = %d\n", 158 sc->sc_dev.dv_xname, error); 159 goto fail_1; 160 } 161 162 if ((error = bus_dmamap_create(sc->sc_dmatag, 163 sizeof(struct gem_control_data), 1, 164 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 165 printf("\n%s: unable to create control data DMA map, " 166 "error = %d\n", sc->sc_dev.dv_xname, error); 167 goto fail_2; 168 } 169 170 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 171 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 172 0)) != 0) { 173 printf("\n%s: unable to load control data DMA map, error = %d\n", 174 sc->sc_dev.dv_xname, error); 175 goto fail_3; 176 } 177 178 /* 179 * Create the receive buffer DMA maps. 180 */ 181 for (i = 0; i < GEM_NRXDESC; i++) { 182 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 183 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 184 printf("\n%s: unable to create rx DMA map %d, " 185 "error = %d\n", sc->sc_dev.dv_xname, i, error); 186 goto fail_5; 187 } 188 sc->sc_rxsoft[i].rxs_mbuf = NULL; 189 } 190 /* 191 * Create the transmit buffer DMA maps. 192 */ 193 for (i = 0; i < GEM_NTXDESC; i++) { 194 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 195 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 196 &sc->sc_txd[i].sd_map)) != 0) { 197 printf("\n%s: unable to create tx DMA map %d, " 198 "error = %d\n", sc->sc_dev.dv_xname, i, error); 199 goto fail_6; 200 } 201 sc->sc_txd[i].sd_mbuf = NULL; 202 } 203 204 /* 205 * From this point forward, the attachment cannot fail. A failure 206 * before this point releases all resources that may have been 207 * allocated. 208 */ 209 210 /* Announce ourselves. */ 211 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 212 213 /* Get RX FIFO size */ 214 sc->sc_rxfifosize = 64 * 215 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_FIFO_SIZE); 216 217 /* Initialize ifnet structure. */ 218 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 219 ifp->if_softc = sc; 220 ifp->if_flags = 221 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 222 ifp->if_start = gem_start; 223 ifp->if_ioctl = gem_ioctl; 224 ifp->if_watchdog = gem_watchdog; 225 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_NTXDESC - 1); 226 IFQ_SET_READY(&ifp->if_snd); 227 228 ifp->if_capabilities = IFCAP_VLAN_MTU; 229 230 /* Initialize ifmedia structures and MII info */ 231 mii->mii_ifp = ifp; 232 mii->mii_readreg = gem_mii_readreg; 233 mii->mii_writereg = gem_mii_writereg; 234 mii->mii_statchg = gem_mii_statchg; 235 236 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 237 238 /* Bad things will happen if we touch this register on ERI. */ 239 if (sc->sc_variant != GEM_SUN_ERI) 240 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 241 GEM_MII_DATAPATH_MODE, 0); 242 243 gem_mifinit(sc); 244 245 mii_flags = MIIF_DOPAUSE; 246 247 /* 248 * Look for an external PHY. 249 */ 250 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 251 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 252 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 253 GEM_MIF_CONFIG, sc->sc_mif_config); 254 255 switch (sc->sc_variant) { 256 case GEM_SUN_ERI: 257 phyad = GEM_PHYAD_EXTERNAL; 258 break; 259 default: 260 phyad = MII_PHY_ANY; 261 break; 262 } 263 264 mii_attach(&sc->sc_dev, mii, 0xffffffff, phyad, 265 MII_OFFSET_ANY, mii_flags); 266 } 267 268 /* 269 * Fall back on an internal PHY if no external PHY was found. 270 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 271 * trusted when the firmware has powered down the chip 272 */ 273 child = LIST_FIRST(&mii->mii_phys); 274 if (child == NULL && 275 (sc->sc_mif_config & GEM_MIF_CONFIG_MDI0 || GEM_IS_APPLE(sc))) { 276 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 277 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 278 GEM_MIF_CONFIG, sc->sc_mif_config); 279 280 switch (sc->sc_variant) { 281 case GEM_SUN_ERI: 282 case GEM_APPLE_K2_GMAC: 283 phyad = GEM_PHYAD_INTERNAL; 284 break; 285 case GEM_APPLE_GMAC: 286 phyad = GEM_PHYAD_EXTERNAL; 287 break; 288 default: 289 phyad = MII_PHY_ANY; 290 break; 291 } 292 293 mii_attach(&sc->sc_dev, mii, 0xffffffff, phyad, 294 MII_OFFSET_ANY, mii_flags); 295 } 296 297 /* 298 * Try the external PCS SERDES if we didn't find any MII 299 * devices. 300 */ 301 child = LIST_FIRST(&mii->mii_phys); 302 if (child == NULL && sc->sc_variant != GEM_SUN_ERI) { 303 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 304 GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_SERDES); 305 306 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 307 GEM_MII_SLINK_CONTROL, 308 GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D); 309 310 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 311 GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 312 313 mii->mii_readreg = gem_pcs_readreg; 314 mii->mii_writereg = gem_pcs_writereg; 315 316 mii_flags |= MIIF_NOISOLATE; 317 318 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 319 MII_OFFSET_ANY, mii_flags); 320 } 321 322 child = LIST_FIRST(&mii->mii_phys); 323 if (child == NULL) { 324 /* No PHY attached */ 325 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 326 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 327 } else { 328 /* 329 * XXX - we can really do the following ONLY if the 330 * phy indeed has the auto negotiation capability!! 331 */ 332 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 333 } 334 335 /* Check if we support GigE media. */ 336 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 337 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 338 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 339 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 340 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 341 sc->sc_flags |= GEM_GIGABIT; 342 break; 343 } 344 } 345 346 /* Attach the interface. */ 347 if_attach(ifp); 348 ether_ifattach(ifp); 349 350 timeout_set(&sc->sc_tick_ch, gem_tick, sc); 351 timeout_set(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 352 return; 353 354 /* 355 * Free any resources we've allocated during the failed attach 356 * attempt. Do this in reverse order and fall through. 357 */ 358 fail_6: 359 for (i = 0; i < GEM_NTXDESC; i++) { 360 if (sc->sc_txd[i].sd_map != NULL) 361 bus_dmamap_destroy(sc->sc_dmatag, 362 sc->sc_txd[i].sd_map); 363 } 364 fail_5: 365 for (i = 0; i < GEM_NRXDESC; i++) { 366 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 367 bus_dmamap_destroy(sc->sc_dmatag, 368 sc->sc_rxsoft[i].rxs_dmamap); 369 } 370 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 371 fail_3: 372 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 373 fail_2: 374 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 375 sizeof(struct gem_control_data)); 376 fail_1: 377 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 378 fail_0: 379 return; 380 } 381 382 void 383 gem_unconfig(struct gem_softc *sc) 384 { 385 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 386 int i; 387 388 gem_stop(ifp, 1); 389 390 for (i = 0; i < GEM_NTXDESC; i++) { 391 if (sc->sc_txd[i].sd_map != NULL) 392 bus_dmamap_destroy(sc->sc_dmatag, 393 sc->sc_txd[i].sd_map); 394 } 395 for (i = 0; i < GEM_NRXDESC; i++) { 396 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 397 bus_dmamap_destroy(sc->sc_dmatag, 398 sc->sc_rxsoft[i].rxs_dmamap); 399 } 400 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 401 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 402 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 403 sizeof(struct gem_control_data)); 404 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 405 406 /* Detach all PHYs */ 407 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 408 409 /* Delete all remaining media. */ 410 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 411 412 ether_ifdetach(ifp); 413 if_detach(ifp); 414 } 415 416 417 void 418 gem_tick(void *arg) 419 { 420 struct gem_softc *sc = arg; 421 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 422 bus_space_tag_t t = sc->sc_bustag; 423 bus_space_handle_t mac = sc->sc_h1; 424 int s; 425 u_int32_t v; 426 427 /* unload collisions counters */ 428 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 429 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 430 ifp->if_collisions += v + 431 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 432 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 433 ifp->if_oerrors += v; 434 435 /* read error counters */ 436 ifp->if_ierrors += 437 bus_space_read_4(t, mac, GEM_MAC_RX_LEN_ERR_CNT) + 438 bus_space_read_4(t, mac, GEM_MAC_RX_ALIGN_ERR) + 439 bus_space_read_4(t, mac, GEM_MAC_RX_CRC_ERR_CNT) + 440 bus_space_read_4(t, mac, GEM_MAC_RX_CODE_VIOL); 441 442 /* clear the hardware counters */ 443 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 444 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 445 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 446 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 447 bus_space_write_4(t, mac, GEM_MAC_RX_LEN_ERR_CNT, 0); 448 bus_space_write_4(t, mac, GEM_MAC_RX_ALIGN_ERR, 0); 449 bus_space_write_4(t, mac, GEM_MAC_RX_CRC_ERR_CNT, 0); 450 bus_space_write_4(t, mac, GEM_MAC_RX_CODE_VIOL, 0); 451 452 s = splnet(); 453 mii_tick(&sc->sc_mii); 454 splx(s); 455 456 timeout_add_sec(&sc->sc_tick_ch, 1); 457 } 458 459 int 460 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, 461 u_int32_t clr, u_int32_t set) 462 { 463 int i; 464 u_int32_t reg; 465 466 for (i = TRIES; i--; DELAY(100)) { 467 reg = bus_space_read_4(sc->sc_bustag, h, r); 468 if ((reg & clr) == 0 && (reg & set) == set) 469 return (1); 470 } 471 472 return (0); 473 } 474 475 void 476 gem_reset(struct gem_softc *sc) 477 { 478 bus_space_tag_t t = sc->sc_bustag; 479 bus_space_handle_t h = sc->sc_h2; 480 int s; 481 482 s = splnet(); 483 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 484 gem_reset_rx(sc); 485 gem_reset_tx(sc); 486 487 /* Do a full reset */ 488 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 489 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 490 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 491 splx(s); 492 } 493 494 495 /* 496 * Drain the receive queue. 497 */ 498 void 499 gem_rxdrain(struct gem_softc *sc) 500 { 501 struct gem_rxsoft *rxs; 502 int i; 503 504 for (i = 0; i < GEM_NRXDESC; i++) { 505 rxs = &sc->sc_rxsoft[i]; 506 if (rxs->rxs_mbuf != NULL) { 507 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 508 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 509 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 510 m_freem(rxs->rxs_mbuf); 511 rxs->rxs_mbuf = NULL; 512 } 513 } 514 sc->sc_rx_prod = sc->sc_rx_cons = 0; 515 } 516 517 /* 518 * Reset the whole thing. 519 */ 520 void 521 gem_stop(struct ifnet *ifp, int softonly) 522 { 523 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 524 struct gem_sxd *sd; 525 u_int32_t i; 526 527 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 528 529 timeout_del(&sc->sc_tick_ch); 530 531 /* 532 * Mark the interface down and cancel the watchdog timer. 533 */ 534 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 535 ifp->if_timer = 0; 536 537 if (!softonly) { 538 mii_down(&sc->sc_mii); 539 540 gem_reset_rx(sc); 541 gem_reset_tx(sc); 542 } 543 544 /* 545 * Release any queued transmit buffers. 546 */ 547 for (i = 0; i < GEM_NTXDESC; i++) { 548 sd = &sc->sc_txd[i]; 549 if (sd->sd_mbuf != NULL) { 550 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 551 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 552 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 553 m_freem(sd->sd_mbuf); 554 sd->sd_mbuf = NULL; 555 } 556 } 557 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 558 559 gem_rxdrain(sc); 560 } 561 562 563 /* 564 * Reset the receiver 565 */ 566 int 567 gem_reset_rx(struct gem_softc *sc) 568 { 569 bus_space_tag_t t = sc->sc_bustag; 570 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 571 572 /* 573 * Resetting while DMA is in progress can cause a bus hang, so we 574 * disable DMA first. 575 */ 576 gem_disable_rx(sc); 577 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 578 /* Wait till it finishes */ 579 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 580 printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname); 581 /* Wait 5ms extra. */ 582 delay(5000); 583 584 /* Finally, reset the ERX */ 585 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 586 /* Wait till it finishes */ 587 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 588 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 589 return (1); 590 } 591 return (0); 592 } 593 594 595 /* 596 * Reset the transmitter 597 */ 598 int 599 gem_reset_tx(struct gem_softc *sc) 600 { 601 bus_space_tag_t t = sc->sc_bustag; 602 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 603 604 /* 605 * Resetting while DMA is in progress can cause a bus hang, so we 606 * disable DMA first. 607 */ 608 gem_disable_tx(sc); 609 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 610 /* Wait till it finishes */ 611 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 612 printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname); 613 /* Wait 5ms extra. */ 614 delay(5000); 615 616 /* Finally, reset the ETX */ 617 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 618 /* Wait till it finishes */ 619 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 620 printf("%s: cannot reset transmitter\n", 621 sc->sc_dev.dv_xname); 622 return (1); 623 } 624 return (0); 625 } 626 627 /* 628 * Disable receiver. 629 */ 630 int 631 gem_disable_rx(struct gem_softc *sc) 632 { 633 bus_space_tag_t t = sc->sc_bustag; 634 bus_space_handle_t h = sc->sc_h1; 635 u_int32_t cfg; 636 637 /* Flip the enable bit */ 638 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 639 cfg &= ~GEM_MAC_RX_ENABLE; 640 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 641 642 /* Wait for it to finish */ 643 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 644 } 645 646 /* 647 * Disable transmitter. 648 */ 649 int 650 gem_disable_tx(struct gem_softc *sc) 651 { 652 bus_space_tag_t t = sc->sc_bustag; 653 bus_space_handle_t h = sc->sc_h1; 654 u_int32_t cfg; 655 656 /* Flip the enable bit */ 657 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 658 cfg &= ~GEM_MAC_TX_ENABLE; 659 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 660 661 /* Wait for it to finish */ 662 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 663 } 664 665 /* 666 * Initialize interface. 667 */ 668 int 669 gem_meminit(struct gem_softc *sc) 670 { 671 int i; 672 673 /* 674 * Initialize the transmit descriptor ring. 675 */ 676 for (i = 0; i < GEM_NTXDESC; i++) { 677 sc->sc_txdescs[i].gd_flags = 0; 678 sc->sc_txdescs[i].gd_addr = 0; 679 } 680 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 681 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 682 683 /* 684 * Initialize the receive descriptor and receive job 685 * descriptor rings. 686 */ 687 for (i = 0; i < GEM_NRXDESC; i++) { 688 sc->sc_rxdescs[i].gd_flags = 0; 689 sc->sc_rxdescs[i].gd_addr = 0; 690 } 691 /* Hardware reads RX descriptors in multiples of four. */ 692 if_rxr_init(&sc->sc_rx_ring, 4, GEM_NRXDESC - 4); 693 gem_fill_rx_ring(sc); 694 695 return (0); 696 } 697 698 int 699 gem_ringsize(int sz) 700 { 701 switch (sz) { 702 case 32: 703 return GEM_RING_SZ_32; 704 case 64: 705 return GEM_RING_SZ_64; 706 case 128: 707 return GEM_RING_SZ_128; 708 case 256: 709 return GEM_RING_SZ_256; 710 case 512: 711 return GEM_RING_SZ_512; 712 case 1024: 713 return GEM_RING_SZ_1024; 714 case 2048: 715 return GEM_RING_SZ_2048; 716 case 4096: 717 return GEM_RING_SZ_4096; 718 case 8192: 719 return GEM_RING_SZ_8192; 720 default: 721 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 722 return GEM_RING_SZ_32; 723 } 724 } 725 726 /* 727 * Initialization of interface; set up initialization block 728 * and transmit/receive descriptor rings. 729 */ 730 int 731 gem_init(struct ifnet *ifp) 732 { 733 734 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 735 bus_space_tag_t t = sc->sc_bustag; 736 bus_space_handle_t h = sc->sc_h1; 737 int s; 738 u_int32_t v; 739 740 s = splnet(); 741 742 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 743 /* 744 * Initialization sequence. The numbered steps below correspond 745 * to the sequence outlined in section 6.3.5.1 in the Ethernet 746 * Channel Engine manual (part of the PCIO manual). 747 * See also the STP2002-STQ document from Sun Microsystems. 748 */ 749 750 /* step 1 & 2. Reset the Ethernet Channel */ 751 gem_stop(ifp, 0); 752 gem_reset(sc); 753 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 754 755 /* Re-initialize the MIF */ 756 gem_mifinit(sc); 757 758 /* Call MI reset function if any */ 759 if (sc->sc_hwreset) 760 (*sc->sc_hwreset)(sc); 761 762 /* step 3. Setup data structures in host memory */ 763 gem_meminit(sc); 764 765 /* step 4. TX MAC registers & counters */ 766 gem_init_regs(sc); 767 768 /* step 5. RX MAC registers & counters */ 769 gem_iff(sc); 770 771 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 772 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 773 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); 774 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 775 776 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 777 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); 778 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 779 780 /* step 8. Global Configuration & Interrupt Mask */ 781 bus_space_write_4(t, h, GEM_INTMASK, 782 ~(GEM_INTR_TX_INTME| 783 GEM_INTR_TX_EMPTY| 784 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 785 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 786 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 787 GEM_INTR_BERR)); 788 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 789 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 790 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 791 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 792 793 /* step 9. ETX Configuration: use mostly default values */ 794 795 /* Enable DMA */ 796 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 797 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x04ff) << 10) & 798 GEM_TX_CONFIG_TXFIFO_TH; 799 bus_space_write_4(t, h, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 800 bus_space_write_4(t, h, GEM_TX_KICK, 0); 801 802 /* step 10. ERX Configuration */ 803 804 /* Encode Receive Descriptor ring size: four possible values */ 805 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 806 /* Enable DMA */ 807 bus_space_write_4(t, h, GEM_RX_CONFIG, 808 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 809 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 810 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 811 /* 812 * The following value is for an OFF Threshold of about 3/4 full 813 * and an ON Threshold of 1/4 full. 814 */ 815 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 816 (3 * sc->sc_rxfifosize / 256) | 817 ((sc->sc_rxfifosize / 256) << 12)); 818 bus_space_write_4(t, h, GEM_RX_BLANKING, (6 << 12) | 6); 819 820 /* step 11. Configure Media */ 821 mii_mediachg(&sc->sc_mii); 822 823 /* step 12. RX_MAC Configuration Register */ 824 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 825 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 826 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 827 828 /* step 14. Issue Transmit Pending command */ 829 830 /* Call MI initialization function if any */ 831 if (sc->sc_hwinit) 832 (*sc->sc_hwinit)(sc); 833 834 /* step 15. Give the receiver a swift kick */ 835 bus_space_write_4(t, h, GEM_RX_KICK, sc->sc_rx_prod); 836 837 /* Start the one second timer. */ 838 timeout_add_sec(&sc->sc_tick_ch, 1); 839 840 ifp->if_flags |= IFF_RUNNING; 841 ifp->if_flags &= ~IFF_OACTIVE; 842 843 splx(s); 844 845 return (0); 846 } 847 848 void 849 gem_init_regs(struct gem_softc *sc) 850 { 851 bus_space_tag_t t = sc->sc_bustag; 852 bus_space_handle_t h = sc->sc_h1; 853 u_int32_t v; 854 855 /* These regs are not cleared on reset */ 856 sc->sc_inited = 0; 857 if (!sc->sc_inited) { 858 /* Load recommended values */ 859 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 860 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 861 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 862 863 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 864 /* Max frame and max burst size */ 865 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 866 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 867 868 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 869 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 870 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 871 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 872 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 873 ((sc->sc_arpcom.ac_enaddr[5]<<8)|sc->sc_arpcom.ac_enaddr[4])&0x3ff); 874 875 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 876 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 877 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 878 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 879 880 /* MAC control addr set to 0:1:c2:0:1:80 */ 881 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 882 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 883 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 884 885 /* MAC filter addr set to 0:0:0:0:0:0 */ 886 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 887 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 888 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 889 890 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 891 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 892 893 sc->sc_inited = 1; 894 } 895 896 /* Counters need to be zeroed */ 897 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 898 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 899 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 900 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 901 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 902 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 903 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 904 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 905 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 906 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 907 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 908 909 /* Set XOFF PAUSE time */ 910 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1bf0); 911 912 /* 913 * Set the internal arbitration to "infinite" bursts of the 914 * maximum length of 31 * 64 bytes so DMA transfers aren't 915 * split up in cache line size chunks. This greatly improves 916 * especially RX performance. 917 * Enable silicon bug workarounds for the Apple variants. 918 */ 919 v = GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT; 920 if (sc->sc_pci) 921 v |= GEM_CONFIG_BURST_INF; 922 else 923 v |= GEM_CONFIG_BURST_64; 924 if (sc->sc_variant != GEM_SUN_GEM && sc->sc_variant != GEM_SUN_ERI) 925 v |= GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX; 926 bus_space_write_4(t, h, GEM_CONFIG, v); 927 928 /* 929 * Set the station address. 930 */ 931 bus_space_write_4(t, h, GEM_MAC_ADDR0, 932 (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); 933 bus_space_write_4(t, h, GEM_MAC_ADDR1, 934 (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); 935 bus_space_write_4(t, h, GEM_MAC_ADDR2, 936 (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); 937 } 938 939 /* 940 * Receive interrupt. 941 */ 942 int 943 gem_rint(struct gem_softc *sc) 944 { 945 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 946 bus_space_tag_t t = sc->sc_bustag; 947 bus_space_handle_t h = sc->sc_h1; 948 struct gem_rxsoft *rxs; 949 struct mbuf *m; 950 u_int64_t rxstat; 951 int i, len; 952 953 for (i = sc->sc_rx_cons; if_rxr_inuse(&sc->sc_rx_ring) > 0; 954 i = GEM_NEXTRX(i)) { 955 rxs = &sc->sc_rxsoft[i]; 956 957 GEM_CDRXSYNC(sc, i, 958 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 959 960 rxstat = GEM_DMA_READ(sc, &sc->sc_rxdescs[i].gd_flags); 961 962 if (rxstat & GEM_RD_OWN) { 963 /* We have processed all of the receive buffers. */ 964 break; 965 } 966 967 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 968 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 969 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 970 971 m = rxs->rxs_mbuf; 972 rxs->rxs_mbuf = NULL; 973 974 if_rxr_put(&sc->sc_rx_ring, 1); 975 976 if (rxstat & GEM_RD_BAD_CRC) { 977 ifp->if_ierrors++; 978 #ifdef GEM_DEBUG 979 printf("%s: receive error: CRC error\n", 980 sc->sc_dev.dv_xname); 981 #endif 982 m_freem(m); 983 continue; 984 } 985 986 #ifdef GEM_DEBUG 987 if (ifp->if_flags & IFF_DEBUG) { 988 printf(" rxsoft %p descriptor %d: ", rxs, i); 989 printf("gd_flags: 0x%016llx\t", (long long) 990 GEM_DMA_READ(sc, &sc->sc_rxdescs[i].gd_flags)); 991 printf("gd_addr: 0x%016llx\n", (long long) 992 GEM_DMA_READ(sc, &sc->sc_rxdescs[i].gd_addr)); 993 } 994 #endif 995 996 /* No errors; receive the packet. */ 997 len = GEM_RD_BUFLEN(rxstat); 998 999 m->m_data += 2; /* We're already off by two */ 1000 1001 ifp->if_ipackets++; 1002 m->m_pkthdr.rcvif = ifp; 1003 m->m_pkthdr.len = m->m_len = len; 1004 1005 #if NBPFILTER > 0 1006 if (ifp->if_bpf) 1007 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1008 #endif /* NBPFILTER > 0 */ 1009 1010 /* Pass it on. */ 1011 ether_input_mbuf(ifp, m); 1012 } 1013 1014 /* Update the receive pointer. */ 1015 sc->sc_rx_cons = i; 1016 gem_fill_rx_ring(sc); 1017 bus_space_write_4(t, h, GEM_RX_KICK, sc->sc_rx_prod); 1018 1019 DPRINTF(sc, ("gem_rint: done sc->sc_rx_cons %d, complete %d\n", 1020 sc->sc_rx_cons, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1021 1022 return (1); 1023 } 1024 1025 void 1026 gem_fill_rx_ring(struct gem_softc *sc) 1027 { 1028 u_int slots; 1029 1030 for (slots = if_rxr_get(&sc->sc_rx_ring, GEM_NRXDESC - 4); 1031 slots > 0; slots--) { 1032 if (gem_add_rxbuf(sc, sc->sc_rx_prod)) 1033 break; 1034 } 1035 if_rxr_put(&sc->sc_rx_ring, slots); 1036 } 1037 1038 /* 1039 * Add a receive buffer to the indicated descriptor. 1040 */ 1041 int 1042 gem_add_rxbuf(struct gem_softc *sc, int idx) 1043 { 1044 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1045 struct mbuf *m; 1046 int error; 1047 1048 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1049 if (!m) 1050 return (ENOBUFS); 1051 m->m_len = m->m_pkthdr.len = MCLBYTES; 1052 1053 #ifdef GEM_DEBUG 1054 /* bzero the packet to check dma */ 1055 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1056 #endif 1057 1058 rxs->rxs_mbuf = m; 1059 1060 error = bus_dmamap_load_mbuf(sc->sc_dmatag, rxs->rxs_dmamap, m, 1061 BUS_DMA_READ|BUS_DMA_NOWAIT); 1062 if (error) { 1063 printf("%s: can't load rx DMA map %d, error = %d\n", 1064 sc->sc_dev.dv_xname, idx, error); 1065 panic("gem_add_rxbuf"); /* XXX */ 1066 } 1067 1068 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1069 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1070 1071 GEM_INIT_RXDESC(sc, idx); 1072 1073 sc->sc_rx_prod = GEM_NEXTRX(sc->sc_rx_prod); 1074 1075 return (0); 1076 } 1077 1078 int 1079 gem_eint(struct gem_softc *sc, u_int status) 1080 { 1081 if ((status & GEM_INTR_MIF) != 0) { 1082 #ifdef GEM_DEBUG 1083 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1084 #endif 1085 return (1); 1086 } 1087 1088 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS); 1089 return (1); 1090 } 1091 1092 int 1093 gem_pint(struct gem_softc *sc) 1094 { 1095 bus_space_tag_t t = sc->sc_bustag; 1096 bus_space_handle_t seb = sc->sc_h1; 1097 u_int32_t status; 1098 1099 status = bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS); 1100 status |= bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS); 1101 #ifdef GEM_DEBUG 1102 if (status) 1103 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1104 #endif 1105 return (1); 1106 } 1107 1108 int 1109 gem_intr(void *v) 1110 { 1111 struct gem_softc *sc = (struct gem_softc *)v; 1112 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1113 bus_space_tag_t t = sc->sc_bustag; 1114 bus_space_handle_t seb = sc->sc_h1; 1115 u_int32_t status; 1116 int r = 0; 1117 1118 status = bus_space_read_4(t, seb, GEM_STATUS); 1119 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n", 1120 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS)); 1121 1122 if (status == 0xffffffff) 1123 return (0); 1124 1125 if ((status & GEM_INTR_PCS) != 0) 1126 r |= gem_pint(sc); 1127 1128 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1129 r |= gem_eint(sc, status); 1130 1131 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1132 r |= gem_tint(sc, status); 1133 1134 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1135 r |= gem_rint(sc); 1136 1137 /* We should eventually do more than just print out error stats. */ 1138 if (status & GEM_INTR_TX_MAC) { 1139 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1140 #ifdef GEM_DEBUG 1141 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1142 printf("%s: MAC tx fault, status %x\n", 1143 sc->sc_dev.dv_xname, txstat); 1144 #endif 1145 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1146 gem_init(ifp); 1147 } 1148 if (status & GEM_INTR_RX_MAC) { 1149 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1150 #ifdef GEM_DEBUG 1151 if (rxstat & ~GEM_MAC_RX_DONE) 1152 printf("%s: MAC rx fault, status %x\n", 1153 sc->sc_dev.dv_xname, rxstat); 1154 #endif 1155 if (rxstat & GEM_MAC_RX_OVERFLOW) { 1156 ifp->if_ierrors++; 1157 1158 /* 1159 * Apparently a silicon bug causes ERI to hang 1160 * from time to time. So if we detect an RX 1161 * FIFO overflow, we fire off a timer, and 1162 * check whether we're still making progress 1163 * by looking at the RX FIFO write and read 1164 * pointers. 1165 */ 1166 sc->sc_rx_fifo_wr_ptr = 1167 bus_space_read_4(t, seb, GEM_RX_FIFO_WR_PTR); 1168 sc->sc_rx_fifo_rd_ptr = 1169 bus_space_read_4(t, seb, GEM_RX_FIFO_RD_PTR); 1170 timeout_add_msec(&sc->sc_rx_watchdog, 400); 1171 } 1172 #ifdef GEM_DEBUG 1173 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1174 printf("%s: MAC rx fault, status %x\n", 1175 sc->sc_dev.dv_xname, rxstat); 1176 #endif 1177 } 1178 return (r); 1179 } 1180 1181 void 1182 gem_rx_watchdog(void *arg) 1183 { 1184 struct gem_softc *sc = arg; 1185 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1186 bus_space_tag_t t = sc->sc_bustag; 1187 bus_space_handle_t h = sc->sc_h1; 1188 u_int32_t rx_fifo_wr_ptr; 1189 u_int32_t rx_fifo_rd_ptr; 1190 u_int32_t state; 1191 1192 if ((ifp->if_flags & IFF_RUNNING) == 0) 1193 return; 1194 1195 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 1196 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 1197 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 1198 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 1199 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 1200 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 1201 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) { 1202 /* 1203 * The RX state machine is still in overflow state and 1204 * the RX FIFO write and read pointers seem to be 1205 * stuck. Whack the chip over the head to get things 1206 * going again. 1207 */ 1208 gem_init(ifp); 1209 } 1210 } 1211 1212 void 1213 gem_watchdog(struct ifnet *ifp) 1214 { 1215 struct gem_softc *sc = ifp->if_softc; 1216 1217 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1218 "GEM_MAC_RX_CONFIG %x\n", 1219 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 1220 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 1221 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 1222 1223 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1224 ++ifp->if_oerrors; 1225 1226 /* Try to get more packets going. */ 1227 gem_init(ifp); 1228 } 1229 1230 /* 1231 * Initialize the MII Management Interface 1232 */ 1233 void 1234 gem_mifinit(struct gem_softc *sc) 1235 { 1236 bus_space_tag_t t = sc->sc_bustag; 1237 bus_space_handle_t mif = sc->sc_h1; 1238 1239 /* Configure the MIF in frame mode */ 1240 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1241 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1242 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1243 } 1244 1245 /* 1246 * MII interface 1247 * 1248 * The GEM MII interface supports at least three different operating modes: 1249 * 1250 * Bitbang mode is implemented using data, clock and output enable registers. 1251 * 1252 * Frame mode is implemented by loading a complete frame into the frame 1253 * register and polling the valid bit for completion. 1254 * 1255 * Polling mode uses the frame register but completion is indicated by 1256 * an interrupt. 1257 * 1258 */ 1259 int 1260 gem_mii_readreg(struct device *self, int phy, int reg) 1261 { 1262 struct gem_softc *sc = (void *)self; 1263 bus_space_tag_t t = sc->sc_bustag; 1264 bus_space_handle_t mif = sc->sc_h1; 1265 int n; 1266 u_int32_t v; 1267 1268 #ifdef GEM_DEBUG 1269 if (sc->sc_debug) 1270 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1271 #endif 1272 1273 /* Construct the frame command */ 1274 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1275 GEM_MIF_FRAME_READ; 1276 1277 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1278 for (n = 0; n < 100; n++) { 1279 DELAY(1); 1280 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1281 if (v & GEM_MIF_FRAME_TA0) 1282 return (v & GEM_MIF_FRAME_DATA); 1283 } 1284 1285 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1286 return (0); 1287 } 1288 1289 void 1290 gem_mii_writereg(struct device *self, int phy, int reg, int val) 1291 { 1292 struct gem_softc *sc = (void *)self; 1293 bus_space_tag_t t = sc->sc_bustag; 1294 bus_space_handle_t mif = sc->sc_h1; 1295 int n; 1296 u_int32_t v; 1297 1298 #ifdef GEM_DEBUG 1299 if (sc->sc_debug) 1300 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1301 phy, reg, val); 1302 #endif 1303 1304 /* Construct the frame command */ 1305 v = GEM_MIF_FRAME_WRITE | 1306 (phy << GEM_MIF_PHY_SHIFT) | 1307 (reg << GEM_MIF_REG_SHIFT) | 1308 (val & GEM_MIF_FRAME_DATA); 1309 1310 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1311 for (n = 0; n < 100; n++) { 1312 DELAY(1); 1313 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1314 if (v & GEM_MIF_FRAME_TA0) 1315 return; 1316 } 1317 1318 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1319 } 1320 1321 void 1322 gem_mii_statchg(struct device *dev) 1323 { 1324 struct gem_softc *sc = (void *)dev; 1325 #ifdef GEM_DEBUG 1326 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1327 #endif 1328 bus_space_tag_t t = sc->sc_bustag; 1329 bus_space_handle_t mac = sc->sc_h1; 1330 u_int32_t v; 1331 1332 #ifdef GEM_DEBUG 1333 if (sc->sc_debug) 1334 printf("gem_mii_statchg: status change: phy = %d\n", instance); 1335 #endif 1336 1337 /* Set tx full duplex options */ 1338 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1339 delay(10000); /* reg must be cleared and delay before changing. */ 1340 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1341 GEM_MAC_TX_ENABLE; 1342 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1343 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1344 } 1345 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1346 1347 /* XIF Configuration */ 1348 v = GEM_MAC_XIF_TX_MII_ENA; 1349 v |= GEM_MAC_XIF_LINK_LED; 1350 1351 /* External MII needs echo disable if half duplex. */ 1352 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1353 /* turn on full duplex LED */ 1354 v |= GEM_MAC_XIF_FDPLX_LED; 1355 else 1356 /* half duplex -- disable echo */ 1357 v |= GEM_MAC_XIF_ECHO_DISABL; 1358 1359 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1360 case IFM_1000_T: /* Gigabit using GMII interface */ 1361 case IFM_1000_SX: 1362 v |= GEM_MAC_XIF_GMII_MODE; 1363 break; 1364 default: 1365 v &= ~GEM_MAC_XIF_GMII_MODE; 1366 } 1367 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1368 1369 /* 1370 * 802.3x flow control 1371 */ 1372 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG); 1373 v &= ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 1374 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1375 v |= GEM_MAC_CC_RX_PAUSE; 1376 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1377 v |= GEM_MAC_CC_TX_PAUSE; 1378 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 1379 } 1380 1381 int 1382 gem_pcs_readreg(struct device *self, int phy, int reg) 1383 { 1384 struct gem_softc *sc = (void *)self; 1385 bus_space_tag_t t = sc->sc_bustag; 1386 bus_space_handle_t pcs = sc->sc_h1; 1387 1388 #ifdef GEM_DEBUG 1389 if (sc->sc_debug) 1390 printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg); 1391 #endif 1392 1393 if (phy != GEM_PHYAD_EXTERNAL) 1394 return (0); 1395 1396 switch (reg) { 1397 case MII_BMCR: 1398 reg = GEM_MII_CONTROL; 1399 break; 1400 case MII_BMSR: 1401 reg = GEM_MII_STATUS; 1402 break; 1403 case MII_ANAR: 1404 reg = GEM_MII_ANAR; 1405 break; 1406 case MII_ANLPAR: 1407 reg = GEM_MII_ANLPAR; 1408 break; 1409 case MII_EXTSR: 1410 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1411 default: 1412 return (0); 1413 } 1414 1415 return bus_space_read_4(t, pcs, reg); 1416 } 1417 1418 void 1419 gem_pcs_writereg(struct device *self, int phy, int reg, int val) 1420 { 1421 struct gem_softc *sc = (void *)self; 1422 bus_space_tag_t t = sc->sc_bustag; 1423 bus_space_handle_t pcs = sc->sc_h1; 1424 int reset = 0; 1425 1426 #ifdef GEM_DEBUG 1427 if (sc->sc_debug) 1428 printf("gem_pcs_writereg: phy %d reg %d val %x\n", 1429 phy, reg, val); 1430 #endif 1431 1432 if (phy != GEM_PHYAD_EXTERNAL) 1433 return; 1434 1435 if (reg == MII_ANAR) 1436 bus_space_write_4(t, pcs, GEM_MII_CONFIG, 0); 1437 1438 switch (reg) { 1439 case MII_BMCR: 1440 reset = (val & GEM_MII_CONTROL_RESET); 1441 reg = GEM_MII_CONTROL; 1442 break; 1443 case MII_BMSR: 1444 reg = GEM_MII_STATUS; 1445 break; 1446 case MII_ANAR: 1447 reg = GEM_MII_ANAR; 1448 break; 1449 case MII_ANLPAR: 1450 reg = GEM_MII_ANLPAR; 1451 break; 1452 default: 1453 return; 1454 } 1455 1456 bus_space_write_4(t, pcs, reg, val); 1457 1458 if (reset) 1459 gem_bitwait(sc, pcs, GEM_MII_CONTROL, GEM_MII_CONTROL_RESET, 0); 1460 1461 if (reg == GEM_MII_ANAR || reset) { 1462 bus_space_write_4(t, pcs, GEM_MII_SLINK_CONTROL, 1463 GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D); 1464 bus_space_write_4(t, pcs, GEM_MII_CONFIG, 1465 GEM_MII_CONFIG_ENABLE); 1466 } 1467 } 1468 1469 int 1470 gem_mediachange(struct ifnet *ifp) 1471 { 1472 struct gem_softc *sc = ifp->if_softc; 1473 struct mii_data *mii = &sc->sc_mii; 1474 1475 if (mii->mii_instance) { 1476 struct mii_softc *miisc; 1477 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1478 mii_phy_reset(miisc); 1479 } 1480 1481 return (mii_mediachg(&sc->sc_mii)); 1482 } 1483 1484 void 1485 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1486 { 1487 struct gem_softc *sc = ifp->if_softc; 1488 1489 mii_pollstat(&sc->sc_mii); 1490 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1491 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1492 } 1493 1494 /* 1495 * Process an ioctl request. 1496 */ 1497 int 1498 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1499 { 1500 struct gem_softc *sc = ifp->if_softc; 1501 struct ifaddr *ifa = (struct ifaddr *)data; 1502 struct ifreq *ifr = (struct ifreq *)data; 1503 int s, error = 0; 1504 1505 s = splnet(); 1506 1507 switch (cmd) { 1508 case SIOCSIFADDR: 1509 ifp->if_flags |= IFF_UP; 1510 if ((ifp->if_flags & IFF_RUNNING) == 0) 1511 gem_init(ifp); 1512 #ifdef INET 1513 if (ifa->ifa_addr->sa_family == AF_INET) 1514 arp_ifinit(&sc->sc_arpcom, ifa); 1515 #endif 1516 break; 1517 1518 case SIOCSIFFLAGS: 1519 if (ifp->if_flags & IFF_UP) { 1520 if (ifp->if_flags & IFF_RUNNING) 1521 error = ENETRESET; 1522 else 1523 gem_init(ifp); 1524 } else { 1525 if (ifp->if_flags & IFF_RUNNING) 1526 gem_stop(ifp, 0); 1527 } 1528 #ifdef GEM_DEBUG 1529 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1530 #endif 1531 break; 1532 1533 case SIOCGIFMEDIA: 1534 case SIOCSIFMEDIA: 1535 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1536 break; 1537 1538 case SIOCGIFRXR: 1539 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 1540 NULL, MCLBYTES, &sc->sc_rx_ring); 1541 break; 1542 1543 default: 1544 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1545 } 1546 1547 if (error == ENETRESET) { 1548 if (ifp->if_flags & IFF_RUNNING) 1549 gem_iff(sc); 1550 error = 0; 1551 } 1552 1553 splx(s); 1554 return (error); 1555 } 1556 1557 void 1558 gem_iff(struct gem_softc *sc) 1559 { 1560 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1561 struct arpcom *ac = &sc->sc_arpcom; 1562 struct ether_multi *enm; 1563 struct ether_multistep step; 1564 bus_space_tag_t t = sc->sc_bustag; 1565 bus_space_handle_t h = sc->sc_h1; 1566 u_int32_t crc, hash[16], rxcfg; 1567 int i; 1568 1569 rxcfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1570 rxcfg &= ~(GEM_MAC_RX_HASH_FILTER | GEM_MAC_RX_PROMISCUOUS | 1571 GEM_MAC_RX_PROMISC_GRP); 1572 ifp->if_flags &= ~IFF_ALLMULTI; 1573 1574 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1575 ifp->if_flags |= IFF_ALLMULTI; 1576 if (ifp->if_flags & IFF_PROMISC) 1577 rxcfg |= GEM_MAC_RX_PROMISCUOUS; 1578 else 1579 rxcfg |= GEM_MAC_RX_PROMISC_GRP; 1580 } else { 1581 /* 1582 * Set up multicast address filter by passing all multicast 1583 * addresses through a crc generator, and then using the 1584 * high order 8 bits as an index into the 256 bit logical 1585 * address filter. The high order 4 bits selects the word, 1586 * while the other 4 bits select the bit within the word 1587 * (where bit 0 is the MSB). 1588 */ 1589 1590 rxcfg |= GEM_MAC_RX_HASH_FILTER; 1591 1592 /* Clear hash table */ 1593 for (i = 0; i < 16; i++) 1594 hash[i] = 0; 1595 1596 ETHER_FIRST_MULTI(step, ac, enm); 1597 while (enm != NULL) { 1598 crc = ether_crc32_le(enm->enm_addrlo, 1599 ETHER_ADDR_LEN); 1600 1601 /* Just want the 8 most significant bits. */ 1602 crc >>= 24; 1603 1604 /* Set the corresponding bit in the filter. */ 1605 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1606 1607 ETHER_NEXT_MULTI(step, enm); 1608 } 1609 1610 /* Now load the hash table into the chip (if we are using it) */ 1611 for (i = 0; i < 16; i++) { 1612 bus_space_write_4(t, h, 1613 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 1614 hash[i]); 1615 } 1616 } 1617 1618 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, rxcfg); 1619 } 1620 1621 /* 1622 * Transmit interrupt. 1623 */ 1624 int 1625 gem_tint(struct gem_softc *sc, u_int32_t status) 1626 { 1627 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1628 struct gem_sxd *sd; 1629 u_int32_t cons, hwcons; 1630 1631 hwcons = status >> 19; 1632 cons = sc->sc_tx_cons; 1633 while (cons != hwcons) { 1634 sd = &sc->sc_txd[cons]; 1635 if (sd->sd_mbuf != NULL) { 1636 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1637 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1638 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1639 m_freem(sd->sd_mbuf); 1640 sd->sd_mbuf = NULL; 1641 ifp->if_opackets++; 1642 } 1643 sc->sc_tx_cnt--; 1644 if (++cons == GEM_NTXDESC) 1645 cons = 0; 1646 } 1647 sc->sc_tx_cons = cons; 1648 1649 if (sc->sc_tx_cnt < GEM_NTXDESC - 2) 1650 ifp->if_flags &= ~IFF_OACTIVE; 1651 if (sc->sc_tx_cnt == 0) 1652 ifp->if_timer = 0; 1653 1654 gem_start(ifp); 1655 1656 return (1); 1657 } 1658 1659 void 1660 gem_start(struct ifnet *ifp) 1661 { 1662 struct gem_softc *sc = ifp->if_softc; 1663 struct mbuf *m; 1664 u_int64_t flags; 1665 bus_dmamap_t map; 1666 u_int32_t cur, frag, i; 1667 int error; 1668 1669 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1670 return; 1671 1672 while (sc->sc_txd[sc->sc_tx_prod].sd_mbuf == NULL) { 1673 IFQ_POLL(&ifp->if_snd, m); 1674 if (m == NULL) 1675 break; 1676 1677 /* 1678 * Encapsulate this packet and start it going... 1679 * or fail... 1680 */ 1681 1682 cur = frag = sc->sc_tx_prod; 1683 map = sc->sc_txd[cur].sd_map; 1684 1685 error = bus_dmamap_load_mbuf(sc->sc_dmatag, map, m, 1686 BUS_DMA_NOWAIT); 1687 if (error != 0 && error != EFBIG) 1688 goto drop; 1689 if (error != 0) { 1690 /* Too many fragments, linearize. */ 1691 if (m_defrag(m, M_DONTWAIT)) 1692 goto drop; 1693 error = bus_dmamap_load_mbuf(sc->sc_dmatag, map, m, 1694 BUS_DMA_NOWAIT); 1695 if (error != 0) 1696 goto drop; 1697 } 1698 1699 if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) { 1700 bus_dmamap_unload(sc->sc_dmatag, map); 1701 ifp->if_flags |= IFF_OACTIVE; 1702 break; 1703 } 1704 1705 /* We are now committed to transmitting the packet. */ 1706 IFQ_DEQUEUE(&ifp->if_snd, m); 1707 1708 #if NBPFILTER > 0 1709 /* 1710 * If BPF is listening on this interface, let it see the 1711 * packet before we commit it to the wire. 1712 */ 1713 if (ifp->if_bpf) 1714 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1715 #endif 1716 1717 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1718 BUS_DMASYNC_PREWRITE); 1719 1720 for (i = 0; i < map->dm_nsegs; i++) { 1721 GEM_DMA_WRITE(sc, &sc->sc_txdescs[frag].gd_addr, 1722 map->dm_segs[i].ds_addr); 1723 flags = map->dm_segs[i].ds_len & GEM_TD_BUFSIZE; 1724 if (i == 0) 1725 flags |= GEM_TD_START_OF_PACKET; 1726 if (i == (map->dm_nsegs - 1)) 1727 flags |= GEM_TD_END_OF_PACKET; 1728 GEM_DMA_WRITE(sc, &sc->sc_txdescs[frag].gd_flags, 1729 flags); 1730 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1731 GEM_CDTXOFF(frag), sizeof(struct gem_desc), 1732 BUS_DMASYNC_PREWRITE); 1733 cur = frag; 1734 if (++frag == GEM_NTXDESC) 1735 frag = 0; 1736 } 1737 1738 sc->sc_tx_cnt += map->dm_nsegs; 1739 sc->sc_txd[sc->sc_tx_prod].sd_map = sc->sc_txd[cur].sd_map; 1740 sc->sc_txd[cur].sd_map = map; 1741 sc->sc_txd[cur].sd_mbuf = m; 1742 1743 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, frag); 1744 sc->sc_tx_prod = frag; 1745 1746 ifp->if_timer = 5; 1747 } 1748 1749 return; 1750 1751 drop: 1752 IFQ_DEQUEUE(&ifp->if_snd, m); 1753 m_freem(m); 1754 ifp->if_oerrors++; 1755 } 1756