1 /* $OpenBSD: gem.c,v 1.34 2003/07/15 03:52:30 jason Exp $ */ 2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/timeout.h> 43 #include <sys/mbuf.h> 44 #include <sys/syslog.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 52 #include <machine/endian.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/if_ether.h> 63 #endif 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #if NVLAN > 0 70 #include <net/if_vlan_var.h> 71 #endif 72 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii_bitbang.h> 79 80 #include <dev/ic/gemreg.h> 81 #include <dev/ic/gemvar.h> 82 83 #define TRIES 10000 84 85 struct cfdriver gem_cd = { 86 NULL, "gem", DV_IFNET 87 }; 88 89 void gem_start(struct ifnet *); 90 void gem_stop(struct ifnet *, int); 91 int gem_ioctl(struct ifnet *, u_long, caddr_t); 92 void gem_tick(void *); 93 void gem_watchdog(struct ifnet *); 94 void gem_shutdown(void *); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 void gem_reset(struct gem_softc *); 101 int gem_reset_rx(struct gem_softc *sc); 102 int gem_reset_tx(struct gem_softc *sc); 103 int gem_disable_rx(struct gem_softc *sc); 104 int gem_disable_tx(struct gem_softc *sc); 105 void gem_rxdrain(struct gem_softc *sc); 106 int gem_add_rxbuf(struct gem_softc *sc, int idx); 107 void gem_setladrf(struct gem_softc *); 108 int gem_encap(struct gem_softc *, struct mbuf *, u_int32_t *); 109 110 /* MII methods & callbacks */ 111 static int gem_mii_readreg(struct device *, int, int); 112 static void gem_mii_writereg(struct device *, int, int, int); 113 static void gem_mii_statchg(struct device *); 114 115 int gem_mediachange(struct ifnet *); 116 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 117 118 struct mbuf *gem_get(struct gem_softc *, int, int); 119 int gem_put(struct gem_softc *, int, struct mbuf *); 120 void gem_read(struct gem_softc *, int, int); 121 int gem_eint(struct gem_softc *, u_int); 122 int gem_rint(struct gem_softc *); 123 int gem_tint(struct gem_softc *, u_int32_t); 124 void gem_power(int, void *); 125 126 #ifdef GEM_DEBUG 127 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 128 printf x 129 #else 130 #define DPRINTF(sc, x) /* nothing */ 131 #endif 132 133 134 /* 135 * gem_config: 136 * 137 * Attach a Gem interface to the system. 138 */ 139 void 140 gem_config(sc) 141 struct gem_softc *sc; 142 { 143 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 144 struct mii_data *mii = &sc->sc_mii; 145 struct mii_softc *child; 146 int i, error; 147 struct ifmedia_entry *ifm; 148 149 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 150 151 /* Make sure the chip is stopped. */ 152 ifp->if_softc = sc; 153 gem_reset(sc); 154 155 /* 156 * Allocate the control data structures, and create and load the 157 * DMA map for it. 158 */ 159 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 160 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 161 1, &sc->sc_cdnseg, 0)) != 0) { 162 printf("%s: unable to allocate control data, error = %d\n", 163 sc->sc_dev.dv_xname, error); 164 goto fail_0; 165 } 166 167 /* XXX should map this in with correct endianness */ 168 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 169 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 170 BUS_DMA_COHERENT)) != 0) { 171 printf("%s: unable to map control data, error = %d\n", 172 sc->sc_dev.dv_xname, error); 173 goto fail_1; 174 } 175 176 if ((error = bus_dmamap_create(sc->sc_dmatag, 177 sizeof(struct gem_control_data), 1, 178 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 179 printf("%s: unable to create control data DMA map, " 180 "error = %d\n", sc->sc_dev.dv_xname, error); 181 goto fail_2; 182 } 183 184 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 185 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 186 0)) != 0) { 187 printf("%s: unable to load control data DMA map, error = %d\n", 188 sc->sc_dev.dv_xname, error); 189 goto fail_3; 190 } 191 192 /* 193 * Create the receive buffer DMA maps. 194 */ 195 for (i = 0; i < GEM_NRXDESC; i++) { 196 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 197 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 198 printf("%s: unable to create rx DMA map %d, " 199 "error = %d\n", sc->sc_dev.dv_xname, i, error); 200 goto fail_5; 201 } 202 sc->sc_rxsoft[i].rxs_mbuf = NULL; 203 } 204 /* 205 * Create the transmit buffer DMA maps. 206 */ 207 for (i = 0; i < GEM_NTXDESC; i++) { 208 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 209 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 210 &sc->sc_txd[i].sd_map)) != 0) { 211 printf("%s: unable to create tx DMA map %d, " 212 "error = %d\n", sc->sc_dev.dv_xname, i, error); 213 goto fail_6; 214 } 215 sc->sc_txd[i].sd_mbuf = NULL; 216 } 217 218 /* 219 * From this point forward, the attachment cannot fail. A failure 220 * before this point releases all resources that may have been 221 * allocated. 222 */ 223 224 /* Announce ourselves. */ 225 printf("%s: address %s\n", sc->sc_dev.dv_xname, 226 ether_sprintf(sc->sc_enaddr)); 227 228 /* Get RX FIFO size */ 229 sc->sc_rxfifosize = 64 * 230 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 231 232 /* Initialize ifnet structure. */ 233 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 234 ifp->if_softc = sc; 235 ifp->if_flags = 236 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 237 ifp->if_start = gem_start; 238 ifp->if_ioctl = gem_ioctl; 239 ifp->if_watchdog = gem_watchdog; 240 IFQ_SET_READY(&ifp->if_snd); 241 242 /* Initialize ifmedia structures and MII info */ 243 mii->mii_ifp = ifp; 244 mii->mii_readreg = gem_mii_readreg; 245 mii->mii_writereg = gem_mii_writereg; 246 mii->mii_statchg = gem_mii_statchg; 247 248 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 249 250 gem_mifinit(sc); 251 252 mii_attach(&sc->sc_dev, mii, 0xffffffff, 253 MII_PHY_ANY, MII_OFFSET_ANY, 0); 254 255 child = LIST_FIRST(&mii->mii_phys); 256 if (child == NULL) { 257 /* No PHY attached */ 258 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 259 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 260 } else { 261 /* 262 * Walk along the list of attached MII devices and 263 * establish an `MII instance' to `phy number' 264 * mapping. We'll use this mapping in media change 265 * requests to determine which phy to use to program 266 * the MIF configuration register. 267 */ 268 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 269 /* 270 * Note: we support just two PHYs: the built-in 271 * internal device and an external on the MII 272 * connector. 273 */ 274 if (child->mii_phy > 1 || child->mii_inst > 1) { 275 printf("%s: cannot accommodate MII device %s" 276 " at phy %d, instance %d\n", 277 sc->sc_dev.dv_xname, 278 child->mii_dev.dv_xname, 279 child->mii_phy, child->mii_inst); 280 continue; 281 } 282 283 sc->sc_phys[child->mii_inst] = child->mii_phy; 284 } 285 286 /* 287 * Now select and activate the PHY we will use. 288 * 289 * The order of preference is External (MDI1), 290 * Internal (MDI0), Serial Link (no MII). 291 */ 292 if (sc->sc_phys[1]) { 293 #ifdef DEBUG 294 printf("using external phy\n"); 295 #endif 296 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 297 } else { 298 #ifdef DEBUG 299 printf("using internal phy\n"); 300 #endif 301 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 302 } 303 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 304 sc->sc_mif_config); 305 306 /* 307 * XXX - we can really do the following ONLY if the 308 * phy indeed has the auto negotiation capability!! 309 */ 310 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 311 } 312 313 /* 314 * If we support GigE media, we support jumbo frames too. 315 * Unless we are Apple. 316 */ 317 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 318 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 319 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 320 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 321 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 322 #if 0 323 if (sc->sc_variant != GEM_APPLE_GMAC) 324 sc->sc_ethercom.ec_capabilities 325 |= ETHERCAP_JUMBO_MTU; 326 #endif 327 328 sc->sc_flags |= GEM_GIGABIT; 329 break; 330 } 331 } 332 333 /* Attach the interface. */ 334 if_attach(ifp); 335 ether_ifattach(ifp); 336 337 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 338 if (sc->sc_sh == NULL) 339 panic("gem_config: can't establish shutdownhook"); 340 341 timeout_set(&sc->sc_tick_ch, gem_tick, sc); 342 return; 343 344 /* 345 * Free any resources we've allocated during the failed attach 346 * attempt. Do this in reverse order and fall through. 347 */ 348 fail_6: 349 for (i = 0; i < GEM_NTXDESC; i++) { 350 if (sc->sc_txd[i].sd_map != NULL) 351 bus_dmamap_destroy(sc->sc_dmatag, 352 sc->sc_txd[i].sd_map); 353 } 354 fail_5: 355 for (i = 0; i < GEM_NRXDESC; i++) { 356 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 357 bus_dmamap_destroy(sc->sc_dmatag, 358 sc->sc_rxsoft[i].rxs_dmamap); 359 } 360 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 361 fail_3: 362 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 363 fail_2: 364 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 365 sizeof(struct gem_control_data)); 366 fail_1: 367 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 368 fail_0: 369 return; 370 } 371 372 373 void 374 gem_tick(arg) 375 void *arg; 376 { 377 struct gem_softc *sc = arg; 378 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 379 bus_space_tag_t t = sc->sc_bustag; 380 bus_space_handle_t mac = sc->sc_h; 381 int s; 382 383 /* unload collisions counters */ 384 ifp->if_collisions += 385 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 386 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 387 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 388 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 389 390 /* clear the hardware counters */ 391 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 392 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 393 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 394 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 395 396 s = splimp(); 397 mii_tick(&sc->sc_mii); 398 splx(s); 399 400 timeout_add(&sc->sc_tick_ch, hz); 401 } 402 403 void 404 gem_reset(sc) 405 struct gem_softc *sc; 406 { 407 bus_space_tag_t t = sc->sc_bustag; 408 bus_space_handle_t h = sc->sc_h; 409 int i; 410 int s; 411 412 s = splimp(); 413 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 414 gem_reset_rx(sc); 415 gem_reset_tx(sc); 416 417 /* Do a full reset */ 418 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 419 for (i=TRIES; i--; delay(100)) 420 if ((bus_space_read_4(t, h, GEM_RESET) & 421 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 422 break; 423 if ((bus_space_read_4(t, h, GEM_RESET) & 424 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 425 printf("%s: cannot reset device\n", 426 sc->sc_dev.dv_xname); 427 } 428 splx(s); 429 } 430 431 432 /* 433 * gem_rxdrain: 434 * 435 * Drain the receive queue. 436 */ 437 void 438 gem_rxdrain(struct gem_softc *sc) 439 { 440 struct gem_rxsoft *rxs; 441 int i; 442 443 for (i = 0; i < GEM_NRXDESC; i++) { 444 rxs = &sc->sc_rxsoft[i]; 445 if (rxs->rxs_mbuf != NULL) { 446 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 447 m_freem(rxs->rxs_mbuf); 448 rxs->rxs_mbuf = NULL; 449 } 450 } 451 } 452 453 /* 454 * Reset the whole thing. 455 */ 456 void 457 gem_stop(struct ifnet *ifp, int disable) 458 { 459 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 460 struct gem_sxd *sd; 461 u_int32_t i; 462 463 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 464 465 timeout_del(&sc->sc_tick_ch); 466 mii_down(&sc->sc_mii); 467 468 gem_reset_rx(sc); 469 gem_reset_tx(sc); 470 471 /* 472 * Release any queued transmit buffers. 473 */ 474 for (i = 0; i < GEM_NTXDESC; i++) { 475 sd = &sc->sc_txd[i]; 476 if (sd->sd_mbuf != NULL) { 477 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 478 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 479 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 480 m_freem(sd->sd_mbuf); 481 sd->sd_mbuf = NULL; 482 } 483 } 484 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 485 486 if (disable) { 487 gem_rxdrain(sc); 488 } 489 490 /* 491 * Mark the interface down and cancel the watchdog timer. 492 */ 493 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 494 ifp->if_timer = 0; 495 } 496 497 498 /* 499 * Reset the receiver 500 */ 501 int 502 gem_reset_rx(struct gem_softc *sc) 503 { 504 bus_space_tag_t t = sc->sc_bustag; 505 bus_space_handle_t h = sc->sc_h; 506 int i; 507 508 /* 509 * Resetting while DMA is in progress can cause a bus hang, so we 510 * disable DMA first. 511 */ 512 gem_disable_rx(sc); 513 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 514 /* Wait till it finishes */ 515 for (i = TRIES; i--; delay(100)) 516 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 517 break; 518 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 519 printf("%s: cannot disable rx dma\n", 520 sc->sc_dev.dv_xname); 521 522 /* Wait 5ms extra. */ 523 delay(5000); 524 525 /* Finally, reset the ERX */ 526 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 527 /* Wait till it finishes */ 528 for (i = TRIES; i--; delay(100)) 529 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 530 break; 531 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 532 printf("%s: cannot reset receiver\n", 533 sc->sc_dev.dv_xname); 534 return (1); 535 } 536 return (0); 537 } 538 539 540 /* 541 * Reset the transmitter 542 */ 543 int 544 gem_reset_tx(struct gem_softc *sc) 545 { 546 bus_space_tag_t t = sc->sc_bustag; 547 bus_space_handle_t h = sc->sc_h; 548 int i; 549 550 /* 551 * Resetting while DMA is in progress can cause a bus hang, so we 552 * disable DMA first. 553 */ 554 gem_disable_tx(sc); 555 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 556 /* Wait till it finishes */ 557 for (i = TRIES; i--; delay(100)) 558 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 559 break; 560 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 561 printf("%s: cannot disable tx dma\n", 562 sc->sc_dev.dv_xname); 563 564 /* Wait 5ms extra. */ 565 delay(5000); 566 567 /* Finally, reset the ETX */ 568 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 569 /* Wait till it finishes */ 570 for (i = TRIES; i--; delay(100)) 571 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 572 break; 573 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 574 printf("%s: cannot reset transmitter\n", 575 sc->sc_dev.dv_xname); 576 return (1); 577 } 578 return (0); 579 } 580 581 /* 582 * disable receiver. 583 */ 584 int 585 gem_disable_rx(struct gem_softc *sc) 586 { 587 bus_space_tag_t t = sc->sc_bustag; 588 bus_space_handle_t h = sc->sc_h; 589 int i; 590 u_int32_t cfg; 591 592 /* Flip the enable bit */ 593 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 594 cfg &= ~GEM_MAC_RX_ENABLE; 595 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 596 597 /* Wait for it to finish */ 598 for (i = TRIES; i--; delay(100)) 599 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 600 GEM_MAC_RX_ENABLE) == 0) 601 return (0); 602 return (1); 603 } 604 605 /* 606 * disable transmitter. 607 */ 608 int 609 gem_disable_tx(struct gem_softc *sc) 610 { 611 bus_space_tag_t t = sc->sc_bustag; 612 bus_space_handle_t h = sc->sc_h; 613 int i; 614 u_int32_t cfg; 615 616 /* Flip the enable bit */ 617 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 618 cfg &= ~GEM_MAC_TX_ENABLE; 619 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 620 621 /* Wait for it to finish */ 622 for (i = TRIES; i--; delay(100)) 623 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 624 GEM_MAC_TX_ENABLE) == 0) 625 return (0); 626 return (1); 627 } 628 629 /* 630 * Initialize interface. 631 */ 632 int 633 gem_meminit(struct gem_softc *sc) 634 { 635 struct gem_rxsoft *rxs; 636 int i, error; 637 638 /* 639 * Initialize the transmit descriptor ring. 640 */ 641 for (i = 0; i < GEM_NTXDESC; i++) { 642 sc->sc_txdescs[i].gd_flags = 0; 643 sc->sc_txdescs[i].gd_addr = 0; 644 } 645 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 646 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 647 648 /* 649 * Initialize the receive descriptor and receive job 650 * descriptor rings. 651 */ 652 for (i = 0; i < GEM_NRXDESC; i++) { 653 rxs = &sc->sc_rxsoft[i]; 654 if (rxs->rxs_mbuf == NULL) { 655 if ((error = gem_add_rxbuf(sc, i)) != 0) { 656 printf("%s: unable to allocate or map rx " 657 "buffer %d, error = %d\n", 658 sc->sc_dev.dv_xname, i, error); 659 /* 660 * XXX Should attempt to run with fewer receive 661 * XXX buffers instead of just failing. 662 */ 663 gem_rxdrain(sc); 664 return (1); 665 } 666 } else 667 GEM_INIT_RXDESC(sc, i); 668 } 669 sc->sc_rxptr = 0; 670 671 return (0); 672 } 673 674 static int 675 gem_ringsize(int sz) 676 { 677 int v; 678 679 switch (sz) { 680 case 32: 681 v = GEM_RING_SZ_32; 682 break; 683 case 64: 684 v = GEM_RING_SZ_64; 685 break; 686 case 128: 687 v = GEM_RING_SZ_128; 688 break; 689 case 256: 690 v = GEM_RING_SZ_256; 691 break; 692 case 512: 693 v = GEM_RING_SZ_512; 694 break; 695 case 1024: 696 v = GEM_RING_SZ_1024; 697 break; 698 case 2048: 699 v = GEM_RING_SZ_2048; 700 break; 701 case 4096: 702 v = GEM_RING_SZ_4096; 703 break; 704 case 8192: 705 v = GEM_RING_SZ_8192; 706 break; 707 default: 708 v = GEM_RING_SZ_32; 709 printf("gem: invalid Receive Descriptor ring size\n"); 710 break; 711 } 712 return (v); 713 } 714 715 /* 716 * Initialization of interface; set up initialization block 717 * and transmit/receive descriptor rings. 718 */ 719 int 720 gem_init(struct ifnet *ifp) 721 { 722 723 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 724 bus_space_tag_t t = sc->sc_bustag; 725 bus_space_handle_t h = sc->sc_h; 726 int s; 727 u_int max_frame_size; 728 u_int32_t v; 729 730 s = splimp(); 731 732 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 733 /* 734 * Initialization sequence. The numbered steps below correspond 735 * to the sequence outlined in section 6.3.5.1 in the Ethernet 736 * Channel Engine manual (part of the PCIO manual). 737 * See also the STP2002-STQ document from Sun Microsystems. 738 */ 739 740 /* step 1 & 2. Reset the Ethernet Channel */ 741 gem_stop(ifp, 0); 742 gem_reset(sc); 743 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 744 745 /* Re-initialize the MIF */ 746 gem_mifinit(sc); 747 748 /* Call MI reset function if any */ 749 if (sc->sc_hwreset) 750 (*sc->sc_hwreset)(sc); 751 752 /* step 3. Setup data structures in host memory */ 753 gem_meminit(sc); 754 755 /* step 4. TX MAC registers & counters */ 756 gem_init_regs(sc); 757 max_frame_size = max(ifp->if_mtu, ETHERMTU); 758 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 759 #if 0 760 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 761 max_frame_size += ETHER_VLAN_ENCAP_LEN; 762 #endif 763 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 764 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 765 766 /* step 5. RX MAC registers & counters */ 767 gem_setladrf(sc); 768 769 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 770 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 771 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); 772 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 773 774 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 775 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); 776 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 777 778 /* step 8. Global Configuration & Interrupt Mask */ 779 bus_space_write_4(t, h, GEM_INTMASK, 780 ~(GEM_INTR_TX_INTME| 781 GEM_INTR_TX_EMPTY| 782 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 783 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 784 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 785 GEM_INTR_BERR)); 786 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 787 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 788 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 789 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 790 791 /* step 9. ETX Configuration: use mostly default values */ 792 793 /* Enable DMA */ 794 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 795 bus_space_write_4(t, h, GEM_TX_CONFIG, 796 v|GEM_TX_CONFIG_TXDMA_EN| 797 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 798 bus_space_write_4(t, h, GEM_TX_KICK, 0); 799 800 /* step 10. ERX Configuration */ 801 802 /* Encode Receive Descriptor ring size: four possible values */ 803 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 804 805 /* Enable DMA */ 806 bus_space_write_4(t, h, GEM_RX_CONFIG, 807 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 808 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 809 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 810 /* 811 * The following value is for an OFF Threshold of about 3/4 full 812 * and an ON Threshold of 1/4 full. 813 */ 814 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 815 (3 * sc->sc_rxfifosize / 256) | 816 ( (sc->sc_rxfifosize / 256) << 12)); 817 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 818 819 /* step 11. Configure Media */ 820 mii_mediachg(&sc->sc_mii); 821 822 /* step 12. RX_MAC Configuration Register */ 823 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 824 v |= GEM_MAC_RX_ENABLE; 825 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 826 827 /* step 14. Issue Transmit Pending command */ 828 829 /* Call MI initialization function if any */ 830 if (sc->sc_hwinit) 831 (*sc->sc_hwinit)(sc); 832 833 834 /* step 15. Give the receiver a swift kick */ 835 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 836 837 /* Start the one second timer. */ 838 timeout_add(&sc->sc_tick_ch, hz); 839 840 ifp->if_flags |= IFF_RUNNING; 841 ifp->if_flags &= ~IFF_OACTIVE; 842 ifp->if_timer = 0; 843 splx(s); 844 845 return (0); 846 } 847 848 void 849 gem_init_regs(struct gem_softc *sc) 850 { 851 bus_space_tag_t t = sc->sc_bustag; 852 bus_space_handle_t h = sc->sc_h; 853 u_int32_t v; 854 855 /* These regs are not cleared on reset */ 856 sc->sc_inited = 0; 857 if (!sc->sc_inited) { 858 859 /* Wooo. Magic values. */ 860 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 861 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 862 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 863 864 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 865 /* Max frame and max burst size */ 866 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 867 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 868 869 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 870 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 871 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 872 /* Dunno.... */ 873 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 874 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 875 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 876 877 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 878 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 879 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 880 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 881 /* MAC control addr set to 0:1:c2:0:1:80 */ 882 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 883 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 884 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 885 886 /* MAC filter addr set to 0:0:0:0:0:0 */ 887 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 888 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 889 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 890 891 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 892 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 893 894 sc->sc_inited = 1; 895 } 896 897 /* Counters need to be zeroed */ 898 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 899 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 900 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 901 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 902 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 903 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 904 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 905 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 906 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 907 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 908 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 909 910 /* Un-pause stuff */ 911 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 912 913 /* 914 * Set the station address. 915 */ 916 bus_space_write_4(t, h, GEM_MAC_ADDR0, 917 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 918 bus_space_write_4(t, h, GEM_MAC_ADDR1, 919 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 920 bus_space_write_4(t, h, GEM_MAC_ADDR2, 921 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 922 923 924 /* 925 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 926 */ 927 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 928 v = GEM_MAC_XIF_TX_MII_ENA; 929 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 930 v |= GEM_MAC_XIF_FDPLX_LED; 931 if (sc->sc_flags & GEM_GIGABIT) 932 v |= GEM_MAC_XIF_GMII_MODE; 933 } 934 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 935 } 936 937 /* 938 * Receive interrupt. 939 */ 940 int 941 gem_rint(sc) 942 struct gem_softc *sc; 943 { 944 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 945 bus_space_tag_t t = sc->sc_bustag; 946 bus_space_handle_t h = sc->sc_h; 947 struct ether_header *eh; 948 struct gem_rxsoft *rxs; 949 struct mbuf *m; 950 u_int64_t rxstat; 951 int i, len; 952 953 for (i = sc->sc_rxptr;; i = GEM_NEXTRX(i)) { 954 rxs = &sc->sc_rxsoft[i]; 955 956 GEM_CDRXSYNC(sc, i, 957 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 958 959 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 960 961 if (rxstat & GEM_RD_OWN) { 962 /* 963 * We have processed all of the receive buffers. 964 */ 965 break; 966 } 967 968 if (rxstat & GEM_RD_BAD_CRC) { 969 printf("%s: receive error: CRC error\n", 970 sc->sc_dev.dv_xname); 971 GEM_INIT_RXDESC(sc, i); 972 continue; 973 } 974 975 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 976 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 977 #ifdef GEM_DEBUG 978 if (ifp->if_flags & IFF_DEBUG) { 979 printf(" rxsoft %p descriptor %d: ", rxs, i); 980 printf("gd_flags: 0x%016llx\t", (long long) 981 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 982 printf("gd_addr: 0x%016llx\n", (long long) 983 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 984 } 985 #endif 986 987 /* 988 * No errors; receive the packet. Note the Gem 989 * includes the CRC with every packet. 990 */ 991 len = GEM_RD_BUFLEN(rxstat); 992 993 /* 994 * Allocate a new mbuf cluster. If that fails, we are 995 * out of memory, and must drop the packet and recycle 996 * the buffer that's already attached to this descriptor. 997 */ 998 m = rxs->rxs_mbuf; 999 if (gem_add_rxbuf(sc, i) != 0) { 1000 ifp->if_ierrors++; 1001 GEM_INIT_RXDESC(sc, i); 1002 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1003 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1004 continue; 1005 } 1006 m->m_data += 2; /* We're already off by two */ 1007 1008 ifp->if_ipackets++; 1009 eh = mtod(m, struct ether_header *); 1010 m->m_pkthdr.rcvif = ifp; 1011 m->m_pkthdr.len = m->m_len = len; 1012 1013 #if NBPFILTER > 0 1014 /* 1015 * Pass this up to any BPF listeners, but only 1016 * pass it up the stack if its for us. 1017 */ 1018 if (ifp->if_bpf) 1019 bpf_mtap(ifp->if_bpf, m); 1020 #endif /* NPBFILTER > 0 */ 1021 1022 /* Pass it on. */ 1023 ether_input_mbuf(ifp, m); 1024 } 1025 1026 /* Update the receive pointer. */ 1027 sc->sc_rxptr = i; 1028 bus_space_write_4(t, h, GEM_RX_KICK, i); 1029 1030 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1031 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1032 1033 return (1); 1034 } 1035 1036 1037 /* 1038 * gem_add_rxbuf: 1039 * 1040 * Add a receive buffer to the indicated descriptor. 1041 */ 1042 int 1043 gem_add_rxbuf(struct gem_softc *sc, int idx) 1044 { 1045 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1046 struct mbuf *m; 1047 int error; 1048 1049 MGETHDR(m, M_DONTWAIT, MT_DATA); 1050 if (m == NULL) 1051 return (ENOBUFS); 1052 1053 MCLGET(m, M_DONTWAIT); 1054 if ((m->m_flags & M_EXT) == 0) { 1055 m_freem(m); 1056 return (ENOBUFS); 1057 } 1058 1059 #ifdef GEM_DEBUG 1060 /* bzero the packet to check dma */ 1061 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1062 #endif 1063 1064 if (rxs->rxs_mbuf != NULL) 1065 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1066 1067 rxs->rxs_mbuf = m; 1068 1069 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1070 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1071 BUS_DMA_READ|BUS_DMA_NOWAIT); 1072 if (error) { 1073 printf("%s: can't load rx DMA map %d, error = %d\n", 1074 sc->sc_dev.dv_xname, idx, error); 1075 panic("gem_add_rxbuf"); /* XXX */ 1076 } 1077 1078 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1079 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1080 1081 GEM_INIT_RXDESC(sc, idx); 1082 1083 return (0); 1084 } 1085 1086 1087 int 1088 gem_eint(sc, status) 1089 struct gem_softc *sc; 1090 u_int status; 1091 { 1092 if ((status & GEM_INTR_MIF) != 0) { 1093 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1094 return (1); 1095 } 1096 1097 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS); 1098 return (1); 1099 } 1100 1101 1102 int 1103 gem_intr(v) 1104 void *v; 1105 { 1106 struct gem_softc *sc = (struct gem_softc *)v; 1107 bus_space_tag_t t = sc->sc_bustag; 1108 bus_space_handle_t seb = sc->sc_h; 1109 u_int32_t status; 1110 int r = 0; 1111 1112 status = bus_space_read_4(t, seb, GEM_STATUS); 1113 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n", 1114 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS)); 1115 1116 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1117 r |= gem_eint(sc, status); 1118 1119 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1120 r |= gem_tint(sc, status); 1121 1122 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1123 r |= gem_rint(sc); 1124 1125 /* We should eventually do more than just print out error stats. */ 1126 if (status & GEM_INTR_TX_MAC) { 1127 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1128 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1129 printf("%s: MAC tx fault, status %x\n", 1130 sc->sc_dev.dv_xname, txstat); 1131 } 1132 if (status & GEM_INTR_RX_MAC) { 1133 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1134 1135 rxstat &= ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1136 if (rxstat & GEM_MAC_RX_OVERFLOW) { 1137 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1138 1139 gem_init(ifp); 1140 ifp->if_ierrors++; 1141 } else { 1142 /* 1143 * Leave this in here until I figure out what to do 1144 * about other errors. 1145 */ 1146 printf("%s: MAC rx fault, status %x\n", 1147 sc->sc_dev.dv_xname, rxstat); 1148 } 1149 } 1150 return (r); 1151 } 1152 1153 1154 void 1155 gem_watchdog(ifp) 1156 struct ifnet *ifp; 1157 { 1158 struct gem_softc *sc = ifp->if_softc; 1159 1160 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1161 "GEM_MAC_RX_CONFIG %x\n", 1162 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1163 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1164 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1165 1166 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1167 ++ifp->if_oerrors; 1168 1169 /* Try to get more packets going. */ 1170 gem_init(ifp); 1171 } 1172 1173 /* 1174 * Initialize the MII Management Interface 1175 */ 1176 void 1177 gem_mifinit(sc) 1178 struct gem_softc *sc; 1179 { 1180 bus_space_tag_t t = sc->sc_bustag; 1181 bus_space_handle_t mif = sc->sc_h; 1182 1183 /* Configure the MIF in frame mode */ 1184 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1185 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1186 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1187 } 1188 1189 /* 1190 * MII interface 1191 * 1192 * The GEM MII interface supports at least three different operating modes: 1193 * 1194 * Bitbang mode is implemented using data, clock and output enable registers. 1195 * 1196 * Frame mode is implemented by loading a complete frame into the frame 1197 * register and polling the valid bit for completion. 1198 * 1199 * Polling mode uses the frame register but completion is indicated by 1200 * an interrupt. 1201 * 1202 */ 1203 static int 1204 gem_mii_readreg(self, phy, reg) 1205 struct device *self; 1206 int phy, reg; 1207 { 1208 struct gem_softc *sc = (void *)self; 1209 bus_space_tag_t t = sc->sc_bustag; 1210 bus_space_handle_t mif = sc->sc_h; 1211 int n; 1212 u_int32_t v; 1213 1214 #ifdef GEM_DEBUG1 1215 if (sc->sc_debug) 1216 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1217 #endif 1218 1219 /* Construct the frame command */ 1220 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1221 GEM_MIF_FRAME_READ; 1222 1223 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1224 for (n = 0; n < 100; n++) { 1225 DELAY(1); 1226 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1227 if (v & GEM_MIF_FRAME_TA0) 1228 return (v & GEM_MIF_FRAME_DATA); 1229 } 1230 1231 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1232 return (0); 1233 } 1234 1235 static void 1236 gem_mii_writereg(self, phy, reg, val) 1237 struct device *self; 1238 int phy, reg, val; 1239 { 1240 struct gem_softc *sc = (void *)self; 1241 bus_space_tag_t t = sc->sc_bustag; 1242 bus_space_handle_t mif = sc->sc_h; 1243 int n; 1244 u_int32_t v; 1245 1246 #ifdef GEM_DEBUG1 1247 if (sc->sc_debug) 1248 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1249 phy, reg, val); 1250 #endif 1251 1252 #if 0 1253 /* Select the desired PHY in the MIF configuration register */ 1254 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1255 /* Clear PHY select bit */ 1256 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1257 if (phy == GEM_PHYAD_EXTERNAL) 1258 /* Set PHY select bit to get at external device */ 1259 v |= GEM_MIF_CONFIG_PHY_SEL; 1260 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1261 #endif 1262 /* Construct the frame command */ 1263 v = GEM_MIF_FRAME_WRITE | 1264 (phy << GEM_MIF_PHY_SHIFT) | 1265 (reg << GEM_MIF_REG_SHIFT) | 1266 (val & GEM_MIF_FRAME_DATA); 1267 1268 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1269 for (n = 0; n < 100; n++) { 1270 DELAY(1); 1271 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1272 if (v & GEM_MIF_FRAME_TA0) 1273 return; 1274 } 1275 1276 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1277 } 1278 1279 static void 1280 gem_mii_statchg(dev) 1281 struct device *dev; 1282 { 1283 struct gem_softc *sc = (void *)dev; 1284 #ifdef GEM_DEBUG 1285 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1286 #endif 1287 bus_space_tag_t t = sc->sc_bustag; 1288 bus_space_handle_t mac = sc->sc_h; 1289 u_int32_t v; 1290 1291 #ifdef GEM_DEBUG 1292 if (sc->sc_debug) 1293 printf("gem_mii_statchg: status change: phy = %d\n", 1294 sc->sc_phys[instance]); 1295 #endif 1296 1297 1298 /* Set tx full duplex options */ 1299 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1300 delay(10000); /* reg must be cleared and delay before changing. */ 1301 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1302 GEM_MAC_TX_ENABLE; 1303 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1304 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1305 } 1306 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1307 1308 /* XIF Configuration */ 1309 /* We should really calculate all this rather than rely on defaults */ 1310 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1311 v = GEM_MAC_XIF_LINK_LED; 1312 v |= GEM_MAC_XIF_TX_MII_ENA; 1313 /* If an external transceiver is connected, enable its MII drivers */ 1314 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1315 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1316 /* External MII needs echo disable if half duplex. */ 1317 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1318 /* turn on full duplex LED */ 1319 v |= GEM_MAC_XIF_FDPLX_LED; 1320 else 1321 /* half duplex -- disable echo */ 1322 v |= GEM_MAC_XIF_ECHO_DISABL; 1323 1324 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1325 case IFM_1000_T: /* Gigabit using GMII interface */ 1326 v |= GEM_MAC_XIF_GMII_MODE; 1327 break; 1328 default: 1329 v &= ~GEM_MAC_XIF_GMII_MODE; 1330 } 1331 } else 1332 /* Internal MII needs buf enable */ 1333 v |= GEM_MAC_XIF_MII_BUF_ENA; 1334 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1335 } 1336 1337 int 1338 gem_mediachange(ifp) 1339 struct ifnet *ifp; 1340 { 1341 struct gem_softc *sc = ifp->if_softc; 1342 struct mii_data *mii = &sc->sc_mii; 1343 1344 if (mii->mii_instance) { 1345 struct mii_softc *miisc; 1346 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1347 miisc = LIST_NEXT(miisc, mii_list)) 1348 mii_phy_reset(miisc); 1349 } 1350 1351 return (mii_mediachg(&sc->sc_mii)); 1352 } 1353 1354 void 1355 gem_mediastatus(ifp, ifmr) 1356 struct ifnet *ifp; 1357 struct ifmediareq *ifmr; 1358 { 1359 struct gem_softc *sc = ifp->if_softc; 1360 1361 mii_pollstat(&sc->sc_mii); 1362 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1363 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1364 } 1365 1366 /* 1367 * Process an ioctl request. 1368 */ 1369 int 1370 gem_ioctl(ifp, cmd, data) 1371 struct ifnet *ifp; 1372 u_long cmd; 1373 caddr_t data; 1374 { 1375 struct gem_softc *sc = ifp->if_softc; 1376 struct ifaddr *ifa = (struct ifaddr *)data; 1377 struct ifreq *ifr = (struct ifreq *)data; 1378 int s, error = 0; 1379 1380 s = splimp(); 1381 1382 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 1383 splx(s); 1384 return (error); 1385 } 1386 1387 switch (cmd) { 1388 1389 case SIOCSIFADDR: 1390 ifp->if_flags |= IFF_UP; 1391 1392 switch (ifa->ifa_addr->sa_family) { 1393 #ifdef INET 1394 case AF_INET: 1395 gem_init(ifp); 1396 arp_ifinit(&sc->sc_arpcom, ifa); 1397 break; 1398 #endif 1399 #ifdef NS 1400 case AF_NS: 1401 { 1402 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1403 1404 if (ns_nullhost(*ina)) 1405 ina->x_host = 1406 *(union ns_host *)LLADDR(ifp->if_sadl); 1407 else { 1408 memcpy(LLADDR(ifp->if_sadl), 1409 ina->x_host.c_host, sizeof(sc->sc_enaddr)); 1410 } 1411 /* Set new address. */ 1412 gem_init(ifp); 1413 break; 1414 } 1415 #endif 1416 default: 1417 gem_init(ifp); 1418 break; 1419 } 1420 break; 1421 1422 case SIOCSIFFLAGS: 1423 if ((ifp->if_flags & IFF_UP) == 0 && 1424 (ifp->if_flags & IFF_RUNNING) != 0) { 1425 /* 1426 * If interface is marked down and it is running, then 1427 * stop it. 1428 */ 1429 gem_stop(ifp, 1); 1430 ifp->if_flags &= ~IFF_RUNNING; 1431 } else if ((ifp->if_flags & IFF_UP) != 0 && 1432 (ifp->if_flags & IFF_RUNNING) == 0) { 1433 /* 1434 * If interface is marked up and it is stopped, then 1435 * start it. 1436 */ 1437 gem_init(ifp); 1438 } else if ((ifp->if_flags & IFF_UP) != 0) { 1439 /* 1440 * Reset the interface to pick up changes in any other 1441 * flags that affect hardware registers. 1442 */ 1443 /*gem_stop(sc);*/ 1444 gem_init(ifp); 1445 } 1446 #ifdef HMEDEBUG 1447 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1448 #endif 1449 break; 1450 1451 case SIOCADDMULTI: 1452 case SIOCDELMULTI: 1453 error = (cmd == SIOCADDMULTI) ? 1454 ether_addmulti(ifr, &sc->sc_arpcom) : 1455 ether_delmulti(ifr, &sc->sc_arpcom); 1456 1457 if (error == ENETRESET) { 1458 /* 1459 * Multicast list has changed; set the hardware filter 1460 * accordingly. 1461 */ 1462 gem_init(ifp); 1463 error = 0; 1464 } 1465 break; 1466 1467 case SIOCGIFMEDIA: 1468 case SIOCSIFMEDIA: 1469 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1470 break; 1471 1472 default: 1473 error = EINVAL; 1474 break; 1475 } 1476 1477 splx(s); 1478 return (error); 1479 } 1480 1481 1482 void 1483 gem_shutdown(arg) 1484 void *arg; 1485 { 1486 struct gem_softc *sc = (struct gem_softc *)arg; 1487 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1488 1489 gem_stop(ifp, 1); 1490 } 1491 1492 /* 1493 * Set up the logical address filter. 1494 */ 1495 void 1496 gem_setladrf(sc) 1497 struct gem_softc *sc; 1498 { 1499 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1500 struct ether_multi *enm; 1501 struct ether_multistep step; 1502 struct arpcom *ac = &sc->sc_arpcom; 1503 bus_space_tag_t t = sc->sc_bustag; 1504 bus_space_handle_t h = sc->sc_h; 1505 u_int32_t crc, hash[16], v; 1506 int i; 1507 1508 /* Get current RX configuration */ 1509 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1510 1511 1512 /* 1513 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1514 * and hash filter. Depending on the case, the right bit will be 1515 * enabled. 1516 */ 1517 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1518 GEM_MAC_RX_PROMISC_GRP); 1519 1520 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1521 /* Turn on promiscuous mode */ 1522 v |= GEM_MAC_RX_PROMISCUOUS; 1523 ifp->if_flags |= IFF_ALLMULTI; 1524 goto chipit; 1525 } 1526 1527 /* 1528 * Set up multicast address filter by passing all multicast addresses 1529 * through a crc generator, and then using the high order 8 bits as an 1530 * index into the 256 bit logical address filter. The high order 4 1531 * bits select the word, while the other 4 bits select the bit within 1532 * the word (where bit 0 is the MSB). 1533 */ 1534 1535 /* Clear hash table */ 1536 for (i = 0; i < 16; i++) 1537 hash[i] = 0; 1538 1539 1540 ETHER_FIRST_MULTI(step, ac, enm); 1541 while (enm != NULL) { 1542 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1543 /* 1544 * We must listen to a range of multicast addresses. 1545 * For now, just accept all multicasts, rather than 1546 * trying to set only those filter bits needed to match 1547 * the range. (At this time, the only use of address 1548 * ranges is for IP multicast routing, for which the 1549 * range is big enough to require all bits set.) 1550 * XXX use the addr filter for this 1551 */ 1552 ifp->if_flags |= IFF_ALLMULTI; 1553 v |= GEM_MAC_RX_PROMISC_GRP; 1554 goto chipit; 1555 } 1556 1557 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1558 1559 /* Just want the 8 most significant bits. */ 1560 crc >>= 24; 1561 1562 /* Set the corresponding bit in the filter. */ 1563 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1564 1565 ETHER_NEXT_MULTI(step, enm); 1566 } 1567 1568 v |= GEM_MAC_RX_HASH_FILTER; 1569 ifp->if_flags &= ~IFF_ALLMULTI; 1570 1571 /* Now load the hash table into the chip (if we are using it) */ 1572 for (i = 0; i < 16; i++) { 1573 bus_space_write_4(t, h, 1574 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1575 hash[i]); 1576 } 1577 1578 chipit: 1579 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1580 } 1581 1582 int 1583 gem_encap(sc, mhead, bixp) 1584 struct gem_softc *sc; 1585 struct mbuf *mhead; 1586 u_int32_t *bixp; 1587 { 1588 u_int64_t flags; 1589 u_int32_t cur, frag, i; 1590 bus_dmamap_t map; 1591 1592 cur = frag = *bixp; 1593 map = sc->sc_txd[cur].sd_map; 1594 1595 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1596 BUS_DMA_NOWAIT) != 0) { 1597 return (ENOBUFS); 1598 } 1599 1600 if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) { 1601 bus_dmamap_unload(sc->sc_dmatag, map); 1602 return (ENOBUFS); 1603 } 1604 1605 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1606 BUS_DMASYNC_PREWRITE); 1607 1608 for (i = 0; i < map->dm_nsegs; i++) { 1609 sc->sc_txdescs[frag].gd_addr = 1610 GEM_DMA_WRITE(sc, map->dm_segs[i].ds_addr); 1611 flags = (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE) | 1612 (i == 0 ? GEM_TD_START_OF_PACKET : 0) | 1613 ((i == (map->dm_nsegs - 1)) ? GEM_TD_END_OF_PACKET : 0); 1614 sc->sc_txdescs[frag].gd_flags = GEM_DMA_WRITE(sc, flags); 1615 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1616 GEM_CDTXOFF(frag), sizeof(struct gem_desc), 1617 BUS_DMASYNC_PREWRITE); 1618 cur = frag; 1619 if (++frag == GEM_NTXDESC) 1620 frag = 0; 1621 } 1622 1623 sc->sc_tx_cnt += map->dm_nsegs; 1624 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1625 sc->sc_txd[cur].sd_map = map; 1626 sc->sc_txd[cur].sd_mbuf = mhead; 1627 1628 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, frag); 1629 1630 *bixp = frag; 1631 1632 /* sync descriptors */ 1633 1634 return (0); 1635 } 1636 1637 /* 1638 * Transmit interrupt. 1639 */ 1640 int 1641 gem_tint(sc, status) 1642 struct gem_softc *sc; 1643 u_int32_t status; 1644 { 1645 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1646 struct gem_sxd *sd; 1647 u_int32_t cons, hwcons; 1648 1649 hwcons = status >> 19; 1650 cons = sc->sc_tx_cons; 1651 while (cons != hwcons) { 1652 sd = &sc->sc_txd[cons]; 1653 if (sd->sd_mbuf != NULL) { 1654 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1655 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1656 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1657 m_freem(sd->sd_mbuf); 1658 sd->sd_mbuf = NULL; 1659 } 1660 sc->sc_tx_cnt--; 1661 ifp->if_opackets++; 1662 if (++cons == GEM_NTXDESC) 1663 cons = 0; 1664 } 1665 sc->sc_tx_cons = cons; 1666 1667 gem_start(ifp); 1668 1669 if (sc->sc_tx_cnt == 0) 1670 ifp->if_timer = 0; 1671 1672 return (1); 1673 } 1674 1675 void 1676 gem_start(ifp) 1677 struct ifnet *ifp; 1678 { 1679 struct gem_softc *sc = ifp->if_softc; 1680 struct mbuf *m; 1681 u_int32_t bix; 1682 1683 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1684 return; 1685 1686 bix = sc->sc_tx_prod; 1687 while (sc->sc_txd[bix].sd_mbuf == NULL) { 1688 IFQ_POLL(&ifp->if_snd, m); 1689 if (m == NULL) 1690 break; 1691 1692 #if NBPFILTER > 0 1693 /* 1694 * If BPF is listening on this interface, let it see the 1695 * packet before we commit it to the wire. 1696 */ 1697 if (ifp->if_bpf) 1698 bpf_mtap(ifp->if_bpf, m); 1699 #endif 1700 1701 /* 1702 * Encapsulate this packet and start it going... 1703 * or fail... 1704 */ 1705 if (gem_encap(sc, m, &bix)) { 1706 ifp->if_timer = 2; 1707 break; 1708 } 1709 1710 IFQ_DEQUEUE(&ifp->if_snd, m); 1711 ifp->if_timer = 5; 1712 } 1713 1714 sc->sc_tx_prod = bix; 1715 } 1716