1 /* $OpenBSD: gem.c,v 1.122 2017/06/08 01:34:00 dlg Exp $ */ 2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/timeout.h> 42 #include <sys/mbuf.h> 43 #include <sys/syslog.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/endian.h> 51 #include <sys/atomic.h> 52 53 #include <net/if.h> 54 #include <net/if_media.h> 55 56 #include <netinet/in.h> 57 #include <netinet/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/ic/gemreg.h> 70 #include <dev/ic/gemvar.h> 71 72 #define TRIES 10000 73 74 struct cfdriver gem_cd = { 75 NULL, "gem", DV_IFNET 76 }; 77 78 void gem_start(struct ifqueue *); 79 void gem_stop(struct ifnet *, int); 80 int gem_ioctl(struct ifnet *, u_long, caddr_t); 81 void gem_tick(void *); 82 void gem_watchdog(struct ifnet *); 83 int gem_init(struct ifnet *); 84 void gem_init_regs(struct gem_softc *); 85 int gem_ringsize(int); 86 int gem_meminit(struct gem_softc *); 87 void gem_mifinit(struct gem_softc *); 88 int gem_bitwait(struct gem_softc *, bus_space_handle_t, int, 89 u_int32_t, u_int32_t); 90 void gem_reset(struct gem_softc *); 91 int gem_reset_rx(struct gem_softc *); 92 int gem_reset_tx(struct gem_softc *); 93 int gem_disable_rx(struct gem_softc *); 94 int gem_disable_tx(struct gem_softc *); 95 void gem_rx_watchdog(void *); 96 void gem_rxdrain(struct gem_softc *); 97 void gem_fill_rx_ring(struct gem_softc *); 98 int gem_add_rxbuf(struct gem_softc *, int idx); 99 int gem_load_mbuf(struct gem_softc *, struct gem_sxd *, 100 struct mbuf *); 101 void gem_iff(struct gem_softc *); 102 103 /* MII methods & callbacks */ 104 int gem_mii_readreg(struct device *, int, int); 105 void gem_mii_writereg(struct device *, int, int, int); 106 void gem_mii_statchg(struct device *); 107 int gem_pcs_readreg(struct device *, int, int); 108 void gem_pcs_writereg(struct device *, int, int, int); 109 110 int gem_mediachange(struct ifnet *); 111 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 112 113 int gem_eint(struct gem_softc *, u_int); 114 int gem_rint(struct gem_softc *); 115 int gem_tint(struct gem_softc *, u_int32_t); 116 int gem_pint(struct gem_softc *); 117 118 #ifdef GEM_DEBUG 119 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 120 printf x 121 #else 122 #define DPRINTF(sc, x) /* nothing */ 123 #endif 124 125 /* 126 * Attach a Gem interface to the system. 127 */ 128 void 129 gem_config(struct gem_softc *sc) 130 { 131 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 132 struct mii_data *mii = &sc->sc_mii; 133 struct mii_softc *child; 134 int i, error, mii_flags, phyad; 135 struct ifmedia_entry *ifm; 136 137 /* Make sure the chip is stopped. */ 138 ifp->if_softc = sc; 139 gem_reset(sc); 140 141 /* 142 * Allocate the control data structures, and create and load the 143 * DMA map for it. 144 */ 145 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 146 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 147 1, &sc->sc_cdnseg, 0)) != 0) { 148 printf("\n%s: unable to allocate control data, error = %d\n", 149 sc->sc_dev.dv_xname, error); 150 goto fail_0; 151 } 152 153 /* XXX should map this in with correct endianness */ 154 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 155 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 156 BUS_DMA_COHERENT)) != 0) { 157 printf("\n%s: unable to map control data, error = %d\n", 158 sc->sc_dev.dv_xname, error); 159 goto fail_1; 160 } 161 162 if ((error = bus_dmamap_create(sc->sc_dmatag, 163 sizeof(struct gem_control_data), 1, 164 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 165 printf("\n%s: unable to create control data DMA map, " 166 "error = %d\n", sc->sc_dev.dv_xname, error); 167 goto fail_2; 168 } 169 170 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 171 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 172 0)) != 0) { 173 printf("\n%s: unable to load control data DMA map, error = %d\n", 174 sc->sc_dev.dv_xname, error); 175 goto fail_3; 176 } 177 178 /* 179 * Create the receive buffer DMA maps. 180 */ 181 for (i = 0; i < GEM_NRXDESC; i++) { 182 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 183 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 184 printf("\n%s: unable to create rx DMA map %d, " 185 "error = %d\n", sc->sc_dev.dv_xname, i, error); 186 goto fail_5; 187 } 188 sc->sc_rxsoft[i].rxs_mbuf = NULL; 189 } 190 /* 191 * Create the transmit buffer DMA maps. 192 */ 193 for (i = 0; i < GEM_NTXDESC; i++) { 194 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 195 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 196 &sc->sc_txd[i].sd_map)) != 0) { 197 printf("\n%s: unable to create tx DMA map %d, " 198 "error = %d\n", sc->sc_dev.dv_xname, i, error); 199 goto fail_6; 200 } 201 sc->sc_txd[i].sd_mbuf = NULL; 202 } 203 204 /* 205 * From this point forward, the attachment cannot fail. A failure 206 * before this point releases all resources that may have been 207 * allocated. 208 */ 209 210 /* Announce ourselves. */ 211 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 212 213 /* Get RX FIFO size */ 214 sc->sc_rxfifosize = 64 * 215 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_FIFO_SIZE); 216 217 /* Initialize ifnet structure. */ 218 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 219 ifp->if_softc = sc; 220 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 221 ifp->if_xflags = IFXF_MPSAFE; 222 ifp->if_qstart = gem_start; 223 ifp->if_ioctl = gem_ioctl; 224 ifp->if_watchdog = gem_watchdog; 225 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_NTXDESC - 1); 226 227 ifp->if_capabilities = IFCAP_VLAN_MTU; 228 229 /* Initialize ifmedia structures and MII info */ 230 mii->mii_ifp = ifp; 231 mii->mii_readreg = gem_mii_readreg; 232 mii->mii_writereg = gem_mii_writereg; 233 mii->mii_statchg = gem_mii_statchg; 234 235 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 236 237 /* Bad things will happen if we touch this register on ERI. */ 238 if (sc->sc_variant != GEM_SUN_ERI) 239 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 240 GEM_MII_DATAPATH_MODE, 0); 241 242 gem_mifinit(sc); 243 244 mii_flags = MIIF_DOPAUSE; 245 246 /* 247 * Look for an external PHY. 248 */ 249 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 250 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 251 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 252 GEM_MIF_CONFIG, sc->sc_mif_config); 253 254 switch (sc->sc_variant) { 255 case GEM_SUN_ERI: 256 phyad = GEM_PHYAD_EXTERNAL; 257 break; 258 default: 259 phyad = MII_PHY_ANY; 260 break; 261 } 262 263 mii_attach(&sc->sc_dev, mii, 0xffffffff, phyad, 264 MII_OFFSET_ANY, mii_flags); 265 } 266 267 /* 268 * Fall back on an internal PHY if no external PHY was found. 269 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 270 * trusted when the firmware has powered down the chip 271 */ 272 child = LIST_FIRST(&mii->mii_phys); 273 if (child == NULL && 274 (sc->sc_mif_config & GEM_MIF_CONFIG_MDI0 || GEM_IS_APPLE(sc))) { 275 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 276 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 277 GEM_MIF_CONFIG, sc->sc_mif_config); 278 279 switch (sc->sc_variant) { 280 case GEM_SUN_ERI: 281 case GEM_APPLE_K2_GMAC: 282 phyad = GEM_PHYAD_INTERNAL; 283 break; 284 case GEM_APPLE_GMAC: 285 phyad = GEM_PHYAD_EXTERNAL; 286 break; 287 default: 288 phyad = MII_PHY_ANY; 289 break; 290 } 291 292 mii_attach(&sc->sc_dev, mii, 0xffffffff, phyad, 293 MII_OFFSET_ANY, mii_flags); 294 } 295 296 /* 297 * Try the external PCS SERDES if we didn't find any MII 298 * devices. 299 */ 300 child = LIST_FIRST(&mii->mii_phys); 301 if (child == NULL && sc->sc_variant != GEM_SUN_ERI) { 302 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 303 GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_SERDES); 304 305 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 306 GEM_MII_SLINK_CONTROL, 307 GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D); 308 309 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 310 GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 311 312 mii->mii_readreg = gem_pcs_readreg; 313 mii->mii_writereg = gem_pcs_writereg; 314 315 mii_flags |= MIIF_NOISOLATE; 316 317 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 318 MII_OFFSET_ANY, mii_flags); 319 } 320 321 child = LIST_FIRST(&mii->mii_phys); 322 if (child == NULL) { 323 /* No PHY attached */ 324 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 325 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 326 } else { 327 /* 328 * XXX - we can really do the following ONLY if the 329 * phy indeed has the auto negotiation capability!! 330 */ 331 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 332 } 333 334 /* Check if we support GigE media. */ 335 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 336 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 337 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 338 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 339 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 340 sc->sc_flags |= GEM_GIGABIT; 341 break; 342 } 343 } 344 345 /* Attach the interface. */ 346 if_attach(ifp); 347 ether_ifattach(ifp); 348 349 timeout_set(&sc->sc_tick_ch, gem_tick, sc); 350 timeout_set(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 351 return; 352 353 /* 354 * Free any resources we've allocated during the failed attach 355 * attempt. Do this in reverse order and fall through. 356 */ 357 fail_6: 358 for (i = 0; i < GEM_NTXDESC; i++) { 359 if (sc->sc_txd[i].sd_map != NULL) 360 bus_dmamap_destroy(sc->sc_dmatag, 361 sc->sc_txd[i].sd_map); 362 } 363 fail_5: 364 for (i = 0; i < GEM_NRXDESC; i++) { 365 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 366 bus_dmamap_destroy(sc->sc_dmatag, 367 sc->sc_rxsoft[i].rxs_dmamap); 368 } 369 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 370 fail_3: 371 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 372 fail_2: 373 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 374 sizeof(struct gem_control_data)); 375 fail_1: 376 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 377 fail_0: 378 return; 379 } 380 381 void 382 gem_unconfig(struct gem_softc *sc) 383 { 384 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 385 int i; 386 387 gem_stop(ifp, 1); 388 389 for (i = 0; i < GEM_NTXDESC; i++) { 390 if (sc->sc_txd[i].sd_map != NULL) 391 bus_dmamap_destroy(sc->sc_dmatag, 392 sc->sc_txd[i].sd_map); 393 } 394 for (i = 0; i < GEM_NRXDESC; i++) { 395 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 396 bus_dmamap_destroy(sc->sc_dmatag, 397 sc->sc_rxsoft[i].rxs_dmamap); 398 } 399 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 400 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 401 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 402 sizeof(struct gem_control_data)); 403 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 404 405 /* Detach all PHYs */ 406 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 407 408 /* Delete all remaining media. */ 409 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 410 411 ether_ifdetach(ifp); 412 if_detach(ifp); 413 } 414 415 416 void 417 gem_tick(void *arg) 418 { 419 struct gem_softc *sc = arg; 420 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 421 bus_space_tag_t t = sc->sc_bustag; 422 bus_space_handle_t mac = sc->sc_h1; 423 int s; 424 u_int32_t v; 425 426 /* unload collisions counters */ 427 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 428 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 429 ifp->if_collisions += v + 430 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 431 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 432 ifp->if_oerrors += v; 433 434 /* read error counters */ 435 ifp->if_ierrors += 436 bus_space_read_4(t, mac, GEM_MAC_RX_LEN_ERR_CNT) + 437 bus_space_read_4(t, mac, GEM_MAC_RX_ALIGN_ERR) + 438 bus_space_read_4(t, mac, GEM_MAC_RX_CRC_ERR_CNT) + 439 bus_space_read_4(t, mac, GEM_MAC_RX_CODE_VIOL); 440 441 /* clear the hardware counters */ 442 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 443 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 444 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 445 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 446 bus_space_write_4(t, mac, GEM_MAC_RX_LEN_ERR_CNT, 0); 447 bus_space_write_4(t, mac, GEM_MAC_RX_ALIGN_ERR, 0); 448 bus_space_write_4(t, mac, GEM_MAC_RX_CRC_ERR_CNT, 0); 449 bus_space_write_4(t, mac, GEM_MAC_RX_CODE_VIOL, 0); 450 451 s = splnet(); 452 mii_tick(&sc->sc_mii); 453 splx(s); 454 455 timeout_add_sec(&sc->sc_tick_ch, 1); 456 } 457 458 int 459 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, 460 u_int32_t clr, u_int32_t set) 461 { 462 int i; 463 u_int32_t reg; 464 465 for (i = TRIES; i--; DELAY(100)) { 466 reg = bus_space_read_4(sc->sc_bustag, h, r); 467 if ((reg & clr) == 0 && (reg & set) == set) 468 return (1); 469 } 470 471 return (0); 472 } 473 474 void 475 gem_reset(struct gem_softc *sc) 476 { 477 bus_space_tag_t t = sc->sc_bustag; 478 bus_space_handle_t h = sc->sc_h2; 479 int s; 480 481 s = splnet(); 482 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 483 gem_reset_rx(sc); 484 gem_reset_tx(sc); 485 486 /* Do a full reset */ 487 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 488 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 489 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 490 splx(s); 491 } 492 493 494 /* 495 * Drain the receive queue. 496 */ 497 void 498 gem_rxdrain(struct gem_softc *sc) 499 { 500 struct gem_rxsoft *rxs; 501 int i; 502 503 for (i = 0; i < GEM_NRXDESC; i++) { 504 rxs = &sc->sc_rxsoft[i]; 505 if (rxs->rxs_mbuf != NULL) { 506 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 507 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 508 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 509 m_freem(rxs->rxs_mbuf); 510 rxs->rxs_mbuf = NULL; 511 } 512 } 513 sc->sc_rx_prod = sc->sc_rx_cons = 0; 514 } 515 516 /* 517 * Reset the whole thing. 518 */ 519 void 520 gem_stop(struct ifnet *ifp, int softonly) 521 { 522 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 523 struct gem_sxd *sd; 524 u_int32_t i; 525 526 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 527 528 timeout_del(&sc->sc_tick_ch); 529 530 /* 531 * Mark the interface down and cancel the watchdog timer. 532 */ 533 ifp->if_flags &= ~IFF_RUNNING; 534 ifq_clr_oactive(&ifp->if_snd); 535 ifp->if_timer = 0; 536 537 if (!softonly) { 538 mii_down(&sc->sc_mii); 539 540 gem_reset_rx(sc); 541 gem_reset_tx(sc); 542 } 543 544 intr_barrier(sc->sc_ih); 545 ifq_barrier(&ifp->if_snd); 546 547 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 548 549 /* 550 * Release any queued transmit buffers. 551 */ 552 for (i = 0; i < GEM_NTXDESC; i++) { 553 sd = &sc->sc_txd[i]; 554 if (sd->sd_mbuf != NULL) { 555 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 556 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 557 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 558 m_freem(sd->sd_mbuf); 559 sd->sd_mbuf = NULL; 560 } 561 } 562 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 563 564 gem_rxdrain(sc); 565 } 566 567 568 /* 569 * Reset the receiver 570 */ 571 int 572 gem_reset_rx(struct gem_softc *sc) 573 { 574 bus_space_tag_t t = sc->sc_bustag; 575 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 576 577 /* 578 * Resetting while DMA is in progress can cause a bus hang, so we 579 * disable DMA first. 580 */ 581 gem_disable_rx(sc); 582 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 583 /* Wait till it finishes */ 584 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 585 printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname); 586 /* Wait 5ms extra. */ 587 delay(5000); 588 589 /* Finally, reset the ERX */ 590 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 591 /* Wait till it finishes */ 592 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 593 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 594 return (1); 595 } 596 return (0); 597 } 598 599 600 /* 601 * Reset the transmitter 602 */ 603 int 604 gem_reset_tx(struct gem_softc *sc) 605 { 606 bus_space_tag_t t = sc->sc_bustag; 607 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 608 609 /* 610 * Resetting while DMA is in progress can cause a bus hang, so we 611 * disable DMA first. 612 */ 613 gem_disable_tx(sc); 614 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 615 /* Wait till it finishes */ 616 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 617 printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname); 618 /* Wait 5ms extra. */ 619 delay(5000); 620 621 /* Finally, reset the ETX */ 622 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 623 /* Wait till it finishes */ 624 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 625 printf("%s: cannot reset transmitter\n", 626 sc->sc_dev.dv_xname); 627 return (1); 628 } 629 return (0); 630 } 631 632 /* 633 * Disable receiver. 634 */ 635 int 636 gem_disable_rx(struct gem_softc *sc) 637 { 638 bus_space_tag_t t = sc->sc_bustag; 639 bus_space_handle_t h = sc->sc_h1; 640 u_int32_t cfg; 641 642 /* Flip the enable bit */ 643 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 644 cfg &= ~GEM_MAC_RX_ENABLE; 645 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 646 647 /* Wait for it to finish */ 648 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 649 } 650 651 /* 652 * Disable transmitter. 653 */ 654 int 655 gem_disable_tx(struct gem_softc *sc) 656 { 657 bus_space_tag_t t = sc->sc_bustag; 658 bus_space_handle_t h = sc->sc_h1; 659 u_int32_t cfg; 660 661 /* Flip the enable bit */ 662 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 663 cfg &= ~GEM_MAC_TX_ENABLE; 664 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 665 666 /* Wait for it to finish */ 667 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 668 } 669 670 /* 671 * Initialize interface. 672 */ 673 int 674 gem_meminit(struct gem_softc *sc) 675 { 676 int i; 677 678 /* 679 * Initialize the transmit descriptor ring. 680 */ 681 for (i = 0; i < GEM_NTXDESC; i++) { 682 sc->sc_txdescs[i].gd_flags = 0; 683 sc->sc_txdescs[i].gd_addr = 0; 684 } 685 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 686 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 687 688 /* 689 * Initialize the receive descriptor and receive job 690 * descriptor rings. 691 */ 692 for (i = 0; i < GEM_NRXDESC; i++) { 693 sc->sc_rxdescs[i].gd_flags = 0; 694 sc->sc_rxdescs[i].gd_addr = 0; 695 } 696 /* Hardware reads RX descriptors in multiples of four. */ 697 if_rxr_init(&sc->sc_rx_ring, 4, GEM_NRXDESC - 4); 698 gem_fill_rx_ring(sc); 699 700 return (0); 701 } 702 703 int 704 gem_ringsize(int sz) 705 { 706 switch (sz) { 707 case 32: 708 return GEM_RING_SZ_32; 709 case 64: 710 return GEM_RING_SZ_64; 711 case 128: 712 return GEM_RING_SZ_128; 713 case 256: 714 return GEM_RING_SZ_256; 715 case 512: 716 return GEM_RING_SZ_512; 717 case 1024: 718 return GEM_RING_SZ_1024; 719 case 2048: 720 return GEM_RING_SZ_2048; 721 case 4096: 722 return GEM_RING_SZ_4096; 723 case 8192: 724 return GEM_RING_SZ_8192; 725 default: 726 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 727 return GEM_RING_SZ_32; 728 } 729 } 730 731 /* 732 * Initialization of interface; set up initialization block 733 * and transmit/receive descriptor rings. 734 */ 735 int 736 gem_init(struct ifnet *ifp) 737 { 738 739 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 740 bus_space_tag_t t = sc->sc_bustag; 741 bus_space_handle_t h = sc->sc_h1; 742 int s; 743 u_int32_t v; 744 745 s = splnet(); 746 747 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 748 /* 749 * Initialization sequence. The numbered steps below correspond 750 * to the sequence outlined in section 6.3.5.1 in the Ethernet 751 * Channel Engine manual (part of the PCIO manual). 752 * See also the STP2002-STQ document from Sun Microsystems. 753 */ 754 755 /* step 1 & 2. Reset the Ethernet Channel */ 756 gem_stop(ifp, 0); 757 gem_reset(sc); 758 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 759 760 /* Re-initialize the MIF */ 761 gem_mifinit(sc); 762 763 /* Call MI reset function if any */ 764 if (sc->sc_hwreset) 765 (*sc->sc_hwreset)(sc); 766 767 /* step 3. Setup data structures in host memory */ 768 gem_meminit(sc); 769 770 /* step 4. TX MAC registers & counters */ 771 gem_init_regs(sc); 772 773 /* step 5. RX MAC registers & counters */ 774 gem_iff(sc); 775 776 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 777 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 778 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); 779 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 780 781 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 782 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); 783 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 784 785 /* step 8. Global Configuration & Interrupt Mask */ 786 bus_space_write_4(t, h, GEM_INTMASK, 787 ~(GEM_INTR_TX_INTME| 788 GEM_INTR_TX_EMPTY| 789 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 790 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 791 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 792 GEM_INTR_BERR)); 793 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 794 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 795 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 796 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 797 798 /* step 9. ETX Configuration: use mostly default values */ 799 800 /* Enable DMA */ 801 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 802 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x04ff) << 10) & 803 GEM_TX_CONFIG_TXFIFO_TH; 804 bus_space_write_4(t, h, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 805 bus_space_write_4(t, h, GEM_TX_KICK, 0); 806 807 /* step 10. ERX Configuration */ 808 809 /* Encode Receive Descriptor ring size: four possible values */ 810 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 811 /* Enable DMA */ 812 bus_space_write_4(t, h, GEM_RX_CONFIG, 813 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 814 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 815 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 816 /* 817 * The following value is for an OFF Threshold of about 3/4 full 818 * and an ON Threshold of 1/4 full. 819 */ 820 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 821 (3 * sc->sc_rxfifosize / 256) | 822 ((sc->sc_rxfifosize / 256) << 12)); 823 bus_space_write_4(t, h, GEM_RX_BLANKING, (6 << 12) | 6); 824 825 /* step 11. Configure Media */ 826 mii_mediachg(&sc->sc_mii); 827 828 /* step 12. RX_MAC Configuration Register */ 829 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 830 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 831 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 832 833 /* step 14. Issue Transmit Pending command */ 834 835 /* Call MI initialization function if any */ 836 if (sc->sc_hwinit) 837 (*sc->sc_hwinit)(sc); 838 839 /* step 15. Give the receiver a swift kick */ 840 bus_space_write_4(t, h, GEM_RX_KICK, sc->sc_rx_prod); 841 842 /* Start the one second timer. */ 843 timeout_add_sec(&sc->sc_tick_ch, 1); 844 845 ifp->if_flags |= IFF_RUNNING; 846 ifq_clr_oactive(&ifp->if_snd); 847 848 splx(s); 849 850 return (0); 851 } 852 853 void 854 gem_init_regs(struct gem_softc *sc) 855 { 856 bus_space_tag_t t = sc->sc_bustag; 857 bus_space_handle_t h = sc->sc_h1; 858 u_int32_t v; 859 860 /* These regs are not cleared on reset */ 861 sc->sc_inited = 0; 862 if (!sc->sc_inited) { 863 /* Load recommended values */ 864 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 865 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 866 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 867 868 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 869 /* Max frame and max burst size */ 870 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 871 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 872 873 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 874 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 875 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 876 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 877 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 878 ((sc->sc_arpcom.ac_enaddr[5]<<8)|sc->sc_arpcom.ac_enaddr[4])&0x3ff); 879 880 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 881 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 882 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 883 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 884 885 /* MAC control addr set to 0:1:c2:0:1:80 */ 886 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 887 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 888 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 889 890 /* MAC filter addr set to 0:0:0:0:0:0 */ 891 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 892 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 893 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 894 895 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 896 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 897 898 sc->sc_inited = 1; 899 } 900 901 /* Counters need to be zeroed */ 902 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 903 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 904 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 905 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 906 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 907 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 908 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 909 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 910 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 911 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 912 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 913 914 /* Set XOFF PAUSE time */ 915 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1bf0); 916 917 /* 918 * Set the internal arbitration to "infinite" bursts of the 919 * maximum length of 31 * 64 bytes so DMA transfers aren't 920 * split up in cache line size chunks. This greatly improves 921 * especially RX performance. 922 * Enable silicon bug workarounds for the Apple variants. 923 */ 924 v = GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT; 925 if (sc->sc_pci) 926 v |= GEM_CONFIG_BURST_INF; 927 else 928 v |= GEM_CONFIG_BURST_64; 929 if (sc->sc_variant != GEM_SUN_GEM && sc->sc_variant != GEM_SUN_ERI) 930 v |= GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX; 931 bus_space_write_4(t, h, GEM_CONFIG, v); 932 933 /* 934 * Set the station address. 935 */ 936 bus_space_write_4(t, h, GEM_MAC_ADDR0, 937 (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); 938 bus_space_write_4(t, h, GEM_MAC_ADDR1, 939 (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); 940 bus_space_write_4(t, h, GEM_MAC_ADDR2, 941 (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); 942 } 943 944 /* 945 * Receive interrupt. 946 */ 947 int 948 gem_rint(struct gem_softc *sc) 949 { 950 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 951 bus_space_tag_t t = sc->sc_bustag; 952 bus_space_handle_t h = sc->sc_h1; 953 struct gem_rxsoft *rxs; 954 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 955 struct mbuf *m; 956 u_int64_t rxstat; 957 int i, len; 958 959 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 960 return (0); 961 962 for (i = sc->sc_rx_cons; if_rxr_inuse(&sc->sc_rx_ring) > 0; 963 i = GEM_NEXTRX(i)) { 964 rxs = &sc->sc_rxsoft[i]; 965 966 GEM_CDRXSYNC(sc, i, 967 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 968 969 rxstat = GEM_DMA_READ(sc, &sc->sc_rxdescs[i].gd_flags); 970 971 if (rxstat & GEM_RD_OWN) { 972 /* We have processed all of the receive buffers. */ 973 break; 974 } 975 976 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 977 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 978 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 979 980 m = rxs->rxs_mbuf; 981 rxs->rxs_mbuf = NULL; 982 983 if_rxr_put(&sc->sc_rx_ring, 1); 984 985 if (rxstat & GEM_RD_BAD_CRC) { 986 ifp->if_ierrors++; 987 #ifdef GEM_DEBUG 988 printf("%s: receive error: CRC error\n", 989 sc->sc_dev.dv_xname); 990 #endif 991 m_freem(m); 992 continue; 993 } 994 995 #ifdef GEM_DEBUG 996 if (ifp->if_flags & IFF_DEBUG) { 997 printf(" rxsoft %p descriptor %d: ", rxs, i); 998 printf("gd_flags: 0x%016llx\t", (long long) 999 GEM_DMA_READ(sc, &sc->sc_rxdescs[i].gd_flags)); 1000 printf("gd_addr: 0x%016llx\n", (long long) 1001 GEM_DMA_READ(sc, &sc->sc_rxdescs[i].gd_addr)); 1002 } 1003 #endif 1004 1005 /* No errors; receive the packet. */ 1006 len = GEM_RD_BUFLEN(rxstat); 1007 1008 m->m_data += 2; /* We're already off by two */ 1009 m->m_pkthdr.len = m->m_len = len; 1010 1011 ml_enqueue(&ml, m); 1012 } 1013 1014 /* Update the receive pointer. */ 1015 sc->sc_rx_cons = i; 1016 gem_fill_rx_ring(sc); 1017 bus_space_write_4(t, h, GEM_RX_KICK, sc->sc_rx_prod); 1018 1019 DPRINTF(sc, ("gem_rint: done sc->sc_rx_cons %d, complete %d\n", 1020 sc->sc_rx_cons, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1021 1022 if_input(ifp, &ml); 1023 1024 return (1); 1025 } 1026 1027 void 1028 gem_fill_rx_ring(struct gem_softc *sc) 1029 { 1030 u_int slots; 1031 1032 for (slots = if_rxr_get(&sc->sc_rx_ring, GEM_NRXDESC - 4); 1033 slots > 0; slots--) { 1034 if (gem_add_rxbuf(sc, sc->sc_rx_prod)) 1035 break; 1036 } 1037 if_rxr_put(&sc->sc_rx_ring, slots); 1038 } 1039 1040 /* 1041 * Add a receive buffer to the indicated descriptor. 1042 */ 1043 int 1044 gem_add_rxbuf(struct gem_softc *sc, int idx) 1045 { 1046 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1047 struct mbuf *m; 1048 int error; 1049 1050 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1051 if (!m) 1052 return (ENOBUFS); 1053 m->m_len = m->m_pkthdr.len = MCLBYTES; 1054 1055 #ifdef GEM_DEBUG 1056 /* bzero the packet to check dma */ 1057 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1058 #endif 1059 1060 rxs->rxs_mbuf = m; 1061 1062 error = bus_dmamap_load_mbuf(sc->sc_dmatag, rxs->rxs_dmamap, m, 1063 BUS_DMA_READ|BUS_DMA_NOWAIT); 1064 if (error) { 1065 printf("%s: can't load rx DMA map %d, error = %d\n", 1066 sc->sc_dev.dv_xname, idx, error); 1067 panic("gem_add_rxbuf"); /* XXX */ 1068 } 1069 1070 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1071 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1072 1073 GEM_INIT_RXDESC(sc, idx); 1074 1075 sc->sc_rx_prod = GEM_NEXTRX(sc->sc_rx_prod); 1076 1077 return (0); 1078 } 1079 1080 int 1081 gem_eint(struct gem_softc *sc, u_int status) 1082 { 1083 if ((status & GEM_INTR_MIF) != 0) { 1084 #ifdef GEM_DEBUG 1085 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1086 #endif 1087 return (1); 1088 } 1089 1090 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS); 1091 return (1); 1092 } 1093 1094 int 1095 gem_pint(struct gem_softc *sc) 1096 { 1097 bus_space_tag_t t = sc->sc_bustag; 1098 bus_space_handle_t seb = sc->sc_h1; 1099 u_int32_t status; 1100 1101 status = bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS); 1102 status |= bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS); 1103 #ifdef GEM_DEBUG 1104 if (status) 1105 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1106 #endif 1107 return (1); 1108 } 1109 1110 int 1111 gem_intr(void *v) 1112 { 1113 struct gem_softc *sc = (struct gem_softc *)v; 1114 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1115 bus_space_tag_t t = sc->sc_bustag; 1116 bus_space_handle_t seb = sc->sc_h1; 1117 u_int32_t status; 1118 int r = 0; 1119 1120 status = bus_space_read_4(t, seb, GEM_STATUS); 1121 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n", 1122 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS)); 1123 1124 if (status == 0xffffffff) 1125 return (0); 1126 1127 if ((status & GEM_INTR_PCS) != 0) 1128 r |= gem_pint(sc); 1129 1130 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1131 r |= gem_eint(sc, status); 1132 1133 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1134 r |= gem_tint(sc, status); 1135 1136 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1137 r |= gem_rint(sc); 1138 1139 /* We should eventually do more than just print out error stats. */ 1140 if (status & GEM_INTR_TX_MAC) { 1141 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1142 #ifdef GEM_DEBUG 1143 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1144 printf("%s: MAC tx fault, status %x\n", 1145 sc->sc_dev.dv_xname, txstat); 1146 #endif 1147 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) { 1148 KERNEL_LOCK(); 1149 gem_init(ifp); 1150 KERNEL_UNLOCK(); 1151 } 1152 } 1153 if (status & GEM_INTR_RX_MAC) { 1154 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1155 #ifdef GEM_DEBUG 1156 if (rxstat & ~GEM_MAC_RX_DONE) 1157 printf("%s: MAC rx fault, status %x\n", 1158 sc->sc_dev.dv_xname, rxstat); 1159 #endif 1160 if (rxstat & GEM_MAC_RX_OVERFLOW) { 1161 ifp->if_ierrors++; 1162 1163 /* 1164 * Apparently a silicon bug causes ERI to hang 1165 * from time to time. So if we detect an RX 1166 * FIFO overflow, we fire off a timer, and 1167 * check whether we're still making progress 1168 * by looking at the RX FIFO write and read 1169 * pointers. 1170 */ 1171 sc->sc_rx_fifo_wr_ptr = 1172 bus_space_read_4(t, seb, GEM_RX_FIFO_WR_PTR); 1173 sc->sc_rx_fifo_rd_ptr = 1174 bus_space_read_4(t, seb, GEM_RX_FIFO_RD_PTR); 1175 timeout_add_msec(&sc->sc_rx_watchdog, 400); 1176 } 1177 #ifdef GEM_DEBUG 1178 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1179 printf("%s: MAC rx fault, status %x\n", 1180 sc->sc_dev.dv_xname, rxstat); 1181 #endif 1182 } 1183 return (r); 1184 } 1185 1186 void 1187 gem_rx_watchdog(void *arg) 1188 { 1189 struct gem_softc *sc = arg; 1190 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1191 bus_space_tag_t t = sc->sc_bustag; 1192 bus_space_handle_t h = sc->sc_h1; 1193 u_int32_t rx_fifo_wr_ptr; 1194 u_int32_t rx_fifo_rd_ptr; 1195 u_int32_t state; 1196 1197 if ((ifp->if_flags & IFF_RUNNING) == 0) 1198 return; 1199 1200 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 1201 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 1202 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 1203 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 1204 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 1205 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 1206 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) { 1207 /* 1208 * The RX state machine is still in overflow state and 1209 * the RX FIFO write and read pointers seem to be 1210 * stuck. Whack the chip over the head to get things 1211 * going again. 1212 */ 1213 gem_init(ifp); 1214 } 1215 } 1216 1217 void 1218 gem_watchdog(struct ifnet *ifp) 1219 { 1220 struct gem_softc *sc = ifp->if_softc; 1221 1222 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1223 "GEM_MAC_RX_CONFIG %x\n", 1224 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 1225 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 1226 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 1227 1228 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1229 ++ifp->if_oerrors; 1230 1231 /* Try to get more packets going. */ 1232 gem_init(ifp); 1233 } 1234 1235 /* 1236 * Initialize the MII Management Interface 1237 */ 1238 void 1239 gem_mifinit(struct gem_softc *sc) 1240 { 1241 bus_space_tag_t t = sc->sc_bustag; 1242 bus_space_handle_t mif = sc->sc_h1; 1243 1244 /* Configure the MIF in frame mode */ 1245 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1246 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1247 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1248 } 1249 1250 /* 1251 * MII interface 1252 * 1253 * The GEM MII interface supports at least three different operating modes: 1254 * 1255 * Bitbang mode is implemented using data, clock and output enable registers. 1256 * 1257 * Frame mode is implemented by loading a complete frame into the frame 1258 * register and polling the valid bit for completion. 1259 * 1260 * Polling mode uses the frame register but completion is indicated by 1261 * an interrupt. 1262 * 1263 */ 1264 int 1265 gem_mii_readreg(struct device *self, int phy, int reg) 1266 { 1267 struct gem_softc *sc = (void *)self; 1268 bus_space_tag_t t = sc->sc_bustag; 1269 bus_space_handle_t mif = sc->sc_h1; 1270 int n; 1271 u_int32_t v; 1272 1273 #ifdef GEM_DEBUG 1274 if (sc->sc_debug) 1275 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1276 #endif 1277 1278 /* Construct the frame command */ 1279 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1280 GEM_MIF_FRAME_READ; 1281 1282 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1283 for (n = 0; n < 100; n++) { 1284 DELAY(1); 1285 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1286 if (v & GEM_MIF_FRAME_TA0) 1287 return (v & GEM_MIF_FRAME_DATA); 1288 } 1289 1290 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1291 return (0); 1292 } 1293 1294 void 1295 gem_mii_writereg(struct device *self, int phy, int reg, int val) 1296 { 1297 struct gem_softc *sc = (void *)self; 1298 bus_space_tag_t t = sc->sc_bustag; 1299 bus_space_handle_t mif = sc->sc_h1; 1300 int n; 1301 u_int32_t v; 1302 1303 #ifdef GEM_DEBUG 1304 if (sc->sc_debug) 1305 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1306 phy, reg, val); 1307 #endif 1308 1309 /* Construct the frame command */ 1310 v = GEM_MIF_FRAME_WRITE | 1311 (phy << GEM_MIF_PHY_SHIFT) | 1312 (reg << GEM_MIF_REG_SHIFT) | 1313 (val & GEM_MIF_FRAME_DATA); 1314 1315 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1316 for (n = 0; n < 100; n++) { 1317 DELAY(1); 1318 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1319 if (v & GEM_MIF_FRAME_TA0) 1320 return; 1321 } 1322 1323 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1324 } 1325 1326 void 1327 gem_mii_statchg(struct device *dev) 1328 { 1329 struct gem_softc *sc = (void *)dev; 1330 #ifdef GEM_DEBUG 1331 uint64_t instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1332 #endif 1333 bus_space_tag_t t = sc->sc_bustag; 1334 bus_space_handle_t mac = sc->sc_h1; 1335 u_int32_t v; 1336 1337 #ifdef GEM_DEBUG 1338 if (sc->sc_debug) 1339 printf("gem_mii_statchg: status change: phy = %lld\n", instance); 1340 #endif 1341 1342 /* Set tx full duplex options */ 1343 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1344 delay(10000); /* reg must be cleared and delay before changing. */ 1345 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1346 GEM_MAC_TX_ENABLE; 1347 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1348 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1349 } 1350 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1351 1352 /* XIF Configuration */ 1353 v = GEM_MAC_XIF_TX_MII_ENA; 1354 v |= GEM_MAC_XIF_LINK_LED; 1355 1356 /* External MII needs echo disable if half duplex. */ 1357 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1358 /* turn on full duplex LED */ 1359 v |= GEM_MAC_XIF_FDPLX_LED; 1360 else 1361 /* half duplex -- disable echo */ 1362 v |= GEM_MAC_XIF_ECHO_DISABL; 1363 1364 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1365 case IFM_1000_T: /* Gigabit using GMII interface */ 1366 case IFM_1000_SX: 1367 v |= GEM_MAC_XIF_GMII_MODE; 1368 break; 1369 default: 1370 v &= ~GEM_MAC_XIF_GMII_MODE; 1371 } 1372 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1373 1374 /* 1375 * 802.3x flow control 1376 */ 1377 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG); 1378 v &= ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 1379 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1380 v |= GEM_MAC_CC_RX_PAUSE; 1381 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1382 v |= GEM_MAC_CC_TX_PAUSE; 1383 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 1384 } 1385 1386 int 1387 gem_pcs_readreg(struct device *self, int phy, int reg) 1388 { 1389 struct gem_softc *sc = (void *)self; 1390 bus_space_tag_t t = sc->sc_bustag; 1391 bus_space_handle_t pcs = sc->sc_h1; 1392 1393 #ifdef GEM_DEBUG 1394 if (sc->sc_debug) 1395 printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg); 1396 #endif 1397 1398 if (phy != GEM_PHYAD_EXTERNAL) 1399 return (0); 1400 1401 switch (reg) { 1402 case MII_BMCR: 1403 reg = GEM_MII_CONTROL; 1404 break; 1405 case MII_BMSR: 1406 reg = GEM_MII_STATUS; 1407 break; 1408 case MII_ANAR: 1409 reg = GEM_MII_ANAR; 1410 break; 1411 case MII_ANLPAR: 1412 reg = GEM_MII_ANLPAR; 1413 break; 1414 case MII_EXTSR: 1415 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1416 default: 1417 return (0); 1418 } 1419 1420 return bus_space_read_4(t, pcs, reg); 1421 } 1422 1423 void 1424 gem_pcs_writereg(struct device *self, int phy, int reg, int val) 1425 { 1426 struct gem_softc *sc = (void *)self; 1427 bus_space_tag_t t = sc->sc_bustag; 1428 bus_space_handle_t pcs = sc->sc_h1; 1429 int reset = 0; 1430 1431 #ifdef GEM_DEBUG 1432 if (sc->sc_debug) 1433 printf("gem_pcs_writereg: phy %d reg %d val %x\n", 1434 phy, reg, val); 1435 #endif 1436 1437 if (phy != GEM_PHYAD_EXTERNAL) 1438 return; 1439 1440 if (reg == MII_ANAR) 1441 bus_space_write_4(t, pcs, GEM_MII_CONFIG, 0); 1442 1443 switch (reg) { 1444 case MII_BMCR: 1445 reset = (val & GEM_MII_CONTROL_RESET); 1446 reg = GEM_MII_CONTROL; 1447 break; 1448 case MII_BMSR: 1449 reg = GEM_MII_STATUS; 1450 break; 1451 case MII_ANAR: 1452 reg = GEM_MII_ANAR; 1453 break; 1454 case MII_ANLPAR: 1455 reg = GEM_MII_ANLPAR; 1456 break; 1457 default: 1458 return; 1459 } 1460 1461 bus_space_write_4(t, pcs, reg, val); 1462 1463 if (reset) 1464 gem_bitwait(sc, pcs, GEM_MII_CONTROL, GEM_MII_CONTROL_RESET, 0); 1465 1466 if (reg == GEM_MII_ANAR || reset) { 1467 bus_space_write_4(t, pcs, GEM_MII_SLINK_CONTROL, 1468 GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D); 1469 bus_space_write_4(t, pcs, GEM_MII_CONFIG, 1470 GEM_MII_CONFIG_ENABLE); 1471 } 1472 } 1473 1474 int 1475 gem_mediachange(struct ifnet *ifp) 1476 { 1477 struct gem_softc *sc = ifp->if_softc; 1478 struct mii_data *mii = &sc->sc_mii; 1479 1480 if (mii->mii_instance) { 1481 struct mii_softc *miisc; 1482 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1483 mii_phy_reset(miisc); 1484 } 1485 1486 return (mii_mediachg(&sc->sc_mii)); 1487 } 1488 1489 void 1490 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1491 { 1492 struct gem_softc *sc = ifp->if_softc; 1493 1494 mii_pollstat(&sc->sc_mii); 1495 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1496 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1497 } 1498 1499 /* 1500 * Process an ioctl request. 1501 */ 1502 int 1503 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1504 { 1505 struct gem_softc *sc = ifp->if_softc; 1506 struct ifreq *ifr = (struct ifreq *)data; 1507 int s, error = 0; 1508 1509 s = splnet(); 1510 1511 switch (cmd) { 1512 case SIOCSIFADDR: 1513 ifp->if_flags |= IFF_UP; 1514 if ((ifp->if_flags & IFF_RUNNING) == 0) 1515 gem_init(ifp); 1516 break; 1517 1518 case SIOCSIFFLAGS: 1519 if (ifp->if_flags & IFF_UP) { 1520 if (ifp->if_flags & IFF_RUNNING) 1521 error = ENETRESET; 1522 else 1523 gem_init(ifp); 1524 } else { 1525 if (ifp->if_flags & IFF_RUNNING) 1526 gem_stop(ifp, 0); 1527 } 1528 #ifdef GEM_DEBUG 1529 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1530 #endif 1531 break; 1532 1533 case SIOCGIFMEDIA: 1534 case SIOCSIFMEDIA: 1535 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1536 break; 1537 1538 case SIOCGIFRXR: 1539 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 1540 NULL, MCLBYTES, &sc->sc_rx_ring); 1541 break; 1542 1543 default: 1544 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1545 } 1546 1547 if (error == ENETRESET) { 1548 if (ifp->if_flags & IFF_RUNNING) 1549 gem_iff(sc); 1550 error = 0; 1551 } 1552 1553 splx(s); 1554 return (error); 1555 } 1556 1557 void 1558 gem_iff(struct gem_softc *sc) 1559 { 1560 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1561 struct arpcom *ac = &sc->sc_arpcom; 1562 struct ether_multi *enm; 1563 struct ether_multistep step; 1564 bus_space_tag_t t = sc->sc_bustag; 1565 bus_space_handle_t h = sc->sc_h1; 1566 u_int32_t crc, hash[16], rxcfg; 1567 int i; 1568 1569 rxcfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1570 rxcfg &= ~(GEM_MAC_RX_HASH_FILTER | GEM_MAC_RX_PROMISCUOUS | 1571 GEM_MAC_RX_PROMISC_GRP); 1572 ifp->if_flags &= ~IFF_ALLMULTI; 1573 1574 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1575 ifp->if_flags |= IFF_ALLMULTI; 1576 if (ifp->if_flags & IFF_PROMISC) 1577 rxcfg |= GEM_MAC_RX_PROMISCUOUS; 1578 else 1579 rxcfg |= GEM_MAC_RX_PROMISC_GRP; 1580 } else { 1581 /* 1582 * Set up multicast address filter by passing all multicast 1583 * addresses through a crc generator, and then using the 1584 * high order 8 bits as an index into the 256 bit logical 1585 * address filter. The high order 4 bits selects the word, 1586 * while the other 4 bits select the bit within the word 1587 * (where bit 0 is the MSB). 1588 */ 1589 1590 rxcfg |= GEM_MAC_RX_HASH_FILTER; 1591 1592 /* Clear hash table */ 1593 for (i = 0; i < 16; i++) 1594 hash[i] = 0; 1595 1596 ETHER_FIRST_MULTI(step, ac, enm); 1597 while (enm != NULL) { 1598 crc = ether_crc32_le(enm->enm_addrlo, 1599 ETHER_ADDR_LEN); 1600 1601 /* Just want the 8 most significant bits. */ 1602 crc >>= 24; 1603 1604 /* Set the corresponding bit in the filter. */ 1605 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1606 1607 ETHER_NEXT_MULTI(step, enm); 1608 } 1609 1610 /* Now load the hash table into the chip (if we are using it) */ 1611 for (i = 0; i < 16; i++) { 1612 bus_space_write_4(t, h, 1613 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 1614 hash[i]); 1615 } 1616 } 1617 1618 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, rxcfg); 1619 } 1620 1621 /* 1622 * Transmit interrupt. 1623 */ 1624 int 1625 gem_tint(struct gem_softc *sc, u_int32_t status) 1626 { 1627 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1628 struct gem_sxd *sd; 1629 u_int32_t cons, prod; 1630 int free = 0; 1631 1632 prod = status >> 19; 1633 cons = sc->sc_tx_cons; 1634 while (cons != prod) { 1635 sd = &sc->sc_txd[cons]; 1636 if (sd->sd_mbuf != NULL) { 1637 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1638 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1639 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1640 m_freem(sd->sd_mbuf); 1641 sd->sd_mbuf = NULL; 1642 } 1643 1644 free = 1; 1645 1646 cons++; 1647 cons &= GEM_NTXDESC - 1; 1648 } 1649 1650 if (free == 0) 1651 return (0); 1652 1653 sc->sc_tx_cons = cons; 1654 1655 if (sc->sc_tx_prod == cons) 1656 ifp->if_timer = 0; 1657 1658 if (ifq_is_oactive(&ifp->if_snd)) 1659 ifq_restart(&ifp->if_snd); 1660 1661 return (1); 1662 } 1663 1664 int 1665 gem_load_mbuf(struct gem_softc *sc, struct gem_sxd *sd, struct mbuf *m) 1666 { 1667 int error; 1668 1669 error = bus_dmamap_load_mbuf(sc->sc_dmatag, sd->sd_map, m, 1670 BUS_DMA_NOWAIT); 1671 switch (error) { 1672 case 0: 1673 break; 1674 1675 case EFBIG: /* mbuf chain is too fragmented */ 1676 if (m_defrag(m, M_DONTWAIT) == 0 && 1677 bus_dmamap_load_mbuf(sc->sc_dmatag, sd->sd_map, m, 1678 BUS_DMA_NOWAIT) == 0) 1679 break; 1680 /* FALLTHROUGH */ 1681 default: 1682 return (1); 1683 } 1684 1685 return (0); 1686 } 1687 1688 void 1689 gem_start(struct ifqueue *ifq) 1690 { 1691 struct ifnet *ifp = ifq->ifq_if; 1692 struct gem_softc *sc = ifp->if_softc; 1693 struct gem_sxd *sd; 1694 struct mbuf *m; 1695 uint64_t flags, nflags; 1696 bus_dmamap_t map; 1697 uint32_t prod; 1698 uint32_t free, used = 0; 1699 uint32_t first, last; 1700 int i; 1701 1702 prod = sc->sc_tx_prod; 1703 1704 /* figure out space */ 1705 free = sc->sc_tx_cons; 1706 if (free <= prod) 1707 free += GEM_NTXDESC; 1708 free -= prod; 1709 1710 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1711 0, sizeof(struct gem_desc) * GEM_NTXDESC, 1712 BUS_DMASYNC_PREWRITE); 1713 1714 for (;;) { 1715 if (used + GEM_NTXSEGS + 1 > free) { 1716 ifq_set_oactive(&ifp->if_snd); 1717 break; 1718 } 1719 1720 m = ifq_dequeue(ifq); 1721 if (m == NULL) 1722 break; 1723 1724 first = prod; 1725 sd = &sc->sc_txd[first]; 1726 map = sd->sd_map; 1727 1728 if (gem_load_mbuf(sc, sd, m)) { 1729 m_freem(m); 1730 ifp->if_oerrors++; 1731 continue; 1732 } 1733 1734 #if NBPFILTER > 0 1735 if (ifp->if_bpf) 1736 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1737 #endif 1738 1739 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1740 BUS_DMASYNC_PREWRITE); 1741 1742 nflags = GEM_TD_START_OF_PACKET; 1743 for (i = 0; i < map->dm_nsegs; i++) { 1744 flags = nflags | 1745 (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE); 1746 1747 GEM_DMA_WRITE(sc, &sc->sc_txdescs[prod].gd_addr, 1748 map->dm_segs[i].ds_addr); 1749 GEM_DMA_WRITE(sc, &sc->sc_txdescs[prod].gd_flags, 1750 flags); 1751 1752 last = prod; 1753 prod++; 1754 prod &= GEM_NTXDESC - 1; 1755 1756 nflags = 0; 1757 } 1758 GEM_DMA_WRITE(sc, &sc->sc_txdescs[last].gd_flags, 1759 GEM_TD_END_OF_PACKET | flags); 1760 1761 used += map->dm_nsegs; 1762 sc->sc_txd[last].sd_mbuf = m; 1763 sc->sc_txd[first].sd_map = sc->sc_txd[last].sd_map; 1764 sc->sc_txd[last].sd_map = map; 1765 } 1766 1767 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1768 0, sizeof(struct gem_desc) * GEM_NTXDESC, 1769 BUS_DMASYNC_POSTWRITE); 1770 1771 if (used == 0) 1772 return; 1773 1774 /* Commit. */ 1775 sc->sc_tx_prod = prod; 1776 1777 /* Transmit. */ 1778 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, prod); 1779 1780 /* Set timeout in case hardware has problems transmitting. */ 1781 ifp->if_timer = 5; 1782 } 1783