1 /* $OpenBSD: gem.c,v 1.68 2006/12/21 22:13:36 jason Exp $ */ 2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/timeout.h> 42 #include <sys/mbuf.h> 43 #include <sys/syslog.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 struct cfdriver gem_cd = { 79 NULL, "gem", DV_IFNET 80 }; 81 82 void gem_start(struct ifnet *); 83 void gem_stop(struct ifnet *, int); 84 int gem_ioctl(struct ifnet *, u_long, caddr_t); 85 void gem_tick(void *); 86 void gem_watchdog(struct ifnet *); 87 void gem_shutdown(void *); 88 int gem_init(struct ifnet *); 89 void gem_init_regs(struct gem_softc *); 90 int gem_ringsize(int); 91 int gem_meminit(struct gem_softc *); 92 void gem_mifinit(struct gem_softc *); 93 int gem_bitwait(struct gem_softc *, bus_space_handle_t, int, 94 u_int32_t, u_int32_t); 95 void gem_reset(struct gem_softc *); 96 int gem_reset_rx(struct gem_softc *); 97 int gem_reset_tx(struct gem_softc *); 98 int gem_disable_rx(struct gem_softc *); 99 int gem_disable_tx(struct gem_softc *); 100 void gem_rxdrain(struct gem_softc *); 101 int gem_add_rxbuf(struct gem_softc *, int idx); 102 void gem_setladrf(struct gem_softc *); 103 int gem_encap(struct gem_softc *, struct mbuf *, u_int32_t *); 104 105 /* MII methods & callbacks */ 106 int gem_mii_readreg(struct device *, int, int); 107 void gem_mii_writereg(struct device *, int, int, int); 108 void gem_mii_statchg(struct device *); 109 int gem_pcs_readreg(struct device *, int, int); 110 void gem_pcs_writereg(struct device *, int, int, int); 111 112 int gem_mediachange(struct ifnet *); 113 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 114 115 struct mbuf *gem_get(struct gem_softc *, int, int); 116 int gem_eint(struct gem_softc *, u_int); 117 int gem_rint(struct gem_softc *); 118 int gem_tint(struct gem_softc *, u_int32_t); 119 int gem_pint(struct gem_softc *); 120 121 #ifdef GEM_DEBUG 122 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 123 printf x 124 #else 125 #define DPRINTF(sc, x) /* nothing */ 126 #endif 127 128 /* 129 * gem_config: 130 * 131 * Attach a Gem interface to the system. 132 */ 133 void 134 gem_config(struct gem_softc *sc) 135 { 136 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 137 struct mii_data *mii = &sc->sc_mii; 138 struct mii_softc *child; 139 int i, error; 140 struct ifmedia_entry *ifm; 141 142 /* Make sure the chip is stopped. */ 143 ifp->if_softc = sc; 144 gem_reset(sc); 145 146 /* 147 * Allocate the control data structures, and create and load the 148 * DMA map for it. 149 */ 150 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 151 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 152 1, &sc->sc_cdnseg, 0)) != 0) { 153 printf("\n%s: unable to allocate control data, error = %d\n", 154 sc->sc_dev.dv_xname, error); 155 goto fail_0; 156 } 157 158 /* XXX should map this in with correct endianness */ 159 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 160 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 161 BUS_DMA_COHERENT)) != 0) { 162 printf("\n%s: unable to map control data, error = %d\n", 163 sc->sc_dev.dv_xname, error); 164 goto fail_1; 165 } 166 167 if ((error = bus_dmamap_create(sc->sc_dmatag, 168 sizeof(struct gem_control_data), 1, 169 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 170 printf("\n%s: unable to create control data DMA map, " 171 "error = %d\n", sc->sc_dev.dv_xname, error); 172 goto fail_2; 173 } 174 175 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 176 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 177 0)) != 0) { 178 printf("\n%s: unable to load control data DMA map, error = %d\n", 179 sc->sc_dev.dv_xname, error); 180 goto fail_3; 181 } 182 183 /* 184 * Create the receive buffer DMA maps. 185 */ 186 for (i = 0; i < GEM_NRXDESC; i++) { 187 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 188 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 189 printf("\n%s: unable to create rx DMA map %d, " 190 "error = %d\n", sc->sc_dev.dv_xname, i, error); 191 goto fail_5; 192 } 193 sc->sc_rxsoft[i].rxs_mbuf = NULL; 194 } 195 /* 196 * Create the transmit buffer DMA maps. 197 */ 198 for (i = 0; i < GEM_NTXDESC; i++) { 199 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 200 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 201 &sc->sc_txd[i].sd_map)) != 0) { 202 printf("\n%s: unable to create tx DMA map %d, " 203 "error = %d\n", sc->sc_dev.dv_xname, i, error); 204 goto fail_6; 205 } 206 sc->sc_txd[i].sd_mbuf = NULL; 207 } 208 209 /* 210 * From this point forward, the attachment cannot fail. A failure 211 * before this point releases all resources that may have been 212 * allocated. 213 */ 214 215 /* Announce ourselves. */ 216 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 217 218 /* Get RX FIFO size */ 219 sc->sc_rxfifosize = 64 * 220 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_FIFO_SIZE); 221 222 /* Initialize ifnet structure. */ 223 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 224 ifp->if_softc = sc; 225 ifp->if_flags = 226 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 227 ifp->if_start = gem_start; 228 ifp->if_ioctl = gem_ioctl; 229 ifp->if_watchdog = gem_watchdog; 230 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_NTXDESC - 1); 231 IFQ_SET_READY(&ifp->if_snd); 232 233 ifp->if_capabilities = IFCAP_VLAN_MTU; 234 235 /* Initialize ifmedia structures and MII info */ 236 mii->mii_ifp = ifp; 237 mii->mii_readreg = gem_mii_readreg; 238 mii->mii_writereg = gem_mii_writereg; 239 mii->mii_statchg = gem_mii_statchg; 240 241 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 242 243 gem_mifinit(sc); 244 245 if (sc->sc_tcvr == -1) 246 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 247 MII_OFFSET_ANY, 0); 248 else 249 mii_attach(&sc->sc_dev, mii, 0xffffffff, sc->sc_tcvr, 250 MII_OFFSET_ANY, 0); 251 252 child = LIST_FIRST(&mii->mii_phys); 253 if (child == NULL && 254 sc->sc_mif_config & (GEM_MIF_CONFIG_MDI0|GEM_MIF_CONFIG_MDI1)) { 255 /* 256 * Try the external PCS SERDES if we didn't find any 257 * MII devices. 258 */ 259 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 260 GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_SERDES); 261 262 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 263 GEM_MII_SLINK_CONTROL, 264 GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D); 265 266 bus_space_write_4(sc->sc_bustag, sc->sc_h1, 267 GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 268 269 mii->mii_readreg = gem_pcs_readreg; 270 mii->mii_writereg = gem_pcs_writereg; 271 272 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 273 MII_OFFSET_ANY, MIIF_NOISOLATE); 274 } 275 276 child = LIST_FIRST(&mii->mii_phys); 277 if (child == NULL) { 278 /* No PHY attached */ 279 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 280 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 281 } else { 282 /* 283 * Walk along the list of attached MII devices and 284 * establish an `MII instance' to `phy number' 285 * mapping. We'll use this mapping in media change 286 * requests to determine which phy to use to program 287 * the MIF configuration register. 288 */ 289 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 290 /* 291 * Note: we support just two PHYs: the built-in 292 * internal device and an external on the MII 293 * connector. 294 */ 295 if (child->mii_phy > 1 || child->mii_inst > 1) { 296 printf("%s: cannot accommodate MII device %s" 297 " at phy %d, instance %d\n", 298 sc->sc_dev.dv_xname, 299 child->mii_dev.dv_xname, 300 child->mii_phy, child->mii_inst); 301 continue; 302 } 303 304 sc->sc_phys[child->mii_inst] = child->mii_phy; 305 } 306 307 /* 308 * Now select and activate the PHY we will use. 309 * 310 * The order of preference is External (MDI1), 311 * Internal (MDI0), Serial Link (no MII). 312 */ 313 if (sc->sc_phys[1]) { 314 #ifdef GEM_DEBUG 315 printf("using external phy\n"); 316 #endif 317 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 318 } else { 319 #ifdef GEM_DEBUG 320 printf("using internal phy\n"); 321 #endif 322 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 323 } 324 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_MIF_CONFIG, 325 sc->sc_mif_config); 326 327 /* 328 * XXX - we can really do the following ONLY if the 329 * phy indeed has the auto negotiation capability!! 330 */ 331 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 332 } 333 334 /* 335 * If we support GigE media, we support jumbo frames too. 336 * Unless we are Apple. 337 */ 338 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 339 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 340 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 341 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 342 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 343 sc->sc_flags |= GEM_GIGABIT; 344 break; 345 } 346 } 347 348 /* Attach the interface. */ 349 if_attach(ifp); 350 ether_ifattach(ifp); 351 352 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 353 if (sc->sc_sh == NULL) 354 panic("gem_config: can't establish shutdownhook"); 355 356 timeout_set(&sc->sc_tick_ch, gem_tick, sc); 357 return; 358 359 /* 360 * Free any resources we've allocated during the failed attach 361 * attempt. Do this in reverse order and fall through. 362 */ 363 fail_6: 364 for (i = 0; i < GEM_NTXDESC; i++) { 365 if (sc->sc_txd[i].sd_map != NULL) 366 bus_dmamap_destroy(sc->sc_dmatag, 367 sc->sc_txd[i].sd_map); 368 } 369 fail_5: 370 for (i = 0; i < GEM_NRXDESC; i++) { 371 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 372 bus_dmamap_destroy(sc->sc_dmatag, 373 sc->sc_rxsoft[i].rxs_dmamap); 374 } 375 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 376 fail_3: 377 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 378 fail_2: 379 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 380 sizeof(struct gem_control_data)); 381 fail_1: 382 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 383 fail_0: 384 return; 385 } 386 387 388 void 389 gem_tick(void *arg) 390 { 391 struct gem_softc *sc = arg; 392 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 393 bus_space_tag_t t = sc->sc_bustag; 394 bus_space_handle_t mac = sc->sc_h1; 395 int s; 396 397 /* unload collisions counters */ 398 ifp->if_collisions += 399 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 400 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 401 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 402 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 403 404 /* clear the hardware counters */ 405 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 406 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 407 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 408 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 409 410 s = splnet(); 411 mii_tick(&sc->sc_mii); 412 splx(s); 413 414 timeout_add(&sc->sc_tick_ch, hz); 415 } 416 417 int 418 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, 419 u_int32_t clr, u_int32_t set) 420 { 421 int i; 422 u_int32_t reg; 423 424 for (i = TRIES; i--; DELAY(100)) { 425 reg = bus_space_read_4(sc->sc_bustag, h, r); 426 if ((reg & clr) == 0 && (reg & set) == set) 427 return (1); 428 } 429 430 return (0); 431 } 432 433 void 434 gem_reset(struct gem_softc *sc) 435 { 436 bus_space_tag_t t = sc->sc_bustag; 437 bus_space_handle_t h = sc->sc_h2; 438 int s; 439 440 s = splnet(); 441 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 442 gem_reset_rx(sc); 443 gem_reset_tx(sc); 444 445 /* Do a full reset */ 446 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 447 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 448 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 449 splx(s); 450 } 451 452 453 /* 454 * gem_rxdrain: 455 * 456 * Drain the receive queue. 457 */ 458 void 459 gem_rxdrain(struct gem_softc *sc) 460 { 461 struct gem_rxsoft *rxs; 462 int i; 463 464 for (i = 0; i < GEM_NRXDESC; i++) { 465 rxs = &sc->sc_rxsoft[i]; 466 if (rxs->rxs_mbuf != NULL) { 467 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 468 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 469 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 470 m_freem(rxs->rxs_mbuf); 471 rxs->rxs_mbuf = NULL; 472 } 473 } 474 } 475 476 /* 477 * Reset the whole thing. 478 */ 479 void 480 gem_stop(struct ifnet *ifp, int disable) 481 { 482 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 483 struct gem_sxd *sd; 484 u_int32_t i; 485 486 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 487 488 timeout_del(&sc->sc_tick_ch); 489 490 /* 491 * Mark the interface down and cancel the watchdog timer. 492 */ 493 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 494 ifp->if_timer = 0; 495 496 mii_down(&sc->sc_mii); 497 498 gem_reset_rx(sc); 499 gem_reset_tx(sc); 500 501 /* 502 * Release any queued transmit buffers. 503 */ 504 for (i = 0; i < GEM_NTXDESC; i++) { 505 sd = &sc->sc_txd[i]; 506 if (sd->sd_mbuf != NULL) { 507 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 508 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 509 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 510 m_freem(sd->sd_mbuf); 511 sd->sd_mbuf = NULL; 512 } 513 } 514 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 515 516 if (disable) 517 gem_rxdrain(sc); 518 } 519 520 521 /* 522 * Reset the receiver 523 */ 524 int 525 gem_reset_rx(struct gem_softc *sc) 526 { 527 bus_space_tag_t t = sc->sc_bustag; 528 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 529 530 /* 531 * Resetting while DMA is in progress can cause a bus hang, so we 532 * disable DMA first. 533 */ 534 gem_disable_rx(sc); 535 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 536 /* Wait till it finishes */ 537 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 538 printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname); 539 /* Wait 5ms extra. */ 540 delay(5000); 541 542 /* Finally, reset the ERX */ 543 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 544 /* Wait till it finishes */ 545 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 546 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 547 return (1); 548 } 549 return (0); 550 } 551 552 553 /* 554 * Reset the transmitter 555 */ 556 int 557 gem_reset_tx(struct gem_softc *sc) 558 { 559 bus_space_tag_t t = sc->sc_bustag; 560 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 561 562 /* 563 * Resetting while DMA is in progress can cause a bus hang, so we 564 * disable DMA first. 565 */ 566 gem_disable_tx(sc); 567 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 568 /* Wait till it finishes */ 569 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 570 printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname); 571 /* Wait 5ms extra. */ 572 delay(5000); 573 574 /* Finally, reset the ETX */ 575 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 576 /* Wait till it finishes */ 577 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 578 printf("%s: cannot reset transmitter\n", 579 sc->sc_dev.dv_xname); 580 return (1); 581 } 582 return (0); 583 } 584 585 /* 586 * disable receiver. 587 */ 588 int 589 gem_disable_rx(struct gem_softc *sc) 590 { 591 bus_space_tag_t t = sc->sc_bustag; 592 bus_space_handle_t h = sc->sc_h1; 593 u_int32_t cfg; 594 595 /* Flip the enable bit */ 596 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 597 cfg &= ~GEM_MAC_RX_ENABLE; 598 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 599 600 /* Wait for it to finish */ 601 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 602 } 603 604 /* 605 * disable transmitter. 606 */ 607 int 608 gem_disable_tx(struct gem_softc *sc) 609 { 610 bus_space_tag_t t = sc->sc_bustag; 611 bus_space_handle_t h = sc->sc_h1; 612 u_int32_t cfg; 613 614 /* Flip the enable bit */ 615 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 616 cfg &= ~GEM_MAC_TX_ENABLE; 617 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 618 619 /* Wait for it to finish */ 620 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 621 } 622 623 /* 624 * Initialize interface. 625 */ 626 int 627 gem_meminit(struct gem_softc *sc) 628 { 629 struct gem_rxsoft *rxs; 630 int i, error; 631 632 /* 633 * Initialize the transmit descriptor ring. 634 */ 635 for (i = 0; i < GEM_NTXDESC; i++) { 636 sc->sc_txdescs[i].gd_flags = 0; 637 sc->sc_txdescs[i].gd_addr = 0; 638 } 639 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 640 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 641 642 /* 643 * Initialize the receive descriptor and receive job 644 * descriptor rings. 645 */ 646 for (i = 0; i < GEM_NRXDESC; i++) { 647 rxs = &sc->sc_rxsoft[i]; 648 if (rxs->rxs_mbuf == NULL) { 649 if ((error = gem_add_rxbuf(sc, i)) != 0) { 650 printf("%s: unable to allocate or map rx " 651 "buffer %d, error = %d\n", 652 sc->sc_dev.dv_xname, i, error); 653 /* 654 * XXX Should attempt to run with fewer receive 655 * XXX buffers instead of just failing. 656 */ 657 gem_rxdrain(sc); 658 return (1); 659 } 660 } else 661 GEM_INIT_RXDESC(sc, i); 662 } 663 sc->sc_rxptr = 0; 664 665 return (0); 666 } 667 668 int 669 gem_ringsize(int sz) 670 { 671 switch (sz) { 672 case 32: 673 return GEM_RING_SZ_32; 674 case 64: 675 return GEM_RING_SZ_64; 676 case 128: 677 return GEM_RING_SZ_128; 678 case 256: 679 return GEM_RING_SZ_256; 680 case 512: 681 return GEM_RING_SZ_512; 682 case 1024: 683 return GEM_RING_SZ_1024; 684 case 2048: 685 return GEM_RING_SZ_2048; 686 case 4096: 687 return GEM_RING_SZ_4096; 688 case 8192: 689 return GEM_RING_SZ_8192; 690 default: 691 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 692 return GEM_RING_SZ_32; 693 } 694 } 695 696 /* 697 * Initialization of interface; set up initialization block 698 * and transmit/receive descriptor rings. 699 */ 700 int 701 gem_init(struct ifnet *ifp) 702 { 703 704 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 705 bus_space_tag_t t = sc->sc_bustag; 706 bus_space_handle_t h = sc->sc_h1; 707 int s; 708 u_int max_frame_size; 709 u_int32_t v; 710 711 s = splnet(); 712 713 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 714 /* 715 * Initialization sequence. The numbered steps below correspond 716 * to the sequence outlined in section 6.3.5.1 in the Ethernet 717 * Channel Engine manual (part of the PCIO manual). 718 * See also the STP2002-STQ document from Sun Microsystems. 719 */ 720 721 /* step 1 & 2. Reset the Ethernet Channel */ 722 gem_stop(ifp, 0); 723 gem_reset(sc); 724 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 725 726 /* Re-initialize the MIF */ 727 gem_mifinit(sc); 728 729 /* Call MI reset function if any */ 730 if (sc->sc_hwreset) 731 (*sc->sc_hwreset)(sc); 732 733 /* step 3. Setup data structures in host memory */ 734 gem_meminit(sc); 735 736 /* step 4. TX MAC registers & counters */ 737 gem_init_regs(sc); 738 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 739 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 740 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 741 742 /* step 5. RX MAC registers & counters */ 743 gem_setladrf(sc); 744 745 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 746 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 747 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); 748 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 749 750 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 751 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); 752 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 753 754 /* step 8. Global Configuration & Interrupt Mask */ 755 bus_space_write_4(t, h, GEM_INTMASK, 756 ~(GEM_INTR_TX_INTME| 757 GEM_INTR_TX_EMPTY| 758 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 759 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 760 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 761 GEM_INTR_BERR)); 762 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 763 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 764 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 765 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 766 767 /* step 9. ETX Configuration: use mostly default values */ 768 769 /* Enable DMA */ 770 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 771 bus_space_write_4(t, h, GEM_TX_CONFIG, 772 v|GEM_TX_CONFIG_TXDMA_EN| 773 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 774 bus_space_write_4(t, h, GEM_TX_KICK, 0); 775 776 /* step 10. ERX Configuration */ 777 778 /* Encode Receive Descriptor ring size: four possible values */ 779 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 780 781 /* Enable DMA */ 782 bus_space_write_4(t, h, GEM_RX_CONFIG, 783 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 784 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 785 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 786 /* 787 * The following value is for an OFF Threshold of about 3/4 full 788 * and an ON Threshold of 1/4 full. 789 */ 790 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 791 (3 * sc->sc_rxfifosize / 256) | 792 ( (sc->sc_rxfifosize / 256) << 12)); 793 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 794 795 /* step 11. Configure Media */ 796 mii_mediachg(&sc->sc_mii); 797 798 /* step 12. RX_MAC Configuration Register */ 799 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 800 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 801 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 802 803 /* step 14. Issue Transmit Pending command */ 804 805 /* Call MI initialization function if any */ 806 if (sc->sc_hwinit) 807 (*sc->sc_hwinit)(sc); 808 809 810 /* step 15. Give the receiver a swift kick */ 811 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 812 813 /* Start the one second timer. */ 814 timeout_add(&sc->sc_tick_ch, hz); 815 816 ifp->if_flags |= IFF_RUNNING; 817 ifp->if_flags &= ~IFF_OACTIVE; 818 ifp->if_timer = 0; 819 splx(s); 820 821 return (0); 822 } 823 824 void 825 gem_init_regs(struct gem_softc *sc) 826 { 827 bus_space_tag_t t = sc->sc_bustag; 828 bus_space_handle_t h = sc->sc_h1; 829 u_int32_t v; 830 831 /* These regs are not cleared on reset */ 832 sc->sc_inited = 0; 833 if (!sc->sc_inited) { 834 835 /* Wooo. Magic values. */ 836 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 837 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 838 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 839 840 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 841 /* Max frame and max burst size */ 842 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 843 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 844 845 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 846 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 847 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 848 /* Dunno.... */ 849 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 850 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 851 ((sc->sc_arpcom.ac_enaddr[5]<<8)|sc->sc_arpcom.ac_enaddr[4])&0x3ff); 852 853 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 854 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 855 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 856 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 857 /* MAC control addr set to 0:1:c2:0:1:80 */ 858 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 859 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 860 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 861 862 /* MAC filter addr set to 0:0:0:0:0:0 */ 863 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 864 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 865 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 866 867 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 868 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 869 870 sc->sc_inited = 1; 871 } 872 873 /* Counters need to be zeroed */ 874 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 875 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 876 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 877 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 878 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 879 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 880 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 881 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 882 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 883 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 884 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 885 886 /* Un-pause stuff */ 887 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 888 889 /* 890 * Set the station address. 891 */ 892 bus_space_write_4(t, h, GEM_MAC_ADDR0, 893 (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); 894 bus_space_write_4(t, h, GEM_MAC_ADDR1, 895 (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); 896 bus_space_write_4(t, h, GEM_MAC_ADDR2, 897 (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); 898 899 900 /* 901 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 902 */ 903 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 904 v = GEM_MAC_XIF_TX_MII_ENA; 905 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 906 v |= GEM_MAC_XIF_FDPLX_LED; 907 if (sc->sc_flags & GEM_GIGABIT) 908 v |= GEM_MAC_XIF_GMII_MODE; 909 } 910 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 911 } 912 913 /* 914 * Receive interrupt. 915 */ 916 int 917 gem_rint(struct gem_softc *sc) 918 { 919 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 920 bus_space_tag_t t = sc->sc_bustag; 921 bus_space_handle_t h = sc->sc_h1; 922 struct ether_header *eh; 923 struct gem_rxsoft *rxs; 924 struct mbuf *m; 925 u_int64_t rxstat; 926 int i, len; 927 928 for (i = sc->sc_rxptr;; i = GEM_NEXTRX(i)) { 929 rxs = &sc->sc_rxsoft[i]; 930 931 GEM_CDRXSYNC(sc, i, 932 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 933 934 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 935 936 if (rxstat & GEM_RD_OWN) { 937 /* 938 * We have processed all of the receive buffers. 939 */ 940 break; 941 } 942 943 if (rxstat & GEM_RD_BAD_CRC) { 944 #ifdef GEM_DEBUG 945 printf("%s: receive error: CRC error\n", 946 sc->sc_dev.dv_xname); 947 #endif 948 GEM_INIT_RXDESC(sc, i); 949 continue; 950 } 951 952 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 953 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 954 #ifdef GEM_DEBUG 955 if (ifp->if_flags & IFF_DEBUG) { 956 printf(" rxsoft %p descriptor %d: ", rxs, i); 957 printf("gd_flags: 0x%016llx\t", (long long) 958 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 959 printf("gd_addr: 0x%016llx\n", (long long) 960 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 961 } 962 #endif 963 964 /* No errors; receive the packet. */ 965 len = GEM_RD_BUFLEN(rxstat); 966 967 /* 968 * Allocate a new mbuf cluster. If that fails, we are 969 * out of memory, and must drop the packet and recycle 970 * the buffer that's already attached to this descriptor. 971 */ 972 m = rxs->rxs_mbuf; 973 if (gem_add_rxbuf(sc, i) != 0) { 974 ifp->if_ierrors++; 975 GEM_INIT_RXDESC(sc, i); 976 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 977 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 978 continue; 979 } 980 m->m_data += 2; /* We're already off by two */ 981 982 ifp->if_ipackets++; 983 eh = mtod(m, struct ether_header *); 984 m->m_pkthdr.rcvif = ifp; 985 m->m_pkthdr.len = m->m_len = len; 986 987 #if NBPFILTER > 0 988 /* 989 * Pass this up to any BPF listeners, but only 990 * pass it up the stack if its for us. 991 */ 992 if (ifp->if_bpf) 993 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 994 #endif /* NPBFILTER > 0 */ 995 996 /* Pass it on. */ 997 ether_input_mbuf(ifp, m); 998 } 999 1000 /* Update the receive pointer. */ 1001 sc->sc_rxptr = i; 1002 bus_space_write_4(t, h, GEM_RX_KICK, i); 1003 1004 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1005 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1006 1007 return (1); 1008 } 1009 1010 1011 /* 1012 * gem_add_rxbuf: 1013 * 1014 * Add a receive buffer to the indicated descriptor. 1015 */ 1016 int 1017 gem_add_rxbuf(struct gem_softc *sc, int idx) 1018 { 1019 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1020 struct mbuf *m; 1021 int error; 1022 1023 MGETHDR(m, M_DONTWAIT, MT_DATA); 1024 if (m == NULL) 1025 return (ENOBUFS); 1026 1027 MCLGET(m, M_DONTWAIT); 1028 if ((m->m_flags & M_EXT) == 0) { 1029 m_freem(m); 1030 return (ENOBUFS); 1031 } 1032 1033 #ifdef GEM_DEBUG 1034 /* bzero the packet to check dma */ 1035 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1036 #endif 1037 1038 if (rxs->rxs_mbuf != NULL) 1039 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1040 1041 rxs->rxs_mbuf = m; 1042 1043 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1044 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1045 BUS_DMA_READ|BUS_DMA_NOWAIT); 1046 if (error) { 1047 printf("%s: can't load rx DMA map %d, error = %d\n", 1048 sc->sc_dev.dv_xname, idx, error); 1049 panic("gem_add_rxbuf"); /* XXX */ 1050 } 1051 1052 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1053 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1054 1055 GEM_INIT_RXDESC(sc, idx); 1056 1057 return (0); 1058 } 1059 1060 1061 int 1062 gem_eint(struct gem_softc *sc, u_int status) 1063 { 1064 if ((status & GEM_INTR_MIF) != 0) { 1065 #ifdef GEM_DEBUG 1066 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1067 #endif 1068 return (1); 1069 } 1070 1071 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS); 1072 return (1); 1073 } 1074 1075 int 1076 gem_pint(struct gem_softc *sc) 1077 { 1078 bus_space_tag_t t = sc->sc_bustag; 1079 bus_space_handle_t seb = sc->sc_h1; 1080 u_int32_t status; 1081 1082 status = bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS); 1083 status |= bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS); 1084 #ifdef GEM_DEBUG 1085 if (status) 1086 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1087 #endif 1088 return (1); 1089 } 1090 1091 int 1092 gem_intr(void *v) 1093 { 1094 struct gem_softc *sc = (struct gem_softc *)v; 1095 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1096 bus_space_tag_t t = sc->sc_bustag; 1097 bus_space_handle_t seb = sc->sc_h1; 1098 u_int32_t status; 1099 int r = 0; 1100 1101 status = bus_space_read_4(t, seb, GEM_STATUS); 1102 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n", 1103 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS)); 1104 1105 if ((status & GEM_INTR_PCS) != 0) 1106 r |= gem_pint(sc); 1107 1108 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1109 r |= gem_eint(sc, status); 1110 1111 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1112 r |= gem_tint(sc, status); 1113 1114 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1115 r |= gem_rint(sc); 1116 1117 /* We should eventually do more than just print out error stats. */ 1118 if (status & GEM_INTR_TX_MAC) { 1119 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1120 #ifdef GEM_DEBUG 1121 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1122 printf("%s: MAC tx fault, status %x\n", 1123 sc->sc_dev.dv_xname, txstat); 1124 #endif 1125 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1126 gem_init(ifp); 1127 } 1128 if (status & GEM_INTR_RX_MAC) { 1129 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1130 #ifdef GEM_DEBUG 1131 if (rxstat & ~GEM_MAC_RX_DONE) 1132 printf("%s: MAC rx fault, status %x\n", 1133 sc->sc_dev.dv_xname, rxstat); 1134 #endif 1135 /* 1136 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1137 * due to a silicon bug so handle them silently. 1138 */ 1139 if (rxstat & GEM_MAC_RX_OVERFLOW) { 1140 ifp->if_ierrors++; 1141 gem_init(ifp); 1142 } 1143 #ifdef GEM_DEBUG 1144 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1145 printf("%s: MAC rx fault, status %x\n", 1146 sc->sc_dev.dv_xname, rxstat); 1147 #endif 1148 } 1149 return (r); 1150 } 1151 1152 1153 void 1154 gem_watchdog(struct ifnet *ifp) 1155 { 1156 struct gem_softc *sc = ifp->if_softc; 1157 1158 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1159 "GEM_MAC_RX_CONFIG %x\n", 1160 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 1161 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 1162 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 1163 1164 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1165 ++ifp->if_oerrors; 1166 1167 /* Try to get more packets going. */ 1168 gem_init(ifp); 1169 } 1170 1171 /* 1172 * Initialize the MII Management Interface 1173 */ 1174 void 1175 gem_mifinit(struct gem_softc *sc) 1176 { 1177 bus_space_tag_t t = sc->sc_bustag; 1178 bus_space_handle_t mif = sc->sc_h1; 1179 1180 if (GEM_IS_APPLE(sc)) { 1181 if (sc->sc_variant == GEM_APPLE_K2_GMAC) 1182 sc->sc_tcvr = 1; 1183 else 1184 sc->sc_tcvr = 0; 1185 } else { 1186 sc->sc_tcvr = -1; 1187 } 1188 1189 /* Configure the MIF in frame mode */ 1190 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1191 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1192 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1193 } 1194 1195 /* 1196 * MII interface 1197 * 1198 * The GEM MII interface supports at least three different operating modes: 1199 * 1200 * Bitbang mode is implemented using data, clock and output enable registers. 1201 * 1202 * Frame mode is implemented by loading a complete frame into the frame 1203 * register and polling the valid bit for completion. 1204 * 1205 * Polling mode uses the frame register but completion is indicated by 1206 * an interrupt. 1207 * 1208 */ 1209 int 1210 gem_mii_readreg(struct device *self, int phy, int reg) 1211 { 1212 struct gem_softc *sc = (void *)self; 1213 bus_space_tag_t t = sc->sc_bustag; 1214 bus_space_handle_t mif = sc->sc_h1; 1215 int n; 1216 u_int32_t v; 1217 1218 #ifdef GEM_DEBUG 1219 if (sc->sc_debug) 1220 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1221 #endif 1222 1223 /* Construct the frame command */ 1224 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1225 GEM_MIF_FRAME_READ; 1226 1227 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1228 for (n = 0; n < 100; n++) { 1229 DELAY(1); 1230 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1231 if (v & GEM_MIF_FRAME_TA0) 1232 return (v & GEM_MIF_FRAME_DATA); 1233 } 1234 1235 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1236 return (0); 1237 } 1238 1239 void 1240 gem_mii_writereg(struct device *self, int phy, int reg, int val) 1241 { 1242 struct gem_softc *sc = (void *)self; 1243 bus_space_tag_t t = sc->sc_bustag; 1244 bus_space_handle_t mif = sc->sc_h1; 1245 int n; 1246 u_int32_t v; 1247 1248 #ifdef GEM_DEBUG 1249 if (sc->sc_debug) 1250 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1251 phy, reg, val); 1252 #endif 1253 1254 #if 0 1255 /* Select the desired PHY in the MIF configuration register */ 1256 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1257 /* Clear PHY select bit */ 1258 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1259 if (phy == GEM_PHYAD_EXTERNAL) 1260 /* Set PHY select bit to get at external device */ 1261 v |= GEM_MIF_CONFIG_PHY_SEL; 1262 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1263 #endif 1264 /* Construct the frame command */ 1265 v = GEM_MIF_FRAME_WRITE | 1266 (phy << GEM_MIF_PHY_SHIFT) | 1267 (reg << GEM_MIF_REG_SHIFT) | 1268 (val & GEM_MIF_FRAME_DATA); 1269 1270 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1271 for (n = 0; n < 100; n++) { 1272 DELAY(1); 1273 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1274 if (v & GEM_MIF_FRAME_TA0) 1275 return; 1276 } 1277 1278 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1279 } 1280 1281 void 1282 gem_mii_statchg(struct device *dev) 1283 { 1284 struct gem_softc *sc = (void *)dev; 1285 #ifdef GEM_DEBUG 1286 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1287 #endif 1288 bus_space_tag_t t = sc->sc_bustag; 1289 bus_space_handle_t mac = sc->sc_h1; 1290 u_int32_t v; 1291 1292 #ifdef GEM_DEBUG 1293 if (sc->sc_debug) 1294 printf("gem_mii_statchg: status change: phy = %d\n", 1295 sc->sc_phys[instance]); 1296 #endif 1297 1298 1299 /* Set tx full duplex options */ 1300 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1301 delay(10000); /* reg must be cleared and delay before changing. */ 1302 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1303 GEM_MAC_TX_ENABLE; 1304 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1305 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1306 } 1307 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1308 1309 /* XIF Configuration */ 1310 /* We should really calculate all this rather than rely on defaults */ 1311 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1312 v = GEM_MAC_XIF_LINK_LED; 1313 v |= GEM_MAC_XIF_TX_MII_ENA; 1314 /* If an external transceiver is connected, enable its MII drivers */ 1315 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1316 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1317 /* External MII needs echo disable if half duplex. */ 1318 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1319 /* turn on full duplex LED */ 1320 v |= GEM_MAC_XIF_FDPLX_LED; 1321 else 1322 /* half duplex -- disable echo */ 1323 v |= GEM_MAC_XIF_ECHO_DISABL; 1324 1325 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1326 case IFM_1000_T: /* Gigabit using GMII interface */ 1327 case IFM_1000_SX: 1328 v |= GEM_MAC_XIF_GMII_MODE; 1329 break; 1330 default: 1331 v &= ~GEM_MAC_XIF_GMII_MODE; 1332 } 1333 } else 1334 /* Internal MII needs buf enable */ 1335 v |= GEM_MAC_XIF_MII_BUF_ENA; 1336 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1337 } 1338 1339 int 1340 gem_pcs_readreg(struct device *self, int phy, int reg) 1341 { 1342 struct gem_softc *sc = (void *)self; 1343 bus_space_tag_t t = sc->sc_bustag; 1344 bus_space_handle_t pcs = sc->sc_h1; 1345 1346 #ifdef GEM_DEBUG 1347 if (sc->sc_debug) 1348 printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg); 1349 #endif 1350 1351 if (phy != GEM_PHYAD_EXTERNAL) 1352 return (0); 1353 1354 switch (reg) { 1355 case MII_BMCR: 1356 reg = GEM_MII_CONTROL; 1357 break; 1358 case MII_BMSR: 1359 reg = GEM_MII_STATUS; 1360 break; 1361 case MII_ANAR: 1362 reg = GEM_MII_ANAR; 1363 break; 1364 case MII_ANLPAR: 1365 reg = GEM_MII_ANLPAR; 1366 break; 1367 case MII_EXTSR: 1368 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1369 default: 1370 return (0); 1371 } 1372 1373 return bus_space_read_4(t, pcs, reg); 1374 } 1375 1376 void 1377 gem_pcs_writereg(struct device *self, int phy, int reg, int val) 1378 { 1379 struct gem_softc *sc = (void *)self; 1380 bus_space_tag_t t = sc->sc_bustag; 1381 bus_space_handle_t pcs = sc->sc_h1; 1382 1383 #ifdef GEM_DEBUG 1384 if (sc->sc_debug) 1385 printf("gem_pcs_writereg: phy %d reg %d val %x\n", 1386 phy, reg, val); 1387 #endif 1388 1389 if (phy != GEM_PHYAD_EXTERNAL) 1390 return; 1391 1392 switch (reg) { 1393 case MII_BMCR: 1394 reg = GEM_MII_CONTROL; 1395 break; 1396 case MII_BMSR: 1397 reg = GEM_MII_STATUS; 1398 break; 1399 case MII_ANAR: 1400 reg = GEM_MII_ANAR; 1401 break; 1402 case MII_ANLPAR: 1403 reg = GEM_MII_ANLPAR; 1404 break; 1405 default: 1406 return; 1407 } 1408 1409 bus_space_write_4(t, pcs, reg, val); 1410 1411 if (reg == GEM_MII_ANAR) { 1412 bus_space_write_4(t, pcs, GEM_MII_SLINK_CONTROL, 1413 GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D); 1414 bus_space_write_4(t, pcs, GEM_MII_CONFIG, 1415 GEM_MII_CONFIG_ENABLE); 1416 } 1417 } 1418 1419 int 1420 gem_mediachange(struct ifnet *ifp) 1421 { 1422 struct gem_softc *sc = ifp->if_softc; 1423 struct mii_data *mii = &sc->sc_mii; 1424 1425 if (mii->mii_instance) { 1426 struct mii_softc *miisc; 1427 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1428 mii_phy_reset(miisc); 1429 } 1430 1431 return (mii_mediachg(&sc->sc_mii)); 1432 } 1433 1434 void 1435 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1436 { 1437 struct gem_softc *sc = ifp->if_softc; 1438 1439 mii_pollstat(&sc->sc_mii); 1440 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1441 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1442 } 1443 1444 /* 1445 * Process an ioctl request. 1446 */ 1447 int 1448 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1449 { 1450 struct gem_softc *sc = ifp->if_softc; 1451 struct ifaddr *ifa = (struct ifaddr *)data; 1452 struct ifreq *ifr = (struct ifreq *)data; 1453 int s, error = 0; 1454 1455 s = splnet(); 1456 1457 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 1458 splx(s); 1459 return (error); 1460 } 1461 1462 switch (cmd) { 1463 1464 case SIOCSIFADDR: 1465 ifp->if_flags |= IFF_UP; 1466 if ((ifp->if_flags & IFF_RUNNING) == 0) 1467 gem_init(ifp); 1468 #ifdef INET 1469 if (ifa->ifa_addr->sa_family == AF_INET) 1470 arp_ifinit(&sc->sc_arpcom, ifa); 1471 #endif 1472 break; 1473 1474 case SIOCSIFFLAGS: 1475 if (ifp->if_flags & IFF_UP) { 1476 if ((ifp->if_flags & IFF_RUNNING) && 1477 ((ifp->if_flags ^ sc->sc_if_flags) & 1478 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1479 gem_setladrf(sc); 1480 else { 1481 if ((ifp->if_flags & IFF_RUNNING) == 0) 1482 gem_init(ifp); 1483 } 1484 } else { 1485 if (ifp->if_flags & IFF_RUNNING) 1486 gem_stop(ifp, 1); 1487 } 1488 sc->sc_if_flags = ifp->if_flags; 1489 1490 #ifdef GEM_DEBUG 1491 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1492 #endif 1493 break; 1494 1495 case SIOCSIFMTU: 1496 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 1497 error = EINVAL; 1498 } else if (ifp->if_mtu != ifr->ifr_mtu) { 1499 ifp->if_mtu = ifr->ifr_mtu; 1500 } 1501 break; 1502 1503 case SIOCADDMULTI: 1504 case SIOCDELMULTI: 1505 error = (cmd == SIOCADDMULTI) ? 1506 ether_addmulti(ifr, &sc->sc_arpcom) : 1507 ether_delmulti(ifr, &sc->sc_arpcom); 1508 1509 if (error == ENETRESET) { 1510 /* 1511 * Multicast list has changed; set the hardware filter 1512 * accordingly. 1513 */ 1514 if (ifp->if_flags & IFF_RUNNING) 1515 gem_setladrf(sc); 1516 error = 0; 1517 } 1518 break; 1519 1520 case SIOCGIFMEDIA: 1521 case SIOCSIFMEDIA: 1522 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1523 break; 1524 1525 default: 1526 error = EINVAL; 1527 break; 1528 } 1529 1530 splx(s); 1531 return (error); 1532 } 1533 1534 1535 void 1536 gem_shutdown(void *arg) 1537 { 1538 struct gem_softc *sc = (struct gem_softc *)arg; 1539 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1540 1541 gem_stop(ifp, 1); 1542 } 1543 1544 /* 1545 * Set up the logical address filter. 1546 */ 1547 void 1548 gem_setladrf(struct gem_softc *sc) 1549 { 1550 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1551 struct ether_multi *enm; 1552 struct ether_multistep step; 1553 struct arpcom *ac = &sc->sc_arpcom; 1554 bus_space_tag_t t = sc->sc_bustag; 1555 bus_space_handle_t h = sc->sc_h1; 1556 u_int32_t crc, hash[16], v; 1557 int i; 1558 1559 /* Get current RX configuration */ 1560 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1561 1562 1563 /* 1564 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1565 * and hash filter. Depending on the case, the right bit will be 1566 * enabled. 1567 */ 1568 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1569 GEM_MAC_RX_PROMISC_GRP); 1570 1571 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1572 /* Turn on promiscuous mode */ 1573 v |= GEM_MAC_RX_PROMISCUOUS; 1574 ifp->if_flags |= IFF_ALLMULTI; 1575 goto chipit; 1576 } 1577 1578 /* 1579 * Set up multicast address filter by passing all multicast addresses 1580 * through a crc generator, and then using the high order 8 bits as an 1581 * index into the 256 bit logical address filter. The high order 4 1582 * bits selects the word, while the other 4 bits select the bit within 1583 * the word (where bit 0 is the MSB). 1584 */ 1585 1586 /* Clear hash table */ 1587 for (i = 0; i < 16; i++) 1588 hash[i] = 0; 1589 1590 1591 ETHER_FIRST_MULTI(step, ac, enm); 1592 while (enm != NULL) { 1593 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1594 /* 1595 * We must listen to a range of multicast addresses. 1596 * For now, just accept all multicasts, rather than 1597 * trying to set only those filter bits needed to match 1598 * the range. (At this time, the only use of address 1599 * ranges is for IP multicast routing, for which the 1600 * range is big enough to require all bits set.) 1601 * XXX use the addr filter for this 1602 */ 1603 ifp->if_flags |= IFF_ALLMULTI; 1604 v |= GEM_MAC_RX_PROMISC_GRP; 1605 goto chipit; 1606 } 1607 1608 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1609 1610 /* Just want the 8 most significant bits. */ 1611 crc >>= 24; 1612 1613 /* Set the corresponding bit in the filter. */ 1614 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1615 1616 ETHER_NEXT_MULTI(step, enm); 1617 } 1618 1619 v |= GEM_MAC_RX_HASH_FILTER; 1620 ifp->if_flags &= ~IFF_ALLMULTI; 1621 1622 /* Now load the hash table into the chip (if we are using it) */ 1623 for (i = 0; i < 16; i++) { 1624 bus_space_write_4(t, h, 1625 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1626 hash[i]); 1627 } 1628 1629 chipit: 1630 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1631 } 1632 1633 int 1634 gem_encap(struct gem_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1635 { 1636 u_int64_t flags; 1637 u_int32_t cur, frag, i; 1638 bus_dmamap_t map; 1639 1640 cur = frag = *bixp; 1641 map = sc->sc_txd[cur].sd_map; 1642 1643 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1644 BUS_DMA_NOWAIT) != 0) { 1645 return (ENOBUFS); 1646 } 1647 1648 if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) { 1649 bus_dmamap_unload(sc->sc_dmatag, map); 1650 return (ENOBUFS); 1651 } 1652 1653 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1654 BUS_DMASYNC_PREWRITE); 1655 1656 for (i = 0; i < map->dm_nsegs; i++) { 1657 sc->sc_txdescs[frag].gd_addr = 1658 GEM_DMA_WRITE(sc, map->dm_segs[i].ds_addr); 1659 flags = (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE) | 1660 (i == 0 ? GEM_TD_START_OF_PACKET : 0) | 1661 ((i == (map->dm_nsegs - 1)) ? GEM_TD_END_OF_PACKET : 0); 1662 sc->sc_txdescs[frag].gd_flags = GEM_DMA_WRITE(sc, flags); 1663 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1664 GEM_CDTXOFF(frag), sizeof(struct gem_desc), 1665 BUS_DMASYNC_PREWRITE); 1666 cur = frag; 1667 if (++frag == GEM_NTXDESC) 1668 frag = 0; 1669 } 1670 1671 sc->sc_tx_cnt += map->dm_nsegs; 1672 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1673 sc->sc_txd[cur].sd_map = map; 1674 sc->sc_txd[cur].sd_mbuf = mhead; 1675 1676 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, frag); 1677 1678 *bixp = frag; 1679 1680 /* sync descriptors */ 1681 1682 return (0); 1683 } 1684 1685 /* 1686 * Transmit interrupt. 1687 */ 1688 int 1689 gem_tint(struct gem_softc *sc, u_int32_t status) 1690 { 1691 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1692 struct gem_sxd *sd; 1693 u_int32_t cons, hwcons; 1694 1695 hwcons = status >> 19; 1696 cons = sc->sc_tx_cons; 1697 while (cons != hwcons) { 1698 sd = &sc->sc_txd[cons]; 1699 if (sd->sd_mbuf != NULL) { 1700 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1701 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1702 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1703 m_freem(sd->sd_mbuf); 1704 sd->sd_mbuf = NULL; 1705 } 1706 sc->sc_tx_cnt--; 1707 ifp->if_opackets++; 1708 if (++cons == GEM_NTXDESC) 1709 cons = 0; 1710 } 1711 sc->sc_tx_cons = cons; 1712 1713 gem_start(ifp); 1714 1715 if (sc->sc_tx_cnt == 0) 1716 ifp->if_timer = 0; 1717 1718 return (1); 1719 } 1720 1721 void 1722 gem_start(struct ifnet *ifp) 1723 { 1724 struct gem_softc *sc = ifp->if_softc; 1725 struct mbuf *m; 1726 u_int32_t bix; 1727 1728 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1729 return; 1730 1731 bix = sc->sc_tx_prod; 1732 while (sc->sc_txd[bix].sd_mbuf == NULL) { 1733 IFQ_POLL(&ifp->if_snd, m); 1734 if (m == NULL) 1735 break; 1736 1737 #if NBPFILTER > 0 1738 /* 1739 * If BPF is listening on this interface, let it see the 1740 * packet before we commit it to the wire. 1741 */ 1742 if (ifp->if_bpf) 1743 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1744 #endif 1745 1746 /* 1747 * Encapsulate this packet and start it going... 1748 * or fail... 1749 */ 1750 if (gem_encap(sc, m, &bix)) { 1751 ifp->if_timer = 2; 1752 break; 1753 } 1754 1755 IFQ_DEQUEUE(&ifp->if_snd, m); 1756 ifp->if_timer = 5; 1757 } 1758 1759 sc->sc_tx_prod = bix; 1760 } 1761