1 /* $OpenBSD: elink3.c,v 1.76 2009/11/24 18:12:39 claudio Exp $ */ 2 /* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org> 6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Herb Peyerl. 20 * 4. The name of Herb Peyerl may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/ioctl.h> 42 #include <sys/errno.h> 43 #include <sys/syslog.h> 44 #include <sys/selinfo.h> 45 #include <sys/timeout.h> 46 #include <sys/device.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_types.h> 51 #include <net/netisr.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/cpu.h> 67 #include <machine/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/ic/elink3var.h> 73 #include <dev/ic/elink3reg.h> 74 75 /* 76 * Structure to map media-present bits in boards to 77 * ifmedia codes and printable media names. Used for table-driven 78 * ifmedia initialization. 79 */ 80 struct ep_media { 81 int epm_eeprom_data; /* bitmask for eeprom config */ 82 int epm_conn; /* sc->ep_connectors code for medium */ 83 char *epm_name; /* name of medium */ 84 int epm_ifmedia; /* ifmedia word for medium */ 85 int epm_ifdata; 86 }; 87 88 /* 89 * ep_media table for Vortex/Demon/Boomerang: 90 * map from media-present bits in register RESET_OPTIONS+2 91 * to ifmedia "media words" and printable names. 92 * 93 * XXX indexed directly by INTERNAL_CONFIG default_media field, 94 * (i.e., EPMEDIA_ constants) forcing order of entries. 95 * Note that 3 is reserved. 96 */ 97 const struct ep_media ep_vortex_media[] = { 98 { EP_PCI_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, 99 EPMEDIA_10BASE_T }, 100 { EP_PCI_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, 101 EPMEDIA_AUI }, 102 { 0, 0, "reserved", IFM_NONE, EPMEDIA_RESV1 }, 103 { EP_PCI_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, 104 EPMEDIA_10BASE_2 }, 105 { EP_PCI_100BASE_TX, EPC_100TX, "100-TX", IFM_ETHER|IFM_100_TX, 106 EPMEDIA_100BASE_TX }, 107 { EP_PCI_100BASE_FX, EPC_100FX, "100-FX", IFM_ETHER|IFM_100_FX, 108 EPMEDIA_100BASE_FX }, 109 { EP_PCI_100BASE_MII,EPC_MII, "mii", IFM_ETHER|IFM_100_TX, 110 EPMEDIA_MII }, 111 { EP_PCI_100BASE_T4, EPC_100T4, "100-T4", IFM_ETHER|IFM_100_T4, 112 EPMEDIA_100BASE_T4 } 113 }; 114 115 /* 116 * ep_media table for 3c509/3c509b/3c579/3c589: 117 * map from media-present bits in register CNFG_CNTRL 118 * (window 0, offset ?) to ifmedia "media words" and printable names. 119 */ 120 struct ep_media ep_isa_media[] = { 121 { EP_W0_CC_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, EPMEDIA_10BASE_T }, 122 { EP_W0_CC_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, EPMEDIA_AUI }, 123 { EP_W0_CC_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, EPMEDIA_10BASE_2 }, 124 }; 125 126 /* Map vortex reset_options bits to if_media codes. */ 127 const u_int ep_default_to_media[] = { 128 IFM_ETHER | IFM_10_T, 129 IFM_ETHER | IFM_10_5, 130 0, /* reserved by 3Com */ 131 IFM_ETHER | IFM_10_2, 132 IFM_ETHER | IFM_100_TX, 133 IFM_ETHER | IFM_100_FX, 134 IFM_ETHER | IFM_100_TX, /* XXX really MII: need to talk to PHY */ 135 IFM_ETHER | IFM_100_T4, 136 }; 137 138 struct cfdriver ep_cd = { 139 NULL, "ep", DV_IFNET 140 }; 141 142 void ep_vortex_probemedia(struct ep_softc *sc); 143 void ep_isa_probemedia(struct ep_softc *sc); 144 145 void eptxstat(struct ep_softc *); 146 int epstatus(struct ep_softc *); 147 int epioctl(struct ifnet *, u_long, caddr_t); 148 void epstart(struct ifnet *); 149 void epwatchdog(struct ifnet *); 150 void epreset(struct ep_softc *); 151 void epread(struct ep_softc *); 152 struct mbuf *epget(struct ep_softc *, int); 153 void epmbuffill(void *); 154 void epmbufempty(struct ep_softc *); 155 void epsetfilter(struct ep_softc *); 156 void ep_roadrunner_mii_enable(struct ep_softc *); 157 int epsetmedia(struct ep_softc *, int); 158 159 /* ifmedia callbacks */ 160 int ep_media_change(struct ifnet *); 161 void ep_media_status(struct ifnet *, struct ifmediareq *); 162 163 /* MII callbacks */ 164 int ep_mii_readreg(struct device *, int, int); 165 void ep_mii_writereg(struct device *, int, int, int); 166 void ep_statchg(struct device *); 167 168 void ep_mii_setbit(struct ep_softc *, u_int16_t); 169 void ep_mii_clrbit(struct ep_softc *, u_int16_t); 170 u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t); 171 void ep_mii_sync(struct ep_softc *); 172 void ep_mii_sendbits(struct ep_softc *, u_int32_t, int); 173 174 int epbusyeeprom(struct ep_softc *); 175 u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t); 176 177 static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg); 178 static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t); 179 static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t); 180 static __inline int ep_w1_reg(struct ep_softc *, int); 181 182 /* 183 * Issue a (reset) command, and be sure it has completed. 184 * Used for global reset, TX_RESET, RX_RESET. 185 */ 186 static inline void 187 ep_reset_cmd(sc, cmd, arg) 188 struct ep_softc *sc; 189 u_int cmd, arg; 190 { 191 bus_space_tag_t iot = sc->sc_iot; 192 bus_space_handle_t ioh = sc->sc_ioh; 193 194 bus_space_write_2(iot, ioh, cmd, arg); 195 ep_finish_reset(iot, ioh); 196 } 197 198 /* 199 * Wait for any pending reset to complete. 200 */ 201 static inline void 202 ep_finish_reset(iot, ioh) 203 bus_space_tag_t iot; 204 bus_space_handle_t ioh; 205 { 206 int i; 207 208 for (i = 0; i < 10000; i++) { 209 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 210 S_COMMAND_IN_PROGRESS) == 0) 211 break; 212 DELAY(10); 213 } 214 } 215 216 static inline void 217 ep_discard_rxtop(iot, ioh) 218 bus_space_tag_t iot; 219 bus_space_handle_t ioh; 220 { 221 int i; 222 223 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 224 225 /* 226 * Spin for about 1 msec, to avoid forcing a DELAY() between 227 * every received packet (adding latency and limiting pkt-recv rate). 228 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 229 * is about right. 230 */ 231 for (i = 0; i < 8000; i++) { 232 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 233 S_COMMAND_IN_PROGRESS) == 0) 234 return; 235 } 236 237 /* not fast enough, do DELAY()s */ 238 ep_finish_reset(iot, ioh); 239 } 240 241 /* 242 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset. 243 */ 244 static __inline int 245 ep_w1_reg(sc, reg) 246 struct ep_softc *sc; 247 int reg; 248 { 249 switch (sc->ep_chipset) { 250 case EP_CHIPSET_ROADRUNNER: 251 switch (reg) { 252 case EP_W1_FREE_TX: 253 case EP_W1_RUNNER_RDCTL: 254 case EP_W1_RUNNER_WRCTL: 255 return (reg); 256 } 257 return (reg + 0x10); 258 } 259 return (reg); 260 } 261 262 /* 263 * Back-end attach and configure. 264 */ 265 void 266 epconfig(sc, chipset, enaddr) 267 struct ep_softc *sc; 268 u_short chipset; 269 u_int8_t *enaddr; 270 { 271 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 272 bus_space_tag_t iot = sc->sc_iot; 273 bus_space_handle_t ioh = sc->sc_ioh; 274 u_int16_t i; 275 276 sc->ep_chipset = chipset; 277 278 /* 279 * We could have been groveling around in other register 280 * windows in the front-end; make sure we're in window 0 281 * to read the EEPROM. 282 */ 283 GO_WINDOW(0); 284 285 if (enaddr == NULL) { 286 /* 287 * Read the station address from the eeprom. 288 */ 289 for (i = 0; i < 3; i++) { 290 u_int16_t x = ep_read_eeprom(sc, i); 291 292 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8; 293 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x; 294 } 295 } else { 296 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 297 } 298 299 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 300 if (sc->ep_flags & EP_FLAGS_MII) 301 printf("\n"); 302 else 303 printf(", "); 304 305 /* 306 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte 307 * packets. Commands only take an 11-bit parameter, and 11 bits 308 * isn't enough to hold a full-size packet length. 309 * Commands to these cards implicitly upshift a packet size 310 * or threshold by 2 bits. 311 * To detect cards with large-packet support, we probe by setting 312 * the transmit threshold register, then change windows and 313 * read back the threshold register directly, and see if the 314 * threshold value was shifted or not. 315 */ 316 bus_space_write_2(iot, ioh, EP_COMMAND, 317 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 318 GO_WINDOW(5); 319 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 320 GO_WINDOW(1); 321 switch (i) { 322 case EP_LARGEWIN_PROBE: 323 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 324 sc->txashift = 0; 325 break; 326 327 case (EP_LARGEWIN_PROBE << 2): 328 sc->txashift = 2; 329 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */ 330 break; 331 332 default: 333 printf("wrote %x to TX_AVAIL_THRESH, read back %x. " 334 "Interface disabled\n", EP_THRESH_DISABLE, (int) i); 335 return; 336 } 337 338 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc); 339 340 /* 341 * Ensure Tx-available interrupts are enabled for 342 * start the interface. 343 * XXX should be in epinit()? 344 */ 345 bus_space_write_2(iot, ioh, EP_COMMAND, 346 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 347 348 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 349 ifp->if_softc = sc; 350 ifp->if_start = epstart; 351 ifp->if_ioctl = epioctl; 352 ifp->if_watchdog = epwatchdog; 353 ifp->if_flags = 354 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 355 /* 64 packets are around 100ms on 10Mbps */ 356 IFQ_SET_MAXLEN(&ifp->if_snd, 64); 357 IFQ_SET_READY(&ifp->if_snd); 358 359 if_attach(ifp); 360 ether_ifattach(ifp); 361 362 /* 363 * Finish configuration: 364 * determine chipset if the front-end couldn't do so, 365 * show board details, set media. 366 */ 367 368 GO_WINDOW(0); 369 370 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 371 ep_media_status); 372 sc->sc_mii.mii_ifp = ifp; 373 sc->sc_mii.mii_readreg = ep_mii_readreg; 374 sc->sc_mii.mii_writereg = ep_mii_writereg; 375 sc->sc_mii.mii_statchg = ep_statchg; 376 377 /* 378 * If we've got an indirect (ISA, PCMCIA?) board, the chipset 379 * is unknown. If the board has large-packet support, it's a 380 * Vortex/Boomerang, otherwise it's a 3c509. 381 * XXX use eeprom capability word instead? 382 */ 383 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN && sc->txashift) { 384 printf("warning: unknown chipset, possibly 3c515?\n"); 385 #ifdef notyet 386 sc->sc_chipset = EP_CHIPSET_VORTEX; 387 #endif /* notyet */ 388 } 389 390 /* 391 * Ascertain which media types are present and inform ifmedia. 392 */ 393 switch (sc->ep_chipset) { 394 case EP_CHIPSET_ROADRUNNER: 395 if (sc->ep_flags & EP_FLAGS_MII) { 396 ep_roadrunner_mii_enable(sc); 397 GO_WINDOW(0); 398 } 399 /* FALLTHROUGH */ 400 401 case EP_CHIPSET_BOOMERANG: 402 /* 403 * If the device has MII, probe it. We won't be using 404 * any `native' media in this case, only PHYs. If 405 * we don't, just treat the Boomerang like the Vortex. 406 */ 407 if (sc->ep_flags & EP_FLAGS_MII) { 408 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 409 MII_PHY_ANY, MII_OFFSET_ANY, 0); 410 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 411 ifmedia_add(&sc->sc_mii.mii_media, 412 IFM_ETHER|IFM_NONE, 0, NULL); 413 ifmedia_set(&sc->sc_mii.mii_media, 414 IFM_ETHER|IFM_NONE); 415 } else { 416 ifmedia_set(&sc->sc_mii.mii_media, 417 IFM_ETHER|IFM_AUTO); 418 } 419 break; 420 } 421 /* FALLTHROUGH */ 422 423 /* on a direct bus, the attach routine can tell, but check anyway. */ 424 case EP_CHIPSET_VORTEX: 425 case EP_CHIPSET_BOOMERANG2: 426 ep_vortex_probemedia(sc); 427 break; 428 429 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */ 430 case EP_CHIPSET_3C509: 431 default: 432 ep_isa_probemedia(sc); 433 break; 434 } 435 436 GO_WINDOW(1); /* Window 1 is operating window */ 437 438 sc->tx_start_thresh = 20; /* probably a good starting point. */ 439 440 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 441 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 442 } 443 444 int 445 ep_detach(self) 446 struct device *self; 447 { 448 struct ep_softc *sc = (struct ep_softc *)self; 449 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 450 451 if (sc->ep_flags & EP_FLAGS_MII) 452 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 453 454 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 455 456 ether_ifdetach(ifp); 457 if_detach(ifp); 458 459 return (0); 460 } 461 462 /* 463 * Find supported media on 3c509-generation hardware that doesn't have 464 * a "reset_options" register in window 3. 465 * Use the config_cntrl register in window 0 instead. 466 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 467 * that implement CONFIG_CTRL. We don't have a good way to set the 468 * default active medium; punt to ifconfig instead. 469 * 470 * XXX what about 3c515, pcmcia 10/100? 471 */ 472 void 473 ep_isa_probemedia(sc) 474 struct ep_softc *sc; 475 { 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 struct ifmedia *ifm = &sc->sc_mii.mii_media; 479 int conn, i; 480 u_int16_t ep_w0_config, port; 481 482 conn = 0; 483 GO_WINDOW(0); 484 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 485 for (i = 0; i < nitems(ep_isa_media); i++) { 486 struct ep_media * epm = ep_isa_media + i; 487 488 if ((ep_w0_config & epm->epm_eeprom_data) != 0) { 489 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 490 if (conn) 491 printf("/"); 492 printf("%s", epm->epm_name); 493 conn |= epm->epm_conn; 494 } 495 } 496 sc->ep_connectors = conn; 497 498 /* get default medium from EEPROM */ 499 if (epbusyeeprom(sc)) 500 return; /* XXX why is eeprom busy? */ 501 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 502 READ_EEPROM | EEPROM_ADDR_CFG); 503 if (epbusyeeprom(sc)) 504 return; /* XXX why is eeprom busy? */ 505 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 506 port = port >> 14; 507 508 printf(" (default %s)\n", ep_vortex_media[port].epm_name); 509 510 /* tell ifconfig what currently-active media is. */ 511 ifmedia_set(ifm, ep_default_to_media[port]); 512 513 /* XXX autoselect not yet implemented */ 514 } 515 516 517 /* 518 * Find media present on large-packet-capable elink3 devices. 519 * Show onboard configuration of large-packet-capable elink3 devices 520 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 521 * Use media and card-version info in window 3 instead. 522 * 523 * XXX how much of this works with 3c515, pcmcia 10/100? 524 */ 525 void 526 ep_vortex_probemedia(sc) 527 struct ep_softc *sc; 528 { 529 bus_space_tag_t iot = sc->sc_iot; 530 bus_space_handle_t ioh = sc->sc_ioh; 531 struct ifmedia *ifm = &sc->sc_mii.mii_media; 532 u_int config1, conn; 533 int reset_options; 534 int default_media; /* 3-bit encoding of default (EEPROM) media */ 535 int autoselect; /* boolean: should default to autoselect */ 536 const char *medium_name; 537 register int i; 538 539 GO_WINDOW(3); 540 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 541 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 542 GO_WINDOW(0); 543 544 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 545 autoselect = (config1 & CONFIG_AUTOSELECT) >> CONFIG_AUTOSELECT_SHIFT; 546 547 /* set available media options */ 548 conn = 0; 549 for (i = 0; i < nitems(ep_vortex_media); i++) { 550 const struct ep_media *epm = ep_vortex_media + i; 551 552 if ((reset_options & epm->epm_eeprom_data) != 0) { 553 if (conn) 554 printf("/"); 555 printf("%s", epm->epm_name); 556 conn |= epm->epm_conn; 557 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 558 } 559 } 560 561 sc->ep_connectors = conn; 562 563 /* Show eeprom's idea of default media. */ 564 medium_name = (default_media > nitems(ep_vortex_media) - 1) 565 ? "(unknown/impossible media)" 566 : ep_vortex_media[default_media].epm_name; 567 printf(" default %s%s", 568 medium_name, (autoselect) ? "/autoselect" : ""); 569 /* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/ 570 571 #ifdef notyet 572 /* 573 * Set default: either the active interface the card 574 * reads from the EEPROM, or if autoselect is true, 575 * whatever we find is actually connected. 576 * 577 * XXX autoselect not yet implemented. 578 */ 579 #endif /* notyet */ 580 581 /* tell ifconfig what currently-active media is. */ 582 ifmedia_set(ifm, ep_default_to_media[default_media]); 583 } 584 585 /* 586 * Bring device up. 587 * 588 * The order in here seems important. Otherwise we may not receive 589 * interrupts. ?! 590 */ 591 void 592 epinit(sc) 593 register struct ep_softc *sc; 594 { 595 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 596 bus_space_tag_t iot = sc->sc_iot; 597 bus_space_handle_t ioh = sc->sc_ioh; 598 int i; 599 600 /* make sure any pending reset has completed before touching board */ 601 ep_finish_reset(iot, ioh); 602 603 /* cancel any pending I/O */ 604 epstop(sc); 605 606 if (sc->bustype != EP_BUS_PCI) { 607 GO_WINDOW(0); 608 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 609 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 610 } 611 612 if (sc->bustype == EP_BUS_PCMCIA) { 613 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 614 } 615 616 GO_WINDOW(2); 617 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 618 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 619 sc->sc_arpcom.ac_enaddr[i]); 620 621 if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA) 622 /* 623 * Reset the station-address receive filter. 624 * A bug workaround for busmastering (Vortex, Demon) cards. 625 */ 626 for (i = 0; i < 6; i++) 627 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 628 629 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 630 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 631 632 GO_WINDOW(1); /* Window 1 is operating window */ 633 for (i = 0; i < 31; i++) 634 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 635 636 /* Set threshold for for Tx-space available interrupt. */ 637 bus_space_write_2(iot, ioh, EP_COMMAND, 638 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 639 640 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 641 /* Enable options in the PCMCIA LAN COR register, via 642 * RoadRunner Window 1. 643 * 644 * XXX MAGIC CONSTANTS! 645 */ 646 u_int16_t cor; 647 648 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 649 650 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 651 bus_space_write_2(iot, ioh, 0, cor); 652 653 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 654 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 655 656 if (sc->ep_flags & EP_FLAGS_MII) { 657 ep_roadrunner_mii_enable(sc); 658 GO_WINDOW(1); 659 } 660 } 661 662 /* Enable interrupts. */ 663 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | 664 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 665 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | 666 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 667 668 /* 669 * Attempt to get rid of any stray interrupts that occurred during 670 * configuration. On the i386 this isn't possible because one may 671 * already be queued. However, a single stray interrupt is 672 * unimportant. 673 */ 674 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 675 676 epsetfilter(sc); 677 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 678 679 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 680 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 681 682 epmbuffill(sc); 683 684 /* Interface is now `running', with no output active. */ 685 ifp->if_flags |= IFF_RUNNING; 686 ifp->if_flags &= ~IFF_OACTIVE; 687 688 /* Attempt to start output, if any. */ 689 epstart(ifp); 690 } 691 692 /* 693 * Set multicast receive filter. 694 * elink3 hardware has no selective multicast filter in hardware. 695 * Enable reception of all multicasts and filter in software. 696 */ 697 void 698 epsetfilter(sc) 699 register struct ep_softc *sc; 700 { 701 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 702 703 GO_WINDOW(1); /* Window 1 is operating window */ 704 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 705 FIL_INDIVIDUAL | FIL_BRDCST | 706 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 707 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 708 } 709 710 711 int 712 ep_media_change(ifp) 713 struct ifnet *ifp; 714 { 715 register struct ep_softc *sc = ifp->if_softc; 716 717 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 718 } 719 720 /* 721 * Reset and enable the MII on the RoadRunner. 722 */ 723 void 724 ep_roadrunner_mii_enable(sc) 725 struct ep_softc *sc; 726 { 727 bus_space_tag_t iot = sc->sc_iot; 728 bus_space_handle_t ioh = sc->sc_ioh; 729 730 GO_WINDOW(3); 731 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 732 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 733 delay(1000); 734 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 735 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII); 736 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 737 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 738 delay(1000); 739 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 740 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 741 } 742 743 /* 744 * Set active media to a specific given EPMEDIA_<> value. 745 * For vortex/demon/boomerang cards, update media field in w3_internal_config, 746 * and power on selected transceiver. 747 * For 3c509-generation cards (3c509/3c579/3c589/3c509B), 748 * update media field in w0_address_config, and power on selected xcvr. 749 */ 750 int 751 epsetmedia(sc, medium) 752 struct ep_softc *sc; 753 int medium; 754 { 755 bus_space_tag_t iot = sc->sc_iot; 756 bus_space_handle_t ioh = sc->sc_ioh; 757 int w4_media; 758 int config0, config1; 759 760 /* 761 * you can `ifconfig (link0|-link0) ep0' to get the following 762 * behaviour: 763 * -link0 disable AUI/UTP. enable BNC. 764 * link0 disable BNC. enable AUI. 765 * link1 if the card has a UTP connector, and link0 is 766 * set too, then you get the UTP port. 767 */ 768 769 /* 770 * First, change the media-control bits in EP_W4_MEDIA_TYPE. 771 */ 772 773 /* Turn everything off. First turn off linkbeat and UTP. */ 774 GO_WINDOW(4); 775 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 776 w4_media = w4_media & ~(ENABLE_UTP|SQE_ENABLE); 777 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media); 778 779 /* Turn off coax */ 780 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 781 delay(1000); 782 783 /* If the device has MII, select it, and then tell the 784 * PHY which media to use. 785 */ 786 if (sc->ep_flags & EP_FLAGS_MII) { 787 GO_WINDOW(3); 788 789 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 790 int resopt; 791 792 resopt = bus_space_read_2(iot, ioh, 793 EP_W3_RESET_OPTIONS); 794 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 795 resopt | EP_RUNNER_ENABLE_MII); 796 } 797 798 config0 = (u_int)bus_space_read_2(iot, ioh, 799 EP_W3_INTERNAL_CONFIG); 800 config1 = (u_int)bus_space_read_2(iot, ioh, 801 EP_W3_INTERNAL_CONFIG + 2); 802 803 config1 = config1 & ~CONFIG_MEDIAMASK; 804 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 805 806 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 807 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 808 GO_WINDOW(1); /* back to operating window */ 809 810 mii_mediachg(&sc->sc_mii); 811 return (0); 812 } 813 814 /* 815 * Now turn on the selected media/transceiver. 816 */ 817 GO_WINDOW(4); 818 switch (medium) { 819 case EPMEDIA_10BASE_T: 820 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP | 821 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0))); 822 break; 823 824 case EPMEDIA_10BASE_2: 825 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 826 DELAY(1000); /* 50ms not enough? */ 827 break; 828 829 /* XXX following only for new-generation cards */ 830 case EPMEDIA_100BASE_TX: 831 case EPMEDIA_100BASE_FX: 832 case EPMEDIA_100BASE_T4: /* XXX check documentation */ 833 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 834 w4_media | LINKBEAT_ENABLE); 835 DELAY(1000); /* not strictly necessary? */ 836 break; 837 838 case EPMEDIA_AUI: 839 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 840 w4_media | SQE_ENABLE); 841 DELAY(1000); /* not strictly necessary? */ 842 break; 843 case EPMEDIA_MII: 844 break; 845 default: 846 #if defined(EP_DEBUG) 847 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium); 848 #endif 849 break; 850 851 } 852 853 /* 854 * Tell the chip which PHY [sic] to use. 855 */ 856 switch (sc->ep_chipset) { 857 case EP_CHIPSET_VORTEX: 858 case EP_CHIPSET_BOOMERANG2: 859 GO_WINDOW(3); 860 config0 = (u_int)bus_space_read_2(iot, ioh, 861 EP_W3_INTERNAL_CONFIG); 862 config1 = (u_int)bus_space_read_2(iot, ioh, 863 EP_W3_INTERNAL_CONFIG + 2); 864 865 #if defined(EP_DEBUG) 866 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n", 867 sc->sc_dev.dv_xname, config0, config1); 868 #endif 869 config1 = config1 & ~CONFIG_MEDIAMASK; 870 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT); 871 872 #if defined(EP_DEBUG) 873 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n", 874 sc->sc_dev.dv_xname, medium, config1); 875 #endif 876 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 877 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 878 break; 879 880 default: 881 GO_WINDOW(0); 882 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 883 config0 &= 0x3fff; 884 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 885 config0 | (medium << 14)); 886 DELAY(1000); 887 break; 888 } 889 890 GO_WINDOW(1); /* Window 1 is operating window */ 891 return (0); 892 } 893 894 895 /* 896 * Get currently-selected media from card. 897 * (if_media callback, may be called before interface is brought up). 898 */ 899 void 900 ep_media_status(ifp, req) 901 struct ifnet *ifp; 902 struct ifmediareq *req; 903 { 904 register struct ep_softc *sc = ifp->if_softc; 905 bus_space_tag_t iot = sc->sc_iot; 906 bus_space_handle_t ioh = sc->sc_ioh; 907 u_int config1; 908 u_int ep_mediastatus; 909 910 /* 911 * If we have MII, go ask the PHY what's going on. 912 */ 913 if (sc->ep_flags & EP_FLAGS_MII) { 914 mii_pollstat(&sc->sc_mii); 915 req->ifm_active = sc->sc_mii.mii_media_active; 916 req->ifm_status = sc->sc_mii.mii_media_status; 917 return; 918 } 919 920 /* XXX read from softc when we start autosensing media */ 921 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 922 923 switch (sc->ep_chipset) { 924 case EP_CHIPSET_VORTEX: 925 case EP_CHIPSET_BOOMERANG: 926 GO_WINDOW(3); 927 delay(5000); 928 929 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 930 GO_WINDOW(1); 931 932 config1 = 933 (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 934 req->ifm_active = ep_default_to_media[config1]; 935 936 /* XXX check full-duplex bits? */ 937 938 GO_WINDOW(4); 939 req->ifm_status = IFM_AVALID; /* XXX */ 940 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 941 if (ep_mediastatus & LINKBEAT_DETECT) 942 req->ifm_status |= IFM_ACTIVE; /* XXX automedia */ 943 944 break; 945 946 case EP_CHIPSET_UNKNOWN: 947 case EP_CHIPSET_3C509: 948 req->ifm_status = 0; /* XXX */ 949 break; 950 951 default: 952 printf("%s: media_status on unknown chipset 0x%x\n", 953 ifp->if_xname, sc->ep_chipset); 954 break; 955 } 956 957 /* XXX look for softc heartbeat for other chips or media */ 958 959 GO_WINDOW(1); 960 return; 961 } 962 963 964 965 /* 966 * Start outputting on the interface. 967 * Always called as splnet(). 968 */ 969 void 970 epstart(ifp) 971 struct ifnet *ifp; 972 { 973 register struct ep_softc *sc = ifp->if_softc; 974 bus_space_tag_t iot = sc->sc_iot; 975 bus_space_handle_t ioh = sc->sc_ioh; 976 struct mbuf *m, *m0; 977 int sh, len, pad, txreg; 978 979 /* Don't transmit if interface is busy or not running */ 980 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 981 return; 982 983 startagain: 984 /* Sneak a peek at the next packet */ 985 IFQ_POLL(&ifp->if_snd, m0); 986 if (m0 == NULL) 987 return; 988 989 /* We need to use m->m_pkthdr.len, so require the header */ 990 if ((m0->m_flags & M_PKTHDR) == 0) 991 panic("epstart: no header mbuf"); 992 len = m0->m_pkthdr.len; 993 994 pad = (4 - len) & 3; 995 996 /* 997 * The 3c509 automatically pads short packets to minimum ethernet 998 * length, but we drop packets that are too large. Perhaps we should 999 * truncate them instead? 1000 */ 1001 if (len + pad > ETHER_MAX_LEN) { 1002 /* packet is obviously too large: toss it */ 1003 ++ifp->if_oerrors; 1004 IFQ_DEQUEUE(&ifp->if_snd, m0); 1005 m_freem(m0); 1006 goto readcheck; 1007 } 1008 1009 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 1010 len + pad + 4) { 1011 bus_space_write_2(iot, ioh, EP_COMMAND, 1012 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift)); 1013 /* not enough room in FIFO */ 1014 ifp->if_flags |= IFF_OACTIVE; 1015 return; 1016 } else { 1017 bus_space_write_2(iot, ioh, EP_COMMAND, 1018 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE); 1019 } 1020 1021 IFQ_DEQUEUE(&ifp->if_snd, m0); 1022 if (m0 == NULL) 1023 return; 1024 1025 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1026 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/)); 1027 1028 #if NBPFILTER > 0 1029 if (ifp->if_bpf) 1030 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1031 #endif 1032 1033 /* 1034 * Do the output at splhigh() so that an interrupt from another device 1035 * won't cause a FIFO underrun. 1036 */ 1037 sh = splhigh(); 1038 1039 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1040 1041 bus_space_write_2(iot, ioh, txreg, len); 1042 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1043 if (EP_IS_BUS_32(sc->bustype)) { 1044 for (m = m0; m; ) { 1045 if (m->m_len > 3) 1046 bus_space_write_raw_multi_4(iot, ioh, txreg, 1047 mtod(m, u_int8_t *), m->m_len & ~3); 1048 if (m->m_len & 3) 1049 bus_space_write_multi_1(iot, ioh, txreg, 1050 mtod(m, u_int8_t *) + (m->m_len & ~3), 1051 m->m_len & 3); 1052 MFREE(m, m0); 1053 m = m0; 1054 } 1055 } else { 1056 for (m = m0; m; ) { 1057 if (m->m_len > 1) 1058 bus_space_write_raw_multi_2(iot, ioh, txreg, 1059 mtod(m, u_int8_t *), m->m_len & ~1); 1060 if (m->m_len & 1) 1061 bus_space_write_1(iot, ioh, txreg, 1062 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1063 MFREE(m, m0); 1064 m = m0; 1065 } 1066 } 1067 while (pad--) 1068 bus_space_write_1(iot, ioh, txreg, 0); 1069 1070 splx(sh); 1071 1072 ++ifp->if_opackets; 1073 1074 readcheck: 1075 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1076 ERR_INCOMPLETE) == 0) { 1077 /* We received a complete packet. */ 1078 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1079 1080 if ((status & S_INTR_LATCH) == 0) { 1081 /* 1082 * No interrupt, read the packet and continue 1083 * Is this supposed to happen? Is my motherboard 1084 * completely busted? 1085 */ 1086 epread(sc); 1087 } else 1088 /* Got an interrupt, return to get it serviced. */ 1089 return; 1090 } else { 1091 /* Check if we are stuck and reset [see XXX comment] */ 1092 if (epstatus(sc)) { 1093 #ifdef EP_DEBUG 1094 if (ifp->if_flags & IFF_DEBUG) 1095 printf("%s: adapter reset\n", 1096 sc->sc_dev.dv_xname); 1097 #endif 1098 epreset(sc); 1099 } 1100 } 1101 1102 goto startagain; 1103 } 1104 1105 1106 /* 1107 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1108 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1109 * We detect this situation and we reset the adapter. 1110 * It happens at times when there is a lot of broadcast traffic 1111 * on the cable (once in a blue moon). 1112 */ 1113 int 1114 epstatus(sc) 1115 register struct ep_softc *sc; 1116 { 1117 bus_space_tag_t iot = sc->sc_iot; 1118 bus_space_handle_t ioh = sc->sc_ioh; 1119 u_int16_t fifost; 1120 1121 /* 1122 * Check the FIFO status and act accordingly 1123 */ 1124 GO_WINDOW(4); 1125 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1126 GO_WINDOW(1); 1127 1128 if (fifost & FIFOS_RX_UNDERRUN) { 1129 #ifdef EP_DEBUG 1130 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1131 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1132 #endif 1133 epreset(sc); 1134 return 0; 1135 } 1136 1137 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1138 #ifdef EP_DEBUG 1139 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1140 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1141 #endif 1142 return 1; 1143 } 1144 1145 if (fifost & FIFOS_RX_OVERRUN) { 1146 #ifdef EP_DEBUG 1147 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1148 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1149 #endif 1150 return 1; 1151 } 1152 1153 if (fifost & FIFOS_TX_OVERRUN) { 1154 #ifdef EP_DEBUG 1155 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1156 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1157 #endif 1158 epreset(sc); 1159 return 0; 1160 } 1161 1162 return 0; 1163 } 1164 1165 1166 void 1167 eptxstat(sc) 1168 register struct ep_softc *sc; 1169 { 1170 bus_space_tag_t iot = sc->sc_iot; 1171 bus_space_handle_t ioh = sc->sc_ioh; 1172 int i; 1173 1174 /* 1175 * We need to read+write TX_STATUS until we get a 0 status 1176 * in order to turn off the interrupt flag. 1177 */ 1178 while ((i = bus_space_read_1(iot, ioh, 1179 ep_w1_reg(sc, EP_W1_TX_STATUS))) & TXS_COMPLETE) { 1180 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1181 0x0); 1182 1183 if (i & TXS_JABBER) { 1184 ++sc->sc_arpcom.ac_if.if_oerrors; 1185 #ifdef EP_DEBUG 1186 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1187 printf("%s: jabber (%x)\n", 1188 sc->sc_dev.dv_xname, i); 1189 #endif 1190 epreset(sc); 1191 } else if (i & TXS_UNDERRUN) { 1192 ++sc->sc_arpcom.ac_if.if_oerrors; 1193 #ifdef EP_DEBUG 1194 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1195 printf("%s: fifo underrun (%x) @%d\n", 1196 sc->sc_dev.dv_xname, i, 1197 sc->tx_start_thresh); 1198 #endif 1199 if (sc->tx_succ_ok < 100) 1200 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1201 sc->tx_start_thresh + 20); 1202 sc->tx_succ_ok = 0; 1203 epreset(sc); 1204 } else if (i & TXS_MAX_COLLISION) { 1205 ++sc->sc_arpcom.ac_if.if_collisions; 1206 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1207 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1208 } else 1209 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1210 } 1211 } 1212 1213 int 1214 epintr(arg) 1215 void *arg; 1216 { 1217 register struct ep_softc *sc = arg; 1218 bus_space_tag_t iot = sc->sc_iot; 1219 bus_space_handle_t ioh = sc->sc_ioh; 1220 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1221 u_int16_t status; 1222 int ret = 0; 1223 1224 for (;;) { 1225 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1226 1227 status = bus_space_read_2(iot, ioh, EP_STATUS); 1228 1229 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1230 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) 1231 break; 1232 1233 ret = 1; 1234 1235 /* 1236 * Acknowledge any interrupts. It's important that we do this 1237 * first, since there would otherwise be a race condition. 1238 * Due to the i386 interrupt queueing, we may get spurious 1239 * interrupts occasionally. 1240 */ 1241 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status); 1242 1243 if (status & S_RX_COMPLETE) 1244 epread(sc); 1245 if (status & S_TX_AVAIL) { 1246 ifp->if_flags &= ~IFF_OACTIVE; 1247 epstart(ifp); 1248 } 1249 if (status & S_CARD_FAILURE) { 1250 epreset(sc); 1251 return (1); 1252 } 1253 if (status & S_TX_COMPLETE) { 1254 eptxstat(sc); 1255 epstart(ifp); 1256 } 1257 } 1258 1259 /* no more interrupts */ 1260 return (ret); 1261 } 1262 1263 void 1264 epread(sc) 1265 register struct ep_softc *sc; 1266 { 1267 bus_space_tag_t iot = sc->sc_iot; 1268 bus_space_handle_t ioh = sc->sc_ioh; 1269 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1270 struct mbuf *m; 1271 int len; 1272 1273 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1274 1275 again: 1276 #ifdef EP_DEBUG 1277 if (ifp->if_flags & IFF_DEBUG) { 1278 int err = len & ERR_MASK; 1279 char *s = NULL; 1280 1281 if (len & ERR_INCOMPLETE) 1282 s = "incomplete packet"; 1283 else if (err == ERR_OVERRUN) 1284 s = "packet overrun"; 1285 else if (err == ERR_RUNT) 1286 s = "runt packet"; 1287 else if (err == ERR_ALIGNMENT) 1288 s = "bad alignment"; 1289 else if (err == ERR_CRC) 1290 s = "bad crc"; 1291 else if (err == ERR_OVERSIZE) 1292 s = "oversized packet"; 1293 else if (err == ERR_DRIBBLE) 1294 s = "dribble bits"; 1295 1296 if (s) 1297 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1298 } 1299 #endif 1300 1301 if (len & ERR_INCOMPLETE) 1302 return; 1303 1304 if (len & ERR_RX) { 1305 ++ifp->if_ierrors; 1306 goto abort; 1307 } 1308 1309 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1310 1311 /* Pull packet off interface. */ 1312 m = epget(sc, len); 1313 if (m == NULL) { 1314 ifp->if_ierrors++; 1315 goto abort; 1316 } 1317 1318 ++ifp->if_ipackets; 1319 1320 #if NBPFILTER > 0 1321 /* 1322 * Check if there's a BPF listener on this interface. 1323 * If so, hand off the raw packet to BPF. 1324 */ 1325 if (ifp->if_bpf) 1326 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1327 #endif 1328 1329 ether_input_mbuf(ifp, m); 1330 1331 /* 1332 * In periods of high traffic we can actually receive enough 1333 * packets so that the fifo overrun bit will be set at this point, 1334 * even though we just read a packet. In this case we 1335 * are not going to receive any more interrupts. We check for 1336 * this condition and read again until the fifo is not full. 1337 * We could simplify this test by not using epstatus(), but 1338 * rechecking the RX_STATUS register directly. This test could 1339 * result in unnecessary looping in cases where there is a new 1340 * packet but the fifo is not full, but it will not fix the 1341 * stuck behavior. 1342 * 1343 * Even with this improvement, we still get packet overrun errors 1344 * which are hurting performance. Maybe when I get some more time 1345 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1346 */ 1347 if (epstatus(sc)) { 1348 len = bus_space_read_2(iot, ioh, 1349 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1350 /* Check if we are stuck and reset [see XXX comment] */ 1351 if (len & ERR_INCOMPLETE) { 1352 #ifdef EP_DEBUG 1353 if (ifp->if_flags & IFF_DEBUG) 1354 printf("%s: adapter reset\n", 1355 sc->sc_dev.dv_xname); 1356 #endif 1357 epreset(sc); 1358 return; 1359 } 1360 goto again; 1361 } 1362 1363 return; 1364 1365 abort: 1366 ep_discard_rxtop(iot, ioh); 1367 } 1368 1369 struct mbuf * 1370 epget(sc, totlen) 1371 struct ep_softc *sc; 1372 int totlen; 1373 { 1374 bus_space_tag_t iot = sc->sc_iot; 1375 bus_space_handle_t ioh = sc->sc_ioh; 1376 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1377 struct mbuf *m; 1378 int len, pad, off, sh, rxreg; 1379 1380 splassert(IPL_NET); 1381 1382 m = sc->mb[sc->next_mb]; 1383 sc->mb[sc->next_mb] = NULL; 1384 if (m == NULL) { 1385 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1386 /* If the queue is no longer full, refill. */ 1387 if (!timeout_pending(&sc->sc_epmbuffill_tmo)) 1388 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1389 } 1390 if (!m) 1391 return (NULL); 1392 1393 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1394 1395 len = MCLBYTES; 1396 m->m_pkthdr.rcvif = ifp; 1397 m->m_pkthdr.len = totlen; 1398 m->m_len = totlen; 1399 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1400 m->m_data += pad; 1401 len -= pad; 1402 1403 /* 1404 * We read the packet at splhigh() so that an interrupt from another 1405 * device doesn't cause the card's buffer to overflow while we're 1406 * reading it. We may still lose packets at other times. 1407 */ 1408 sh = splhigh(); 1409 1410 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1411 1412 off = 0; 1413 while (totlen) { 1414 len = min(totlen, M_TRAILINGSPACE(m)); 1415 if (len == 0) 1416 panic("ep_get: packet does not fit in MCLBYTES"); 1417 1418 if (EP_IS_BUS_32(sc->bustype)) 1419 pad = (u_long)(mtod(m, u_int8_t *) + off) & 0x3; 1420 else 1421 pad = (u_long)(mtod(m, u_int8_t *) + off) & 0x1; 1422 1423 if (pad) { 1424 bus_space_read_multi_1(iot, ioh, rxreg, 1425 mtod(m, u_int8_t *) + off, pad); 1426 } else if (EP_IS_BUS_32(sc->bustype) && len > 3) { 1427 len &= ~3; 1428 bus_space_read_raw_multi_4(iot, ioh, rxreg, 1429 mtod(m, u_int8_t *) + off, len); 1430 } else if (len > 1) { 1431 len &= ~1; 1432 bus_space_read_raw_multi_2(iot, ioh, rxreg, 1433 mtod(m, u_int8_t *) + off, len); 1434 } else { 1435 bus_space_read_multi_1(iot, ioh, rxreg, 1436 mtod(m, u_int8_t *) + off, len); 1437 } 1438 off += len; 1439 totlen -= len; 1440 } 1441 1442 ep_discard_rxtop(iot, ioh); 1443 1444 splx(sh); 1445 1446 return m; 1447 } 1448 1449 int 1450 epioctl(ifp, cmd, data) 1451 register struct ifnet *ifp; 1452 u_long cmd; 1453 caddr_t data; 1454 { 1455 struct ep_softc *sc = ifp->if_softc; 1456 struct ifaddr *ifa = (struct ifaddr *)data; 1457 struct ifreq *ifr = (struct ifreq *)data; 1458 int s, error = 0; 1459 1460 s = splnet(); 1461 1462 switch (cmd) { 1463 case SIOCSIFADDR: 1464 ifp->if_flags |= IFF_UP; 1465 1466 switch (ifa->ifa_addr->sa_family) { 1467 #ifdef INET 1468 case AF_INET: 1469 epinit(sc); 1470 arp_ifinit(&sc->sc_arpcom, ifa); 1471 break; 1472 #endif 1473 default: 1474 epinit(sc); 1475 break; 1476 } 1477 break; 1478 1479 case SIOCSIFMEDIA: 1480 case SIOCGIFMEDIA: 1481 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1482 break; 1483 1484 case SIOCSIFFLAGS: 1485 if ((ifp->if_flags & IFF_UP) == 0 && 1486 (ifp->if_flags & IFF_RUNNING) != 0) { 1487 /* 1488 * If interface is marked down and it is running, then 1489 * stop it. 1490 */ 1491 epstop(sc); 1492 ifp->if_flags &= ~IFF_RUNNING; 1493 } else if ((ifp->if_flags & IFF_UP) != 0 && 1494 (ifp->if_flags & IFF_RUNNING) == 0) { 1495 /* 1496 * If interface is marked up and it is stopped, then 1497 * start it. 1498 */ 1499 epinit(sc); 1500 } else if ((ifp->if_flags & IFF_UP) != 0) { 1501 /* 1502 * Reset the interface to pick up changes in any other 1503 * flags that affect hardware registers. 1504 */ 1505 epinit(sc); 1506 } 1507 break; 1508 1509 default: 1510 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1511 } 1512 1513 if (error == ENETRESET) { 1514 if (ifp->if_flags & IFF_RUNNING) 1515 epreset(sc); 1516 error = 0; 1517 } 1518 1519 splx(s); 1520 return (error); 1521 } 1522 1523 void 1524 epreset(sc) 1525 struct ep_softc *sc; 1526 { 1527 int s; 1528 1529 s = splnet(); 1530 epinit(sc); 1531 splx(s); 1532 } 1533 1534 void 1535 epwatchdog(ifp) 1536 struct ifnet *ifp; 1537 { 1538 struct ep_softc *sc = ifp->if_softc; 1539 1540 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1541 ++sc->sc_arpcom.ac_if.if_oerrors; 1542 1543 epreset(sc); 1544 } 1545 1546 void 1547 epstop(sc) 1548 register struct ep_softc *sc; 1549 { 1550 bus_space_tag_t iot = sc->sc_iot; 1551 bus_space_handle_t ioh = sc->sc_ioh; 1552 1553 if (sc->ep_flags & EP_FLAGS_MII) { 1554 mii_down(&sc->sc_mii); 1555 } 1556 1557 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1558 /* Clear the FIFO buffer count, thus halting 1559 * any currently-running transactions. 1560 */ 1561 GO_WINDOW(1); /* sanity */ 1562 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1563 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1564 } 1565 1566 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1567 ep_discard_rxtop(iot, ioh); 1568 1569 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1570 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1571 1572 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 1573 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 1574 1575 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1576 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1577 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1578 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1579 1580 epmbufempty(sc); 1581 } 1582 1583 /* 1584 * We get eeprom data from the id_port given an offset into the 1585 * eeprom. Basically; after the ID_sequence is sent to all of 1586 * the cards; they enter the ID_CMD state where they will accept 1587 * command requests. 0x80-0xbf loads the eeprom data. We then 1588 * read the port 16 times and with every read; the cards check 1589 * for contention (ie: if one card writes a 0 bit and another 1590 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1591 * each card compares the data on the bus; if there is a difference 1592 * then that card goes into ID_WAIT state again). In the meantime; 1593 * one bit of data is returned in the AX register which is conveniently 1594 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1595 * bit of data with each read. 1596 * 1597 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1598 */ 1599 u_int16_t 1600 epreadeeprom(iot, ioh, offset) 1601 bus_space_tag_t iot; 1602 bus_space_handle_t ioh; 1603 int offset; 1604 { 1605 u_int16_t data = 0; 1606 int i; 1607 1608 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1609 delay(1000); 1610 for (i = 0; i < 16; i++) 1611 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1612 return (data); 1613 } 1614 1615 int 1616 epbusyeeprom(sc) 1617 struct ep_softc *sc; 1618 { 1619 bus_space_tag_t iot = sc->sc_iot; 1620 bus_space_handle_t ioh = sc->sc_ioh; 1621 int i = 100, j; 1622 1623 while (i--) { 1624 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1625 if (j & EEPROM_BUSY) 1626 delay(100); 1627 else 1628 break; 1629 } 1630 if (!i) { 1631 printf("\n%s: eeprom failed to come ready\n", 1632 sc->sc_dev.dv_xname); 1633 return (1); 1634 } 1635 if (sc->bustype != EP_BUS_PCMCIA && sc->bustype != EP_BUS_PCI && 1636 (j & EEPROM_TST_MODE)) { 1637 printf("\n%s: erase pencil mark, or disable PnP mode!\n", 1638 sc->sc_dev.dv_xname); 1639 return (1); 1640 } 1641 return (0); 1642 } 1643 1644 u_int16_t 1645 ep_read_eeprom(sc, offset) 1646 struct ep_softc *sc; 1647 u_int16_t offset; 1648 { 1649 u_int16_t readcmd; 1650 1651 /* 1652 * RoadRunner has a larger EEPROM, so a different read command 1653 * is required. 1654 */ 1655 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) 1656 readcmd = READ_EEPROM_RR; 1657 else 1658 readcmd = READ_EEPROM; 1659 1660 if (epbusyeeprom(sc)) 1661 return (0); /* XXX why is eeprom busy? */ 1662 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND, 1663 readcmd | offset); 1664 if (epbusyeeprom(sc)) 1665 return (0); /* XXX why is eeprom busy? */ 1666 1667 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)); 1668 } 1669 1670 void 1671 epmbuffill(v) 1672 void *v; 1673 { 1674 struct ep_softc *sc = v; 1675 int s, i; 1676 1677 s = splnet(); 1678 for (i = 0; i < MAX_MBS; i++) { 1679 if (sc->mb[i] == NULL) { 1680 sc->mb[i] = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1681 if (sc->mb[i] == NULL) 1682 break; 1683 } 1684 } 1685 /* If the queue was not filled, try again. */ 1686 if (i < MAX_MBS) 1687 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1688 splx(s); 1689 } 1690 1691 void 1692 epmbufempty(sc) 1693 struct ep_softc *sc; 1694 { 1695 int s, i; 1696 1697 s = splnet(); 1698 for (i = 0; i<MAX_MBS; i++) { 1699 if (sc->mb[i]) { 1700 m_freem(sc->mb[i]); 1701 sc->mb[i] = NULL; 1702 } 1703 } 1704 sc->next_mb = 0; 1705 timeout_del(&sc->sc_epmbuffill_tmo); 1706 splx(s); 1707 } 1708 1709 void 1710 ep_mii_setbit(sc, bit) 1711 struct ep_softc *sc; 1712 u_int16_t bit; 1713 { 1714 u_int16_t val; 1715 1716 /* We assume we're already in Window 4 */ 1717 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1718 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1719 val | bit); 1720 } 1721 1722 void 1723 ep_mii_clrbit(sc, bit) 1724 struct ep_softc *sc; 1725 u_int16_t bit; 1726 { 1727 u_int16_t val; 1728 1729 /* We assume we're already in Window 4 */ 1730 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1731 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1732 val & ~bit); 1733 } 1734 1735 u_int16_t 1736 ep_mii_readbit(sc, bit) 1737 struct ep_softc *sc; 1738 u_int16_t bit; 1739 { 1740 1741 /* We assume we're already in Window 4 */ 1742 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1743 bit); 1744 } 1745 1746 void 1747 ep_mii_sync(sc) 1748 struct ep_softc *sc; 1749 { 1750 int i; 1751 1752 /* We assume we're already in Window 4 */ 1753 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1754 for (i = 0; i < 32; i++) { 1755 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1756 ep_mii_setbit(sc, PHYSMGMT_CLK); 1757 } 1758 } 1759 1760 void 1761 ep_mii_sendbits(sc, data, nbits) 1762 struct ep_softc *sc; 1763 u_int32_t data; 1764 int nbits; 1765 { 1766 int i; 1767 1768 /* We assume we're already in Window 4 */ 1769 ep_mii_setbit(sc, PHYSMGMT_DIR); 1770 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1771 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1772 ep_mii_readbit(sc, PHYSMGMT_CLK); 1773 if (data & i) 1774 ep_mii_setbit(sc, PHYSMGMT_DATA); 1775 else 1776 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1777 ep_mii_setbit(sc, PHYSMGMT_CLK); 1778 ep_mii_readbit(sc, PHYSMGMT_CLK); 1779 } 1780 } 1781 1782 int 1783 ep_mii_readreg(self, phy, reg) 1784 struct device *self; 1785 int phy, reg; 1786 { 1787 struct ep_softc *sc = (struct ep_softc *)self; 1788 int val = 0, i, err; 1789 1790 /* 1791 * Read the PHY register by manually driving the MII control lines. 1792 */ 1793 1794 GO_WINDOW(4); 1795 1796 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1797 1798 ep_mii_sync(sc); 1799 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1800 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1801 ep_mii_sendbits(sc, phy, 5); 1802 ep_mii_sendbits(sc, reg, 5); 1803 1804 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1805 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1806 ep_mii_setbit(sc, PHYSMGMT_CLK); 1807 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1808 1809 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1810 ep_mii_setbit(sc, PHYSMGMT_CLK); 1811 1812 /* Even if an error occurs, must still clock out the cycle. */ 1813 for (i = 0; i < 16; i++) { 1814 val <<= 1; 1815 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1816 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1817 val |= 1; 1818 ep_mii_setbit(sc, PHYSMGMT_CLK); 1819 } 1820 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1821 ep_mii_setbit(sc, PHYSMGMT_CLK); 1822 1823 GO_WINDOW(1); /* back to operating window */ 1824 1825 return (err ? 0 : val); 1826 } 1827 1828 void 1829 ep_mii_writereg(self, phy, reg, val) 1830 struct device *self; 1831 int phy, reg, val; 1832 { 1833 struct ep_softc *sc = (struct ep_softc *)self; 1834 1835 /* 1836 * Write the PHY register by manually driving the MII control lines. 1837 */ 1838 1839 GO_WINDOW(4); 1840 1841 ep_mii_sync(sc); 1842 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1843 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1844 ep_mii_sendbits(sc, phy, 5); 1845 ep_mii_sendbits(sc, reg, 5); 1846 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1847 ep_mii_sendbits(sc, val, 16); 1848 1849 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1850 ep_mii_setbit(sc, PHYSMGMT_CLK); 1851 1852 GO_WINDOW(1); /* back to operating window */ 1853 } 1854 1855 void 1856 ep_statchg(self) 1857 struct device *self; 1858 { 1859 struct ep_softc *sc = (struct ep_softc *)self; 1860 bus_space_tag_t iot = sc->sc_iot; 1861 bus_space_handle_t ioh = sc->sc_ioh; 1862 int mctl; 1863 1864 /* XXX Update ifp->if_baudrate */ 1865 1866 GO_WINDOW(3); 1867 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 1868 if (sc->sc_mii.mii_media_active & IFM_FDX) 1869 mctl |= MAC_CONTROL_FDX; 1870 else 1871 mctl &= ~MAC_CONTROL_FDX; 1872 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 1873 GO_WINDOW(1); /* back to operating window */ 1874 } 1875