1 /* $OpenBSD: elink3.c,v 1.53 2001/07/08 23:38:05 fgsch Exp $ */ 2 /* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org> 6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Herb Peyerl. 20 * 4. The name of Herb Peyerl may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/ioctl.h> 42 #include <sys/errno.h> 43 #include <sys/syslog.h> 44 #include <sys/select.h> 45 #include <sys/device.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_types.h> 50 #include <net/netisr.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #include <net/bpfdesc.h> 64 #endif 65 66 #include <machine/cpu.h> 67 #include <machine/bus.h> 68 #include <machine/intr.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/ic/elink3var.h> 74 #include <dev/ic/elink3reg.h> 75 76 /* 77 * Structure to map media-present bits in boards to 78 * ifmedia codes and printable media names. Used for table-driven 79 * ifmedia initialization. 80 */ 81 struct ep_media { 82 int epm_eeprom_data; /* bitmask for eeprom config */ 83 int epm_conn; /* sc->ep_connectors code for medium */ 84 char* epm_name; /* name of medium */ 85 int epm_ifmedia; /* ifmedia word for medium */ 86 int epm_ifdata; 87 }; 88 89 /* 90 * ep_media table for Vortex/Demon/Boomerang: 91 * map from media-present bits in register RESET_OPTIONS+2 92 * to ifmedia "media words" and printable names. 93 * 94 * XXX indexed directly by INTERNAL_CONFIG default_media field, 95 * (i.e., EPMEDIA_ constants) forcing order of entries. 96 * Note that 3 is reserved. 97 */ 98 struct ep_media ep_vortex_media[8] = { 99 { EP_PCI_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, 100 EPMEDIA_10BASE_T }, 101 { EP_PCI_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, 102 EPMEDIA_AUI }, 103 { 0, 0, "reserved", IFM_NONE, EPMEDIA_RESV1 }, 104 { EP_PCI_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, 105 EPMEDIA_10BASE_2 }, 106 { EP_PCI_100BASE_TX, EPC_100TX, "100-TX", IFM_ETHER|IFM_100_TX, 107 EPMEDIA_100BASE_TX }, 108 { EP_PCI_100BASE_FX, EPC_100FX, "100-FX", IFM_ETHER|IFM_100_FX, 109 EPMEDIA_100BASE_FX }, 110 { EP_PCI_100BASE_MII,EPC_MII, "mii", IFM_ETHER|IFM_100_TX, 111 EPMEDIA_MII }, 112 { EP_PCI_100BASE_T4, EPC_100T4, "100-T4", IFM_ETHER|IFM_100_T4, 113 EPMEDIA_100BASE_T4 } 114 }; 115 116 /* 117 * ep_media table for 3c509/3c509b/3c579/3c589: 118 * map from media-present bits in register CNFG_CNTRL 119 * (window 0, offset ?) to ifmedia "media words" and printable names. 120 */ 121 struct ep_media ep_isa_media[3] = { 122 { EP_W0_CC_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, EPMEDIA_10BASE_T }, 123 { EP_W0_CC_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, EPMEDIA_AUI }, 124 { EP_W0_CC_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, EPMEDIA_10BASE_2 }, 125 }; 126 127 /* Map vortex reset_options bits to if_media codes. */ 128 const u_int ep_default_to_media[8] = { 129 IFM_ETHER | IFM_10_T, 130 IFM_ETHER | IFM_10_5, 131 0, /* reserved by 3Com */ 132 IFM_ETHER | IFM_10_2, 133 IFM_ETHER | IFM_100_TX, 134 IFM_ETHER | IFM_100_FX, 135 IFM_ETHER | IFM_100_TX, /* XXX really MII: need to talk to PHY */ 136 IFM_ETHER | IFM_100_T4, 137 }; 138 139 struct cfdriver ep_cd = { 140 NULL, "ep", DV_IFNET 141 }; 142 143 void ep_vortex_probemedia __P((struct ep_softc *sc)); 144 void ep_isa_probemedia __P((struct ep_softc *sc)); 145 146 void eptxstat __P((struct ep_softc *)); 147 int epstatus __P((struct ep_softc *)); 148 int epioctl __P((struct ifnet *, u_long, caddr_t)); 149 void epstart __P((struct ifnet *)); 150 void epwatchdog __P((struct ifnet *)); 151 void epreset __P((struct ep_softc *)); 152 void epread __P((struct ep_softc *)); 153 struct mbuf *epget __P((struct ep_softc *, int)); 154 void epmbuffill __P((void *)); 155 void epmbufempty __P((struct ep_softc *)); 156 void epsetfilter __P((struct ep_softc *)); 157 void ep_roadrunner_mii_enable __P((struct ep_softc *)); 158 int epsetmedia __P((struct ep_softc *, int)); 159 160 /* ifmedia callbacks */ 161 int ep_media_change __P((struct ifnet *)); 162 void ep_media_status __P((struct ifnet *, struct ifmediareq *)); 163 164 /* MII callbacks */ 165 int ep_mii_readreg __P((struct device *, int, int)); 166 void ep_mii_writereg __P((struct device *, int, int, int)); 167 void ep_statchg __P((struct device *)); 168 169 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 170 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 171 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 172 void ep_mii_sync __P((struct ep_softc *)); 173 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 174 175 int epbusyeeprom __P((struct ep_softc *)); 176 u_int16_t ep_read_eeprom __P((struct ep_softc *, u_int16_t)); 177 178 static inline void ep_reset_cmd __P((struct ep_softc *sc, u_int cmd,u_int arg)); 179 static inline void ep_finish_reset __P((bus_space_tag_t, bus_space_handle_t)); 180 static inline void ep_discard_rxtop __P((bus_space_tag_t, bus_space_handle_t)); 181 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 182 183 /* 184 * Issue a (reset) command, and be sure it has completed. 185 * Used for global reset, TX_RESET, RX_RESET. 186 */ 187 static inline void 188 ep_reset_cmd(sc, cmd, arg) 189 struct ep_softc *sc; 190 u_int cmd, arg; 191 { 192 bus_space_tag_t iot = sc->sc_iot; 193 bus_space_handle_t ioh = sc->sc_ioh; 194 195 bus_space_write_2(iot, ioh, cmd, arg); 196 ep_finish_reset(iot, ioh); 197 } 198 199 /* 200 * Wait for any pending reset to complete. 201 */ 202 static inline void 203 ep_finish_reset(iot, ioh) 204 bus_space_tag_t iot; 205 bus_space_handle_t ioh; 206 { 207 int i; 208 209 for (i = 0; i < 10000; i++) { 210 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 211 S_COMMAND_IN_PROGRESS) == 0) 212 break; 213 DELAY(10); 214 } 215 } 216 217 static inline void 218 ep_discard_rxtop(iot, ioh) 219 bus_space_tag_t iot; 220 bus_space_handle_t ioh; 221 { 222 int i; 223 224 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 225 226 /* 227 * Spin for about 1 msec, to avoid forcing a DELAY() between 228 * every received packet (adding latency and limiting pkt-recv rate). 229 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 230 * is about right. 231 */ 232 for (i = 0; i < 8000; i++) { 233 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 234 S_COMMAND_IN_PROGRESS) == 0) 235 return; 236 } 237 238 /* not fast enough, do DELAY()s */ 239 ep_finish_reset(iot, ioh); 240 } 241 242 /* 243 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset. 244 */ 245 static __inline int 246 ep_w1_reg(sc, reg) 247 struct ep_softc *sc; 248 int reg; 249 { 250 switch (sc->ep_chipset) { 251 case EP_CHIPSET_ROADRUNNER: 252 switch (reg) { 253 case EP_W1_FREE_TX: 254 case EP_W1_RUNNER_RDCTL: 255 case EP_W1_RUNNER_WRCTL: 256 return (reg); 257 } 258 return (reg + 0x10); 259 } 260 return (reg); 261 } 262 263 /* 264 * Back-end attach and configure. 265 */ 266 void 267 epconfig(sc, chipset, enaddr) 268 struct ep_softc *sc; 269 u_short chipset; 270 u_int8_t *enaddr; 271 { 272 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 273 bus_space_tag_t iot = sc->sc_iot; 274 bus_space_handle_t ioh = sc->sc_ioh; 275 u_int16_t i; 276 277 sc->ep_chipset = chipset; 278 279 /* 280 * We could have been groveling around in other register 281 * windows in the front-end; make sure we're in window 0 282 * to read the EEPROM. 283 */ 284 GO_WINDOW(0); 285 286 if (enaddr == NULL) { 287 /* 288 * Read the station address from the eeprom. 289 */ 290 for (i = 0; i < 3; i++) { 291 u_int16_t x = ep_read_eeprom(sc, i); 292 293 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8; 294 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x; 295 } 296 } else { 297 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 298 } 299 300 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 301 if (sc->ep_flags & EP_FLAGS_MII) 302 printf("\n"); 303 else 304 printf(", "); 305 306 /* 307 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte 308 * packets. Commands only take an 11-bit parameter, and 11 bits 309 * isn't enough to hold a full-size packet length. 310 * Commands to these cards implicitly upshift a packet size 311 * or threshold by 2 bits. 312 * To detect cards with large-packet support, we probe by setting 313 * the transmit threshold register, then change windows and 314 * read back the threshold register directly, and see if the 315 * threshold value was shifted or not. 316 */ 317 bus_space_write_2(iot, ioh, EP_COMMAND, 318 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 319 GO_WINDOW(5); 320 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 321 GO_WINDOW(1); 322 switch (i) { 323 case EP_LARGEWIN_PROBE: 324 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 325 sc->txashift = 0; 326 break; 327 328 case (EP_LARGEWIN_PROBE << 2): 329 sc->txashift = 2; 330 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */ 331 break; 332 333 default: 334 printf("wrote %x to TX_AVAIL_THRESH, read back %x. " 335 "Interface disabled\n", EP_THRESH_DISABLE, (int) i); 336 return; 337 } 338 339 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc); 340 341 /* 342 * Ensure Tx-available interrupts are enabled for 343 * start the interface. 344 * XXX should be in epinit()? 345 */ 346 bus_space_write_2(iot, ioh, EP_COMMAND, 347 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 348 349 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 350 ifp->if_softc = sc; 351 ifp->if_start = epstart; 352 ifp->if_ioctl = epioctl; 353 ifp->if_watchdog = epwatchdog; 354 ifp->if_flags = 355 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 356 IFQ_SET_READY(&ifp->if_snd); 357 358 if_attach(ifp); 359 ether_ifattach(ifp); 360 361 /* 362 * Finish configuration: 363 * determine chipset if the front-end couldn't do so, 364 * show board details, set media. 365 */ 366 367 GO_WINDOW(0); 368 369 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 370 ep_media_status); 371 sc->sc_mii.mii_ifp = ifp; 372 sc->sc_mii.mii_readreg = ep_mii_readreg; 373 sc->sc_mii.mii_writereg = ep_mii_writereg; 374 sc->sc_mii.mii_statchg = ep_statchg; 375 376 /* 377 * If we've got an indirect (ISA, PCMCIA?) board, the chipset 378 * is unknown. If the board has large-packet support, it's a 379 * Vortex/Boomerang, otherwise it's a 3c509. 380 * XXX use eeprom capability word instead? 381 */ 382 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN && sc->txashift) { 383 printf("warning: unknown chipset, possibly 3c515?\n"); 384 #ifdef notyet 385 sc->sc_chipset = EP_CHIPSET_VORTEX; 386 #endif /* notyet */ 387 } 388 389 /* 390 * Ascertain which media types are present and inform ifmedia. 391 */ 392 switch (sc->ep_chipset) { 393 case EP_CHIPSET_ROADRUNNER: 394 if (sc->ep_flags & EP_FLAGS_MII) { 395 ep_roadrunner_mii_enable(sc); 396 GO_WINDOW(0); 397 } 398 /* FALLTHROUGH */ 399 400 case EP_CHIPSET_BOOMERANG: 401 /* 402 * If the device has MII, probe it. We won't be using 403 * any `native' media in this case, only PHYs. If 404 * we don't, just treat the Boomerang like the Vortex. 405 */ 406 if (sc->ep_flags & EP_FLAGS_MII) { 407 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 408 MII_PHY_ANY, MII_OFFSET_ANY, 0); 409 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 410 ifmedia_add(&sc->sc_mii.mii_media, 411 IFM_ETHER|IFM_NONE, 0, NULL); 412 ifmedia_set(&sc->sc_mii.mii_media, 413 IFM_ETHER|IFM_NONE); 414 } else { 415 ifmedia_set(&sc->sc_mii.mii_media, 416 IFM_ETHER|IFM_AUTO); 417 } 418 break; 419 } 420 /* FALLTHROUGH */ 421 422 /* on a direct bus, the attach routine can tell, but check anyway. */ 423 case EP_CHIPSET_VORTEX: 424 case EP_CHIPSET_BOOMERANG2: 425 ep_vortex_probemedia(sc); 426 break; 427 428 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */ 429 case EP_CHIPSET_3C509: 430 default: 431 ep_isa_probemedia(sc); 432 break; 433 } 434 435 GO_WINDOW(1); /* Window 1 is operating window */ 436 437 sc->tx_start_thresh = 20; /* probably a good starting point. */ 438 439 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 440 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 441 } 442 443 int 444 ep_detach(self) 445 struct device *self; 446 { 447 struct ep_softc *sc = (struct ep_softc *)self; 448 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 449 450 if (sc->ep_flags & EP_FLAGS_MII) 451 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 452 453 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 454 455 ether_ifdetach(ifp); 456 if_detach(ifp); 457 458 return (0); 459 } 460 461 /* 462 * Find supported media on 3c509-generation hardware that doesn't have 463 * a "reset_options" register in window 3. 464 * Use the config_cntrl register in window 0 instead. 465 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 466 * that implement CONFIG_CTRL. We don't have a good way to set the 467 * default active mediuim; punt to ifconfig instead. 468 * 469 * XXX what about 3c515, pcmcia 10/100? 470 */ 471 void 472 ep_isa_probemedia(sc) 473 struct ep_softc *sc; 474 { 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 struct ifmedia *ifm = &sc->sc_mii.mii_media; 478 int conn, i; 479 u_int16_t ep_w0_config, port; 480 481 conn = 0; 482 GO_WINDOW(0); 483 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 484 for (i = 0; i < 3; i++) { 485 struct ep_media * epm = ep_isa_media + i; 486 487 if ((ep_w0_config & epm->epm_eeprom_data) != 0) { 488 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 489 if (conn) 490 printf("/"); 491 printf("%s", epm->epm_name); 492 conn |= epm->epm_conn; 493 } 494 } 495 sc->ep_connectors = conn; 496 497 /* get default medium from EEPROM */ 498 if (epbusyeeprom(sc)) 499 return; /* XXX why is eeprom busy? */ 500 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 501 READ_EEPROM | EEPROM_ADDR_CFG); 502 if (epbusyeeprom(sc)) 503 return; /* XXX why is eeprom busy? */ 504 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 505 port = port >> 14; 506 507 printf(" (default %s)\n", ep_vortex_media[port].epm_name); 508 509 /* tell ifconfig what currently-active media is. */ 510 ifmedia_set(ifm, ep_default_to_media[port]); 511 512 /* XXX autoselect not yet implemented */ 513 } 514 515 516 /* 517 * Find media present on large-packet-capable elink3 devices. 518 * Show onboard configuration of large-packet-capable elink3 devices 519 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 520 * Use media and card-version info in window 3 instead. 521 * 522 * XXX how much of this works with 3c515, pcmcia 10/100? 523 */ 524 void 525 ep_vortex_probemedia(sc) 526 struct ep_softc *sc; 527 { 528 bus_space_tag_t iot = sc->sc_iot; 529 bus_space_handle_t ioh = sc->sc_ioh; 530 struct ifmedia *ifm = &sc->sc_mii.mii_media; 531 u_int config1, conn; 532 int reset_options; 533 int default_media; /* 3-bit encoding of default (EEPROM) media */ 534 int autoselect; /* boolean: should default to autoselect */ 535 const char *medium_name; 536 register int i; 537 538 GO_WINDOW(3); 539 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 540 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 541 GO_WINDOW(0); 542 543 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 544 autoselect = (config1 & CONFIG_AUTOSELECT) >> CONFIG_AUTOSELECT_SHIFT; 545 546 /* set available media options */ 547 conn = 0; 548 for (i = 0; i < 8; i++) { 549 struct ep_media * epm = ep_vortex_media + i; 550 551 if ((reset_options & epm->epm_eeprom_data) != 0) { 552 if (conn) 553 printf("/"); 554 printf("%s", epm->epm_name); 555 conn |= epm->epm_conn; 556 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 557 } 558 } 559 560 sc->ep_connectors = conn; 561 562 /* Show eeprom's idea of default media. */ 563 medium_name = (default_media > 8) 564 ? "(unknown/impossible media)" 565 : ep_vortex_media[default_media].epm_name; 566 printf(" default %s%s", 567 medium_name, (autoselect) ? "/autoselect" : ""); 568 /* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/ 569 570 #ifdef notyet 571 /* 572 * Set default: either the active interface the card 573 * reads from the EEPROM, or if autoselect is true, 574 * whatever we find is actually connected. 575 * 576 * XXX autoselect not yet implemented. 577 */ 578 #endif /* notyet */ 579 580 /* tell ifconfig what currently-active media is. */ 581 ifmedia_set(ifm, ep_default_to_media[default_media]); 582 } 583 584 /* 585 * Bring device up. 586 * 587 * The order in here seems important. Otherwise we may not receive 588 * interrupts. ?! 589 */ 590 void 591 epinit(sc) 592 register struct ep_softc *sc; 593 { 594 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 595 bus_space_tag_t iot = sc->sc_iot; 596 bus_space_handle_t ioh = sc->sc_ioh; 597 int i; 598 599 /* make sure any pending reset has completed before touching board */ 600 ep_finish_reset(iot, ioh); 601 602 /* cancel any pending I/O */ 603 epstop(sc); 604 605 if (sc->bustype != EP_BUS_PCI) { 606 GO_WINDOW(0); 607 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 608 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 609 } 610 611 if (sc->bustype == EP_BUS_PCMCIA) { 612 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 613 } 614 615 GO_WINDOW(2); 616 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 617 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 618 sc->sc_arpcom.ac_enaddr[i]); 619 620 if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA) 621 /* 622 * Reset the station-address receive filter. 623 * A bug workaround for busmastering (Vortex, Demon) cards. 624 */ 625 for (i = 0; i < 6; i++) 626 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 627 628 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 629 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 630 631 GO_WINDOW(1); /* Window 1 is operating window */ 632 for (i = 0; i < 31; i++) 633 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 634 635 /* Set threshold for for Tx-space available interrupt. */ 636 bus_space_write_2(iot, ioh, EP_COMMAND, 637 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 638 639 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 640 /* Enable options in the PCMCIA LAN COR register, via 641 * RoadRunner Window 1. 642 * 643 * XXX MAGIC CONSTANTS! 644 */ 645 u_int16_t cor; 646 647 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 648 649 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 650 bus_space_write_2(iot, ioh, 0, cor); 651 652 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 653 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 654 655 if (sc->ep_flags & EP_FLAGS_MII) { 656 ep_roadrunner_mii_enable(sc); 657 GO_WINDOW(1); 658 } 659 } 660 661 /* Enable interrupts. */ 662 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | 663 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 664 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | 665 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 666 667 /* 668 * Attempt to get rid of any stray interrupts that occured during 669 * configuration. On the i386 this isn't possible because one may 670 * already be queued. However, a single stray interrupt is 671 * unimportant. 672 */ 673 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 674 675 epsetfilter(sc); 676 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 677 678 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 679 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 680 681 epmbuffill(sc); 682 683 /* Interface is now `running', with no output active. */ 684 ifp->if_flags |= IFF_RUNNING; 685 ifp->if_flags &= ~IFF_OACTIVE; 686 687 /* Attempt to start output, if any. */ 688 epstart(ifp); 689 } 690 691 /* 692 * Set multicast receive filter. 693 * elink3 hardware has no selective multicast filter in hardware. 694 * Enable reception of all multicasts and filter in software. 695 */ 696 void 697 epsetfilter(sc) 698 register struct ep_softc *sc; 699 { 700 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 701 702 GO_WINDOW(1); /* Window 1 is operating window */ 703 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 704 FIL_INDIVIDUAL | FIL_BRDCST | 705 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 706 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 707 } 708 709 710 int 711 ep_media_change(ifp) 712 struct ifnet *ifp; 713 { 714 register struct ep_softc *sc = ifp->if_softc; 715 716 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 717 } 718 719 /* 720 * Reset and enable the MII on the RoadRunner. 721 */ 722 void 723 ep_roadrunner_mii_enable(sc) 724 struct ep_softc *sc; 725 { 726 bus_space_tag_t iot = sc->sc_iot; 727 bus_space_handle_t ioh = sc->sc_ioh; 728 729 GO_WINDOW(3); 730 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 731 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 732 delay(1000); 733 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 734 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII); 735 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 736 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 737 delay(1000); 738 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 739 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 740 } 741 742 /* 743 * Set active media to a specific given EPMEDIA_<> value. 744 * For vortex/demon/boomerang cards, update media field in w3_internal_config, 745 * and power on selected transceiver. 746 * For 3c509-generation cards (3c509/3c579/3c589/3c509B), 747 * update media field in w0_address_config, and power on selected xcvr. 748 */ 749 int 750 epsetmedia(sc, medium) 751 struct ep_softc *sc; 752 int medium; 753 { 754 bus_space_tag_t iot = sc->sc_iot; 755 bus_space_handle_t ioh = sc->sc_ioh; 756 int w4_media; 757 int config0, config1; 758 759 /* 760 * you can `ifconfig (link0|-link0) ep0' to get the following 761 * behaviour: 762 * -link0 disable AUI/UTP. enable BNC. 763 * link0 disable BNC. enable AUI. 764 * link1 if the card has a UTP connector, and link0 is 765 * set too, then you get the UTP port. 766 */ 767 768 /* 769 * First, change the media-control bits in EP_W4_MEDIA_TYPE. 770 */ 771 772 /* Turn everything off. First turn off linkbeat and UTP. */ 773 GO_WINDOW(4); 774 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 775 w4_media = w4_media & ~(ENABLE_UTP|SQE_ENABLE); 776 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media); 777 778 /* Turn off coax */ 779 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 780 delay(1000); 781 782 /* If the device has MII, select it, and then tell the 783 * PHY which media to use. 784 */ 785 if (sc->ep_flags & EP_FLAGS_MII) { 786 int config0, config1; 787 788 GO_WINDOW(3); 789 790 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 791 int resopt; 792 793 resopt = bus_space_read_2(iot, ioh, 794 EP_W3_RESET_OPTIONS); 795 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 796 resopt | EP_RUNNER_ENABLE_MII); 797 } 798 799 config0 = (u_int)bus_space_read_2(iot, ioh, 800 EP_W3_INTERNAL_CONFIG); 801 config1 = (u_int)bus_space_read_2(iot, ioh, 802 EP_W3_INTERNAL_CONFIG + 2); 803 804 config1 = config1 & ~CONFIG_MEDIAMASK; 805 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 806 807 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 808 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 809 GO_WINDOW(1); /* back to operating window */ 810 811 mii_mediachg(&sc->sc_mii); 812 return (0); 813 } 814 815 /* 816 * Now turn on the selected media/transceiver. 817 */ 818 GO_WINDOW(4); 819 switch (medium) { 820 case EPMEDIA_10BASE_T: 821 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP | 822 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0))); 823 break; 824 825 case EPMEDIA_10BASE_2: 826 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 827 DELAY(1000); /* 50ms not enough? */ 828 break; 829 830 /* XXX following only for new-generation cards */ 831 case EPMEDIA_100BASE_TX: 832 case EPMEDIA_100BASE_FX: 833 case EPMEDIA_100BASE_T4: /* XXX check documentation */ 834 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 835 w4_media | LINKBEAT_ENABLE); 836 DELAY(1000); /* not strictly necessary? */ 837 break; 838 839 case EPMEDIA_AUI: 840 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 841 w4_media | SQE_ENABLE); 842 DELAY(1000); /* not strictly necessary? */ 843 break; 844 case EPMEDIA_MII: 845 break; 846 default: 847 #if defined(EP_DEBUG) 848 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium); 849 #endif 850 break; 851 852 } 853 854 /* 855 * Tell the chip which PHY [sic] to use. 856 */ 857 switch (sc->ep_chipset) { 858 case EP_CHIPSET_VORTEX: 859 case EP_CHIPSET_BOOMERANG2: 860 GO_WINDOW(3); 861 config0 = (u_int)bus_space_read_2(iot, ioh, 862 EP_W3_INTERNAL_CONFIG); 863 config1 = (u_int)bus_space_read_2(iot, ioh, 864 EP_W3_INTERNAL_CONFIG + 2); 865 866 #if defined(EP_DEBUG) 867 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n", 868 sc->sc_dev.dv_xname, config0, config1); 869 #endif 870 config1 = config1 & ~CONFIG_MEDIAMASK; 871 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT); 872 873 #if defined(EP_DEBUG) 874 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n", 875 sc->sc_dev.dv_xname, medium, config1); 876 #endif 877 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 878 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 879 break; 880 881 default: 882 GO_WINDOW(0); 883 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 884 config0 &= 0x3fff; 885 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 886 config0 | (medium << 14)); 887 DELAY(1000); 888 break; 889 } 890 891 GO_WINDOW(1); /* Window 1 is operating window */ 892 return (0); 893 } 894 895 896 /* 897 * Get currently-selected media from card. 898 * (if_media callback, may be called before interface is brought up). 899 */ 900 void 901 ep_media_status(ifp, req) 902 struct ifnet *ifp; 903 struct ifmediareq *req; 904 { 905 register struct ep_softc *sc = ifp->if_softc; 906 bus_space_tag_t iot = sc->sc_iot; 907 bus_space_handle_t ioh = sc->sc_ioh; 908 u_int config1; 909 u_int ep_mediastatus; 910 911 /* 912 * If we have MII, go ask the PHY what's going on. 913 */ 914 if (sc->ep_flags & EP_FLAGS_MII) { 915 mii_pollstat(&sc->sc_mii); 916 req->ifm_active = sc->sc_mii.mii_media_active; 917 req->ifm_status = sc->sc_mii.mii_media_status; 918 return; 919 } 920 921 /* XXX read from softc when we start autosensing media */ 922 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 923 924 switch (sc->ep_chipset) { 925 case EP_CHIPSET_VORTEX: 926 case EP_CHIPSET_BOOMERANG: 927 GO_WINDOW(3); 928 delay(5000); 929 930 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 931 GO_WINDOW(1); 932 933 config1 = 934 (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 935 req->ifm_active = ep_default_to_media[config1]; 936 937 /* XXX check full-duplex bits? */ 938 939 GO_WINDOW(4); 940 req->ifm_status = IFM_AVALID; /* XXX */ 941 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 942 if (ep_mediastatus & LINKBEAT_DETECT) 943 req->ifm_status |= IFM_ACTIVE; /* XXX automedia */ 944 945 break; 946 947 case EP_CHIPSET_UNKNOWN: 948 case EP_CHIPSET_3C509: 949 req->ifm_status = 0; /* XXX */ 950 break; 951 952 default: 953 printf("%s: media_status on unknown chipset 0x%x\n", 954 ifp->if_xname, sc->ep_chipset); 955 break; 956 } 957 958 /* XXX look for softc heartbeat for other chips or media */ 959 960 GO_WINDOW(1); 961 return; 962 } 963 964 965 966 /* 967 * Start outputting on the interface. 968 * Always called as splnet(). 969 */ 970 void 971 epstart(ifp) 972 struct ifnet *ifp; 973 { 974 register struct ep_softc *sc = ifp->if_softc; 975 bus_space_tag_t iot = sc->sc_iot; 976 bus_space_handle_t ioh = sc->sc_ioh; 977 struct mbuf *m, *m0; 978 int sh, len, pad; 979 bus_addr_t txreg; 980 981 /* Don't transmit if interface is busy or not running */ 982 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 983 return; 984 985 startagain: 986 /* Sneak a peek at the next packet */ 987 IFQ_POLL(&ifp->if_snd, m0); 988 if (m0 == 0) 989 return; 990 991 /* We need to use m->m_pkthdr.len, so require the header */ 992 if ((m0->m_flags & M_PKTHDR) == 0) 993 panic("epstart: no header mbuf"); 994 len = m0->m_pkthdr.len; 995 996 pad = (4 - len) & 3; 997 998 /* 999 * The 3c509 automatically pads short packets to minimum ethernet 1000 * length, but we drop packets that are too large. Perhaps we should 1001 * truncate them instead? 1002 */ 1003 if (len + pad > ETHER_MAX_LEN) { 1004 /* packet is obviously too large: toss it */ 1005 ++ifp->if_oerrors; 1006 IFQ_DEQUEUE(&ifp->if_snd, m0); 1007 m_freem(m0); 1008 goto readcheck; 1009 } 1010 1011 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 1012 len + pad + 4) { 1013 bus_space_write_2(iot, ioh, EP_COMMAND, 1014 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift)); 1015 /* not enough room in FIFO */ 1016 ifp->if_flags |= IFF_OACTIVE; 1017 return; 1018 } else { 1019 bus_space_write_2(iot, ioh, EP_COMMAND, 1020 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE); 1021 } 1022 IFQ_DEQUEUE(&ifp->if_snd, m0); 1023 if (m0 == 0) /* not really needed */ 1024 return; 1025 1026 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1027 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/)); 1028 1029 #if NBPFILTER > 0 1030 if (ifp->if_bpf) 1031 bpf_mtap(ifp->if_bpf, m0); 1032 #endif 1033 1034 /* 1035 * Do the output at splhigh() so that an interrupt from another device 1036 * won't cause a FIFO underrun. 1037 */ 1038 sh = splhigh(); 1039 1040 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1041 1042 bus_space_write_2(iot, ioh, txreg, len); 1043 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1044 if (EP_IS_BUS_32(sc->bustype)) { 1045 for (m = m0; m; ) { 1046 if (m->m_len > 3) 1047 bus_space_write_raw_multi_4(iot, ioh, txreg, 1048 mtod(m, u_int8_t *), m->m_len & ~3); 1049 if (m->m_len & 3) 1050 bus_space_write_multi_1(iot, ioh, txreg, 1051 mtod(m, u_int8_t *) + (m->m_len & ~3), 1052 m->m_len & 3); 1053 MFREE(m, m0); 1054 m = m0; 1055 } 1056 } else { 1057 for (m = m0; m; ) { 1058 if (m->m_len > 1) 1059 bus_space_write_raw_multi_2(iot, ioh, txreg, 1060 mtod(m, u_int8_t *), m->m_len & ~1); 1061 if (m->m_len & 1) 1062 bus_space_write_1(iot, ioh, txreg, 1063 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1064 MFREE(m, m0); 1065 m = m0; 1066 } 1067 } 1068 while (pad--) 1069 bus_space_write_1(iot, ioh, txreg, 0); 1070 1071 splx(sh); 1072 1073 ++ifp->if_opackets; 1074 1075 readcheck: 1076 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1077 ERR_INCOMPLETE) == 0) { 1078 /* We received a complete packet. */ 1079 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1080 1081 if ((status & S_INTR_LATCH) == 0) { 1082 /* 1083 * No interrupt, read the packet and continue 1084 * Is this supposed to happen? Is my motherboard 1085 * completely busted? 1086 */ 1087 epread(sc); 1088 } else 1089 /* Got an interrupt, return to get it serviced. */ 1090 return; 1091 } else { 1092 /* Check if we are stuck and reset [see XXX comment] */ 1093 if (epstatus(sc)) { 1094 #ifdef EP_DEBUG 1095 if (ifp->if_flags & IFF_DEBUG) 1096 printf("%s: adapter reset\n", 1097 sc->sc_dev.dv_xname); 1098 #endif 1099 epreset(sc); 1100 } 1101 } 1102 1103 goto startagain; 1104 } 1105 1106 1107 /* 1108 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1109 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1110 * We detect this situation and we reset the adapter. 1111 * It happens at times when there is a lot of broadcast traffic 1112 * on the cable (once in a blue moon). 1113 */ 1114 int 1115 epstatus(sc) 1116 register struct ep_softc *sc; 1117 { 1118 bus_space_tag_t iot = sc->sc_iot; 1119 bus_space_handle_t ioh = sc->sc_ioh; 1120 u_int16_t fifost; 1121 1122 /* 1123 * Check the FIFO status and act accordingly 1124 */ 1125 GO_WINDOW(4); 1126 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1127 GO_WINDOW(1); 1128 1129 if (fifost & FIFOS_RX_UNDERRUN) { 1130 #ifdef EP_DEBUG 1131 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1132 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1133 #endif 1134 epreset(sc); 1135 return 0; 1136 } 1137 1138 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1139 #ifdef EP_DEBUG 1140 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1141 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1142 #endif 1143 return 1; 1144 } 1145 1146 if (fifost & FIFOS_RX_OVERRUN) { 1147 #ifdef EP_DEBUG 1148 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1149 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1150 #endif 1151 return 1; 1152 } 1153 1154 if (fifost & FIFOS_TX_OVERRUN) { 1155 #ifdef EP_DEBUG 1156 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1157 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1158 #endif 1159 epreset(sc); 1160 return 0; 1161 } 1162 1163 return 0; 1164 } 1165 1166 1167 void 1168 eptxstat(sc) 1169 register struct ep_softc *sc; 1170 { 1171 bus_space_tag_t iot = sc->sc_iot; 1172 bus_space_handle_t ioh = sc->sc_ioh; 1173 int i; 1174 1175 /* 1176 * We need to read+write TX_STATUS until we get a 0 status 1177 * in order to turn off the interrupt flag. 1178 */ 1179 while ((i = bus_space_read_1(iot, ioh, 1180 ep_w1_reg(sc, EP_W1_TX_STATUS))) & TXS_COMPLETE) { 1181 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1182 0x0); 1183 1184 if (i & TXS_JABBER) { 1185 ++sc->sc_arpcom.ac_if.if_oerrors; 1186 #ifdef EP_DEBUG 1187 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1188 printf("%s: jabber (%x)\n", 1189 sc->sc_dev.dv_xname, i); 1190 #endif 1191 epreset(sc); 1192 } else if (i & TXS_UNDERRUN) { 1193 ++sc->sc_arpcom.ac_if.if_oerrors; 1194 #ifdef EP_DEBUG 1195 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1196 printf("%s: fifo underrun (%x) @%d\n", 1197 sc->sc_dev.dv_xname, i, 1198 sc->tx_start_thresh); 1199 #endif 1200 if (sc->tx_succ_ok < 100) 1201 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1202 sc->tx_start_thresh + 20); 1203 sc->tx_succ_ok = 0; 1204 epreset(sc); 1205 } else if (i & TXS_MAX_COLLISION) { 1206 ++sc->sc_arpcom.ac_if.if_collisions; 1207 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1208 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1209 } else 1210 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1211 } 1212 } 1213 1214 int 1215 epintr(arg) 1216 void *arg; 1217 { 1218 register struct ep_softc *sc = arg; 1219 bus_space_tag_t iot = sc->sc_iot; 1220 bus_space_handle_t ioh = sc->sc_ioh; 1221 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1222 u_int16_t status; 1223 int ret = 0; 1224 1225 for (;;) { 1226 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1227 1228 status = bus_space_read_2(iot, ioh, EP_STATUS); 1229 1230 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1231 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) 1232 break; 1233 1234 ret = 1; 1235 1236 /* 1237 * Acknowledge any interrupts. It's important that we do this 1238 * first, since there would otherwise be a race condition. 1239 * Due to the i386 interrupt queueing, we may get spurious 1240 * interrupts occasionally. 1241 */ 1242 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status); 1243 1244 if (status & S_RX_COMPLETE) 1245 epread(sc); 1246 if (status & S_TX_AVAIL) { 1247 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1248 epstart(&sc->sc_arpcom.ac_if); 1249 } 1250 if (status & S_CARD_FAILURE) { 1251 epreset(sc); 1252 return (1); 1253 } 1254 if (status & S_TX_COMPLETE) { 1255 eptxstat(sc); 1256 epstart(ifp); 1257 } 1258 } 1259 1260 /* no more interrupts */ 1261 return (ret); 1262 } 1263 1264 void 1265 epread(sc) 1266 register struct ep_softc *sc; 1267 { 1268 bus_space_tag_t iot = sc->sc_iot; 1269 bus_space_handle_t ioh = sc->sc_ioh; 1270 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1271 struct mbuf *m; 1272 int len; 1273 1274 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1275 1276 again: 1277 #ifdef EP_DEBUG 1278 if (ifp->if_flags & IFF_DEBUG) { 1279 int err = len & ERR_MASK; 1280 char *s = NULL; 1281 1282 if (len & ERR_INCOMPLETE) 1283 s = "incomplete packet"; 1284 else if (err == ERR_OVERRUN) 1285 s = "packet overrun"; 1286 else if (err == ERR_RUNT) 1287 s = "runt packet"; 1288 else if (err == ERR_ALIGNMENT) 1289 s = "bad alignment"; 1290 else if (err == ERR_CRC) 1291 s = "bad crc"; 1292 else if (err == ERR_OVERSIZE) 1293 s = "oversized packet"; 1294 else if (err == ERR_DRIBBLE) 1295 s = "dribble bits"; 1296 1297 if (s) 1298 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1299 } 1300 #endif 1301 1302 if (len & ERR_INCOMPLETE) 1303 return; 1304 1305 if (len & ERR_RX) { 1306 ++ifp->if_ierrors; 1307 goto abort; 1308 } 1309 1310 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1311 1312 /* Pull packet off interface. */ 1313 m = epget(sc, len); 1314 if (m == 0) { 1315 ifp->if_ierrors++; 1316 goto abort; 1317 } 1318 1319 ++ifp->if_ipackets; 1320 1321 #if NBPFILTER > 0 1322 /* 1323 * Check if there's a BPF listener on this interface. 1324 * If so, hand off the raw packet to BPF. 1325 */ 1326 if (ifp->if_bpf) 1327 bpf_mtap(ifp->if_bpf, m); 1328 #endif 1329 1330 ether_input_mbuf(ifp, m); 1331 1332 /* 1333 * In periods of high traffic we can actually receive enough 1334 * packets so that the fifo overrun bit will be set at this point, 1335 * even though we just read a packet. In this case we 1336 * are not going to receive any more interrupts. We check for 1337 * this condition and read again until the fifo is not full. 1338 * We could simplify this test by not using epstatus(), but 1339 * rechecking the RX_STATUS register directly. This test could 1340 * result in unnecessary looping in cases where there is a new 1341 * packet but the fifo is not full, but it will not fix the 1342 * stuck behavior. 1343 * 1344 * Even with this improvement, we still get packet overrun errors 1345 * which are hurting performance. Maybe when I get some more time 1346 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1347 */ 1348 if (epstatus(sc)) { 1349 len = bus_space_read_2(iot, ioh, 1350 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1351 /* Check if we are stuck and reset [see XXX comment] */ 1352 if (len & ERR_INCOMPLETE) { 1353 #ifdef EP_DEBUG 1354 if (ifp->if_flags & IFF_DEBUG) 1355 printf("%s: adapter reset\n", 1356 sc->sc_dev.dv_xname); 1357 #endif 1358 epreset(sc); 1359 return; 1360 } 1361 goto again; 1362 } 1363 1364 return; 1365 1366 abort: 1367 ep_discard_rxtop(iot, ioh); 1368 } 1369 1370 struct mbuf * 1371 epget(sc, totlen) 1372 struct ep_softc *sc; 1373 int totlen; 1374 { 1375 bus_space_tag_t iot = sc->sc_iot; 1376 bus_space_handle_t ioh = sc->sc_ioh; 1377 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1378 struct mbuf *top, **mp, *m; 1379 int len, pad; 1380 int sh; 1381 bus_addr_t rxreg; 1382 1383 m = sc->mb[sc->next_mb]; 1384 sc->mb[sc->next_mb] = 0; 1385 if (m == 0) { 1386 MGETHDR(m, M_DONTWAIT, MT_DATA); 1387 if (m == 0) 1388 return 0; 1389 } else { 1390 /* If the queue is no longer full, refill. */ 1391 if (sc->last_mb == sc->next_mb) 1392 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1393 /* Convert one of our saved mbuf's. */ 1394 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1395 m->m_data = m->m_pktdat; 1396 m->m_flags = M_PKTHDR; 1397 m_tag_init(m); 1398 } 1399 m->m_pkthdr.rcvif = ifp; 1400 m->m_pkthdr.len = totlen; 1401 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1402 len = MHLEN; 1403 if (totlen >= MINCLSIZE) { 1404 MCLGET(m, M_DONTWAIT); 1405 if (m->m_flags & M_EXT) 1406 len = MCLBYTES; 1407 } 1408 m->m_data += pad; 1409 len -= pad; 1410 top = 0; 1411 mp = ⊤ 1412 1413 /* 1414 * We read the packet at splhigh() so that an interrupt from another 1415 * device doesn't cause the card's buffer to overflow while we're 1416 * reading it. We may still lose packets at other times. 1417 */ 1418 sh = splhigh(); 1419 1420 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1421 1422 while (totlen > 0) { 1423 if (top) { 1424 m = sc->mb[sc->next_mb]; 1425 sc->mb[sc->next_mb] = 0; 1426 if (m == 0) { 1427 MGET(m, M_DONTWAIT, MT_DATA); 1428 if (m == 0) { 1429 splx(sh); 1430 m_freem(top); 1431 return 0; 1432 } 1433 } else { 1434 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1435 } 1436 len = MLEN; 1437 } 1438 if (top && totlen >= MINCLSIZE) { 1439 MCLGET(m, M_DONTWAIT); 1440 if (m->m_flags & M_EXT) 1441 len = MCLBYTES; 1442 } 1443 len = min(totlen, len); 1444 if (EP_IS_BUS_32(sc->bustype)) { 1445 if (len > 3) { 1446 len &= ~3; 1447 bus_space_read_raw_multi_4(iot, ioh, rxreg, 1448 mtod(m, u_int8_t *), len); 1449 } else 1450 bus_space_read_multi_1(iot, ioh, rxreg, 1451 mtod(m, u_int8_t *), len); 1452 } else { 1453 if (len > 1) { 1454 len &= ~1; 1455 bus_space_read_raw_multi_2(iot, ioh, rxreg, 1456 mtod(m, u_int8_t *), len); 1457 } else 1458 *(mtod(m, u_int8_t *)) = 1459 bus_space_read_1(iot, ioh, rxreg); 1460 } 1461 m->m_len = len; 1462 totlen -= len; 1463 *mp = m; 1464 mp = &m->m_next; 1465 } 1466 1467 ep_discard_rxtop(iot, ioh); 1468 1469 splx(sh); 1470 1471 return top; 1472 } 1473 1474 int 1475 epioctl(ifp, cmd, data) 1476 register struct ifnet *ifp; 1477 u_long cmd; 1478 caddr_t data; 1479 { 1480 struct ep_softc *sc = ifp->if_softc; 1481 struct ifaddr *ifa = (struct ifaddr *)data; 1482 struct ifreq *ifr = (struct ifreq *)data; 1483 int s, error = 0; 1484 1485 s = splnet(); 1486 1487 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 1488 splx(s); 1489 return error; 1490 } 1491 1492 switch (cmd) { 1493 1494 case SIOCSIFADDR: 1495 ifp->if_flags |= IFF_UP; 1496 1497 switch (ifa->ifa_addr->sa_family) { 1498 #ifdef INET 1499 case AF_INET: 1500 epinit(sc); 1501 arp_ifinit(&sc->sc_arpcom, ifa); 1502 break; 1503 #endif 1504 default: 1505 epinit(sc); 1506 break; 1507 } 1508 break; 1509 1510 case SIOCSIFMEDIA: 1511 case SIOCGIFMEDIA: 1512 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1513 break; 1514 1515 case SIOCSIFMTU: 1516 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 1517 error = EINVAL; 1518 } else if (ifp->if_mtu != ifr->ifr_mtu) { 1519 ifp->if_mtu = ifr->ifr_mtu; 1520 } 1521 break; 1522 1523 1524 case SIOCSIFFLAGS: 1525 if ((ifp->if_flags & IFF_UP) == 0 && 1526 (ifp->if_flags & IFF_RUNNING) != 0) { 1527 /* 1528 * If interface is marked down and it is running, then 1529 * stop it. 1530 */ 1531 epstop(sc); 1532 ifp->if_flags &= ~IFF_RUNNING; 1533 } else if ((ifp->if_flags & IFF_UP) != 0 && 1534 (ifp->if_flags & IFF_RUNNING) == 0) { 1535 /* 1536 * If interface is marked up and it is stopped, then 1537 * start it. 1538 */ 1539 epinit(sc); 1540 } else { 1541 /* 1542 * deal with flags changes: 1543 * IFF_MULTICAST, IFF_PROMISC, 1544 * IFF_LINK0, IFF_LINK1. 1545 */ 1546 epsetfilter(sc); 1547 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 1548 } 1549 break; 1550 1551 case SIOCADDMULTI: 1552 case SIOCDELMULTI: 1553 error = (cmd == SIOCADDMULTI) ? 1554 ether_addmulti(ifr, &sc->sc_arpcom) : 1555 ether_delmulti(ifr, &sc->sc_arpcom); 1556 1557 if (error == ENETRESET) { 1558 /* 1559 * Multicast list has changed; set the hardware filter 1560 * accordingly. 1561 */ 1562 epreset(sc); 1563 error = 0; 1564 } 1565 break; 1566 1567 default: 1568 error = EINVAL; 1569 break; 1570 } 1571 1572 splx(s); 1573 return (error); 1574 } 1575 1576 void 1577 epreset(sc) 1578 struct ep_softc *sc; 1579 { 1580 int s; 1581 1582 s = splnet(); 1583 epinit(sc); 1584 splx(s); 1585 } 1586 1587 void 1588 epwatchdog(ifp) 1589 struct ifnet *ifp; 1590 { 1591 struct ep_softc *sc = ifp->if_softc; 1592 1593 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1594 ++sc->sc_arpcom.ac_if.if_oerrors; 1595 1596 epreset(sc); 1597 } 1598 1599 void 1600 epstop(sc) 1601 register struct ep_softc *sc; 1602 { 1603 bus_space_tag_t iot = sc->sc_iot; 1604 bus_space_handle_t ioh = sc->sc_ioh; 1605 1606 if (sc->ep_flags & EP_FLAGS_MII) { 1607 mii_down(&sc->sc_mii); 1608 } 1609 1610 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1611 /* Clear the FIFO buffer count, thus halting 1612 * any currently-running transactions. 1613 */ 1614 GO_WINDOW(1); /* sanity */ 1615 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1616 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1617 } 1618 1619 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1620 ep_discard_rxtop(iot, ioh); 1621 1622 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1623 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1624 1625 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 1626 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 1627 1628 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1629 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1630 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1631 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1632 1633 epmbufempty(sc); 1634 } 1635 1636 /* 1637 * We get eeprom data from the id_port given an offset into the 1638 * eeprom. Basically; after the ID_sequence is sent to all of 1639 * the cards; they enter the ID_CMD state where they will accept 1640 * command requests. 0x80-0xbf loads the eeprom data. We then 1641 * read the port 16 times and with every read; the cards check 1642 * for contention (ie: if one card writes a 0 bit and another 1643 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1644 * each card compares the data on the bus; if there is a difference 1645 * then that card goes into ID_WAIT state again). In the meantime; 1646 * one bit of data is returned in the AX register which is conveniently 1647 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1648 * bit of data with each read. 1649 * 1650 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1651 */ 1652 u_int16_t 1653 epreadeeprom(iot, ioh, offset) 1654 bus_space_tag_t iot; 1655 bus_space_handle_t ioh; 1656 int offset; 1657 { 1658 u_int16_t data = 0; 1659 int i; 1660 1661 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1662 delay(1000); 1663 for (i = 0; i < 16; i++) 1664 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1665 return (data); 1666 } 1667 1668 int 1669 epbusyeeprom(sc) 1670 struct ep_softc *sc; 1671 { 1672 bus_space_tag_t iot = sc->sc_iot; 1673 bus_space_handle_t ioh = sc->sc_ioh; 1674 int i = 100, j; 1675 1676 while (i--) { 1677 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1678 if (j & EEPROM_BUSY) 1679 delay(100); 1680 else 1681 break; 1682 } 1683 if (!i) { 1684 printf("\n%s: eeprom failed to come ready\n", 1685 sc->sc_dev.dv_xname); 1686 return (1); 1687 } 1688 if (sc->bustype != EP_BUS_PCMCIA && sc->bustype != EP_BUS_PCI && 1689 (j & EEPROM_TST_MODE)) { 1690 printf("\n%s: erase pencil mark, or disable PnP mode!\n", 1691 sc->sc_dev.dv_xname); 1692 return (1); 1693 } 1694 return (0); 1695 } 1696 1697 u_int16_t 1698 ep_read_eeprom(sc, offset) 1699 struct ep_softc *sc; 1700 u_int16_t offset; 1701 { 1702 u_int16_t readcmd; 1703 1704 /* 1705 * RoadRunner has a larger EEPROM, so a different read command 1706 * is required. 1707 */ 1708 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) 1709 readcmd = READ_EEPROM_RR; 1710 else 1711 readcmd = READ_EEPROM; 1712 1713 if (epbusyeeprom(sc)) 1714 return (0); /* XXX why is eeprom busy? */ 1715 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND, 1716 readcmd | offset); 1717 if (epbusyeeprom(sc)) 1718 return (0); /* XXX why is eeprom busy? */ 1719 1720 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)); 1721 } 1722 1723 void 1724 epmbuffill(v) 1725 void *v; 1726 { 1727 struct ep_softc *sc = v; 1728 int s, i; 1729 1730 s = splnet(); 1731 i = sc->last_mb; 1732 do { 1733 if (sc->mb[i] == NULL) 1734 MGET(sc->mb[i], M_DONTWAIT, MT_DATA); 1735 if (sc->mb[i] == NULL) 1736 break; 1737 i = (i + 1) % MAX_MBS; 1738 } while (i != sc->next_mb); 1739 sc->last_mb = i; 1740 /* If the queue was not filled, try again. */ 1741 if (sc->last_mb != sc->next_mb) 1742 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1743 splx(s); 1744 } 1745 1746 void 1747 epmbufempty(sc) 1748 struct ep_softc *sc; 1749 { 1750 int s, i; 1751 1752 s = splnet(); 1753 for (i = 0; i<MAX_MBS; i++) { 1754 if (sc->mb[i]) { 1755 m_freem(sc->mb[i]); 1756 sc->mb[i] = NULL; 1757 } 1758 } 1759 sc->last_mb = sc->next_mb = 0; 1760 timeout_del(&sc->sc_epmbuffill_tmo); 1761 splx(s); 1762 } 1763 1764 void 1765 ep_mii_setbit(sc, bit) 1766 struct ep_softc *sc; 1767 u_int16_t bit; 1768 { 1769 u_int16_t val; 1770 1771 /* We assume we're already in Window 4 */ 1772 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1773 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1774 val | bit); 1775 } 1776 1777 void 1778 ep_mii_clrbit(sc, bit) 1779 struct ep_softc *sc; 1780 u_int16_t bit; 1781 { 1782 u_int16_t val; 1783 1784 /* We assume we're already in Window 4 */ 1785 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1786 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1787 val & ~bit); 1788 } 1789 1790 u_int16_t 1791 ep_mii_readbit(sc, bit) 1792 struct ep_softc *sc; 1793 u_int16_t bit; 1794 { 1795 1796 /* We assume we're already in Window 4 */ 1797 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1798 bit); 1799 } 1800 1801 void 1802 ep_mii_sync(sc) 1803 struct ep_softc *sc; 1804 { 1805 int i; 1806 1807 /* We assume we're already in Window 4 */ 1808 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1809 for (i = 0; i < 32; i++) { 1810 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1811 ep_mii_setbit(sc, PHYSMGMT_CLK); 1812 } 1813 } 1814 1815 void 1816 ep_mii_sendbits(sc, data, nbits) 1817 struct ep_softc *sc; 1818 u_int32_t data; 1819 int nbits; 1820 { 1821 int i; 1822 1823 /* We assume we're already in Window 4 */ 1824 ep_mii_setbit(sc, PHYSMGMT_DIR); 1825 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1826 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1827 ep_mii_readbit(sc, PHYSMGMT_CLK); 1828 if (data & i) 1829 ep_mii_setbit(sc, PHYSMGMT_DATA); 1830 else 1831 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1832 ep_mii_setbit(sc, PHYSMGMT_CLK); 1833 ep_mii_readbit(sc, PHYSMGMT_CLK); 1834 } 1835 } 1836 1837 int 1838 ep_mii_readreg(self, phy, reg) 1839 struct device *self; 1840 int phy, reg; 1841 { 1842 struct ep_softc *sc = (struct ep_softc *)self; 1843 int val = 0, i, err; 1844 1845 /* 1846 * Read the PHY register by manually driving the MII control lines. 1847 */ 1848 1849 GO_WINDOW(4); 1850 1851 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1852 1853 ep_mii_sync(sc); 1854 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1855 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1856 ep_mii_sendbits(sc, phy, 5); 1857 ep_mii_sendbits(sc, reg, 5); 1858 1859 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1860 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1861 ep_mii_setbit(sc, PHYSMGMT_CLK); 1862 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1863 1864 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1865 ep_mii_setbit(sc, PHYSMGMT_CLK); 1866 1867 /* Even if an error occurs, must still clock out the cycle. */ 1868 for (i = 0; i < 16; i++) { 1869 val <<= 1; 1870 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1871 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1872 val |= 1; 1873 ep_mii_setbit(sc, PHYSMGMT_CLK); 1874 } 1875 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1876 ep_mii_setbit(sc, PHYSMGMT_CLK); 1877 1878 GO_WINDOW(1); /* back to operating window */ 1879 1880 return (err ? 0 : val); 1881 } 1882 1883 void 1884 ep_mii_writereg(self, phy, reg, val) 1885 struct device *self; 1886 int phy, reg, val; 1887 { 1888 struct ep_softc *sc = (struct ep_softc *)self; 1889 1890 /* 1891 * Write the PHY register by manually driving the MII control lines. 1892 */ 1893 1894 GO_WINDOW(4); 1895 1896 ep_mii_sync(sc); 1897 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1898 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1899 ep_mii_sendbits(sc, phy, 5); 1900 ep_mii_sendbits(sc, reg, 5); 1901 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1902 ep_mii_sendbits(sc, val, 16); 1903 1904 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1905 ep_mii_setbit(sc, PHYSMGMT_CLK); 1906 1907 GO_WINDOW(1); /* back to operating window */ 1908 } 1909 1910 void 1911 ep_statchg(self) 1912 struct device *self; 1913 { 1914 struct ep_softc *sc = (struct ep_softc *)self; 1915 bus_space_tag_t iot = sc->sc_iot; 1916 bus_space_handle_t ioh = sc->sc_ioh; 1917 int mctl; 1918 1919 /* XXX Update ifp->if_baudrate */ 1920 1921 GO_WINDOW(3); 1922 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 1923 if (sc->sc_mii.mii_media_active & IFM_FDX) 1924 mctl |= MAC_CONTROL_FDX; 1925 else 1926 mctl &= ~MAC_CONTROL_FDX; 1927 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 1928 GO_WINDOW(1); /* back to operating window */ 1929 } 1930