1 /* $OpenBSD: elink3.c,v 1.79 2013/08/07 01:06:29 bluhm Exp $ */ 2 /* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org> 6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Herb Peyerl. 20 * 4. The name of Herb Peyerl may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/ioctl.h> 42 #include <sys/errno.h> 43 #include <sys/syslog.h> 44 #include <sys/selinfo.h> 45 #include <sys/timeout.h> 46 #include <sys/device.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_types.h> 51 #include <net/netisr.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <machine/cpu.h> 66 #include <machine/bus.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/ic/elink3var.h> 72 #include <dev/ic/elink3reg.h> 73 74 /* 75 * Structure to map media-present bits in boards to 76 * ifmedia codes and printable media names. Used for table-driven 77 * ifmedia initialization. 78 */ 79 struct ep_media { 80 int epm_eeprom_data; /* bitmask for eeprom config */ 81 int epm_conn; /* sc->ep_connectors code for medium */ 82 char *epm_name; /* name of medium */ 83 int epm_ifmedia; /* ifmedia word for medium */ 84 int epm_ifdata; 85 }; 86 87 /* 88 * ep_media table for Vortex/Demon/Boomerang: 89 * map from media-present bits in register RESET_OPTIONS+2 90 * to ifmedia "media words" and printable names. 91 * 92 * XXX indexed directly by INTERNAL_CONFIG default_media field, 93 * (i.e., EPMEDIA_ constants) forcing order of entries. 94 * Note that 3 is reserved. 95 */ 96 const struct ep_media ep_vortex_media[] = { 97 { EP_PCI_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, 98 EPMEDIA_10BASE_T }, 99 { EP_PCI_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, 100 EPMEDIA_AUI }, 101 { 0, 0, "reserved", IFM_NONE, EPMEDIA_RESV1 }, 102 { EP_PCI_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, 103 EPMEDIA_10BASE_2 }, 104 { EP_PCI_100BASE_TX, EPC_100TX, "100-TX", IFM_ETHER|IFM_100_TX, 105 EPMEDIA_100BASE_TX }, 106 { EP_PCI_100BASE_FX, EPC_100FX, "100-FX", IFM_ETHER|IFM_100_FX, 107 EPMEDIA_100BASE_FX }, 108 { EP_PCI_100BASE_MII,EPC_MII, "mii", IFM_ETHER|IFM_100_TX, 109 EPMEDIA_MII }, 110 { EP_PCI_100BASE_T4, EPC_100T4, "100-T4", IFM_ETHER|IFM_100_T4, 111 EPMEDIA_100BASE_T4 } 112 }; 113 114 /* 115 * ep_media table for 3c509/3c509b/3c579/3c589: 116 * map from media-present bits in register CNFG_CNTRL 117 * (window 0, offset ?) to ifmedia "media words" and printable names. 118 */ 119 struct ep_media ep_isa_media[] = { 120 { EP_W0_CC_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, EPMEDIA_10BASE_T }, 121 { EP_W0_CC_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, EPMEDIA_AUI }, 122 { EP_W0_CC_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, EPMEDIA_10BASE_2 }, 123 }; 124 125 /* Map vortex reset_options bits to if_media codes. */ 126 const u_int ep_default_to_media[] = { 127 IFM_ETHER | IFM_10_T, 128 IFM_ETHER | IFM_10_5, 129 0, /* reserved by 3Com */ 130 IFM_ETHER | IFM_10_2, 131 IFM_ETHER | IFM_100_TX, 132 IFM_ETHER | IFM_100_FX, 133 IFM_ETHER | IFM_100_TX, /* XXX really MII: need to talk to PHY */ 134 IFM_ETHER | IFM_100_T4, 135 }; 136 137 struct cfdriver ep_cd = { 138 NULL, "ep", DV_IFNET 139 }; 140 141 void ep_vortex_probemedia(struct ep_softc *sc); 142 void ep_isa_probemedia(struct ep_softc *sc); 143 144 void eptxstat(struct ep_softc *); 145 int epstatus(struct ep_softc *); 146 int epioctl(struct ifnet *, u_long, caddr_t); 147 void epstart(struct ifnet *); 148 void epwatchdog(struct ifnet *); 149 void epreset(struct ep_softc *); 150 void epread(struct ep_softc *); 151 struct mbuf *epget(struct ep_softc *, int); 152 void epmbuffill(void *); 153 void epmbufempty(struct ep_softc *); 154 void epsetfilter(struct ep_softc *); 155 void ep_roadrunner_mii_enable(struct ep_softc *); 156 int epsetmedia(struct ep_softc *, int); 157 158 /* ifmedia callbacks */ 159 int ep_media_change(struct ifnet *); 160 void ep_media_status(struct ifnet *, struct ifmediareq *); 161 162 /* MII callbacks */ 163 int ep_mii_readreg(struct device *, int, int); 164 void ep_mii_writereg(struct device *, int, int, int); 165 void ep_statchg(struct device *); 166 167 void ep_mii_setbit(struct ep_softc *, u_int16_t); 168 void ep_mii_clrbit(struct ep_softc *, u_int16_t); 169 u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t); 170 void ep_mii_sync(struct ep_softc *); 171 void ep_mii_sendbits(struct ep_softc *, u_int32_t, int); 172 173 int epbusyeeprom(struct ep_softc *); 174 u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t); 175 176 static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg); 177 static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t); 178 static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t); 179 static __inline int ep_w1_reg(struct ep_softc *, int); 180 181 /* 182 * Issue a (reset) command, and be sure it has completed. 183 * Used for global reset, TX_RESET, RX_RESET. 184 */ 185 static inline void 186 ep_reset_cmd(struct ep_softc *sc, u_int cmd, u_int arg) 187 { 188 bus_space_tag_t iot = sc->sc_iot; 189 bus_space_handle_t ioh = sc->sc_ioh; 190 191 bus_space_write_2(iot, ioh, cmd, arg); 192 ep_finish_reset(iot, ioh); 193 } 194 195 /* 196 * Wait for any pending reset to complete. 197 */ 198 static inline void 199 ep_finish_reset(bus_space_tag_t iot, bus_space_handle_t ioh) 200 { 201 int i; 202 203 for (i = 0; i < 10000; i++) { 204 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 205 S_COMMAND_IN_PROGRESS) == 0) 206 break; 207 DELAY(10); 208 } 209 } 210 211 static inline void 212 ep_discard_rxtop(bus_space_tag_t iot, bus_space_handle_t ioh) 213 { 214 int i; 215 216 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 217 218 /* 219 * Spin for about 1 msec, to avoid forcing a DELAY() between 220 * every received packet (adding latency and limiting pkt-recv rate). 221 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 222 * is about right. 223 */ 224 for (i = 0; i < 8000; i++) { 225 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 226 S_COMMAND_IN_PROGRESS) == 0) 227 return; 228 } 229 230 /* not fast enough, do DELAY()s */ 231 ep_finish_reset(iot, ioh); 232 } 233 234 /* 235 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset. 236 */ 237 static __inline int 238 ep_w1_reg(struct ep_softc *sc, int reg) 239 { 240 switch (sc->ep_chipset) { 241 case EP_CHIPSET_ROADRUNNER: 242 switch (reg) { 243 case EP_W1_FREE_TX: 244 case EP_W1_RUNNER_RDCTL: 245 case EP_W1_RUNNER_WRCTL: 246 return (reg); 247 } 248 return (reg + 0x10); 249 } 250 return (reg); 251 } 252 253 /* 254 * Back-end attach and configure. 255 */ 256 void 257 epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr) 258 { 259 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 260 bus_space_tag_t iot = sc->sc_iot; 261 bus_space_handle_t ioh = sc->sc_ioh; 262 u_int16_t i; 263 264 sc->ep_chipset = chipset; 265 266 /* 267 * We could have been groveling around in other register 268 * windows in the front-end; make sure we're in window 0 269 * to read the EEPROM. 270 */ 271 GO_WINDOW(0); 272 273 if (enaddr == NULL) { 274 /* 275 * Read the station address from the eeprom. 276 */ 277 for (i = 0; i < 3; i++) { 278 u_int16_t x = ep_read_eeprom(sc, i); 279 280 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8; 281 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x; 282 } 283 } else { 284 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 285 } 286 287 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 288 if (sc->ep_flags & EP_FLAGS_MII) 289 printf("\n"); 290 else 291 printf(", "); 292 293 /* 294 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte 295 * packets. Commands only take an 11-bit parameter, and 11 bits 296 * isn't enough to hold a full-size packet length. 297 * Commands to these cards implicitly upshift a packet size 298 * or threshold by 2 bits. 299 * To detect cards with large-packet support, we probe by setting 300 * the transmit threshold register, then change windows and 301 * read back the threshold register directly, and see if the 302 * threshold value was shifted or not. 303 */ 304 bus_space_write_2(iot, ioh, EP_COMMAND, 305 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 306 GO_WINDOW(5); 307 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 308 GO_WINDOW(1); 309 switch (i) { 310 case EP_LARGEWIN_PROBE: 311 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 312 sc->txashift = 0; 313 break; 314 315 case (EP_LARGEWIN_PROBE << 2): 316 sc->txashift = 2; 317 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */ 318 break; 319 320 default: 321 printf("wrote %x to TX_AVAIL_THRESH, read back %x. " 322 "Interface disabled\n", EP_THRESH_DISABLE, (int) i); 323 return; 324 } 325 326 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc); 327 328 /* 329 * Ensure Tx-available interrupts are enabled for 330 * start the interface. 331 * XXX should be in epinit()? 332 */ 333 bus_space_write_2(iot, ioh, EP_COMMAND, 334 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 335 336 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 337 ifp->if_softc = sc; 338 ifp->if_start = epstart; 339 ifp->if_ioctl = epioctl; 340 ifp->if_watchdog = epwatchdog; 341 ifp->if_flags = 342 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 343 /* 64 packets are around 100ms on 10Mbps */ 344 IFQ_SET_MAXLEN(&ifp->if_snd, 64); 345 IFQ_SET_READY(&ifp->if_snd); 346 347 if_attach(ifp); 348 ether_ifattach(ifp); 349 350 /* 351 * Finish configuration: 352 * determine chipset if the front-end couldn't do so, 353 * show board details, set media. 354 */ 355 356 GO_WINDOW(0); 357 358 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 359 ep_media_status); 360 sc->sc_mii.mii_ifp = ifp; 361 sc->sc_mii.mii_readreg = ep_mii_readreg; 362 sc->sc_mii.mii_writereg = ep_mii_writereg; 363 sc->sc_mii.mii_statchg = ep_statchg; 364 365 /* 366 * If we've got an indirect (ISA, PCMCIA?) board, the chipset 367 * is unknown. If the board has large-packet support, it's a 368 * Vortex/Boomerang, otherwise it's a 3c509. 369 * XXX use eeprom capability word instead? 370 */ 371 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN && sc->txashift) { 372 printf("warning: unknown chipset, possibly 3c515?\n"); 373 #ifdef notyet 374 sc->sc_chipset = EP_CHIPSET_VORTEX; 375 #endif /* notyet */ 376 } 377 378 /* 379 * Ascertain which media types are present and inform ifmedia. 380 */ 381 switch (sc->ep_chipset) { 382 case EP_CHIPSET_ROADRUNNER: 383 if (sc->ep_flags & EP_FLAGS_MII) { 384 ep_roadrunner_mii_enable(sc); 385 GO_WINDOW(0); 386 } 387 /* FALLTHROUGH */ 388 389 case EP_CHIPSET_BOOMERANG: 390 /* 391 * If the device has MII, probe it. We won't be using 392 * any `native' media in this case, only PHYs. If 393 * we don't, just treat the Boomerang like the Vortex. 394 */ 395 if (sc->ep_flags & EP_FLAGS_MII) { 396 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 397 MII_PHY_ANY, MII_OFFSET_ANY, 0); 398 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 399 ifmedia_add(&sc->sc_mii.mii_media, 400 IFM_ETHER|IFM_NONE, 0, NULL); 401 ifmedia_set(&sc->sc_mii.mii_media, 402 IFM_ETHER|IFM_NONE); 403 } else { 404 ifmedia_set(&sc->sc_mii.mii_media, 405 IFM_ETHER|IFM_AUTO); 406 } 407 break; 408 } 409 /* FALLTHROUGH */ 410 411 /* on a direct bus, the attach routine can tell, but check anyway. */ 412 case EP_CHIPSET_VORTEX: 413 case EP_CHIPSET_BOOMERANG2: 414 ep_vortex_probemedia(sc); 415 break; 416 417 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */ 418 case EP_CHIPSET_3C509: 419 default: 420 ep_isa_probemedia(sc); 421 break; 422 } 423 424 GO_WINDOW(1); /* Window 1 is operating window */ 425 426 sc->tx_start_thresh = 20; /* probably a good starting point. */ 427 428 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 429 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 430 } 431 432 int 433 ep_detach(struct device *self) 434 { 435 struct ep_softc *sc = (struct ep_softc *)self; 436 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 437 438 if (sc->ep_flags & EP_FLAGS_MII) 439 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 440 441 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 442 443 ether_ifdetach(ifp); 444 if_detach(ifp); 445 446 return (0); 447 } 448 449 /* 450 * Find supported media on 3c509-generation hardware that doesn't have 451 * a "reset_options" register in window 3. 452 * Use the config_cntrl register in window 0 instead. 453 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 454 * that implement CONFIG_CTRL. We don't have a good way to set the 455 * default active medium; punt to ifconfig instead. 456 * 457 * XXX what about 3c515, pcmcia 10/100? 458 */ 459 void 460 ep_isa_probemedia(struct ep_softc *sc) 461 { 462 bus_space_tag_t iot = sc->sc_iot; 463 bus_space_handle_t ioh = sc->sc_ioh; 464 struct ifmedia *ifm = &sc->sc_mii.mii_media; 465 int conn, i; 466 u_int16_t ep_w0_config, port; 467 468 conn = 0; 469 GO_WINDOW(0); 470 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 471 for (i = 0; i < nitems(ep_isa_media); i++) { 472 struct ep_media * epm = ep_isa_media + i; 473 474 if ((ep_w0_config & epm->epm_eeprom_data) != 0) { 475 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 476 if (conn) 477 printf("/"); 478 printf("%s", epm->epm_name); 479 conn |= epm->epm_conn; 480 } 481 } 482 sc->ep_connectors = conn; 483 484 /* get default medium from EEPROM */ 485 if (epbusyeeprom(sc)) 486 return; /* XXX why is eeprom busy? */ 487 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 488 READ_EEPROM | EEPROM_ADDR_CFG); 489 if (epbusyeeprom(sc)) 490 return; /* XXX why is eeprom busy? */ 491 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 492 port = port >> 14; 493 494 printf(" (default %s)\n", ep_vortex_media[port].epm_name); 495 496 /* tell ifconfig what currently-active media is. */ 497 ifmedia_set(ifm, ep_default_to_media[port]); 498 499 /* XXX autoselect not yet implemented */ 500 } 501 502 503 /* 504 * Find media present on large-packet-capable elink3 devices. 505 * Show onboard configuration of large-packet-capable elink3 devices 506 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 507 * Use media and card-version info in window 3 instead. 508 * 509 * XXX how much of this works with 3c515, pcmcia 10/100? 510 */ 511 void 512 ep_vortex_probemedia(struct ep_softc *sc) 513 { 514 bus_space_tag_t iot = sc->sc_iot; 515 bus_space_handle_t ioh = sc->sc_ioh; 516 struct ifmedia *ifm = &sc->sc_mii.mii_media; 517 u_int config1, conn; 518 int reset_options; 519 int default_media; /* 3-bit encoding of default (EEPROM) media */ 520 int autoselect; /* boolean: should default to autoselect */ 521 const char *medium_name; 522 register int i; 523 524 GO_WINDOW(3); 525 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 526 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 527 GO_WINDOW(0); 528 529 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 530 autoselect = (config1 & CONFIG_AUTOSELECT) >> CONFIG_AUTOSELECT_SHIFT; 531 532 /* set available media options */ 533 conn = 0; 534 for (i = 0; i < nitems(ep_vortex_media); i++) { 535 const struct ep_media *epm = ep_vortex_media + i; 536 537 if ((reset_options & epm->epm_eeprom_data) != 0) { 538 if (conn) 539 printf("/"); 540 printf("%s", epm->epm_name); 541 conn |= epm->epm_conn; 542 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 543 } 544 } 545 546 sc->ep_connectors = conn; 547 548 /* Show eeprom's idea of default media. */ 549 medium_name = (default_media > nitems(ep_vortex_media) - 1) 550 ? "(unknown/impossible media)" 551 : ep_vortex_media[default_media].epm_name; 552 printf(" default %s%s", 553 medium_name, (autoselect) ? "/autoselect" : ""); 554 /* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/ 555 556 #ifdef notyet 557 /* 558 * Set default: either the active interface the card 559 * reads from the EEPROM, or if autoselect is true, 560 * whatever we find is actually connected. 561 * 562 * XXX autoselect not yet implemented. 563 */ 564 #endif /* notyet */ 565 566 /* tell ifconfig what currently-active media is. */ 567 ifmedia_set(ifm, ep_default_to_media[default_media]); 568 } 569 570 /* 571 * Bring device up. 572 * 573 * The order in here seems important. Otherwise we may not receive 574 * interrupts. ?! 575 */ 576 void 577 epinit(struct ep_softc *sc) 578 { 579 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 580 bus_space_tag_t iot = sc->sc_iot; 581 bus_space_handle_t ioh = sc->sc_ioh; 582 int i; 583 584 /* make sure any pending reset has completed before touching board */ 585 ep_finish_reset(iot, ioh); 586 587 /* cancel any pending I/O */ 588 epstop(sc); 589 590 if (sc->bustype != EP_BUS_PCI) { 591 GO_WINDOW(0); 592 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 593 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 594 } 595 596 if (sc->bustype == EP_BUS_PCMCIA) { 597 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 598 } 599 600 GO_WINDOW(2); 601 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 602 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 603 sc->sc_arpcom.ac_enaddr[i]); 604 605 if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA) 606 /* 607 * Reset the station-address receive filter. 608 * A bug workaround for busmastering (Vortex, Demon) cards. 609 */ 610 for (i = 0; i < 6; i++) 611 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 612 613 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 614 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 615 616 GO_WINDOW(1); /* Window 1 is operating window */ 617 for (i = 0; i < 31; i++) 618 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 619 620 /* Set threshold for for Tx-space available interrupt. */ 621 bus_space_write_2(iot, ioh, EP_COMMAND, 622 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 623 624 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 625 /* Enable options in the PCMCIA LAN COR register, via 626 * RoadRunner Window 1. 627 * 628 * XXX MAGIC CONSTANTS! 629 */ 630 u_int16_t cor; 631 632 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 633 634 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 635 bus_space_write_2(iot, ioh, 0, cor); 636 637 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 638 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 639 640 if (sc->ep_flags & EP_FLAGS_MII) { 641 ep_roadrunner_mii_enable(sc); 642 GO_WINDOW(1); 643 } 644 } 645 646 /* Enable interrupts. */ 647 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | 648 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 649 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | 650 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 651 652 /* 653 * Attempt to get rid of any stray interrupts that occurred during 654 * configuration. On the i386 this isn't possible because one may 655 * already be queued. However, a single stray interrupt is 656 * unimportant. 657 */ 658 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 659 660 epsetfilter(sc); 661 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 662 663 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 664 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 665 666 epmbuffill(sc); 667 668 /* Interface is now `running', with no output active. */ 669 ifp->if_flags |= IFF_RUNNING; 670 ifp->if_flags &= ~IFF_OACTIVE; 671 672 /* Attempt to start output, if any. */ 673 epstart(ifp); 674 } 675 676 /* 677 * Set multicast receive filter. 678 * elink3 hardware has no selective multicast filter in hardware. 679 * Enable reception of all multicasts and filter in software. 680 */ 681 void 682 epsetfilter(struct ep_softc *sc) 683 { 684 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 685 686 GO_WINDOW(1); /* Window 1 is operating window */ 687 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 688 FIL_INDIVIDUAL | FIL_BRDCST | 689 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 690 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 691 } 692 693 694 int 695 ep_media_change(struct ifnet *ifp) 696 { 697 register struct ep_softc *sc = ifp->if_softc; 698 699 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 700 } 701 702 /* 703 * Reset and enable the MII on the RoadRunner. 704 */ 705 void 706 ep_roadrunner_mii_enable(struct ep_softc *sc) 707 { 708 bus_space_tag_t iot = sc->sc_iot; 709 bus_space_handle_t ioh = sc->sc_ioh; 710 711 GO_WINDOW(3); 712 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 713 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 714 delay(1000); 715 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 716 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII); 717 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 718 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 719 delay(1000); 720 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 721 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 722 } 723 724 /* 725 * Set active media to a specific given EPMEDIA_<> value. 726 * For vortex/demon/boomerang cards, update media field in w3_internal_config, 727 * and power on selected transceiver. 728 * For 3c509-generation cards (3c509/3c579/3c589/3c509B), 729 * update media field in w0_address_config, and power on selected xcvr. 730 */ 731 int 732 epsetmedia(struct ep_softc *sc, int medium) 733 { 734 bus_space_tag_t iot = sc->sc_iot; 735 bus_space_handle_t ioh = sc->sc_ioh; 736 int w4_media; 737 int config0, config1; 738 739 /* 740 * you can `ifconfig (link0|-link0) ep0' to get the following 741 * behaviour: 742 * -link0 disable AUI/UTP. enable BNC. 743 * link0 disable BNC. enable AUI. 744 * link1 if the card has a UTP connector, and link0 is 745 * set too, then you get the UTP port. 746 */ 747 748 /* 749 * First, change the media-control bits in EP_W4_MEDIA_TYPE. 750 */ 751 752 /* Turn everything off. First turn off linkbeat and UTP. */ 753 GO_WINDOW(4); 754 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 755 w4_media = w4_media & ~(ENABLE_UTP|SQE_ENABLE); 756 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media); 757 758 /* Turn off coax */ 759 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 760 delay(1000); 761 762 /* If the device has MII, select it, and then tell the 763 * PHY which media to use. 764 */ 765 if (sc->ep_flags & EP_FLAGS_MII) { 766 GO_WINDOW(3); 767 768 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 769 int resopt; 770 771 resopt = bus_space_read_2(iot, ioh, 772 EP_W3_RESET_OPTIONS); 773 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 774 resopt | EP_RUNNER_ENABLE_MII); 775 } 776 777 config0 = (u_int)bus_space_read_2(iot, ioh, 778 EP_W3_INTERNAL_CONFIG); 779 config1 = (u_int)bus_space_read_2(iot, ioh, 780 EP_W3_INTERNAL_CONFIG + 2); 781 782 config1 = config1 & ~CONFIG_MEDIAMASK; 783 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 784 785 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 786 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 787 GO_WINDOW(1); /* back to operating window */ 788 789 mii_mediachg(&sc->sc_mii); 790 return (0); 791 } 792 793 /* 794 * Now turn on the selected media/transceiver. 795 */ 796 GO_WINDOW(4); 797 switch (medium) { 798 case EPMEDIA_10BASE_T: 799 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP | 800 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0))); 801 break; 802 803 case EPMEDIA_10BASE_2: 804 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 805 DELAY(1000); /* 50ms not enough? */ 806 break; 807 808 /* XXX following only for new-generation cards */ 809 case EPMEDIA_100BASE_TX: 810 case EPMEDIA_100BASE_FX: 811 case EPMEDIA_100BASE_T4: /* XXX check documentation */ 812 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 813 w4_media | LINKBEAT_ENABLE); 814 DELAY(1000); /* not strictly necessary? */ 815 break; 816 817 case EPMEDIA_AUI: 818 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 819 w4_media | SQE_ENABLE); 820 DELAY(1000); /* not strictly necessary? */ 821 break; 822 case EPMEDIA_MII: 823 break; 824 default: 825 #if defined(EP_DEBUG) 826 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium); 827 #endif 828 break; 829 830 } 831 832 /* 833 * Tell the chip which PHY [sic] to use. 834 */ 835 switch (sc->ep_chipset) { 836 case EP_CHIPSET_VORTEX: 837 case EP_CHIPSET_BOOMERANG2: 838 GO_WINDOW(3); 839 config0 = (u_int)bus_space_read_2(iot, ioh, 840 EP_W3_INTERNAL_CONFIG); 841 config1 = (u_int)bus_space_read_2(iot, ioh, 842 EP_W3_INTERNAL_CONFIG + 2); 843 844 #if defined(EP_DEBUG) 845 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n", 846 sc->sc_dev.dv_xname, config0, config1); 847 #endif 848 config1 = config1 & ~CONFIG_MEDIAMASK; 849 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT); 850 851 #if defined(EP_DEBUG) 852 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n", 853 sc->sc_dev.dv_xname, medium, config1); 854 #endif 855 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 856 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 857 break; 858 859 default: 860 GO_WINDOW(0); 861 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 862 config0 &= 0x3fff; 863 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 864 config0 | (medium << 14)); 865 DELAY(1000); 866 break; 867 } 868 869 GO_WINDOW(1); /* Window 1 is operating window */ 870 return (0); 871 } 872 873 874 /* 875 * Get currently-selected media from card. 876 * (if_media callback, may be called before interface is brought up). 877 */ 878 void 879 ep_media_status(struct ifnet *ifp, struct ifmediareq *req) 880 { 881 register struct ep_softc *sc = ifp->if_softc; 882 bus_space_tag_t iot = sc->sc_iot; 883 bus_space_handle_t ioh = sc->sc_ioh; 884 u_int config1; 885 u_int ep_mediastatus; 886 887 /* 888 * If we have MII, go ask the PHY what's going on. 889 */ 890 if (sc->ep_flags & EP_FLAGS_MII) { 891 mii_pollstat(&sc->sc_mii); 892 req->ifm_active = sc->sc_mii.mii_media_active; 893 req->ifm_status = sc->sc_mii.mii_media_status; 894 return; 895 } 896 897 /* XXX read from softc when we start autosensing media */ 898 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 899 900 switch (sc->ep_chipset) { 901 case EP_CHIPSET_VORTEX: 902 case EP_CHIPSET_BOOMERANG: 903 GO_WINDOW(3); 904 delay(5000); 905 906 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 907 GO_WINDOW(1); 908 909 config1 = 910 (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 911 req->ifm_active = ep_default_to_media[config1]; 912 913 /* XXX check full-duplex bits? */ 914 915 GO_WINDOW(4); 916 req->ifm_status = IFM_AVALID; /* XXX */ 917 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 918 if (ep_mediastatus & LINKBEAT_DETECT) 919 req->ifm_status |= IFM_ACTIVE; /* XXX automedia */ 920 921 break; 922 923 case EP_CHIPSET_UNKNOWN: 924 case EP_CHIPSET_3C509: 925 req->ifm_status = 0; /* XXX */ 926 break; 927 928 default: 929 printf("%s: media_status on unknown chipset 0x%x\n", 930 ifp->if_xname, sc->ep_chipset); 931 break; 932 } 933 934 /* XXX look for softc heartbeat for other chips or media */ 935 936 GO_WINDOW(1); 937 return; 938 } 939 940 941 942 /* 943 * Start outputting on the interface. 944 * Always called as splnet(). 945 */ 946 void 947 epstart(struct ifnet *ifp) 948 { 949 register struct ep_softc *sc = ifp->if_softc; 950 bus_space_tag_t iot = sc->sc_iot; 951 bus_space_handle_t ioh = sc->sc_ioh; 952 struct mbuf *m, *m0; 953 caddr_t data; 954 int sh, len, pad, txreg; 955 956 /* Don't transmit if interface is busy or not running */ 957 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 958 return; 959 960 startagain: 961 /* Sneak a peek at the next packet */ 962 IFQ_POLL(&ifp->if_snd, m0); 963 if (m0 == NULL) 964 return; 965 966 /* We need to use m->m_pkthdr.len, so require the header */ 967 if ((m0->m_flags & M_PKTHDR) == 0) 968 panic("epstart: no header mbuf"); 969 len = m0->m_pkthdr.len; 970 971 pad = (4 - len) & 3; 972 973 /* 974 * The 3c509 automatically pads short packets to minimum ethernet 975 * length, but we drop packets that are too large. Perhaps we should 976 * truncate them instead? 977 */ 978 if (len + pad > ETHER_MAX_LEN) { 979 /* packet is obviously too large: toss it */ 980 ++ifp->if_oerrors; 981 IFQ_DEQUEUE(&ifp->if_snd, m0); 982 m_freem(m0); 983 goto readcheck; 984 } 985 986 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 987 len + pad + 4) { 988 bus_space_write_2(iot, ioh, EP_COMMAND, 989 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift)); 990 /* not enough room in FIFO */ 991 ifp->if_flags |= IFF_OACTIVE; 992 return; 993 } else { 994 bus_space_write_2(iot, ioh, EP_COMMAND, 995 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE); 996 } 997 998 IFQ_DEQUEUE(&ifp->if_snd, m0); 999 if (m0 == NULL) 1000 return; 1001 1002 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1003 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/)); 1004 1005 #if NBPFILTER > 0 1006 if (ifp->if_bpf) 1007 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1008 #endif 1009 1010 /* 1011 * Do the output at splhigh() so that an interrupt from another device 1012 * won't cause a FIFO underrun. 1013 */ 1014 sh = splhigh(); 1015 1016 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1017 1018 bus_space_write_2(iot, ioh, txreg, len); 1019 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1020 if (EP_IS_BUS_32(sc->bustype)) { 1021 for (m = m0; m; ) { 1022 data = mtod(m, u_int8_t *); 1023 if (m->m_len > 3 && ALIGNED_POINTER(data, uint32_t)) { 1024 bus_space_write_raw_multi_4(iot, ioh, txreg, 1025 data, m->m_len & ~3); 1026 if (m->m_len & 3) 1027 bus_space_write_multi_1(iot, ioh, txreg, 1028 data + (m->m_len & ~3), 1029 m->m_len & 3); 1030 } else 1031 bus_space_write_multi_1(iot, ioh, txreg, 1032 data, m->m_len); 1033 MFREE(m, m0); 1034 m = m0; 1035 } 1036 } else { 1037 for (m = m0; m; ) { 1038 data = mtod(m, u_int8_t *); 1039 if (m->m_len > 1 && ALIGNED_POINTER(data, uint16_t)) { 1040 bus_space_write_raw_multi_2(iot, ioh, txreg, 1041 data, m->m_len & ~1); 1042 if (m->m_len & 1) 1043 bus_space_write_1(iot, ioh, txreg, 1044 *(data + m->m_len - 1)); 1045 } else 1046 bus_space_write_multi_1(iot, ioh, txreg, 1047 data, m->m_len); 1048 MFREE(m, m0); 1049 m = m0; 1050 } 1051 } 1052 while (pad--) 1053 bus_space_write_1(iot, ioh, txreg, 0); 1054 1055 splx(sh); 1056 1057 ++ifp->if_opackets; 1058 1059 readcheck: 1060 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1061 ERR_INCOMPLETE) == 0) { 1062 /* We received a complete packet. */ 1063 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1064 1065 if ((status & S_INTR_LATCH) == 0) { 1066 /* 1067 * No interrupt, read the packet and continue 1068 * Is this supposed to happen? Is my motherboard 1069 * completely busted? 1070 */ 1071 epread(sc); 1072 } else 1073 /* Got an interrupt, return to get it serviced. */ 1074 return; 1075 } else { 1076 /* Check if we are stuck and reset [see XXX comment] */ 1077 if (epstatus(sc)) { 1078 #ifdef EP_DEBUG 1079 if (ifp->if_flags & IFF_DEBUG) 1080 printf("%s: adapter reset\n", 1081 sc->sc_dev.dv_xname); 1082 #endif 1083 epreset(sc); 1084 } 1085 } 1086 1087 goto startagain; 1088 } 1089 1090 1091 /* 1092 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1093 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1094 * We detect this situation and we reset the adapter. 1095 * It happens at times when there is a lot of broadcast traffic 1096 * on the cable (once in a blue moon). 1097 */ 1098 int 1099 epstatus(struct ep_softc *sc) 1100 { 1101 bus_space_tag_t iot = sc->sc_iot; 1102 bus_space_handle_t ioh = sc->sc_ioh; 1103 u_int16_t fifost; 1104 1105 /* 1106 * Check the FIFO status and act accordingly 1107 */ 1108 GO_WINDOW(4); 1109 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1110 GO_WINDOW(1); 1111 1112 if (fifost & FIFOS_RX_UNDERRUN) { 1113 #ifdef EP_DEBUG 1114 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1115 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1116 #endif 1117 epreset(sc); 1118 return 0; 1119 } 1120 1121 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1122 #ifdef EP_DEBUG 1123 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1124 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1125 #endif 1126 return 1; 1127 } 1128 1129 if (fifost & FIFOS_RX_OVERRUN) { 1130 #ifdef EP_DEBUG 1131 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1132 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1133 #endif 1134 return 1; 1135 } 1136 1137 if (fifost & FIFOS_TX_OVERRUN) { 1138 #ifdef EP_DEBUG 1139 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1140 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1141 #endif 1142 epreset(sc); 1143 return 0; 1144 } 1145 1146 return 0; 1147 } 1148 1149 1150 void 1151 eptxstat(struct ep_softc *sc) 1152 { 1153 bus_space_tag_t iot = sc->sc_iot; 1154 bus_space_handle_t ioh = sc->sc_ioh; 1155 int i; 1156 1157 /* 1158 * We need to read+write TX_STATUS until we get a 0 status 1159 * in order to turn off the interrupt flag. 1160 */ 1161 while ((i = bus_space_read_1(iot, ioh, 1162 ep_w1_reg(sc, EP_W1_TX_STATUS))) & TXS_COMPLETE) { 1163 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1164 0x0); 1165 1166 if (i & TXS_JABBER) { 1167 ++sc->sc_arpcom.ac_if.if_oerrors; 1168 #ifdef EP_DEBUG 1169 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1170 printf("%s: jabber (%x)\n", 1171 sc->sc_dev.dv_xname, i); 1172 #endif 1173 epreset(sc); 1174 } else if (i & TXS_UNDERRUN) { 1175 ++sc->sc_arpcom.ac_if.if_oerrors; 1176 #ifdef EP_DEBUG 1177 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1178 printf("%s: fifo underrun (%x) @%d\n", 1179 sc->sc_dev.dv_xname, i, 1180 sc->tx_start_thresh); 1181 #endif 1182 if (sc->tx_succ_ok < 100) 1183 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1184 sc->tx_start_thresh + 20); 1185 sc->tx_succ_ok = 0; 1186 epreset(sc); 1187 } else if (i & TXS_MAX_COLLISION) { 1188 ++sc->sc_arpcom.ac_if.if_collisions; 1189 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1190 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1191 } else 1192 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1193 } 1194 } 1195 1196 int 1197 epintr(void *arg) 1198 { 1199 register struct ep_softc *sc = arg; 1200 bus_space_tag_t iot = sc->sc_iot; 1201 bus_space_handle_t ioh = sc->sc_ioh; 1202 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1203 u_int16_t status; 1204 int ret = 0; 1205 1206 for (;;) { 1207 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1208 1209 status = bus_space_read_2(iot, ioh, EP_STATUS); 1210 1211 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1212 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) 1213 break; 1214 1215 ret = 1; 1216 1217 /* 1218 * Acknowledge any interrupts. It's important that we do this 1219 * first, since there would otherwise be a race condition. 1220 * Due to the i386 interrupt queueing, we may get spurious 1221 * interrupts occasionally. 1222 */ 1223 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status); 1224 1225 if (status & S_RX_COMPLETE) 1226 epread(sc); 1227 if (status & S_TX_AVAIL) { 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 epstart(ifp); 1230 } 1231 if (status & S_CARD_FAILURE) { 1232 epreset(sc); 1233 return (1); 1234 } 1235 if (status & S_TX_COMPLETE) { 1236 eptxstat(sc); 1237 epstart(ifp); 1238 } 1239 } 1240 1241 /* no more interrupts */ 1242 return (ret); 1243 } 1244 1245 void 1246 epread(struct ep_softc *sc) 1247 { 1248 bus_space_tag_t iot = sc->sc_iot; 1249 bus_space_handle_t ioh = sc->sc_ioh; 1250 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1251 struct mbuf *m; 1252 int len; 1253 1254 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1255 1256 again: 1257 #ifdef EP_DEBUG 1258 if (ifp->if_flags & IFF_DEBUG) { 1259 int err = len & ERR_MASK; 1260 char *s = NULL; 1261 1262 if (len & ERR_INCOMPLETE) 1263 s = "incomplete packet"; 1264 else if (err == ERR_OVERRUN) 1265 s = "packet overrun"; 1266 else if (err == ERR_RUNT) 1267 s = "runt packet"; 1268 else if (err == ERR_ALIGNMENT) 1269 s = "bad alignment"; 1270 else if (err == ERR_CRC) 1271 s = "bad crc"; 1272 else if (err == ERR_OVERSIZE) 1273 s = "oversized packet"; 1274 else if (err == ERR_DRIBBLE) 1275 s = "dribble bits"; 1276 1277 if (s) 1278 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1279 } 1280 #endif 1281 1282 if (len & ERR_INCOMPLETE) 1283 return; 1284 1285 if (len & ERR_RX) { 1286 ++ifp->if_ierrors; 1287 goto abort; 1288 } 1289 1290 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1291 1292 /* Pull packet off interface. */ 1293 m = epget(sc, len); 1294 if (m == NULL) { 1295 ifp->if_ierrors++; 1296 goto abort; 1297 } 1298 1299 ++ifp->if_ipackets; 1300 1301 #if NBPFILTER > 0 1302 /* 1303 * Check if there's a BPF listener on this interface. 1304 * If so, hand off the raw packet to BPF. 1305 */ 1306 if (ifp->if_bpf) 1307 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1308 #endif 1309 1310 ether_input_mbuf(ifp, m); 1311 1312 /* 1313 * In periods of high traffic we can actually receive enough 1314 * packets so that the fifo overrun bit will be set at this point, 1315 * even though we just read a packet. In this case we 1316 * are not going to receive any more interrupts. We check for 1317 * this condition and read again until the fifo is not full. 1318 * We could simplify this test by not using epstatus(), but 1319 * rechecking the RX_STATUS register directly. This test could 1320 * result in unnecessary looping in cases where there is a new 1321 * packet but the fifo is not full, but it will not fix the 1322 * stuck behavior. 1323 * 1324 * Even with this improvement, we still get packet overrun errors 1325 * which are hurting performance. Maybe when I get some more time 1326 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1327 */ 1328 if (epstatus(sc)) { 1329 len = bus_space_read_2(iot, ioh, 1330 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1331 /* Check if we are stuck and reset [see XXX comment] */ 1332 if (len & ERR_INCOMPLETE) { 1333 #ifdef EP_DEBUG 1334 if (ifp->if_flags & IFF_DEBUG) 1335 printf("%s: adapter reset\n", 1336 sc->sc_dev.dv_xname); 1337 #endif 1338 epreset(sc); 1339 return; 1340 } 1341 goto again; 1342 } 1343 1344 return; 1345 1346 abort: 1347 ep_discard_rxtop(iot, ioh); 1348 } 1349 1350 struct mbuf * 1351 epget(struct ep_softc *sc, int totlen) 1352 { 1353 bus_space_tag_t iot = sc->sc_iot; 1354 bus_space_handle_t ioh = sc->sc_ioh; 1355 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1356 struct mbuf *m; 1357 caddr_t data; 1358 int len, pad, off, sh, rxreg; 1359 1360 splassert(IPL_NET); 1361 1362 m = sc->mb[sc->next_mb]; 1363 sc->mb[sc->next_mb] = NULL; 1364 if (m == NULL) { 1365 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1366 /* If the queue is no longer full, refill. */ 1367 if (!timeout_pending(&sc->sc_epmbuffill_tmo)) 1368 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1369 } 1370 if (!m) 1371 return (NULL); 1372 1373 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1374 1375 len = MCLBYTES; 1376 m->m_pkthdr.rcvif = ifp; 1377 m->m_pkthdr.len = totlen; 1378 m->m_len = totlen; 1379 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1380 m->m_data += pad; 1381 len -= pad; 1382 1383 /* 1384 * We read the packet at splhigh() so that an interrupt from another 1385 * device doesn't cause the card's buffer to overflow while we're 1386 * reading it. We may still lose packets at other times. 1387 */ 1388 sh = splhigh(); 1389 1390 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1391 1392 off = 0; 1393 while (totlen) { 1394 len = min(totlen, M_TRAILINGSPACE(m)); 1395 if (len == 0) 1396 panic("ep_get: packet does not fit in MCLBYTES"); 1397 1398 data = mtod(m, u_int8_t *); 1399 if (EP_IS_BUS_32(sc->bustype)) 1400 pad = 4 - ((u_long)(data + off) & 0x3); 1401 else 1402 pad = (u_long)(data + off) & 0x1; 1403 1404 if (pad) { 1405 if (pad < len) 1406 pad = len; 1407 bus_space_read_multi_1(iot, ioh, rxreg, 1408 data + off, pad); 1409 len = pad; 1410 } else if (EP_IS_BUS_32(sc->bustype) && len > 3 && 1411 ALIGNED_POINTER(data, uint32_t)) { 1412 len &= ~3; 1413 bus_space_read_raw_multi_4(iot, ioh, rxreg, 1414 data + off, len); 1415 } else if (len > 1 && ALIGNED_POINTER(data, uint16_t)) { 1416 len &= ~1; 1417 bus_space_read_raw_multi_2(iot, ioh, rxreg, 1418 data + off, len); 1419 } else 1420 bus_space_read_multi_1(iot, ioh, rxreg, 1421 data + off, len); 1422 1423 off += len; 1424 totlen -= len; 1425 } 1426 1427 ep_discard_rxtop(iot, ioh); 1428 1429 splx(sh); 1430 1431 return m; 1432 } 1433 1434 int 1435 epioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1436 { 1437 struct ep_softc *sc = ifp->if_softc; 1438 struct ifaddr *ifa = (struct ifaddr *)data; 1439 struct ifreq *ifr = (struct ifreq *)data; 1440 int s, error = 0; 1441 1442 s = splnet(); 1443 1444 switch (cmd) { 1445 case SIOCSIFADDR: 1446 ifp->if_flags |= IFF_UP; 1447 1448 switch (ifa->ifa_addr->sa_family) { 1449 #ifdef INET 1450 case AF_INET: 1451 epinit(sc); 1452 arp_ifinit(&sc->sc_arpcom, ifa); 1453 break; 1454 #endif 1455 default: 1456 epinit(sc); 1457 break; 1458 } 1459 break; 1460 1461 case SIOCSIFMEDIA: 1462 case SIOCGIFMEDIA: 1463 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1464 break; 1465 1466 case SIOCSIFFLAGS: 1467 if ((ifp->if_flags & IFF_UP) == 0 && 1468 (ifp->if_flags & IFF_RUNNING) != 0) { 1469 /* 1470 * If interface is marked down and it is running, then 1471 * stop it. 1472 */ 1473 epstop(sc); 1474 ifp->if_flags &= ~IFF_RUNNING; 1475 } else if ((ifp->if_flags & IFF_UP) != 0 && 1476 (ifp->if_flags & IFF_RUNNING) == 0) { 1477 /* 1478 * If interface is marked up and it is stopped, then 1479 * start it. 1480 */ 1481 epinit(sc); 1482 } else if ((ifp->if_flags & IFF_UP) != 0) { 1483 /* 1484 * Reset the interface to pick up changes in any other 1485 * flags that affect hardware registers. 1486 */ 1487 epinit(sc); 1488 } 1489 break; 1490 1491 default: 1492 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1493 } 1494 1495 if (error == ENETRESET) { 1496 if (ifp->if_flags & IFF_RUNNING) 1497 epreset(sc); 1498 error = 0; 1499 } 1500 1501 splx(s); 1502 return (error); 1503 } 1504 1505 void 1506 epreset(struct ep_softc *sc) 1507 { 1508 int s; 1509 1510 s = splnet(); 1511 epinit(sc); 1512 splx(s); 1513 } 1514 1515 void 1516 epwatchdog(struct ifnet *ifp) 1517 { 1518 struct ep_softc *sc = ifp->if_softc; 1519 1520 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1521 ++sc->sc_arpcom.ac_if.if_oerrors; 1522 1523 epreset(sc); 1524 } 1525 1526 void 1527 epstop(struct ep_softc *sc) 1528 { 1529 bus_space_tag_t iot = sc->sc_iot; 1530 bus_space_handle_t ioh = sc->sc_ioh; 1531 1532 if (sc->ep_flags & EP_FLAGS_MII) { 1533 mii_down(&sc->sc_mii); 1534 } 1535 1536 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1537 /* Clear the FIFO buffer count, thus halting 1538 * any currently-running transactions. 1539 */ 1540 GO_WINDOW(1); /* sanity */ 1541 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1542 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1543 } 1544 1545 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1546 ep_discard_rxtop(iot, ioh); 1547 1548 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1549 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1550 1551 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 1552 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 1553 1554 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1555 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1556 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1557 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1558 1559 epmbufempty(sc); 1560 } 1561 1562 /* 1563 * We get eeprom data from the id_port given an offset into the 1564 * eeprom. Basically; after the ID_sequence is sent to all of 1565 * the cards; they enter the ID_CMD state where they will accept 1566 * command requests. 0x80-0xbf loads the eeprom data. We then 1567 * read the port 16 times and with every read; the cards check 1568 * for contention (ie: if one card writes a 0 bit and another 1569 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1570 * each card compares the data on the bus; if there is a difference 1571 * then that card goes into ID_WAIT state again). In the meantime; 1572 * one bit of data is returned in the AX register which is conveniently 1573 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1574 * bit of data with each read. 1575 * 1576 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1577 */ 1578 u_int16_t 1579 epreadeeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int offset) 1580 { 1581 u_int16_t data = 0; 1582 int i; 1583 1584 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1585 delay(1000); 1586 for (i = 0; i < 16; i++) 1587 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1588 return (data); 1589 } 1590 1591 int 1592 epbusyeeprom(struct ep_softc *sc) 1593 { 1594 bus_space_tag_t iot = sc->sc_iot; 1595 bus_space_handle_t ioh = sc->sc_ioh; 1596 int i = 100, j; 1597 1598 while (i--) { 1599 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1600 if (j & EEPROM_BUSY) 1601 delay(100); 1602 else 1603 break; 1604 } 1605 if (!i) { 1606 printf("\n%s: eeprom failed to come ready\n", 1607 sc->sc_dev.dv_xname); 1608 return (1); 1609 } 1610 if (sc->bustype != EP_BUS_PCMCIA && sc->bustype != EP_BUS_PCI && 1611 (j & EEPROM_TST_MODE)) { 1612 printf("\n%s: erase pencil mark, or disable PnP mode!\n", 1613 sc->sc_dev.dv_xname); 1614 return (1); 1615 } 1616 return (0); 1617 } 1618 1619 u_int16_t 1620 ep_read_eeprom(struct ep_softc *sc, u_int16_t offset) 1621 { 1622 u_int16_t readcmd; 1623 1624 /* 1625 * RoadRunner has a larger EEPROM, so a different read command 1626 * is required. 1627 */ 1628 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) 1629 readcmd = READ_EEPROM_RR; 1630 else 1631 readcmd = READ_EEPROM; 1632 1633 if (epbusyeeprom(sc)) 1634 return (0); /* XXX why is eeprom busy? */ 1635 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND, 1636 readcmd | offset); 1637 if (epbusyeeprom(sc)) 1638 return (0); /* XXX why is eeprom busy? */ 1639 1640 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)); 1641 } 1642 1643 void 1644 epmbuffill(void *v) 1645 { 1646 struct ep_softc *sc = v; 1647 int s, i; 1648 1649 s = splnet(); 1650 for (i = 0; i < MAX_MBS; i++) { 1651 if (sc->mb[i] == NULL) { 1652 sc->mb[i] = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1653 if (sc->mb[i] == NULL) 1654 break; 1655 } 1656 } 1657 /* If the queue was not filled, try again. */ 1658 if (i < MAX_MBS) 1659 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1660 splx(s); 1661 } 1662 1663 void 1664 epmbufempty(struct ep_softc *sc) 1665 { 1666 int s, i; 1667 1668 s = splnet(); 1669 for (i = 0; i<MAX_MBS; i++) { 1670 if (sc->mb[i]) { 1671 m_freem(sc->mb[i]); 1672 sc->mb[i] = NULL; 1673 } 1674 } 1675 sc->next_mb = 0; 1676 timeout_del(&sc->sc_epmbuffill_tmo); 1677 splx(s); 1678 } 1679 1680 void 1681 ep_mii_setbit(struct ep_softc *sc, u_int16_t bit) 1682 { 1683 u_int16_t val; 1684 1685 /* We assume we're already in Window 4 */ 1686 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1687 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1688 val | bit); 1689 } 1690 1691 void 1692 ep_mii_clrbit(struct ep_softc *sc, u_int16_t bit) 1693 { 1694 u_int16_t val; 1695 1696 /* We assume we're already in Window 4 */ 1697 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1698 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1699 val & ~bit); 1700 } 1701 1702 u_int16_t 1703 ep_mii_readbit(struct ep_softc *sc, u_int16_t bit) 1704 { 1705 1706 /* We assume we're already in Window 4 */ 1707 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1708 bit); 1709 } 1710 1711 void 1712 ep_mii_sync(struct ep_softc *sc) 1713 { 1714 int i; 1715 1716 /* We assume we're already in Window 4 */ 1717 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1718 for (i = 0; i < 32; i++) { 1719 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1720 ep_mii_setbit(sc, PHYSMGMT_CLK); 1721 } 1722 } 1723 1724 void 1725 ep_mii_sendbits(struct ep_softc *sc, u_int32_t data, int nbits) 1726 { 1727 int i; 1728 1729 /* We assume we're already in Window 4 */ 1730 ep_mii_setbit(sc, PHYSMGMT_DIR); 1731 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1732 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1733 ep_mii_readbit(sc, PHYSMGMT_CLK); 1734 if (data & i) 1735 ep_mii_setbit(sc, PHYSMGMT_DATA); 1736 else 1737 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1738 ep_mii_setbit(sc, PHYSMGMT_CLK); 1739 ep_mii_readbit(sc, PHYSMGMT_CLK); 1740 } 1741 } 1742 1743 int 1744 ep_mii_readreg(struct device *self, int phy, int reg) 1745 { 1746 struct ep_softc *sc = (struct ep_softc *)self; 1747 int val = 0, i, err; 1748 1749 /* 1750 * Read the PHY register by manually driving the MII control lines. 1751 */ 1752 1753 GO_WINDOW(4); 1754 1755 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1756 1757 ep_mii_sync(sc); 1758 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1759 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1760 ep_mii_sendbits(sc, phy, 5); 1761 ep_mii_sendbits(sc, reg, 5); 1762 1763 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1764 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1765 ep_mii_setbit(sc, PHYSMGMT_CLK); 1766 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1767 1768 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1769 ep_mii_setbit(sc, PHYSMGMT_CLK); 1770 1771 /* Even if an error occurs, must still clock out the cycle. */ 1772 for (i = 0; i < 16; i++) { 1773 val <<= 1; 1774 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1775 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1776 val |= 1; 1777 ep_mii_setbit(sc, PHYSMGMT_CLK); 1778 } 1779 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1780 ep_mii_setbit(sc, PHYSMGMT_CLK); 1781 1782 GO_WINDOW(1); /* back to operating window */ 1783 1784 return (err ? 0 : val); 1785 } 1786 1787 void 1788 ep_mii_writereg(struct device *self, int phy, int reg, int val) 1789 { 1790 struct ep_softc *sc = (struct ep_softc *)self; 1791 1792 /* 1793 * Write the PHY register by manually driving the MII control lines. 1794 */ 1795 1796 GO_WINDOW(4); 1797 1798 ep_mii_sync(sc); 1799 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1800 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1801 ep_mii_sendbits(sc, phy, 5); 1802 ep_mii_sendbits(sc, reg, 5); 1803 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1804 ep_mii_sendbits(sc, val, 16); 1805 1806 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1807 ep_mii_setbit(sc, PHYSMGMT_CLK); 1808 1809 GO_WINDOW(1); /* back to operating window */ 1810 } 1811 1812 void 1813 ep_statchg(struct device *self) 1814 { 1815 struct ep_softc *sc = (struct ep_softc *)self; 1816 bus_space_tag_t iot = sc->sc_iot; 1817 bus_space_handle_t ioh = sc->sc_ioh; 1818 int mctl; 1819 1820 /* XXX Update ifp->if_baudrate */ 1821 1822 GO_WINDOW(3); 1823 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 1824 if (sc->sc_mii.mii_media_active & IFM_FDX) 1825 mctl |= MAC_CONTROL_FDX; 1826 else 1827 mctl &= ~MAC_CONTROL_FDX; 1828 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 1829 GO_WINDOW(1); /* back to operating window */ 1830 } 1831