1 /* $OpenBSD: elink3.c,v 1.78 2012/04/09 16:41:33 miod Exp $ */ 2 /* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org> 6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Herb Peyerl. 20 * 4. The name of Herb Peyerl may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/ioctl.h> 42 #include <sys/errno.h> 43 #include <sys/syslog.h> 44 #include <sys/selinfo.h> 45 #include <sys/timeout.h> 46 #include <sys/device.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_types.h> 51 #include <net/netisr.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/cpu.h> 67 #include <machine/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/ic/elink3var.h> 73 #include <dev/ic/elink3reg.h> 74 75 /* 76 * Structure to map media-present bits in boards to 77 * ifmedia codes and printable media names. Used for table-driven 78 * ifmedia initialization. 79 */ 80 struct ep_media { 81 int epm_eeprom_data; /* bitmask for eeprom config */ 82 int epm_conn; /* sc->ep_connectors code for medium */ 83 char *epm_name; /* name of medium */ 84 int epm_ifmedia; /* ifmedia word for medium */ 85 int epm_ifdata; 86 }; 87 88 /* 89 * ep_media table for Vortex/Demon/Boomerang: 90 * map from media-present bits in register RESET_OPTIONS+2 91 * to ifmedia "media words" and printable names. 92 * 93 * XXX indexed directly by INTERNAL_CONFIG default_media field, 94 * (i.e., EPMEDIA_ constants) forcing order of entries. 95 * Note that 3 is reserved. 96 */ 97 const struct ep_media ep_vortex_media[] = { 98 { EP_PCI_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, 99 EPMEDIA_10BASE_T }, 100 { EP_PCI_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, 101 EPMEDIA_AUI }, 102 { 0, 0, "reserved", IFM_NONE, EPMEDIA_RESV1 }, 103 { EP_PCI_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, 104 EPMEDIA_10BASE_2 }, 105 { EP_PCI_100BASE_TX, EPC_100TX, "100-TX", IFM_ETHER|IFM_100_TX, 106 EPMEDIA_100BASE_TX }, 107 { EP_PCI_100BASE_FX, EPC_100FX, "100-FX", IFM_ETHER|IFM_100_FX, 108 EPMEDIA_100BASE_FX }, 109 { EP_PCI_100BASE_MII,EPC_MII, "mii", IFM_ETHER|IFM_100_TX, 110 EPMEDIA_MII }, 111 { EP_PCI_100BASE_T4, EPC_100T4, "100-T4", IFM_ETHER|IFM_100_T4, 112 EPMEDIA_100BASE_T4 } 113 }; 114 115 /* 116 * ep_media table for 3c509/3c509b/3c579/3c589: 117 * map from media-present bits in register CNFG_CNTRL 118 * (window 0, offset ?) to ifmedia "media words" and printable names. 119 */ 120 struct ep_media ep_isa_media[] = { 121 { EP_W0_CC_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, EPMEDIA_10BASE_T }, 122 { EP_W0_CC_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, EPMEDIA_AUI }, 123 { EP_W0_CC_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, EPMEDIA_10BASE_2 }, 124 }; 125 126 /* Map vortex reset_options bits to if_media codes. */ 127 const u_int ep_default_to_media[] = { 128 IFM_ETHER | IFM_10_T, 129 IFM_ETHER | IFM_10_5, 130 0, /* reserved by 3Com */ 131 IFM_ETHER | IFM_10_2, 132 IFM_ETHER | IFM_100_TX, 133 IFM_ETHER | IFM_100_FX, 134 IFM_ETHER | IFM_100_TX, /* XXX really MII: need to talk to PHY */ 135 IFM_ETHER | IFM_100_T4, 136 }; 137 138 struct cfdriver ep_cd = { 139 NULL, "ep", DV_IFNET 140 }; 141 142 void ep_vortex_probemedia(struct ep_softc *sc); 143 void ep_isa_probemedia(struct ep_softc *sc); 144 145 void eptxstat(struct ep_softc *); 146 int epstatus(struct ep_softc *); 147 int epioctl(struct ifnet *, u_long, caddr_t); 148 void epstart(struct ifnet *); 149 void epwatchdog(struct ifnet *); 150 void epreset(struct ep_softc *); 151 void epread(struct ep_softc *); 152 struct mbuf *epget(struct ep_softc *, int); 153 void epmbuffill(void *); 154 void epmbufempty(struct ep_softc *); 155 void epsetfilter(struct ep_softc *); 156 void ep_roadrunner_mii_enable(struct ep_softc *); 157 int epsetmedia(struct ep_softc *, int); 158 159 /* ifmedia callbacks */ 160 int ep_media_change(struct ifnet *); 161 void ep_media_status(struct ifnet *, struct ifmediareq *); 162 163 /* MII callbacks */ 164 int ep_mii_readreg(struct device *, int, int); 165 void ep_mii_writereg(struct device *, int, int, int); 166 void ep_statchg(struct device *); 167 168 void ep_mii_setbit(struct ep_softc *, u_int16_t); 169 void ep_mii_clrbit(struct ep_softc *, u_int16_t); 170 u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t); 171 void ep_mii_sync(struct ep_softc *); 172 void ep_mii_sendbits(struct ep_softc *, u_int32_t, int); 173 174 int epbusyeeprom(struct ep_softc *); 175 u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t); 176 177 static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg); 178 static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t); 179 static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t); 180 static __inline int ep_w1_reg(struct ep_softc *, int); 181 182 /* 183 * Issue a (reset) command, and be sure it has completed. 184 * Used for global reset, TX_RESET, RX_RESET. 185 */ 186 static inline void 187 ep_reset_cmd(struct ep_softc *sc, u_int cmd, u_int arg) 188 { 189 bus_space_tag_t iot = sc->sc_iot; 190 bus_space_handle_t ioh = sc->sc_ioh; 191 192 bus_space_write_2(iot, ioh, cmd, arg); 193 ep_finish_reset(iot, ioh); 194 } 195 196 /* 197 * Wait for any pending reset to complete. 198 */ 199 static inline void 200 ep_finish_reset(bus_space_tag_t iot, bus_space_handle_t ioh) 201 { 202 int i; 203 204 for (i = 0; i < 10000; i++) { 205 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 206 S_COMMAND_IN_PROGRESS) == 0) 207 break; 208 DELAY(10); 209 } 210 } 211 212 static inline void 213 ep_discard_rxtop(bus_space_tag_t iot, bus_space_handle_t ioh) 214 { 215 int i; 216 217 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 218 219 /* 220 * Spin for about 1 msec, to avoid forcing a DELAY() between 221 * every received packet (adding latency and limiting pkt-recv rate). 222 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 223 * is about right. 224 */ 225 for (i = 0; i < 8000; i++) { 226 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 227 S_COMMAND_IN_PROGRESS) == 0) 228 return; 229 } 230 231 /* not fast enough, do DELAY()s */ 232 ep_finish_reset(iot, ioh); 233 } 234 235 /* 236 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset. 237 */ 238 static __inline int 239 ep_w1_reg(struct ep_softc *sc, int reg) 240 { 241 switch (sc->ep_chipset) { 242 case EP_CHIPSET_ROADRUNNER: 243 switch (reg) { 244 case EP_W1_FREE_TX: 245 case EP_W1_RUNNER_RDCTL: 246 case EP_W1_RUNNER_WRCTL: 247 return (reg); 248 } 249 return (reg + 0x10); 250 } 251 return (reg); 252 } 253 254 /* 255 * Back-end attach and configure. 256 */ 257 void 258 epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr) 259 { 260 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 261 bus_space_tag_t iot = sc->sc_iot; 262 bus_space_handle_t ioh = sc->sc_ioh; 263 u_int16_t i; 264 265 sc->ep_chipset = chipset; 266 267 /* 268 * We could have been groveling around in other register 269 * windows in the front-end; make sure we're in window 0 270 * to read the EEPROM. 271 */ 272 GO_WINDOW(0); 273 274 if (enaddr == NULL) { 275 /* 276 * Read the station address from the eeprom. 277 */ 278 for (i = 0; i < 3; i++) { 279 u_int16_t x = ep_read_eeprom(sc, i); 280 281 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8; 282 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x; 283 } 284 } else { 285 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 286 } 287 288 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 289 if (sc->ep_flags & EP_FLAGS_MII) 290 printf("\n"); 291 else 292 printf(", "); 293 294 /* 295 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte 296 * packets. Commands only take an 11-bit parameter, and 11 bits 297 * isn't enough to hold a full-size packet length. 298 * Commands to these cards implicitly upshift a packet size 299 * or threshold by 2 bits. 300 * To detect cards with large-packet support, we probe by setting 301 * the transmit threshold register, then change windows and 302 * read back the threshold register directly, and see if the 303 * threshold value was shifted or not. 304 */ 305 bus_space_write_2(iot, ioh, EP_COMMAND, 306 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 307 GO_WINDOW(5); 308 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 309 GO_WINDOW(1); 310 switch (i) { 311 case EP_LARGEWIN_PROBE: 312 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 313 sc->txashift = 0; 314 break; 315 316 case (EP_LARGEWIN_PROBE << 2): 317 sc->txashift = 2; 318 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */ 319 break; 320 321 default: 322 printf("wrote %x to TX_AVAIL_THRESH, read back %x. " 323 "Interface disabled\n", EP_THRESH_DISABLE, (int) i); 324 return; 325 } 326 327 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc); 328 329 /* 330 * Ensure Tx-available interrupts are enabled for 331 * start the interface. 332 * XXX should be in epinit()? 333 */ 334 bus_space_write_2(iot, ioh, EP_COMMAND, 335 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 336 337 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 338 ifp->if_softc = sc; 339 ifp->if_start = epstart; 340 ifp->if_ioctl = epioctl; 341 ifp->if_watchdog = epwatchdog; 342 ifp->if_flags = 343 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 344 /* 64 packets are around 100ms on 10Mbps */ 345 IFQ_SET_MAXLEN(&ifp->if_snd, 64); 346 IFQ_SET_READY(&ifp->if_snd); 347 348 if_attach(ifp); 349 ether_ifattach(ifp); 350 351 /* 352 * Finish configuration: 353 * determine chipset if the front-end couldn't do so, 354 * show board details, set media. 355 */ 356 357 GO_WINDOW(0); 358 359 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 360 ep_media_status); 361 sc->sc_mii.mii_ifp = ifp; 362 sc->sc_mii.mii_readreg = ep_mii_readreg; 363 sc->sc_mii.mii_writereg = ep_mii_writereg; 364 sc->sc_mii.mii_statchg = ep_statchg; 365 366 /* 367 * If we've got an indirect (ISA, PCMCIA?) board, the chipset 368 * is unknown. If the board has large-packet support, it's a 369 * Vortex/Boomerang, otherwise it's a 3c509. 370 * XXX use eeprom capability word instead? 371 */ 372 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN && sc->txashift) { 373 printf("warning: unknown chipset, possibly 3c515?\n"); 374 #ifdef notyet 375 sc->sc_chipset = EP_CHIPSET_VORTEX; 376 #endif /* notyet */ 377 } 378 379 /* 380 * Ascertain which media types are present and inform ifmedia. 381 */ 382 switch (sc->ep_chipset) { 383 case EP_CHIPSET_ROADRUNNER: 384 if (sc->ep_flags & EP_FLAGS_MII) { 385 ep_roadrunner_mii_enable(sc); 386 GO_WINDOW(0); 387 } 388 /* FALLTHROUGH */ 389 390 case EP_CHIPSET_BOOMERANG: 391 /* 392 * If the device has MII, probe it. We won't be using 393 * any `native' media in this case, only PHYs. If 394 * we don't, just treat the Boomerang like the Vortex. 395 */ 396 if (sc->ep_flags & EP_FLAGS_MII) { 397 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 398 MII_PHY_ANY, MII_OFFSET_ANY, 0); 399 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 400 ifmedia_add(&sc->sc_mii.mii_media, 401 IFM_ETHER|IFM_NONE, 0, NULL); 402 ifmedia_set(&sc->sc_mii.mii_media, 403 IFM_ETHER|IFM_NONE); 404 } else { 405 ifmedia_set(&sc->sc_mii.mii_media, 406 IFM_ETHER|IFM_AUTO); 407 } 408 break; 409 } 410 /* FALLTHROUGH */ 411 412 /* on a direct bus, the attach routine can tell, but check anyway. */ 413 case EP_CHIPSET_VORTEX: 414 case EP_CHIPSET_BOOMERANG2: 415 ep_vortex_probemedia(sc); 416 break; 417 418 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */ 419 case EP_CHIPSET_3C509: 420 default: 421 ep_isa_probemedia(sc); 422 break; 423 } 424 425 GO_WINDOW(1); /* Window 1 is operating window */ 426 427 sc->tx_start_thresh = 20; /* probably a good starting point. */ 428 429 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 430 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 431 } 432 433 int 434 ep_detach(struct device *self) 435 { 436 struct ep_softc *sc = (struct ep_softc *)self; 437 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 438 439 if (sc->ep_flags & EP_FLAGS_MII) 440 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 441 442 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 443 444 ether_ifdetach(ifp); 445 if_detach(ifp); 446 447 return (0); 448 } 449 450 /* 451 * Find supported media on 3c509-generation hardware that doesn't have 452 * a "reset_options" register in window 3. 453 * Use the config_cntrl register in window 0 instead. 454 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 455 * that implement CONFIG_CTRL. We don't have a good way to set the 456 * default active medium; punt to ifconfig instead. 457 * 458 * XXX what about 3c515, pcmcia 10/100? 459 */ 460 void 461 ep_isa_probemedia(struct ep_softc *sc) 462 { 463 bus_space_tag_t iot = sc->sc_iot; 464 bus_space_handle_t ioh = sc->sc_ioh; 465 struct ifmedia *ifm = &sc->sc_mii.mii_media; 466 int conn, i; 467 u_int16_t ep_w0_config, port; 468 469 conn = 0; 470 GO_WINDOW(0); 471 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 472 for (i = 0; i < nitems(ep_isa_media); i++) { 473 struct ep_media * epm = ep_isa_media + i; 474 475 if ((ep_w0_config & epm->epm_eeprom_data) != 0) { 476 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 477 if (conn) 478 printf("/"); 479 printf("%s", epm->epm_name); 480 conn |= epm->epm_conn; 481 } 482 } 483 sc->ep_connectors = conn; 484 485 /* get default medium from EEPROM */ 486 if (epbusyeeprom(sc)) 487 return; /* XXX why is eeprom busy? */ 488 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 489 READ_EEPROM | EEPROM_ADDR_CFG); 490 if (epbusyeeprom(sc)) 491 return; /* XXX why is eeprom busy? */ 492 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 493 port = port >> 14; 494 495 printf(" (default %s)\n", ep_vortex_media[port].epm_name); 496 497 /* tell ifconfig what currently-active media is. */ 498 ifmedia_set(ifm, ep_default_to_media[port]); 499 500 /* XXX autoselect not yet implemented */ 501 } 502 503 504 /* 505 * Find media present on large-packet-capable elink3 devices. 506 * Show onboard configuration of large-packet-capable elink3 devices 507 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 508 * Use media and card-version info in window 3 instead. 509 * 510 * XXX how much of this works with 3c515, pcmcia 10/100? 511 */ 512 void 513 ep_vortex_probemedia(struct ep_softc *sc) 514 { 515 bus_space_tag_t iot = sc->sc_iot; 516 bus_space_handle_t ioh = sc->sc_ioh; 517 struct ifmedia *ifm = &sc->sc_mii.mii_media; 518 u_int config1, conn; 519 int reset_options; 520 int default_media; /* 3-bit encoding of default (EEPROM) media */ 521 int autoselect; /* boolean: should default to autoselect */ 522 const char *medium_name; 523 register int i; 524 525 GO_WINDOW(3); 526 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 527 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 528 GO_WINDOW(0); 529 530 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 531 autoselect = (config1 & CONFIG_AUTOSELECT) >> CONFIG_AUTOSELECT_SHIFT; 532 533 /* set available media options */ 534 conn = 0; 535 for (i = 0; i < nitems(ep_vortex_media); i++) { 536 const struct ep_media *epm = ep_vortex_media + i; 537 538 if ((reset_options & epm->epm_eeprom_data) != 0) { 539 if (conn) 540 printf("/"); 541 printf("%s", epm->epm_name); 542 conn |= epm->epm_conn; 543 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 544 } 545 } 546 547 sc->ep_connectors = conn; 548 549 /* Show eeprom's idea of default media. */ 550 medium_name = (default_media > nitems(ep_vortex_media) - 1) 551 ? "(unknown/impossible media)" 552 : ep_vortex_media[default_media].epm_name; 553 printf(" default %s%s", 554 medium_name, (autoselect) ? "/autoselect" : ""); 555 /* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/ 556 557 #ifdef notyet 558 /* 559 * Set default: either the active interface the card 560 * reads from the EEPROM, or if autoselect is true, 561 * whatever we find is actually connected. 562 * 563 * XXX autoselect not yet implemented. 564 */ 565 #endif /* notyet */ 566 567 /* tell ifconfig what currently-active media is. */ 568 ifmedia_set(ifm, ep_default_to_media[default_media]); 569 } 570 571 /* 572 * Bring device up. 573 * 574 * The order in here seems important. Otherwise we may not receive 575 * interrupts. ?! 576 */ 577 void 578 epinit(struct ep_softc *sc) 579 { 580 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 581 bus_space_tag_t iot = sc->sc_iot; 582 bus_space_handle_t ioh = sc->sc_ioh; 583 int i; 584 585 /* make sure any pending reset has completed before touching board */ 586 ep_finish_reset(iot, ioh); 587 588 /* cancel any pending I/O */ 589 epstop(sc); 590 591 if (sc->bustype != EP_BUS_PCI) { 592 GO_WINDOW(0); 593 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 594 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 595 } 596 597 if (sc->bustype == EP_BUS_PCMCIA) { 598 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 599 } 600 601 GO_WINDOW(2); 602 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 603 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 604 sc->sc_arpcom.ac_enaddr[i]); 605 606 if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA) 607 /* 608 * Reset the station-address receive filter. 609 * A bug workaround for busmastering (Vortex, Demon) cards. 610 */ 611 for (i = 0; i < 6; i++) 612 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 613 614 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 615 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 616 617 GO_WINDOW(1); /* Window 1 is operating window */ 618 for (i = 0; i < 31; i++) 619 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 620 621 /* Set threshold for for Tx-space available interrupt. */ 622 bus_space_write_2(iot, ioh, EP_COMMAND, 623 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 624 625 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 626 /* Enable options in the PCMCIA LAN COR register, via 627 * RoadRunner Window 1. 628 * 629 * XXX MAGIC CONSTANTS! 630 */ 631 u_int16_t cor; 632 633 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 634 635 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 636 bus_space_write_2(iot, ioh, 0, cor); 637 638 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 639 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 640 641 if (sc->ep_flags & EP_FLAGS_MII) { 642 ep_roadrunner_mii_enable(sc); 643 GO_WINDOW(1); 644 } 645 } 646 647 /* Enable interrupts. */ 648 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | 649 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 650 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | 651 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 652 653 /* 654 * Attempt to get rid of any stray interrupts that occurred during 655 * configuration. On the i386 this isn't possible because one may 656 * already be queued. However, a single stray interrupt is 657 * unimportant. 658 */ 659 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 660 661 epsetfilter(sc); 662 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 663 664 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 665 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 666 667 epmbuffill(sc); 668 669 /* Interface is now `running', with no output active. */ 670 ifp->if_flags |= IFF_RUNNING; 671 ifp->if_flags &= ~IFF_OACTIVE; 672 673 /* Attempt to start output, if any. */ 674 epstart(ifp); 675 } 676 677 /* 678 * Set multicast receive filter. 679 * elink3 hardware has no selective multicast filter in hardware. 680 * Enable reception of all multicasts and filter in software. 681 */ 682 void 683 epsetfilter(struct ep_softc *sc) 684 { 685 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 686 687 GO_WINDOW(1); /* Window 1 is operating window */ 688 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 689 FIL_INDIVIDUAL | FIL_BRDCST | 690 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 691 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 692 } 693 694 695 int 696 ep_media_change(struct ifnet *ifp) 697 { 698 register struct ep_softc *sc = ifp->if_softc; 699 700 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 701 } 702 703 /* 704 * Reset and enable the MII on the RoadRunner. 705 */ 706 void 707 ep_roadrunner_mii_enable(struct ep_softc *sc) 708 { 709 bus_space_tag_t iot = sc->sc_iot; 710 bus_space_handle_t ioh = sc->sc_ioh; 711 712 GO_WINDOW(3); 713 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 714 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 715 delay(1000); 716 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 717 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII); 718 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 719 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 720 delay(1000); 721 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 722 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 723 } 724 725 /* 726 * Set active media to a specific given EPMEDIA_<> value. 727 * For vortex/demon/boomerang cards, update media field in w3_internal_config, 728 * and power on selected transceiver. 729 * For 3c509-generation cards (3c509/3c579/3c589/3c509B), 730 * update media field in w0_address_config, and power on selected xcvr. 731 */ 732 int 733 epsetmedia(struct ep_softc *sc, int medium) 734 { 735 bus_space_tag_t iot = sc->sc_iot; 736 bus_space_handle_t ioh = sc->sc_ioh; 737 int w4_media; 738 int config0, config1; 739 740 /* 741 * you can `ifconfig (link0|-link0) ep0' to get the following 742 * behaviour: 743 * -link0 disable AUI/UTP. enable BNC. 744 * link0 disable BNC. enable AUI. 745 * link1 if the card has a UTP connector, and link0 is 746 * set too, then you get the UTP port. 747 */ 748 749 /* 750 * First, change the media-control bits in EP_W4_MEDIA_TYPE. 751 */ 752 753 /* Turn everything off. First turn off linkbeat and UTP. */ 754 GO_WINDOW(4); 755 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 756 w4_media = w4_media & ~(ENABLE_UTP|SQE_ENABLE); 757 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media); 758 759 /* Turn off coax */ 760 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 761 delay(1000); 762 763 /* If the device has MII, select it, and then tell the 764 * PHY which media to use. 765 */ 766 if (sc->ep_flags & EP_FLAGS_MII) { 767 GO_WINDOW(3); 768 769 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 770 int resopt; 771 772 resopt = bus_space_read_2(iot, ioh, 773 EP_W3_RESET_OPTIONS); 774 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 775 resopt | EP_RUNNER_ENABLE_MII); 776 } 777 778 config0 = (u_int)bus_space_read_2(iot, ioh, 779 EP_W3_INTERNAL_CONFIG); 780 config1 = (u_int)bus_space_read_2(iot, ioh, 781 EP_W3_INTERNAL_CONFIG + 2); 782 783 config1 = config1 & ~CONFIG_MEDIAMASK; 784 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 785 786 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 787 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 788 GO_WINDOW(1); /* back to operating window */ 789 790 mii_mediachg(&sc->sc_mii); 791 return (0); 792 } 793 794 /* 795 * Now turn on the selected media/transceiver. 796 */ 797 GO_WINDOW(4); 798 switch (medium) { 799 case EPMEDIA_10BASE_T: 800 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP | 801 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0))); 802 break; 803 804 case EPMEDIA_10BASE_2: 805 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 806 DELAY(1000); /* 50ms not enough? */ 807 break; 808 809 /* XXX following only for new-generation cards */ 810 case EPMEDIA_100BASE_TX: 811 case EPMEDIA_100BASE_FX: 812 case EPMEDIA_100BASE_T4: /* XXX check documentation */ 813 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 814 w4_media | LINKBEAT_ENABLE); 815 DELAY(1000); /* not strictly necessary? */ 816 break; 817 818 case EPMEDIA_AUI: 819 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 820 w4_media | SQE_ENABLE); 821 DELAY(1000); /* not strictly necessary? */ 822 break; 823 case EPMEDIA_MII: 824 break; 825 default: 826 #if defined(EP_DEBUG) 827 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium); 828 #endif 829 break; 830 831 } 832 833 /* 834 * Tell the chip which PHY [sic] to use. 835 */ 836 switch (sc->ep_chipset) { 837 case EP_CHIPSET_VORTEX: 838 case EP_CHIPSET_BOOMERANG2: 839 GO_WINDOW(3); 840 config0 = (u_int)bus_space_read_2(iot, ioh, 841 EP_W3_INTERNAL_CONFIG); 842 config1 = (u_int)bus_space_read_2(iot, ioh, 843 EP_W3_INTERNAL_CONFIG + 2); 844 845 #if defined(EP_DEBUG) 846 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n", 847 sc->sc_dev.dv_xname, config0, config1); 848 #endif 849 config1 = config1 & ~CONFIG_MEDIAMASK; 850 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT); 851 852 #if defined(EP_DEBUG) 853 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n", 854 sc->sc_dev.dv_xname, medium, config1); 855 #endif 856 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 857 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 858 break; 859 860 default: 861 GO_WINDOW(0); 862 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 863 config0 &= 0x3fff; 864 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 865 config0 | (medium << 14)); 866 DELAY(1000); 867 break; 868 } 869 870 GO_WINDOW(1); /* Window 1 is operating window */ 871 return (0); 872 } 873 874 875 /* 876 * Get currently-selected media from card. 877 * (if_media callback, may be called before interface is brought up). 878 */ 879 void 880 ep_media_status(struct ifnet *ifp, struct ifmediareq *req) 881 { 882 register struct ep_softc *sc = ifp->if_softc; 883 bus_space_tag_t iot = sc->sc_iot; 884 bus_space_handle_t ioh = sc->sc_ioh; 885 u_int config1; 886 u_int ep_mediastatus; 887 888 /* 889 * If we have MII, go ask the PHY what's going on. 890 */ 891 if (sc->ep_flags & EP_FLAGS_MII) { 892 mii_pollstat(&sc->sc_mii); 893 req->ifm_active = sc->sc_mii.mii_media_active; 894 req->ifm_status = sc->sc_mii.mii_media_status; 895 return; 896 } 897 898 /* XXX read from softc when we start autosensing media */ 899 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 900 901 switch (sc->ep_chipset) { 902 case EP_CHIPSET_VORTEX: 903 case EP_CHIPSET_BOOMERANG: 904 GO_WINDOW(3); 905 delay(5000); 906 907 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 908 GO_WINDOW(1); 909 910 config1 = 911 (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 912 req->ifm_active = ep_default_to_media[config1]; 913 914 /* XXX check full-duplex bits? */ 915 916 GO_WINDOW(4); 917 req->ifm_status = IFM_AVALID; /* XXX */ 918 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 919 if (ep_mediastatus & LINKBEAT_DETECT) 920 req->ifm_status |= IFM_ACTIVE; /* XXX automedia */ 921 922 break; 923 924 case EP_CHIPSET_UNKNOWN: 925 case EP_CHIPSET_3C509: 926 req->ifm_status = 0; /* XXX */ 927 break; 928 929 default: 930 printf("%s: media_status on unknown chipset 0x%x\n", 931 ifp->if_xname, sc->ep_chipset); 932 break; 933 } 934 935 /* XXX look for softc heartbeat for other chips or media */ 936 937 GO_WINDOW(1); 938 return; 939 } 940 941 942 943 /* 944 * Start outputting on the interface. 945 * Always called as splnet(). 946 */ 947 void 948 epstart(struct ifnet *ifp) 949 { 950 register struct ep_softc *sc = ifp->if_softc; 951 bus_space_tag_t iot = sc->sc_iot; 952 bus_space_handle_t ioh = sc->sc_ioh; 953 struct mbuf *m, *m0; 954 caddr_t data; 955 int sh, len, pad, txreg; 956 957 /* Don't transmit if interface is busy or not running */ 958 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 959 return; 960 961 startagain: 962 /* Sneak a peek at the next packet */ 963 IFQ_POLL(&ifp->if_snd, m0); 964 if (m0 == NULL) 965 return; 966 967 /* We need to use m->m_pkthdr.len, so require the header */ 968 if ((m0->m_flags & M_PKTHDR) == 0) 969 panic("epstart: no header mbuf"); 970 len = m0->m_pkthdr.len; 971 972 pad = (4 - len) & 3; 973 974 /* 975 * The 3c509 automatically pads short packets to minimum ethernet 976 * length, but we drop packets that are too large. Perhaps we should 977 * truncate them instead? 978 */ 979 if (len + pad > ETHER_MAX_LEN) { 980 /* packet is obviously too large: toss it */ 981 ++ifp->if_oerrors; 982 IFQ_DEQUEUE(&ifp->if_snd, m0); 983 m_freem(m0); 984 goto readcheck; 985 } 986 987 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 988 len + pad + 4) { 989 bus_space_write_2(iot, ioh, EP_COMMAND, 990 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift)); 991 /* not enough room in FIFO */ 992 ifp->if_flags |= IFF_OACTIVE; 993 return; 994 } else { 995 bus_space_write_2(iot, ioh, EP_COMMAND, 996 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE); 997 } 998 999 IFQ_DEQUEUE(&ifp->if_snd, m0); 1000 if (m0 == NULL) 1001 return; 1002 1003 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1004 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/)); 1005 1006 #if NBPFILTER > 0 1007 if (ifp->if_bpf) 1008 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1009 #endif 1010 1011 /* 1012 * Do the output at splhigh() so that an interrupt from another device 1013 * won't cause a FIFO underrun. 1014 */ 1015 sh = splhigh(); 1016 1017 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1018 1019 bus_space_write_2(iot, ioh, txreg, len); 1020 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1021 if (EP_IS_BUS_32(sc->bustype)) { 1022 for (m = m0; m; ) { 1023 data = mtod(m, u_int8_t *); 1024 if (m->m_len > 3 && ALIGNED_POINTER(data, uint32_t)) { 1025 bus_space_write_raw_multi_4(iot, ioh, txreg, 1026 data, m->m_len & ~3); 1027 if (m->m_len & 3) 1028 bus_space_write_multi_1(iot, ioh, txreg, 1029 data + (m->m_len & ~3), 1030 m->m_len & 3); 1031 } else 1032 bus_space_write_multi_1(iot, ioh, txreg, 1033 data, m->m_len); 1034 MFREE(m, m0); 1035 m = m0; 1036 } 1037 } else { 1038 for (m = m0; m; ) { 1039 data = mtod(m, u_int8_t *); 1040 if (m->m_len > 1 && ALIGNED_POINTER(data, uint16_t)) { 1041 bus_space_write_raw_multi_2(iot, ioh, txreg, 1042 data, m->m_len & ~1); 1043 if (m->m_len & 1) 1044 bus_space_write_1(iot, ioh, txreg, 1045 *(data + m->m_len - 1)); 1046 } else 1047 bus_space_write_multi_1(iot, ioh, txreg, 1048 data, m->m_len); 1049 MFREE(m, m0); 1050 m = m0; 1051 } 1052 } 1053 while (pad--) 1054 bus_space_write_1(iot, ioh, txreg, 0); 1055 1056 splx(sh); 1057 1058 ++ifp->if_opackets; 1059 1060 readcheck: 1061 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1062 ERR_INCOMPLETE) == 0) { 1063 /* We received a complete packet. */ 1064 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1065 1066 if ((status & S_INTR_LATCH) == 0) { 1067 /* 1068 * No interrupt, read the packet and continue 1069 * Is this supposed to happen? Is my motherboard 1070 * completely busted? 1071 */ 1072 epread(sc); 1073 } else 1074 /* Got an interrupt, return to get it serviced. */ 1075 return; 1076 } else { 1077 /* Check if we are stuck and reset [see XXX comment] */ 1078 if (epstatus(sc)) { 1079 #ifdef EP_DEBUG 1080 if (ifp->if_flags & IFF_DEBUG) 1081 printf("%s: adapter reset\n", 1082 sc->sc_dev.dv_xname); 1083 #endif 1084 epreset(sc); 1085 } 1086 } 1087 1088 goto startagain; 1089 } 1090 1091 1092 /* 1093 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1094 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1095 * We detect this situation and we reset the adapter. 1096 * It happens at times when there is a lot of broadcast traffic 1097 * on the cable (once in a blue moon). 1098 */ 1099 int 1100 epstatus(struct ep_softc *sc) 1101 { 1102 bus_space_tag_t iot = sc->sc_iot; 1103 bus_space_handle_t ioh = sc->sc_ioh; 1104 u_int16_t fifost; 1105 1106 /* 1107 * Check the FIFO status and act accordingly 1108 */ 1109 GO_WINDOW(4); 1110 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1111 GO_WINDOW(1); 1112 1113 if (fifost & FIFOS_RX_UNDERRUN) { 1114 #ifdef EP_DEBUG 1115 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1116 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1117 #endif 1118 epreset(sc); 1119 return 0; 1120 } 1121 1122 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1123 #ifdef EP_DEBUG 1124 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1125 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1126 #endif 1127 return 1; 1128 } 1129 1130 if (fifost & FIFOS_RX_OVERRUN) { 1131 #ifdef EP_DEBUG 1132 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1133 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1134 #endif 1135 return 1; 1136 } 1137 1138 if (fifost & FIFOS_TX_OVERRUN) { 1139 #ifdef EP_DEBUG 1140 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1141 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1142 #endif 1143 epreset(sc); 1144 return 0; 1145 } 1146 1147 return 0; 1148 } 1149 1150 1151 void 1152 eptxstat(struct ep_softc *sc) 1153 { 1154 bus_space_tag_t iot = sc->sc_iot; 1155 bus_space_handle_t ioh = sc->sc_ioh; 1156 int i; 1157 1158 /* 1159 * We need to read+write TX_STATUS until we get a 0 status 1160 * in order to turn off the interrupt flag. 1161 */ 1162 while ((i = bus_space_read_1(iot, ioh, 1163 ep_w1_reg(sc, EP_W1_TX_STATUS))) & TXS_COMPLETE) { 1164 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1165 0x0); 1166 1167 if (i & TXS_JABBER) { 1168 ++sc->sc_arpcom.ac_if.if_oerrors; 1169 #ifdef EP_DEBUG 1170 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1171 printf("%s: jabber (%x)\n", 1172 sc->sc_dev.dv_xname, i); 1173 #endif 1174 epreset(sc); 1175 } else if (i & TXS_UNDERRUN) { 1176 ++sc->sc_arpcom.ac_if.if_oerrors; 1177 #ifdef EP_DEBUG 1178 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1179 printf("%s: fifo underrun (%x) @%d\n", 1180 sc->sc_dev.dv_xname, i, 1181 sc->tx_start_thresh); 1182 #endif 1183 if (sc->tx_succ_ok < 100) 1184 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1185 sc->tx_start_thresh + 20); 1186 sc->tx_succ_ok = 0; 1187 epreset(sc); 1188 } else if (i & TXS_MAX_COLLISION) { 1189 ++sc->sc_arpcom.ac_if.if_collisions; 1190 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1191 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1192 } else 1193 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1194 } 1195 } 1196 1197 int 1198 epintr(void *arg) 1199 { 1200 register struct ep_softc *sc = arg; 1201 bus_space_tag_t iot = sc->sc_iot; 1202 bus_space_handle_t ioh = sc->sc_ioh; 1203 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1204 u_int16_t status; 1205 int ret = 0; 1206 1207 for (;;) { 1208 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1209 1210 status = bus_space_read_2(iot, ioh, EP_STATUS); 1211 1212 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1213 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) 1214 break; 1215 1216 ret = 1; 1217 1218 /* 1219 * Acknowledge any interrupts. It's important that we do this 1220 * first, since there would otherwise be a race condition. 1221 * Due to the i386 interrupt queueing, we may get spurious 1222 * interrupts occasionally. 1223 */ 1224 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status); 1225 1226 if (status & S_RX_COMPLETE) 1227 epread(sc); 1228 if (status & S_TX_AVAIL) { 1229 ifp->if_flags &= ~IFF_OACTIVE; 1230 epstart(ifp); 1231 } 1232 if (status & S_CARD_FAILURE) { 1233 epreset(sc); 1234 return (1); 1235 } 1236 if (status & S_TX_COMPLETE) { 1237 eptxstat(sc); 1238 epstart(ifp); 1239 } 1240 } 1241 1242 /* no more interrupts */ 1243 return (ret); 1244 } 1245 1246 void 1247 epread(struct ep_softc *sc) 1248 { 1249 bus_space_tag_t iot = sc->sc_iot; 1250 bus_space_handle_t ioh = sc->sc_ioh; 1251 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1252 struct mbuf *m; 1253 int len; 1254 1255 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1256 1257 again: 1258 #ifdef EP_DEBUG 1259 if (ifp->if_flags & IFF_DEBUG) { 1260 int err = len & ERR_MASK; 1261 char *s = NULL; 1262 1263 if (len & ERR_INCOMPLETE) 1264 s = "incomplete packet"; 1265 else if (err == ERR_OVERRUN) 1266 s = "packet overrun"; 1267 else if (err == ERR_RUNT) 1268 s = "runt packet"; 1269 else if (err == ERR_ALIGNMENT) 1270 s = "bad alignment"; 1271 else if (err == ERR_CRC) 1272 s = "bad crc"; 1273 else if (err == ERR_OVERSIZE) 1274 s = "oversized packet"; 1275 else if (err == ERR_DRIBBLE) 1276 s = "dribble bits"; 1277 1278 if (s) 1279 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1280 } 1281 #endif 1282 1283 if (len & ERR_INCOMPLETE) 1284 return; 1285 1286 if (len & ERR_RX) { 1287 ++ifp->if_ierrors; 1288 goto abort; 1289 } 1290 1291 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1292 1293 /* Pull packet off interface. */ 1294 m = epget(sc, len); 1295 if (m == NULL) { 1296 ifp->if_ierrors++; 1297 goto abort; 1298 } 1299 1300 ++ifp->if_ipackets; 1301 1302 #if NBPFILTER > 0 1303 /* 1304 * Check if there's a BPF listener on this interface. 1305 * If so, hand off the raw packet to BPF. 1306 */ 1307 if (ifp->if_bpf) 1308 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1309 #endif 1310 1311 ether_input_mbuf(ifp, m); 1312 1313 /* 1314 * In periods of high traffic we can actually receive enough 1315 * packets so that the fifo overrun bit will be set at this point, 1316 * even though we just read a packet. In this case we 1317 * are not going to receive any more interrupts. We check for 1318 * this condition and read again until the fifo is not full. 1319 * We could simplify this test by not using epstatus(), but 1320 * rechecking the RX_STATUS register directly. This test could 1321 * result in unnecessary looping in cases where there is a new 1322 * packet but the fifo is not full, but it will not fix the 1323 * stuck behavior. 1324 * 1325 * Even with this improvement, we still get packet overrun errors 1326 * which are hurting performance. Maybe when I get some more time 1327 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1328 */ 1329 if (epstatus(sc)) { 1330 len = bus_space_read_2(iot, ioh, 1331 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1332 /* Check if we are stuck and reset [see XXX comment] */ 1333 if (len & ERR_INCOMPLETE) { 1334 #ifdef EP_DEBUG 1335 if (ifp->if_flags & IFF_DEBUG) 1336 printf("%s: adapter reset\n", 1337 sc->sc_dev.dv_xname); 1338 #endif 1339 epreset(sc); 1340 return; 1341 } 1342 goto again; 1343 } 1344 1345 return; 1346 1347 abort: 1348 ep_discard_rxtop(iot, ioh); 1349 } 1350 1351 struct mbuf * 1352 epget(struct ep_softc *sc, int totlen) 1353 { 1354 bus_space_tag_t iot = sc->sc_iot; 1355 bus_space_handle_t ioh = sc->sc_ioh; 1356 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1357 struct mbuf *m; 1358 caddr_t data; 1359 int len, pad, off, sh, rxreg; 1360 1361 splassert(IPL_NET); 1362 1363 m = sc->mb[sc->next_mb]; 1364 sc->mb[sc->next_mb] = NULL; 1365 if (m == NULL) { 1366 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1367 /* If the queue is no longer full, refill. */ 1368 if (!timeout_pending(&sc->sc_epmbuffill_tmo)) 1369 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1370 } 1371 if (!m) 1372 return (NULL); 1373 1374 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1375 1376 len = MCLBYTES; 1377 m->m_pkthdr.rcvif = ifp; 1378 m->m_pkthdr.len = totlen; 1379 m->m_len = totlen; 1380 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1381 m->m_data += pad; 1382 len -= pad; 1383 1384 /* 1385 * We read the packet at splhigh() so that an interrupt from another 1386 * device doesn't cause the card's buffer to overflow while we're 1387 * reading it. We may still lose packets at other times. 1388 */ 1389 sh = splhigh(); 1390 1391 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1392 1393 off = 0; 1394 while (totlen) { 1395 len = min(totlen, M_TRAILINGSPACE(m)); 1396 if (len == 0) 1397 panic("ep_get: packet does not fit in MCLBYTES"); 1398 1399 data = mtod(m, u_int8_t *); 1400 if (EP_IS_BUS_32(sc->bustype)) 1401 pad = 4 - ((u_long)(data + off) & 0x3); 1402 else 1403 pad = (u_long)(data + off) & 0x1; 1404 1405 if (pad) { 1406 if (pad < len) 1407 pad = len; 1408 bus_space_read_multi_1(iot, ioh, rxreg, 1409 data + off, pad); 1410 len = pad; 1411 } else if (EP_IS_BUS_32(sc->bustype) && len > 3 && 1412 ALIGNED_POINTER(data, uint32_t)) { 1413 len &= ~3; 1414 bus_space_read_raw_multi_4(iot, ioh, rxreg, 1415 data + off, len); 1416 } else if (len > 1 && ALIGNED_POINTER(data, uint16_t)) { 1417 len &= ~1; 1418 bus_space_read_raw_multi_2(iot, ioh, rxreg, 1419 data + off, len); 1420 } else 1421 bus_space_read_multi_1(iot, ioh, rxreg, 1422 data + off, len); 1423 1424 off += len; 1425 totlen -= len; 1426 } 1427 1428 ep_discard_rxtop(iot, ioh); 1429 1430 splx(sh); 1431 1432 return m; 1433 } 1434 1435 int 1436 epioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1437 { 1438 struct ep_softc *sc = ifp->if_softc; 1439 struct ifaddr *ifa = (struct ifaddr *)data; 1440 struct ifreq *ifr = (struct ifreq *)data; 1441 int s, error = 0; 1442 1443 s = splnet(); 1444 1445 switch (cmd) { 1446 case SIOCSIFADDR: 1447 ifp->if_flags |= IFF_UP; 1448 1449 switch (ifa->ifa_addr->sa_family) { 1450 #ifdef INET 1451 case AF_INET: 1452 epinit(sc); 1453 arp_ifinit(&sc->sc_arpcom, ifa); 1454 break; 1455 #endif 1456 default: 1457 epinit(sc); 1458 break; 1459 } 1460 break; 1461 1462 case SIOCSIFMEDIA: 1463 case SIOCGIFMEDIA: 1464 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1465 break; 1466 1467 case SIOCSIFFLAGS: 1468 if ((ifp->if_flags & IFF_UP) == 0 && 1469 (ifp->if_flags & IFF_RUNNING) != 0) { 1470 /* 1471 * If interface is marked down and it is running, then 1472 * stop it. 1473 */ 1474 epstop(sc); 1475 ifp->if_flags &= ~IFF_RUNNING; 1476 } else if ((ifp->if_flags & IFF_UP) != 0 && 1477 (ifp->if_flags & IFF_RUNNING) == 0) { 1478 /* 1479 * If interface is marked up and it is stopped, then 1480 * start it. 1481 */ 1482 epinit(sc); 1483 } else if ((ifp->if_flags & IFF_UP) != 0) { 1484 /* 1485 * Reset the interface to pick up changes in any other 1486 * flags that affect hardware registers. 1487 */ 1488 epinit(sc); 1489 } 1490 break; 1491 1492 default: 1493 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1494 } 1495 1496 if (error == ENETRESET) { 1497 if (ifp->if_flags & IFF_RUNNING) 1498 epreset(sc); 1499 error = 0; 1500 } 1501 1502 splx(s); 1503 return (error); 1504 } 1505 1506 void 1507 epreset(struct ep_softc *sc) 1508 { 1509 int s; 1510 1511 s = splnet(); 1512 epinit(sc); 1513 splx(s); 1514 } 1515 1516 void 1517 epwatchdog(struct ifnet *ifp) 1518 { 1519 struct ep_softc *sc = ifp->if_softc; 1520 1521 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1522 ++sc->sc_arpcom.ac_if.if_oerrors; 1523 1524 epreset(sc); 1525 } 1526 1527 void 1528 epstop(struct ep_softc *sc) 1529 { 1530 bus_space_tag_t iot = sc->sc_iot; 1531 bus_space_handle_t ioh = sc->sc_ioh; 1532 1533 if (sc->ep_flags & EP_FLAGS_MII) { 1534 mii_down(&sc->sc_mii); 1535 } 1536 1537 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1538 /* Clear the FIFO buffer count, thus halting 1539 * any currently-running transactions. 1540 */ 1541 GO_WINDOW(1); /* sanity */ 1542 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1543 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1544 } 1545 1546 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1547 ep_discard_rxtop(iot, ioh); 1548 1549 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1550 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1551 1552 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 1553 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 1554 1555 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1556 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1557 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1558 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1559 1560 epmbufempty(sc); 1561 } 1562 1563 /* 1564 * We get eeprom data from the id_port given an offset into the 1565 * eeprom. Basically; after the ID_sequence is sent to all of 1566 * the cards; they enter the ID_CMD state where they will accept 1567 * command requests. 0x80-0xbf loads the eeprom data. We then 1568 * read the port 16 times and with every read; the cards check 1569 * for contention (ie: if one card writes a 0 bit and another 1570 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1571 * each card compares the data on the bus; if there is a difference 1572 * then that card goes into ID_WAIT state again). In the meantime; 1573 * one bit of data is returned in the AX register which is conveniently 1574 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1575 * bit of data with each read. 1576 * 1577 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1578 */ 1579 u_int16_t 1580 epreadeeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int offset) 1581 { 1582 u_int16_t data = 0; 1583 int i; 1584 1585 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1586 delay(1000); 1587 for (i = 0; i < 16; i++) 1588 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1589 return (data); 1590 } 1591 1592 int 1593 epbusyeeprom(struct ep_softc *sc) 1594 { 1595 bus_space_tag_t iot = sc->sc_iot; 1596 bus_space_handle_t ioh = sc->sc_ioh; 1597 int i = 100, j; 1598 1599 while (i--) { 1600 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1601 if (j & EEPROM_BUSY) 1602 delay(100); 1603 else 1604 break; 1605 } 1606 if (!i) { 1607 printf("\n%s: eeprom failed to come ready\n", 1608 sc->sc_dev.dv_xname); 1609 return (1); 1610 } 1611 if (sc->bustype != EP_BUS_PCMCIA && sc->bustype != EP_BUS_PCI && 1612 (j & EEPROM_TST_MODE)) { 1613 printf("\n%s: erase pencil mark, or disable PnP mode!\n", 1614 sc->sc_dev.dv_xname); 1615 return (1); 1616 } 1617 return (0); 1618 } 1619 1620 u_int16_t 1621 ep_read_eeprom(struct ep_softc *sc, u_int16_t offset) 1622 { 1623 u_int16_t readcmd; 1624 1625 /* 1626 * RoadRunner has a larger EEPROM, so a different read command 1627 * is required. 1628 */ 1629 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) 1630 readcmd = READ_EEPROM_RR; 1631 else 1632 readcmd = READ_EEPROM; 1633 1634 if (epbusyeeprom(sc)) 1635 return (0); /* XXX why is eeprom busy? */ 1636 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND, 1637 readcmd | offset); 1638 if (epbusyeeprom(sc)) 1639 return (0); /* XXX why is eeprom busy? */ 1640 1641 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)); 1642 } 1643 1644 void 1645 epmbuffill(void *v) 1646 { 1647 struct ep_softc *sc = v; 1648 int s, i; 1649 1650 s = splnet(); 1651 for (i = 0; i < MAX_MBS; i++) { 1652 if (sc->mb[i] == NULL) { 1653 sc->mb[i] = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1654 if (sc->mb[i] == NULL) 1655 break; 1656 } 1657 } 1658 /* If the queue was not filled, try again. */ 1659 if (i < MAX_MBS) 1660 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1661 splx(s); 1662 } 1663 1664 void 1665 epmbufempty(struct ep_softc *sc) 1666 { 1667 int s, i; 1668 1669 s = splnet(); 1670 for (i = 0; i<MAX_MBS; i++) { 1671 if (sc->mb[i]) { 1672 m_freem(sc->mb[i]); 1673 sc->mb[i] = NULL; 1674 } 1675 } 1676 sc->next_mb = 0; 1677 timeout_del(&sc->sc_epmbuffill_tmo); 1678 splx(s); 1679 } 1680 1681 void 1682 ep_mii_setbit(struct ep_softc *sc, u_int16_t bit) 1683 { 1684 u_int16_t val; 1685 1686 /* We assume we're already in Window 4 */ 1687 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1688 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1689 val | bit); 1690 } 1691 1692 void 1693 ep_mii_clrbit(struct ep_softc *sc, u_int16_t bit) 1694 { 1695 u_int16_t val; 1696 1697 /* We assume we're already in Window 4 */ 1698 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1699 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1700 val & ~bit); 1701 } 1702 1703 u_int16_t 1704 ep_mii_readbit(struct ep_softc *sc, u_int16_t bit) 1705 { 1706 1707 /* We assume we're already in Window 4 */ 1708 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1709 bit); 1710 } 1711 1712 void 1713 ep_mii_sync(struct ep_softc *sc) 1714 { 1715 int i; 1716 1717 /* We assume we're already in Window 4 */ 1718 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1719 for (i = 0; i < 32; i++) { 1720 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1721 ep_mii_setbit(sc, PHYSMGMT_CLK); 1722 } 1723 } 1724 1725 void 1726 ep_mii_sendbits(struct ep_softc *sc, u_int32_t data, int nbits) 1727 { 1728 int i; 1729 1730 /* We assume we're already in Window 4 */ 1731 ep_mii_setbit(sc, PHYSMGMT_DIR); 1732 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1733 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1734 ep_mii_readbit(sc, PHYSMGMT_CLK); 1735 if (data & i) 1736 ep_mii_setbit(sc, PHYSMGMT_DATA); 1737 else 1738 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1739 ep_mii_setbit(sc, PHYSMGMT_CLK); 1740 ep_mii_readbit(sc, PHYSMGMT_CLK); 1741 } 1742 } 1743 1744 int 1745 ep_mii_readreg(struct device *self, int phy, int reg) 1746 { 1747 struct ep_softc *sc = (struct ep_softc *)self; 1748 int val = 0, i, err; 1749 1750 /* 1751 * Read the PHY register by manually driving the MII control lines. 1752 */ 1753 1754 GO_WINDOW(4); 1755 1756 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1757 1758 ep_mii_sync(sc); 1759 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1760 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1761 ep_mii_sendbits(sc, phy, 5); 1762 ep_mii_sendbits(sc, reg, 5); 1763 1764 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1765 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1766 ep_mii_setbit(sc, PHYSMGMT_CLK); 1767 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1768 1769 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1770 ep_mii_setbit(sc, PHYSMGMT_CLK); 1771 1772 /* Even if an error occurs, must still clock out the cycle. */ 1773 for (i = 0; i < 16; i++) { 1774 val <<= 1; 1775 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1776 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1777 val |= 1; 1778 ep_mii_setbit(sc, PHYSMGMT_CLK); 1779 } 1780 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1781 ep_mii_setbit(sc, PHYSMGMT_CLK); 1782 1783 GO_WINDOW(1); /* back to operating window */ 1784 1785 return (err ? 0 : val); 1786 } 1787 1788 void 1789 ep_mii_writereg(struct device *self, int phy, int reg, int val) 1790 { 1791 struct ep_softc *sc = (struct ep_softc *)self; 1792 1793 /* 1794 * Write the PHY register by manually driving the MII control lines. 1795 */ 1796 1797 GO_WINDOW(4); 1798 1799 ep_mii_sync(sc); 1800 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1801 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1802 ep_mii_sendbits(sc, phy, 5); 1803 ep_mii_sendbits(sc, reg, 5); 1804 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1805 ep_mii_sendbits(sc, val, 16); 1806 1807 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1808 ep_mii_setbit(sc, PHYSMGMT_CLK); 1809 1810 GO_WINDOW(1); /* back to operating window */ 1811 } 1812 1813 void 1814 ep_statchg(struct device *self) 1815 { 1816 struct ep_softc *sc = (struct ep_softc *)self; 1817 bus_space_tag_t iot = sc->sc_iot; 1818 bus_space_handle_t ioh = sc->sc_ioh; 1819 int mctl; 1820 1821 /* XXX Update ifp->if_baudrate */ 1822 1823 GO_WINDOW(3); 1824 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 1825 if (sc->sc_mii.mii_media_active & IFM_FDX) 1826 mctl |= MAC_CONTROL_FDX; 1827 else 1828 mctl &= ~MAC_CONTROL_FDX; 1829 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 1830 GO_WINDOW(1); /* back to operating window */ 1831 } 1832