1 /* $OpenBSD: elink3.c,v 1.73 2008/11/28 02:44:17 brad Exp $ */ 2 /* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org> 6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Herb Peyerl. 20 * 4. The name of Herb Peyerl may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/ioctl.h> 42 #include <sys/errno.h> 43 #include <sys/syslog.h> 44 #include <sys/selinfo.h> 45 #include <sys/timeout.h> 46 #include <sys/device.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_types.h> 51 #include <net/netisr.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/cpu.h> 67 #include <machine/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/ic/elink3var.h> 73 #include <dev/ic/elink3reg.h> 74 75 /* 76 * Structure to map media-present bits in boards to 77 * ifmedia codes and printable media names. Used for table-driven 78 * ifmedia initialization. 79 */ 80 struct ep_media { 81 int epm_eeprom_data; /* bitmask for eeprom config */ 82 int epm_conn; /* sc->ep_connectors code for medium */ 83 char *epm_name; /* name of medium */ 84 int epm_ifmedia; /* ifmedia word for medium */ 85 int epm_ifdata; 86 }; 87 88 /* 89 * ep_media table for Vortex/Demon/Boomerang: 90 * map from media-present bits in register RESET_OPTIONS+2 91 * to ifmedia "media words" and printable names. 92 * 93 * XXX indexed directly by INTERNAL_CONFIG default_media field, 94 * (i.e., EPMEDIA_ constants) forcing order of entries. 95 * Note that 3 is reserved. 96 */ 97 const struct ep_media ep_vortex_media[8] = { 98 { EP_PCI_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, 99 EPMEDIA_10BASE_T }, 100 { EP_PCI_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, 101 EPMEDIA_AUI }, 102 { 0, 0, "reserved", IFM_NONE, EPMEDIA_RESV1 }, 103 { EP_PCI_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, 104 EPMEDIA_10BASE_2 }, 105 { EP_PCI_100BASE_TX, EPC_100TX, "100-TX", IFM_ETHER|IFM_100_TX, 106 EPMEDIA_100BASE_TX }, 107 { EP_PCI_100BASE_FX, EPC_100FX, "100-FX", IFM_ETHER|IFM_100_FX, 108 EPMEDIA_100BASE_FX }, 109 { EP_PCI_100BASE_MII,EPC_MII, "mii", IFM_ETHER|IFM_100_TX, 110 EPMEDIA_MII }, 111 { EP_PCI_100BASE_T4, EPC_100T4, "100-T4", IFM_ETHER|IFM_100_T4, 112 EPMEDIA_100BASE_T4 } 113 }; 114 115 /* 116 * ep_media table for 3c509/3c509b/3c579/3c589: 117 * map from media-present bits in register CNFG_CNTRL 118 * (window 0, offset ?) to ifmedia "media words" and printable names. 119 */ 120 struct ep_media ep_isa_media[3] = { 121 { EP_W0_CC_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, EPMEDIA_10BASE_T }, 122 { EP_W0_CC_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, EPMEDIA_AUI }, 123 { EP_W0_CC_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, EPMEDIA_10BASE_2 }, 124 }; 125 126 /* Map vortex reset_options bits to if_media codes. */ 127 const u_int ep_default_to_media[8] = { 128 IFM_ETHER | IFM_10_T, 129 IFM_ETHER | IFM_10_5, 130 0, /* reserved by 3Com */ 131 IFM_ETHER | IFM_10_2, 132 IFM_ETHER | IFM_100_TX, 133 IFM_ETHER | IFM_100_FX, 134 IFM_ETHER | IFM_100_TX, /* XXX really MII: need to talk to PHY */ 135 IFM_ETHER | IFM_100_T4, 136 }; 137 138 struct cfdriver ep_cd = { 139 NULL, "ep", DV_IFNET 140 }; 141 142 void ep_vortex_probemedia(struct ep_softc *sc); 143 void ep_isa_probemedia(struct ep_softc *sc); 144 145 void eptxstat(struct ep_softc *); 146 int epstatus(struct ep_softc *); 147 int epioctl(struct ifnet *, u_long, caddr_t); 148 void epstart(struct ifnet *); 149 void epwatchdog(struct ifnet *); 150 void epreset(struct ep_softc *); 151 void epread(struct ep_softc *); 152 struct mbuf *epget(struct ep_softc *, int); 153 void epmbuffill(void *); 154 void epmbufempty(struct ep_softc *); 155 void epsetfilter(struct ep_softc *); 156 void ep_roadrunner_mii_enable(struct ep_softc *); 157 int epsetmedia(struct ep_softc *, int); 158 159 /* ifmedia callbacks */ 160 int ep_media_change(struct ifnet *); 161 void ep_media_status(struct ifnet *, struct ifmediareq *); 162 163 /* MII callbacks */ 164 int ep_mii_readreg(struct device *, int, int); 165 void ep_mii_writereg(struct device *, int, int, int); 166 void ep_statchg(struct device *); 167 168 void ep_mii_setbit(struct ep_softc *, u_int16_t); 169 void ep_mii_clrbit(struct ep_softc *, u_int16_t); 170 u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t); 171 void ep_mii_sync(struct ep_softc *); 172 void ep_mii_sendbits(struct ep_softc *, u_int32_t, int); 173 174 int epbusyeeprom(struct ep_softc *); 175 u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t); 176 177 static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg); 178 static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t); 179 static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t); 180 static __inline int ep_w1_reg(struct ep_softc *, int); 181 182 /* 183 * Issue a (reset) command, and be sure it has completed. 184 * Used for global reset, TX_RESET, RX_RESET. 185 */ 186 static inline void 187 ep_reset_cmd(sc, cmd, arg) 188 struct ep_softc *sc; 189 u_int cmd, arg; 190 { 191 bus_space_tag_t iot = sc->sc_iot; 192 bus_space_handle_t ioh = sc->sc_ioh; 193 194 bus_space_write_2(iot, ioh, cmd, arg); 195 ep_finish_reset(iot, ioh); 196 } 197 198 /* 199 * Wait for any pending reset to complete. 200 */ 201 static inline void 202 ep_finish_reset(iot, ioh) 203 bus_space_tag_t iot; 204 bus_space_handle_t ioh; 205 { 206 int i; 207 208 for (i = 0; i < 10000; i++) { 209 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 210 S_COMMAND_IN_PROGRESS) == 0) 211 break; 212 DELAY(10); 213 } 214 } 215 216 static inline void 217 ep_discard_rxtop(iot, ioh) 218 bus_space_tag_t iot; 219 bus_space_handle_t ioh; 220 { 221 int i; 222 223 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 224 225 /* 226 * Spin for about 1 msec, to avoid forcing a DELAY() between 227 * every received packet (adding latency and limiting pkt-recv rate). 228 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 229 * is about right. 230 */ 231 for (i = 0; i < 8000; i++) { 232 if ((bus_space_read_2(iot, ioh, EP_STATUS) & 233 S_COMMAND_IN_PROGRESS) == 0) 234 return; 235 } 236 237 /* not fast enough, do DELAY()s */ 238 ep_finish_reset(iot, ioh); 239 } 240 241 /* 242 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset. 243 */ 244 static __inline int 245 ep_w1_reg(sc, reg) 246 struct ep_softc *sc; 247 int reg; 248 { 249 switch (sc->ep_chipset) { 250 case EP_CHIPSET_ROADRUNNER: 251 switch (reg) { 252 case EP_W1_FREE_TX: 253 case EP_W1_RUNNER_RDCTL: 254 case EP_W1_RUNNER_WRCTL: 255 return (reg); 256 } 257 return (reg + 0x10); 258 } 259 return (reg); 260 } 261 262 /* 263 * Back-end attach and configure. 264 */ 265 void 266 epconfig(sc, chipset, enaddr) 267 struct ep_softc *sc; 268 u_short chipset; 269 u_int8_t *enaddr; 270 { 271 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 272 bus_space_tag_t iot = sc->sc_iot; 273 bus_space_handle_t ioh = sc->sc_ioh; 274 u_int16_t i; 275 276 sc->ep_chipset = chipset; 277 278 /* 279 * We could have been groveling around in other register 280 * windows in the front-end; make sure we're in window 0 281 * to read the EEPROM. 282 */ 283 GO_WINDOW(0); 284 285 if (enaddr == NULL) { 286 /* 287 * Read the station address from the eeprom. 288 */ 289 for (i = 0; i < 3; i++) { 290 u_int16_t x = ep_read_eeprom(sc, i); 291 292 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8; 293 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x; 294 } 295 } else { 296 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 297 } 298 299 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 300 if (sc->ep_flags & EP_FLAGS_MII) 301 printf("\n"); 302 else 303 printf(", "); 304 305 /* 306 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte 307 * packets. Commands only take an 11-bit parameter, and 11 bits 308 * isn't enough to hold a full-size packet length. 309 * Commands to these cards implicitly upshift a packet size 310 * or threshold by 2 bits. 311 * To detect cards with large-packet support, we probe by setting 312 * the transmit threshold register, then change windows and 313 * read back the threshold register directly, and see if the 314 * threshold value was shifted or not. 315 */ 316 bus_space_write_2(iot, ioh, EP_COMMAND, 317 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 318 GO_WINDOW(5); 319 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 320 GO_WINDOW(1); 321 switch (i) { 322 case EP_LARGEWIN_PROBE: 323 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 324 sc->txashift = 0; 325 break; 326 327 case (EP_LARGEWIN_PROBE << 2): 328 sc->txashift = 2; 329 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */ 330 break; 331 332 default: 333 printf("wrote %x to TX_AVAIL_THRESH, read back %x. " 334 "Interface disabled\n", EP_THRESH_DISABLE, (int) i); 335 return; 336 } 337 338 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc); 339 340 /* 341 * Ensure Tx-available interrupts are enabled for 342 * start the interface. 343 * XXX should be in epinit()? 344 */ 345 bus_space_write_2(iot, ioh, EP_COMMAND, 346 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 347 348 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 349 ifp->if_softc = sc; 350 ifp->if_start = epstart; 351 ifp->if_ioctl = epioctl; 352 ifp->if_watchdog = epwatchdog; 353 ifp->if_flags = 354 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 355 IFQ_SET_READY(&ifp->if_snd); 356 357 if_attach(ifp); 358 ether_ifattach(ifp); 359 360 /* 361 * Finish configuration: 362 * determine chipset if the front-end couldn't do so, 363 * show board details, set media. 364 */ 365 366 GO_WINDOW(0); 367 368 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 369 ep_media_status); 370 sc->sc_mii.mii_ifp = ifp; 371 sc->sc_mii.mii_readreg = ep_mii_readreg; 372 sc->sc_mii.mii_writereg = ep_mii_writereg; 373 sc->sc_mii.mii_statchg = ep_statchg; 374 375 /* 376 * If we've got an indirect (ISA, PCMCIA?) board, the chipset 377 * is unknown. If the board has large-packet support, it's a 378 * Vortex/Boomerang, otherwise it's a 3c509. 379 * XXX use eeprom capability word instead? 380 */ 381 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN && sc->txashift) { 382 printf("warning: unknown chipset, possibly 3c515?\n"); 383 #ifdef notyet 384 sc->sc_chipset = EP_CHIPSET_VORTEX; 385 #endif /* notyet */ 386 } 387 388 /* 389 * Ascertain which media types are present and inform ifmedia. 390 */ 391 switch (sc->ep_chipset) { 392 case EP_CHIPSET_ROADRUNNER: 393 if (sc->ep_flags & EP_FLAGS_MII) { 394 ep_roadrunner_mii_enable(sc); 395 GO_WINDOW(0); 396 } 397 /* FALLTHROUGH */ 398 399 case EP_CHIPSET_BOOMERANG: 400 /* 401 * If the device has MII, probe it. We won't be using 402 * any `native' media in this case, only PHYs. If 403 * we don't, just treat the Boomerang like the Vortex. 404 */ 405 if (sc->ep_flags & EP_FLAGS_MII) { 406 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 407 MII_PHY_ANY, MII_OFFSET_ANY, 0); 408 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 409 ifmedia_add(&sc->sc_mii.mii_media, 410 IFM_ETHER|IFM_NONE, 0, NULL); 411 ifmedia_set(&sc->sc_mii.mii_media, 412 IFM_ETHER|IFM_NONE); 413 } else { 414 ifmedia_set(&sc->sc_mii.mii_media, 415 IFM_ETHER|IFM_AUTO); 416 } 417 break; 418 } 419 /* FALLTHROUGH */ 420 421 /* on a direct bus, the attach routine can tell, but check anyway. */ 422 case EP_CHIPSET_VORTEX: 423 case EP_CHIPSET_BOOMERANG2: 424 ep_vortex_probemedia(sc); 425 break; 426 427 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */ 428 case EP_CHIPSET_3C509: 429 default: 430 ep_isa_probemedia(sc); 431 break; 432 } 433 434 GO_WINDOW(1); /* Window 1 is operating window */ 435 436 sc->tx_start_thresh = 20; /* probably a good starting point. */ 437 438 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 439 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 440 } 441 442 int 443 ep_detach(self) 444 struct device *self; 445 { 446 struct ep_softc *sc = (struct ep_softc *)self; 447 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 448 449 if (sc->ep_flags & EP_FLAGS_MII) 450 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 451 452 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 453 454 ether_ifdetach(ifp); 455 if_detach(ifp); 456 457 return (0); 458 } 459 460 /* 461 * Find supported media on 3c509-generation hardware that doesn't have 462 * a "reset_options" register in window 3. 463 * Use the config_cntrl register in window 0 instead. 464 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 465 * that implement CONFIG_CTRL. We don't have a good way to set the 466 * default active medium; punt to ifconfig instead. 467 * 468 * XXX what about 3c515, pcmcia 10/100? 469 */ 470 void 471 ep_isa_probemedia(sc) 472 struct ep_softc *sc; 473 { 474 bus_space_tag_t iot = sc->sc_iot; 475 bus_space_handle_t ioh = sc->sc_ioh; 476 struct ifmedia *ifm = &sc->sc_mii.mii_media; 477 int conn, i; 478 u_int16_t ep_w0_config, port; 479 480 conn = 0; 481 GO_WINDOW(0); 482 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 483 for (i = 0; i < 3; i++) { 484 struct ep_media * epm = ep_isa_media + i; 485 486 if ((ep_w0_config & epm->epm_eeprom_data) != 0) { 487 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 488 if (conn) 489 printf("/"); 490 printf("%s", epm->epm_name); 491 conn |= epm->epm_conn; 492 } 493 } 494 sc->ep_connectors = conn; 495 496 /* get default medium from EEPROM */ 497 if (epbusyeeprom(sc)) 498 return; /* XXX why is eeprom busy? */ 499 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 500 READ_EEPROM | EEPROM_ADDR_CFG); 501 if (epbusyeeprom(sc)) 502 return; /* XXX why is eeprom busy? */ 503 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 504 port = port >> 14; 505 506 printf(" (default %s)\n", ep_vortex_media[port].epm_name); 507 508 /* tell ifconfig what currently-active media is. */ 509 ifmedia_set(ifm, ep_default_to_media[port]); 510 511 /* XXX autoselect not yet implemented */ 512 } 513 514 515 /* 516 * Find media present on large-packet-capable elink3 devices. 517 * Show onboard configuration of large-packet-capable elink3 devices 518 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 519 * Use media and card-version info in window 3 instead. 520 * 521 * XXX how much of this works with 3c515, pcmcia 10/100? 522 */ 523 void 524 ep_vortex_probemedia(sc) 525 struct ep_softc *sc; 526 { 527 bus_space_tag_t iot = sc->sc_iot; 528 bus_space_handle_t ioh = sc->sc_ioh; 529 struct ifmedia *ifm = &sc->sc_mii.mii_media; 530 u_int config1, conn; 531 int reset_options; 532 int default_media; /* 3-bit encoding of default (EEPROM) media */ 533 int autoselect; /* boolean: should default to autoselect */ 534 const char *medium_name; 535 register int i; 536 537 GO_WINDOW(3); 538 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 539 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 540 GO_WINDOW(0); 541 542 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 543 autoselect = (config1 & CONFIG_AUTOSELECT) >> CONFIG_AUTOSELECT_SHIFT; 544 545 /* set available media options */ 546 conn = 0; 547 for (i = 0; i < 8; i++) { 548 const struct ep_media *epm = ep_vortex_media + i; 549 550 if ((reset_options & epm->epm_eeprom_data) != 0) { 551 if (conn) 552 printf("/"); 553 printf("%s", epm->epm_name); 554 conn |= epm->epm_conn; 555 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0); 556 } 557 } 558 559 sc->ep_connectors = conn; 560 561 /* Show eeprom's idea of default media. */ 562 medium_name = (default_media > 8) 563 ? "(unknown/impossible media)" 564 : ep_vortex_media[default_media].epm_name; 565 printf(" default %s%s", 566 medium_name, (autoselect) ? "/autoselect" : ""); 567 /* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/ 568 569 #ifdef notyet 570 /* 571 * Set default: either the active interface the card 572 * reads from the EEPROM, or if autoselect is true, 573 * whatever we find is actually connected. 574 * 575 * XXX autoselect not yet implemented. 576 */ 577 #endif /* notyet */ 578 579 /* tell ifconfig what currently-active media is. */ 580 ifmedia_set(ifm, ep_default_to_media[default_media]); 581 } 582 583 /* 584 * Bring device up. 585 * 586 * The order in here seems important. Otherwise we may not receive 587 * interrupts. ?! 588 */ 589 void 590 epinit(sc) 591 register struct ep_softc *sc; 592 { 593 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 594 bus_space_tag_t iot = sc->sc_iot; 595 bus_space_handle_t ioh = sc->sc_ioh; 596 int i; 597 598 /* make sure any pending reset has completed before touching board */ 599 ep_finish_reset(iot, ioh); 600 601 /* cancel any pending I/O */ 602 epstop(sc); 603 604 if (sc->bustype != EP_BUS_PCI) { 605 GO_WINDOW(0); 606 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 607 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 608 } 609 610 if (sc->bustype == EP_BUS_PCMCIA) { 611 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 612 } 613 614 GO_WINDOW(2); 615 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 616 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 617 sc->sc_arpcom.ac_enaddr[i]); 618 619 if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA) 620 /* 621 * Reset the station-address receive filter. 622 * A bug workaround for busmastering (Vortex, Demon) cards. 623 */ 624 for (i = 0; i < 6; i++) 625 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 626 627 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 628 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 629 630 GO_WINDOW(1); /* Window 1 is operating window */ 631 for (i = 0; i < 31; i++) 632 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 633 634 /* Set threshold for for Tx-space available interrupt. */ 635 bus_space_write_2(iot, ioh, EP_COMMAND, 636 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift)); 637 638 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 639 /* Enable options in the PCMCIA LAN COR register, via 640 * RoadRunner Window 1. 641 * 642 * XXX MAGIC CONSTANTS! 643 */ 644 u_int16_t cor; 645 646 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 647 648 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 649 bus_space_write_2(iot, ioh, 0, cor); 650 651 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 652 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 653 654 if (sc->ep_flags & EP_FLAGS_MII) { 655 ep_roadrunner_mii_enable(sc); 656 GO_WINDOW(1); 657 } 658 } 659 660 /* Enable interrupts. */ 661 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | 662 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 663 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | 664 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 665 666 /* 667 * Attempt to get rid of any stray interrupts that occurred during 668 * configuration. On the i386 this isn't possible because one may 669 * already be queued. However, a single stray interrupt is 670 * unimportant. 671 */ 672 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 673 674 epsetfilter(sc); 675 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 676 677 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 678 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 679 680 epmbuffill(sc); 681 682 /* Interface is now `running', with no output active. */ 683 ifp->if_flags |= IFF_RUNNING; 684 ifp->if_flags &= ~IFF_OACTIVE; 685 686 /* Attempt to start output, if any. */ 687 epstart(ifp); 688 } 689 690 /* 691 * Set multicast receive filter. 692 * elink3 hardware has no selective multicast filter in hardware. 693 * Enable reception of all multicasts and filter in software. 694 */ 695 void 696 epsetfilter(sc) 697 register struct ep_softc *sc; 698 { 699 register struct ifnet *ifp = &sc->sc_arpcom.ac_if; 700 701 GO_WINDOW(1); /* Window 1 is operating window */ 702 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 703 FIL_INDIVIDUAL | FIL_BRDCST | 704 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 705 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 706 } 707 708 709 int 710 ep_media_change(ifp) 711 struct ifnet *ifp; 712 { 713 register struct ep_softc *sc = ifp->if_softc; 714 715 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data); 716 } 717 718 /* 719 * Reset and enable the MII on the RoadRunner. 720 */ 721 void 722 ep_roadrunner_mii_enable(sc) 723 struct ep_softc *sc; 724 { 725 bus_space_tag_t iot = sc->sc_iot; 726 bus_space_handle_t ioh = sc->sc_ioh; 727 728 GO_WINDOW(3); 729 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 730 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 731 delay(1000); 732 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 733 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII); 734 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 735 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 736 delay(1000); 737 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 738 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII); 739 } 740 741 /* 742 * Set active media to a specific given EPMEDIA_<> value. 743 * For vortex/demon/boomerang cards, update media field in w3_internal_config, 744 * and power on selected transceiver. 745 * For 3c509-generation cards (3c509/3c579/3c589/3c509B), 746 * update media field in w0_address_config, and power on selected xcvr. 747 */ 748 int 749 epsetmedia(sc, medium) 750 struct ep_softc *sc; 751 int medium; 752 { 753 bus_space_tag_t iot = sc->sc_iot; 754 bus_space_handle_t ioh = sc->sc_ioh; 755 int w4_media; 756 int config0, config1; 757 758 /* 759 * you can `ifconfig (link0|-link0) ep0' to get the following 760 * behaviour: 761 * -link0 disable AUI/UTP. enable BNC. 762 * link0 disable BNC. enable AUI. 763 * link1 if the card has a UTP connector, and link0 is 764 * set too, then you get the UTP port. 765 */ 766 767 /* 768 * First, change the media-control bits in EP_W4_MEDIA_TYPE. 769 */ 770 771 /* Turn everything off. First turn off linkbeat and UTP. */ 772 GO_WINDOW(4); 773 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 774 w4_media = w4_media & ~(ENABLE_UTP|SQE_ENABLE); 775 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media); 776 777 /* Turn off coax */ 778 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 779 delay(1000); 780 781 /* If the device has MII, select it, and then tell the 782 * PHY which media to use. 783 */ 784 if (sc->ep_flags & EP_FLAGS_MII) { 785 GO_WINDOW(3); 786 787 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 788 int resopt; 789 790 resopt = bus_space_read_2(iot, ioh, 791 EP_W3_RESET_OPTIONS); 792 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS, 793 resopt | EP_RUNNER_ENABLE_MII); 794 } 795 796 config0 = (u_int)bus_space_read_2(iot, ioh, 797 EP_W3_INTERNAL_CONFIG); 798 config1 = (u_int)bus_space_read_2(iot, ioh, 799 EP_W3_INTERNAL_CONFIG + 2); 800 801 config1 = config1 & ~CONFIG_MEDIAMASK; 802 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 803 804 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 805 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 806 GO_WINDOW(1); /* back to operating window */ 807 808 mii_mediachg(&sc->sc_mii); 809 return (0); 810 } 811 812 /* 813 * Now turn on the selected media/transceiver. 814 */ 815 GO_WINDOW(4); 816 switch (medium) { 817 case EPMEDIA_10BASE_T: 818 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP | 819 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0))); 820 break; 821 822 case EPMEDIA_10BASE_2: 823 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 824 DELAY(1000); /* 50ms not enough? */ 825 break; 826 827 /* XXX following only for new-generation cards */ 828 case EPMEDIA_100BASE_TX: 829 case EPMEDIA_100BASE_FX: 830 case EPMEDIA_100BASE_T4: /* XXX check documentation */ 831 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 832 w4_media | LINKBEAT_ENABLE); 833 DELAY(1000); /* not strictly necessary? */ 834 break; 835 836 case EPMEDIA_AUI: 837 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 838 w4_media | SQE_ENABLE); 839 DELAY(1000); /* not strictly necessary? */ 840 break; 841 case EPMEDIA_MII: 842 break; 843 default: 844 #if defined(EP_DEBUG) 845 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium); 846 #endif 847 break; 848 849 } 850 851 /* 852 * Tell the chip which PHY [sic] to use. 853 */ 854 switch (sc->ep_chipset) { 855 case EP_CHIPSET_VORTEX: 856 case EP_CHIPSET_BOOMERANG2: 857 GO_WINDOW(3); 858 config0 = (u_int)bus_space_read_2(iot, ioh, 859 EP_W3_INTERNAL_CONFIG); 860 config1 = (u_int)bus_space_read_2(iot, ioh, 861 EP_W3_INTERNAL_CONFIG + 2); 862 863 #if defined(EP_DEBUG) 864 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n", 865 sc->sc_dev.dv_xname, config0, config1); 866 #endif 867 config1 = config1 & ~CONFIG_MEDIAMASK; 868 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT); 869 870 #if defined(EP_DEBUG) 871 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n", 872 sc->sc_dev.dv_xname, medium, config1); 873 #endif 874 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 875 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 876 break; 877 878 default: 879 GO_WINDOW(0); 880 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 881 config0 &= 0x3fff; 882 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 883 config0 | (medium << 14)); 884 DELAY(1000); 885 break; 886 } 887 888 GO_WINDOW(1); /* Window 1 is operating window */ 889 return (0); 890 } 891 892 893 /* 894 * Get currently-selected media from card. 895 * (if_media callback, may be called before interface is brought up). 896 */ 897 void 898 ep_media_status(ifp, req) 899 struct ifnet *ifp; 900 struct ifmediareq *req; 901 { 902 register struct ep_softc *sc = ifp->if_softc; 903 bus_space_tag_t iot = sc->sc_iot; 904 bus_space_handle_t ioh = sc->sc_ioh; 905 u_int config1; 906 u_int ep_mediastatus; 907 908 /* 909 * If we have MII, go ask the PHY what's going on. 910 */ 911 if (sc->ep_flags & EP_FLAGS_MII) { 912 mii_pollstat(&sc->sc_mii); 913 req->ifm_active = sc->sc_mii.mii_media_active; 914 req->ifm_status = sc->sc_mii.mii_media_status; 915 return; 916 } 917 918 /* XXX read from softc when we start autosensing media */ 919 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 920 921 switch (sc->ep_chipset) { 922 case EP_CHIPSET_VORTEX: 923 case EP_CHIPSET_BOOMERANG: 924 GO_WINDOW(3); 925 delay(5000); 926 927 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 928 GO_WINDOW(1); 929 930 config1 = 931 (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 932 req->ifm_active = ep_default_to_media[config1]; 933 934 /* XXX check full-duplex bits? */ 935 936 GO_WINDOW(4); 937 req->ifm_status = IFM_AVALID; /* XXX */ 938 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE); 939 if (ep_mediastatus & LINKBEAT_DETECT) 940 req->ifm_status |= IFM_ACTIVE; /* XXX automedia */ 941 942 break; 943 944 case EP_CHIPSET_UNKNOWN: 945 case EP_CHIPSET_3C509: 946 req->ifm_status = 0; /* XXX */ 947 break; 948 949 default: 950 printf("%s: media_status on unknown chipset 0x%x\n", 951 ifp->if_xname, sc->ep_chipset); 952 break; 953 } 954 955 /* XXX look for softc heartbeat for other chips or media */ 956 957 GO_WINDOW(1); 958 return; 959 } 960 961 962 963 /* 964 * Start outputting on the interface. 965 * Always called as splnet(). 966 */ 967 void 968 epstart(ifp) 969 struct ifnet *ifp; 970 { 971 register struct ep_softc *sc = ifp->if_softc; 972 bus_space_tag_t iot = sc->sc_iot; 973 bus_space_handle_t ioh = sc->sc_ioh; 974 struct mbuf *m, *m0; 975 int sh, len, pad, txreg; 976 977 /* Don't transmit if interface is busy or not running */ 978 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 979 return; 980 981 startagain: 982 /* Sneak a peek at the next packet */ 983 IFQ_POLL(&ifp->if_snd, m0); 984 if (m0 == NULL) 985 return; 986 987 /* We need to use m->m_pkthdr.len, so require the header */ 988 if ((m0->m_flags & M_PKTHDR) == 0) 989 panic("epstart: no header mbuf"); 990 len = m0->m_pkthdr.len; 991 992 pad = (4 - len) & 3; 993 994 /* 995 * The 3c509 automatically pads short packets to minimum ethernet 996 * length, but we drop packets that are too large. Perhaps we should 997 * truncate them instead? 998 */ 999 if (len + pad > ETHER_MAX_LEN) { 1000 /* packet is obviously too large: toss it */ 1001 ++ifp->if_oerrors; 1002 IFQ_DEQUEUE(&ifp->if_snd, m0); 1003 m_freem(m0); 1004 goto readcheck; 1005 } 1006 1007 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 1008 len + pad + 4) { 1009 bus_space_write_2(iot, ioh, EP_COMMAND, 1010 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift)); 1011 /* not enough room in FIFO */ 1012 ifp->if_flags |= IFF_OACTIVE; 1013 return; 1014 } else { 1015 bus_space_write_2(iot, ioh, EP_COMMAND, 1016 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE); 1017 } 1018 1019 IFQ_DEQUEUE(&ifp->if_snd, m0); 1020 if (m0 == NULL) 1021 return; 1022 1023 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1024 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/)); 1025 1026 #if NBPFILTER > 0 1027 if (ifp->if_bpf) 1028 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1029 #endif 1030 1031 /* 1032 * Do the output at splhigh() so that an interrupt from another device 1033 * won't cause a FIFO underrun. 1034 */ 1035 sh = splhigh(); 1036 1037 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1038 1039 bus_space_write_2(iot, ioh, txreg, len); 1040 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1041 if (EP_IS_BUS_32(sc->bustype)) { 1042 for (m = m0; m; ) { 1043 if (m->m_len > 3) 1044 bus_space_write_raw_multi_4(iot, ioh, txreg, 1045 mtod(m, u_int8_t *), m->m_len & ~3); 1046 if (m->m_len & 3) 1047 bus_space_write_multi_1(iot, ioh, txreg, 1048 mtod(m, u_int8_t *) + (m->m_len & ~3), 1049 m->m_len & 3); 1050 MFREE(m, m0); 1051 m = m0; 1052 } 1053 } else { 1054 for (m = m0; m; ) { 1055 if (m->m_len > 1) 1056 bus_space_write_raw_multi_2(iot, ioh, txreg, 1057 mtod(m, u_int8_t *), m->m_len & ~1); 1058 if (m->m_len & 1) 1059 bus_space_write_1(iot, ioh, txreg, 1060 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1061 MFREE(m, m0); 1062 m = m0; 1063 } 1064 } 1065 while (pad--) 1066 bus_space_write_1(iot, ioh, txreg, 0); 1067 1068 splx(sh); 1069 1070 ++ifp->if_opackets; 1071 1072 readcheck: 1073 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1074 ERR_INCOMPLETE) == 0) { 1075 /* We received a complete packet. */ 1076 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1077 1078 if ((status & S_INTR_LATCH) == 0) { 1079 /* 1080 * No interrupt, read the packet and continue 1081 * Is this supposed to happen? Is my motherboard 1082 * completely busted? 1083 */ 1084 epread(sc); 1085 } else 1086 /* Got an interrupt, return to get it serviced. */ 1087 return; 1088 } else { 1089 /* Check if we are stuck and reset [see XXX comment] */ 1090 if (epstatus(sc)) { 1091 #ifdef EP_DEBUG 1092 if (ifp->if_flags & IFF_DEBUG) 1093 printf("%s: adapter reset\n", 1094 sc->sc_dev.dv_xname); 1095 #endif 1096 epreset(sc); 1097 } 1098 } 1099 1100 goto startagain; 1101 } 1102 1103 1104 /* 1105 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1106 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1107 * We detect this situation and we reset the adapter. 1108 * It happens at times when there is a lot of broadcast traffic 1109 * on the cable (once in a blue moon). 1110 */ 1111 int 1112 epstatus(sc) 1113 register struct ep_softc *sc; 1114 { 1115 bus_space_tag_t iot = sc->sc_iot; 1116 bus_space_handle_t ioh = sc->sc_ioh; 1117 u_int16_t fifost; 1118 1119 /* 1120 * Check the FIFO status and act accordingly 1121 */ 1122 GO_WINDOW(4); 1123 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1124 GO_WINDOW(1); 1125 1126 if (fifost & FIFOS_RX_UNDERRUN) { 1127 #ifdef EP_DEBUG 1128 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1129 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1130 #endif 1131 epreset(sc); 1132 return 0; 1133 } 1134 1135 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1136 #ifdef EP_DEBUG 1137 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1138 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1139 #endif 1140 return 1; 1141 } 1142 1143 if (fifost & FIFOS_RX_OVERRUN) { 1144 #ifdef EP_DEBUG 1145 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1146 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1147 #endif 1148 return 1; 1149 } 1150 1151 if (fifost & FIFOS_TX_OVERRUN) { 1152 #ifdef EP_DEBUG 1153 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1154 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1155 #endif 1156 epreset(sc); 1157 return 0; 1158 } 1159 1160 return 0; 1161 } 1162 1163 1164 void 1165 eptxstat(sc) 1166 register struct ep_softc *sc; 1167 { 1168 bus_space_tag_t iot = sc->sc_iot; 1169 bus_space_handle_t ioh = sc->sc_ioh; 1170 int i; 1171 1172 /* 1173 * We need to read+write TX_STATUS until we get a 0 status 1174 * in order to turn off the interrupt flag. 1175 */ 1176 while ((i = bus_space_read_1(iot, ioh, 1177 ep_w1_reg(sc, EP_W1_TX_STATUS))) & TXS_COMPLETE) { 1178 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1179 0x0); 1180 1181 if (i & TXS_JABBER) { 1182 ++sc->sc_arpcom.ac_if.if_oerrors; 1183 #ifdef EP_DEBUG 1184 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1185 printf("%s: jabber (%x)\n", 1186 sc->sc_dev.dv_xname, i); 1187 #endif 1188 epreset(sc); 1189 } else if (i & TXS_UNDERRUN) { 1190 ++sc->sc_arpcom.ac_if.if_oerrors; 1191 #ifdef EP_DEBUG 1192 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG) 1193 printf("%s: fifo underrun (%x) @%d\n", 1194 sc->sc_dev.dv_xname, i, 1195 sc->tx_start_thresh); 1196 #endif 1197 if (sc->tx_succ_ok < 100) 1198 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1199 sc->tx_start_thresh + 20); 1200 sc->tx_succ_ok = 0; 1201 epreset(sc); 1202 } else if (i & TXS_MAX_COLLISION) { 1203 ++sc->sc_arpcom.ac_if.if_collisions; 1204 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1205 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1206 } else 1207 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1208 } 1209 } 1210 1211 int 1212 epintr(arg) 1213 void *arg; 1214 { 1215 register struct ep_softc *sc = arg; 1216 bus_space_tag_t iot = sc->sc_iot; 1217 bus_space_handle_t ioh = sc->sc_ioh; 1218 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1219 u_int16_t status; 1220 int ret = 0; 1221 1222 for (;;) { 1223 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1224 1225 status = bus_space_read_2(iot, ioh, EP_STATUS); 1226 1227 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1228 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) 1229 break; 1230 1231 ret = 1; 1232 1233 /* 1234 * Acknowledge any interrupts. It's important that we do this 1235 * first, since there would otherwise be a race condition. 1236 * Due to the i386 interrupt queueing, we may get spurious 1237 * interrupts occasionally. 1238 */ 1239 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status); 1240 1241 if (status & S_RX_COMPLETE) 1242 epread(sc); 1243 if (status & S_TX_AVAIL) { 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 epstart(ifp); 1246 } 1247 if (status & S_CARD_FAILURE) { 1248 epreset(sc); 1249 return (1); 1250 } 1251 if (status & S_TX_COMPLETE) { 1252 eptxstat(sc); 1253 epstart(ifp); 1254 } 1255 } 1256 1257 /* no more interrupts */ 1258 return (ret); 1259 } 1260 1261 void 1262 epread(sc) 1263 register struct ep_softc *sc; 1264 { 1265 bus_space_tag_t iot = sc->sc_iot; 1266 bus_space_handle_t ioh = sc->sc_ioh; 1267 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1268 struct mbuf *m; 1269 int len; 1270 1271 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1272 1273 again: 1274 #ifdef EP_DEBUG 1275 if (ifp->if_flags & IFF_DEBUG) { 1276 int err = len & ERR_MASK; 1277 char *s = NULL; 1278 1279 if (len & ERR_INCOMPLETE) 1280 s = "incomplete packet"; 1281 else if (err == ERR_OVERRUN) 1282 s = "packet overrun"; 1283 else if (err == ERR_RUNT) 1284 s = "runt packet"; 1285 else if (err == ERR_ALIGNMENT) 1286 s = "bad alignment"; 1287 else if (err == ERR_CRC) 1288 s = "bad crc"; 1289 else if (err == ERR_OVERSIZE) 1290 s = "oversized packet"; 1291 else if (err == ERR_DRIBBLE) 1292 s = "dribble bits"; 1293 1294 if (s) 1295 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1296 } 1297 #endif 1298 1299 if (len & ERR_INCOMPLETE) 1300 return; 1301 1302 if (len & ERR_RX) { 1303 ++ifp->if_ierrors; 1304 goto abort; 1305 } 1306 1307 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1308 1309 /* Pull packet off interface. */ 1310 m = epget(sc, len); 1311 if (m == NULL) { 1312 ifp->if_ierrors++; 1313 goto abort; 1314 } 1315 1316 ++ifp->if_ipackets; 1317 1318 #if NBPFILTER > 0 1319 /* 1320 * Check if there's a BPF listener on this interface. 1321 * If so, hand off the raw packet to BPF. 1322 */ 1323 if (ifp->if_bpf) 1324 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1325 #endif 1326 1327 ether_input_mbuf(ifp, m); 1328 1329 /* 1330 * In periods of high traffic we can actually receive enough 1331 * packets so that the fifo overrun bit will be set at this point, 1332 * even though we just read a packet. In this case we 1333 * are not going to receive any more interrupts. We check for 1334 * this condition and read again until the fifo is not full. 1335 * We could simplify this test by not using epstatus(), but 1336 * rechecking the RX_STATUS register directly. This test could 1337 * result in unnecessary looping in cases where there is a new 1338 * packet but the fifo is not full, but it will not fix the 1339 * stuck behavior. 1340 * 1341 * Even with this improvement, we still get packet overrun errors 1342 * which are hurting performance. Maybe when I get some more time 1343 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1344 */ 1345 if (epstatus(sc)) { 1346 len = bus_space_read_2(iot, ioh, 1347 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1348 /* Check if we are stuck and reset [see XXX comment] */ 1349 if (len & ERR_INCOMPLETE) { 1350 #ifdef EP_DEBUG 1351 if (ifp->if_flags & IFF_DEBUG) 1352 printf("%s: adapter reset\n", 1353 sc->sc_dev.dv_xname); 1354 #endif 1355 epreset(sc); 1356 return; 1357 } 1358 goto again; 1359 } 1360 1361 return; 1362 1363 abort: 1364 ep_discard_rxtop(iot, ioh); 1365 } 1366 1367 struct mbuf * 1368 epget(sc, totlen) 1369 struct ep_softc *sc; 1370 int totlen; 1371 { 1372 bus_space_tag_t iot = sc->sc_iot; 1373 bus_space_handle_t ioh = sc->sc_ioh; 1374 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1375 struct mbuf *top, **mp, *m; 1376 int len, pad, sh, rxreg; 1377 1378 m = sc->mb[sc->next_mb]; 1379 sc->mb[sc->next_mb] = NULL; 1380 if (m == NULL) { 1381 MGETHDR(m, M_DONTWAIT, MT_DATA); 1382 if (m == NULL) 1383 return (NULL); 1384 } else { 1385 /* If the queue is no longer full, refill. */ 1386 if (sc->last_mb == sc->next_mb) 1387 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1388 /* Convert one of our saved mbuf's. */ 1389 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1390 m = m_inithdr(m); 1391 } 1392 m->m_pkthdr.rcvif = ifp; 1393 m->m_pkthdr.len = totlen; 1394 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1395 len = MHLEN; 1396 if (totlen >= MINCLSIZE) { 1397 MCLGET(m, M_DONTWAIT); 1398 if (m->m_flags & M_EXT) 1399 len = MCLBYTES; 1400 } 1401 m->m_data += pad; 1402 len -= pad; 1403 top = 0; 1404 mp = ⊤ 1405 1406 /* 1407 * We read the packet at splhigh() so that an interrupt from another 1408 * device doesn't cause the card's buffer to overflow while we're 1409 * reading it. We may still lose packets at other times. 1410 */ 1411 sh = splhigh(); 1412 1413 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1414 1415 while (totlen > 0) { 1416 if (top) { 1417 m = sc->mb[sc->next_mb]; 1418 sc->mb[sc->next_mb] = NULL; 1419 if (m == NULL) { 1420 MGET(m, M_DONTWAIT, MT_DATA); 1421 if (m == NULL) { 1422 splx(sh); 1423 m_freem(top); 1424 return (NULL); 1425 } 1426 } else 1427 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1428 1429 len = MLEN; 1430 } 1431 if (top && totlen >= MINCLSIZE) { 1432 MCLGET(m, M_DONTWAIT); 1433 if (m->m_flags & M_EXT) 1434 len = MCLBYTES; 1435 } 1436 len = min(totlen, len); 1437 if (EP_IS_BUS_32(sc->bustype)) { 1438 if (len > 3) { 1439 len &= ~3; 1440 bus_space_read_raw_multi_4(iot, ioh, rxreg, 1441 mtod(m, u_int8_t *), len); 1442 } else 1443 bus_space_read_multi_1(iot, ioh, rxreg, 1444 mtod(m, u_int8_t *), len); 1445 } else { 1446 if (len > 1) { 1447 len &= ~1; 1448 bus_space_read_raw_multi_2(iot, ioh, rxreg, 1449 mtod(m, u_int8_t *), len); 1450 } else 1451 *(mtod(m, u_int8_t *)) = 1452 bus_space_read_1(iot, ioh, rxreg); 1453 } 1454 m->m_len = len; 1455 totlen -= len; 1456 *mp = m; 1457 mp = &m->m_next; 1458 } 1459 1460 ep_discard_rxtop(iot, ioh); 1461 1462 splx(sh); 1463 1464 return top; 1465 } 1466 1467 int 1468 epioctl(ifp, cmd, data) 1469 register struct ifnet *ifp; 1470 u_long cmd; 1471 caddr_t data; 1472 { 1473 struct ep_softc *sc = ifp->if_softc; 1474 struct ifaddr *ifa = (struct ifaddr *)data; 1475 struct ifreq *ifr = (struct ifreq *)data; 1476 int s, error = 0; 1477 1478 s = splnet(); 1479 1480 switch (cmd) { 1481 case SIOCSIFADDR: 1482 ifp->if_flags |= IFF_UP; 1483 1484 switch (ifa->ifa_addr->sa_family) { 1485 #ifdef INET 1486 case AF_INET: 1487 epinit(sc); 1488 arp_ifinit(&sc->sc_arpcom, ifa); 1489 break; 1490 #endif 1491 default: 1492 epinit(sc); 1493 break; 1494 } 1495 break; 1496 1497 case SIOCSIFMEDIA: 1498 case SIOCGIFMEDIA: 1499 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1500 break; 1501 1502 case SIOCSIFFLAGS: 1503 if ((ifp->if_flags & IFF_UP) == 0 && 1504 (ifp->if_flags & IFF_RUNNING) != 0) { 1505 /* 1506 * If interface is marked down and it is running, then 1507 * stop it. 1508 */ 1509 epstop(sc); 1510 ifp->if_flags &= ~IFF_RUNNING; 1511 } else if ((ifp->if_flags & IFF_UP) != 0 && 1512 (ifp->if_flags & IFF_RUNNING) == 0) { 1513 /* 1514 * If interface is marked up and it is stopped, then 1515 * start it. 1516 */ 1517 epinit(sc); 1518 } else if ((ifp->if_flags & IFF_UP) != 0) { 1519 /* 1520 * Reset the interface to pick up changes in any other 1521 * flags that affect hardware registers. 1522 */ 1523 epinit(sc); 1524 } 1525 break; 1526 1527 default: 1528 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1529 } 1530 1531 if (error == ENETRESET) { 1532 if (ifp->if_flags & IFF_RUNNING) 1533 epreset(sc); 1534 error = 0; 1535 } 1536 1537 splx(s); 1538 return (error); 1539 } 1540 1541 void 1542 epreset(sc) 1543 struct ep_softc *sc; 1544 { 1545 int s; 1546 1547 s = splnet(); 1548 epinit(sc); 1549 splx(s); 1550 } 1551 1552 void 1553 epwatchdog(ifp) 1554 struct ifnet *ifp; 1555 { 1556 struct ep_softc *sc = ifp->if_softc; 1557 1558 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1559 ++sc->sc_arpcom.ac_if.if_oerrors; 1560 1561 epreset(sc); 1562 } 1563 1564 void 1565 epstop(sc) 1566 register struct ep_softc *sc; 1567 { 1568 bus_space_tag_t iot = sc->sc_iot; 1569 bus_space_handle_t ioh = sc->sc_ioh; 1570 1571 if (sc->ep_flags & EP_FLAGS_MII) { 1572 mii_down(&sc->sc_mii); 1573 } 1574 1575 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1576 /* Clear the FIFO buffer count, thus halting 1577 * any currently-running transactions. 1578 */ 1579 GO_WINDOW(1); /* sanity */ 1580 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1581 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1582 } 1583 1584 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1585 ep_discard_rxtop(iot, ioh); 1586 1587 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1588 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1589 1590 ep_reset_cmd(sc, EP_COMMAND, RX_RESET); 1591 ep_reset_cmd(sc, EP_COMMAND, TX_RESET); 1592 1593 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1594 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1595 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1596 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1597 1598 epmbufempty(sc); 1599 } 1600 1601 /* 1602 * We get eeprom data from the id_port given an offset into the 1603 * eeprom. Basically; after the ID_sequence is sent to all of 1604 * the cards; they enter the ID_CMD state where they will accept 1605 * command requests. 0x80-0xbf loads the eeprom data. We then 1606 * read the port 16 times and with every read; the cards check 1607 * for contention (ie: if one card writes a 0 bit and another 1608 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1609 * each card compares the data on the bus; if there is a difference 1610 * then that card goes into ID_WAIT state again). In the meantime; 1611 * one bit of data is returned in the AX register which is conveniently 1612 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1613 * bit of data with each read. 1614 * 1615 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1616 */ 1617 u_int16_t 1618 epreadeeprom(iot, ioh, offset) 1619 bus_space_tag_t iot; 1620 bus_space_handle_t ioh; 1621 int offset; 1622 { 1623 u_int16_t data = 0; 1624 int i; 1625 1626 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1627 delay(1000); 1628 for (i = 0; i < 16; i++) 1629 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1630 return (data); 1631 } 1632 1633 int 1634 epbusyeeprom(sc) 1635 struct ep_softc *sc; 1636 { 1637 bus_space_tag_t iot = sc->sc_iot; 1638 bus_space_handle_t ioh = sc->sc_ioh; 1639 int i = 100, j; 1640 1641 while (i--) { 1642 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1643 if (j & EEPROM_BUSY) 1644 delay(100); 1645 else 1646 break; 1647 } 1648 if (!i) { 1649 printf("\n%s: eeprom failed to come ready\n", 1650 sc->sc_dev.dv_xname); 1651 return (1); 1652 } 1653 if (sc->bustype != EP_BUS_PCMCIA && sc->bustype != EP_BUS_PCI && 1654 (j & EEPROM_TST_MODE)) { 1655 printf("\n%s: erase pencil mark, or disable PnP mode!\n", 1656 sc->sc_dev.dv_xname); 1657 return (1); 1658 } 1659 return (0); 1660 } 1661 1662 u_int16_t 1663 ep_read_eeprom(sc, offset) 1664 struct ep_softc *sc; 1665 u_int16_t offset; 1666 { 1667 u_int16_t readcmd; 1668 1669 /* 1670 * RoadRunner has a larger EEPROM, so a different read command 1671 * is required. 1672 */ 1673 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) 1674 readcmd = READ_EEPROM_RR; 1675 else 1676 readcmd = READ_EEPROM; 1677 1678 if (epbusyeeprom(sc)) 1679 return (0); /* XXX why is eeprom busy? */ 1680 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND, 1681 readcmd | offset); 1682 if (epbusyeeprom(sc)) 1683 return (0); /* XXX why is eeprom busy? */ 1684 1685 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)); 1686 } 1687 1688 void 1689 epmbuffill(v) 1690 void *v; 1691 { 1692 struct ep_softc *sc = v; 1693 int s, i; 1694 1695 s = splnet(); 1696 i = sc->last_mb; 1697 do { 1698 if (sc->mb[i] == NULL) 1699 MGET(sc->mb[i], M_DONTWAIT, MT_DATA); 1700 if (sc->mb[i] == NULL) 1701 break; 1702 i = (i + 1) % MAX_MBS; 1703 } while (i != sc->next_mb); 1704 sc->last_mb = i; 1705 /* If the queue was not filled, try again. */ 1706 if (sc->last_mb != sc->next_mb) 1707 timeout_add(&sc->sc_epmbuffill_tmo, 1); 1708 splx(s); 1709 } 1710 1711 void 1712 epmbufempty(sc) 1713 struct ep_softc *sc; 1714 { 1715 int s, i; 1716 1717 s = splnet(); 1718 for (i = 0; i<MAX_MBS; i++) { 1719 if (sc->mb[i]) { 1720 m_freem(sc->mb[i]); 1721 sc->mb[i] = NULL; 1722 } 1723 } 1724 sc->last_mb = sc->next_mb = 0; 1725 timeout_del(&sc->sc_epmbuffill_tmo); 1726 splx(s); 1727 } 1728 1729 void 1730 ep_mii_setbit(sc, bit) 1731 struct ep_softc *sc; 1732 u_int16_t bit; 1733 { 1734 u_int16_t val; 1735 1736 /* We assume we're already in Window 4 */ 1737 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1738 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1739 val | bit); 1740 } 1741 1742 void 1743 ep_mii_clrbit(sc, bit) 1744 struct ep_softc *sc; 1745 u_int16_t bit; 1746 { 1747 u_int16_t val; 1748 1749 /* We assume we're already in Window 4 */ 1750 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1751 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1752 val & ~bit); 1753 } 1754 1755 u_int16_t 1756 ep_mii_readbit(sc, bit) 1757 struct ep_softc *sc; 1758 u_int16_t bit; 1759 { 1760 1761 /* We assume we're already in Window 4 */ 1762 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1763 bit); 1764 } 1765 1766 void 1767 ep_mii_sync(sc) 1768 struct ep_softc *sc; 1769 { 1770 int i; 1771 1772 /* We assume we're already in Window 4 */ 1773 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1774 for (i = 0; i < 32; i++) { 1775 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1776 ep_mii_setbit(sc, PHYSMGMT_CLK); 1777 } 1778 } 1779 1780 void 1781 ep_mii_sendbits(sc, data, nbits) 1782 struct ep_softc *sc; 1783 u_int32_t data; 1784 int nbits; 1785 { 1786 int i; 1787 1788 /* We assume we're already in Window 4 */ 1789 ep_mii_setbit(sc, PHYSMGMT_DIR); 1790 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1791 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1792 ep_mii_readbit(sc, PHYSMGMT_CLK); 1793 if (data & i) 1794 ep_mii_setbit(sc, PHYSMGMT_DATA); 1795 else 1796 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1797 ep_mii_setbit(sc, PHYSMGMT_CLK); 1798 ep_mii_readbit(sc, PHYSMGMT_CLK); 1799 } 1800 } 1801 1802 int 1803 ep_mii_readreg(self, phy, reg) 1804 struct device *self; 1805 int phy, reg; 1806 { 1807 struct ep_softc *sc = (struct ep_softc *)self; 1808 int val = 0, i, err; 1809 1810 /* 1811 * Read the PHY register by manually driving the MII control lines. 1812 */ 1813 1814 GO_WINDOW(4); 1815 1816 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1817 1818 ep_mii_sync(sc); 1819 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1820 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1821 ep_mii_sendbits(sc, phy, 5); 1822 ep_mii_sendbits(sc, reg, 5); 1823 1824 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1825 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1826 ep_mii_setbit(sc, PHYSMGMT_CLK); 1827 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1828 1829 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1830 ep_mii_setbit(sc, PHYSMGMT_CLK); 1831 1832 /* Even if an error occurs, must still clock out the cycle. */ 1833 for (i = 0; i < 16; i++) { 1834 val <<= 1; 1835 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1836 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1837 val |= 1; 1838 ep_mii_setbit(sc, PHYSMGMT_CLK); 1839 } 1840 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1841 ep_mii_setbit(sc, PHYSMGMT_CLK); 1842 1843 GO_WINDOW(1); /* back to operating window */ 1844 1845 return (err ? 0 : val); 1846 } 1847 1848 void 1849 ep_mii_writereg(self, phy, reg, val) 1850 struct device *self; 1851 int phy, reg, val; 1852 { 1853 struct ep_softc *sc = (struct ep_softc *)self; 1854 1855 /* 1856 * Write the PHY register by manually driving the MII control lines. 1857 */ 1858 1859 GO_WINDOW(4); 1860 1861 ep_mii_sync(sc); 1862 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1863 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1864 ep_mii_sendbits(sc, phy, 5); 1865 ep_mii_sendbits(sc, reg, 5); 1866 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1867 ep_mii_sendbits(sc, val, 16); 1868 1869 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1870 ep_mii_setbit(sc, PHYSMGMT_CLK); 1871 1872 GO_WINDOW(1); /* back to operating window */ 1873 } 1874 1875 void 1876 ep_statchg(self) 1877 struct device *self; 1878 { 1879 struct ep_softc *sc = (struct ep_softc *)self; 1880 bus_space_tag_t iot = sc->sc_iot; 1881 bus_space_handle_t ioh = sc->sc_ioh; 1882 int mctl; 1883 1884 /* XXX Update ifp->if_baudrate */ 1885 1886 GO_WINDOW(3); 1887 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 1888 if (sc->sc_mii.mii_media_active & IFM_FDX) 1889 mctl |= MAC_CONTROL_FDX; 1890 else 1891 mctl &= ~MAC_CONTROL_FDX; 1892 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 1893 GO_WINDOW(1); /* back to operating window */ 1894 } 1895