1 /* $OpenBSD: dc.c,v 1.32 2001/08/12 20:12:12 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_dc.c,v 1.43 2001/01/19 23:55:07 wpaul Exp $ 35 */ 36 37 /* 38 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 39 * series chips and several workalikes including the following: 40 * 41 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 42 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 43 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 44 * ASIX Electronics AX88140A (www.asix.com.tw) 45 * ASIX Electronics AX88141 (www.asix.com.tw) 46 * ADMtek AL981 (www.admtek.com.tw) 47 * ADMtek AN983 (www.admtek.com.tw) 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217, EN2242 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include "bpfilter.h" 93 #include "vlan.h" 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/mbuf.h> 98 #include <sys/protosw.h> 99 #include <sys/socket.h> 100 #include <sys/ioctl.h> 101 #include <sys/errno.h> 102 #include <sys/malloc.h> 103 #include <sys/kernel.h> 104 #include <sys/device.h> 105 #include <sys/timeout.h> 106 107 #include <net/if.h> 108 #include <net/if_dl.h> 109 #include <net/if_types.h> 110 111 #ifdef INET 112 #include <netinet/in.h> 113 #include <netinet/in_systm.h> 114 #include <netinet/in_var.h> 115 #include <netinet/ip.h> 116 #include <netinet/if_ether.h> 117 #endif 118 119 #include <net/if_media.h> 120 121 #if NBPFILTER > 0 122 #include <net/bpf.h> 123 #endif 124 125 #include <vm/vm.h> /* for vtophys */ 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 #include <machine/bus.h> 131 #include <dev/pci/pcidevs.h> 132 133 #define DC_USEIOSPACE 134 #ifdef __alpha__ 135 #define SRM_MEDIA 136 #endif 137 138 #include <dev/ic/dcreg.h> 139 140 int dc_intr __P((void *)); 141 void dc_shutdown __P((void *)); 142 struct dc_type *dc_devtype __P((void *)); 143 int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 144 int dc_encap __P((struct dc_softc *, struct mbuf *, u_int32_t *)); 145 int dc_coal __P((struct dc_softc *, struct mbuf **)); 146 147 void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 148 int dc_rx_resync __P((struct dc_softc *)); 149 void dc_rxeof __P((struct dc_softc *)); 150 void dc_txeof __P((struct dc_softc *)); 151 void dc_tick __P((void *)); 152 void dc_start __P((struct ifnet *)); 153 int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 154 void dc_init __P((void *)); 155 void dc_stop __P((struct dc_softc *)); 156 void dc_watchdog __P((struct ifnet *)); 157 int dc_ifmedia_upd __P((struct ifnet *)); 158 void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 159 160 void dc_delay __P((struct dc_softc *)); 161 void dc_eeprom_width __P((struct dc_softc *)); 162 void dc_eeprom_idle __P((struct dc_softc *)); 163 void dc_eeprom_putbyte __P((struct dc_softc *, int)); 164 void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 165 void dc_eeprom_getword_pnic __P((struct dc_softc *, int, u_int16_t *)); 166 void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, int, int)); 167 168 void dc_mii_writebit __P((struct dc_softc *, int)); 169 int dc_mii_readbit __P((struct dc_softc *)); 170 void dc_mii_sync __P((struct dc_softc *)); 171 void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 172 int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 173 int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 174 int dc_miibus_readreg __P((struct device *, int, int)); 175 void dc_miibus_writereg __P((struct device *, int, int, int)); 176 void dc_miibus_statchg __P((struct device *)); 177 178 void dc_setcfg __P((struct dc_softc *, int)); 179 u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 180 u_int32_t dc_crc_be __P((caddr_t)); 181 void dc_setfilt_21143 __P((struct dc_softc *)); 182 void dc_setfilt_asix __P((struct dc_softc *)); 183 void dc_setfilt_admtek __P((struct dc_softc *)); 184 void dc_setfilt_xircom __P((struct dc_softc *)); 185 186 void dc_setfilt __P((struct dc_softc *)); 187 188 void dc_reset __P((struct dc_softc *)); 189 int dc_list_rx_init __P((struct dc_softc *)); 190 int dc_list_tx_init __P((struct dc_softc *)); 191 192 void dc_read_srom __P((struct dc_softc *, int)); 193 void dc_parse_21143_srom __P((struct dc_softc *)); 194 void dc_decode_leaf_sia __P((struct dc_softc *, 195 struct dc_eblock_sia *)); 196 void dc_decode_leaf_mii __P((struct dc_softc *, 197 struct dc_eblock_mii *)); 198 void dc_decode_leaf_sym __P((struct dc_softc *, 199 struct dc_eblock_sym *)); 200 void dc_apply_fixup __P((struct dc_softc *, int)); 201 202 #define DC_SETBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 204 205 #define DC_CLRBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 207 208 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 209 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 210 211 void dc_delay(sc) 212 struct dc_softc *sc; 213 { 214 int idx; 215 216 for (idx = (300 / 33) + 1; idx > 0; idx--) 217 CSR_READ_4(sc, DC_BUSCTL); 218 } 219 220 void dc_eeprom_width(sc) 221 struct dc_softc *sc; 222 { 223 int i; 224 225 /* Force EEPROM to idle state. */ 226 dc_eeprom_idle(sc); 227 228 /* Enter EEPROM access mode. */ 229 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 230 dc_delay(sc); 231 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 232 dc_delay(sc); 233 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 234 dc_delay(sc); 235 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 236 dc_delay(sc); 237 238 for (i = 3; i--;) { 239 if (6 & (1 << i)) 240 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 241 else 242 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 243 dc_delay(sc); 244 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 245 dc_delay(sc); 246 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 247 dc_delay(sc); 248 } 249 250 for (i = 1; i <= 12; i++) { 251 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 252 dc_delay(sc); 253 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 254 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 255 dc_delay(sc); 256 break; 257 } 258 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 259 dc_delay(sc); 260 } 261 262 /* Turn off EEPROM access mode. */ 263 dc_eeprom_idle(sc); 264 265 if (i < 4 || i > 12) 266 sc->dc_romwidth = 6; 267 else 268 sc->dc_romwidth = i; 269 270 /* Enter EEPROM access mode. */ 271 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 272 dc_delay(sc); 273 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 274 dc_delay(sc); 275 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 276 dc_delay(sc); 277 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 278 dc_delay(sc); 279 280 /* Turn off EEPROM access mode. */ 281 dc_eeprom_idle(sc); 282 } 283 284 void dc_eeprom_idle(sc) 285 struct dc_softc *sc; 286 { 287 register int i; 288 289 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 290 dc_delay(sc); 291 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 292 dc_delay(sc); 293 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 294 dc_delay(sc); 295 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 296 dc_delay(sc); 297 298 for (i = 0; i < 25; i++) { 299 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 300 dc_delay(sc); 301 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 302 dc_delay(sc); 303 } 304 305 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 306 dc_delay(sc); 307 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 308 dc_delay(sc); 309 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 310 311 return; 312 } 313 314 /* 315 * Send a read command and address to the EEPROM, check for ACK. 316 */ 317 void dc_eeprom_putbyte(sc, addr) 318 struct dc_softc *sc; 319 int addr; 320 { 321 register int d, i; 322 323 d = DC_EECMD_READ >> 6; 324 325 for (i = 3; i--; ) { 326 if (d & (1 << i)) 327 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 328 else 329 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 330 dc_delay(sc); 331 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 332 dc_delay(sc); 333 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 334 dc_delay(sc); 335 } 336 337 /* 338 * Feed in each bit and strobe the clock. 339 */ 340 for (i = sc->dc_romwidth; i--;) { 341 if (addr & (1 << i)) { 342 SIO_SET(DC_SIO_EE_DATAIN); 343 } else { 344 SIO_CLR(DC_SIO_EE_DATAIN); 345 } 346 dc_delay(sc); 347 SIO_SET(DC_SIO_EE_CLK); 348 dc_delay(sc); 349 SIO_CLR(DC_SIO_EE_CLK); 350 dc_delay(sc); 351 } 352 353 return; 354 } 355 356 /* 357 * Read a word of data stored in the EEPROM at address 'addr.' 358 * The PNIC 82c168/82c169 has its own non-standard way to read 359 * the EEPROM. 360 */ 361 void dc_eeprom_getword_pnic(sc, addr, dest) 362 struct dc_softc *sc; 363 int addr; 364 u_int16_t *dest; 365 { 366 register int i; 367 u_int32_t r; 368 369 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 370 371 for (i = 0; i < DC_TIMEOUT; i++) { 372 DELAY(1); 373 r = CSR_READ_4(sc, DC_SIO); 374 if (!(r & DC_PN_SIOCTL_BUSY)) { 375 *dest = (u_int16_t)(r & 0xFFFF); 376 return; 377 } 378 } 379 380 return; 381 } 382 383 /* 384 * Read a word of data stored in the EEPROM at address 'addr.' 385 */ 386 void dc_eeprom_getword(sc, addr, dest) 387 struct dc_softc *sc; 388 int addr; 389 u_int16_t *dest; 390 { 391 register int i; 392 u_int16_t word = 0; 393 394 /* Force EEPROM to idle state. */ 395 dc_eeprom_idle(sc); 396 397 /* Enter EEPROM access mode. */ 398 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 399 dc_delay(sc); 400 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 401 dc_delay(sc); 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 405 dc_delay(sc); 406 407 /* 408 * Send address of word we want to read. 409 */ 410 dc_eeprom_putbyte(sc, addr); 411 412 /* 413 * Start reading bits from EEPROM. 414 */ 415 for (i = 0x8000; i; i >>= 1) { 416 SIO_SET(DC_SIO_EE_CLK); 417 dc_delay(sc); 418 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 419 word |= i; 420 dc_delay(sc); 421 SIO_CLR(DC_SIO_EE_CLK); 422 dc_delay(sc); 423 } 424 425 /* Turn off EEPROM access mode. */ 426 dc_eeprom_idle(sc); 427 428 *dest = word; 429 430 return; 431 } 432 433 /* 434 * Read a sequence of words from the EEPROM. 435 */ 436 void dc_read_eeprom(sc, dest, off, cnt, swap) 437 struct dc_softc *sc; 438 caddr_t dest; 439 int off; 440 int cnt; 441 int swap; 442 { 443 int i; 444 u_int16_t word = 0, *ptr; 445 446 for (i = 0; i < cnt; i++) { 447 if (DC_IS_PNIC(sc)) 448 dc_eeprom_getword_pnic(sc, off + i, &word); 449 else 450 dc_eeprom_getword(sc, off + i, &word); 451 ptr = (u_int16_t *)(dest + (i * 2)); 452 if (swap) 453 *ptr = ntohs(word); 454 else 455 *ptr = word; 456 } 457 458 return; 459 } 460 461 /* 462 * The following two routines are taken from the Macronix 98713 463 * Application Notes pp.19-21. 464 */ 465 /* 466 * Write a bit to the MII bus. 467 */ 468 void dc_mii_writebit(sc, bit) 469 struct dc_softc *sc; 470 int bit; 471 { 472 if (bit) 473 CSR_WRITE_4(sc, DC_SIO, 474 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 475 else 476 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 477 478 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 479 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 480 481 return; 482 } 483 484 /* 485 * Read a bit from the MII bus. 486 */ 487 int dc_mii_readbit(sc) 488 struct dc_softc *sc; 489 { 490 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 491 CSR_READ_4(sc, DC_SIO); 492 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 493 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 494 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 495 return(1); 496 497 return(0); 498 } 499 500 /* 501 * Sync the PHYs by setting data bit and strobing the clock 32 times. 502 */ 503 void dc_mii_sync(sc) 504 struct dc_softc *sc; 505 { 506 register int i; 507 508 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 509 510 for (i = 0; i < 32; i++) 511 dc_mii_writebit(sc, 1); 512 513 return; 514 } 515 516 /* 517 * Clock a series of bits through the MII. 518 */ 519 void dc_mii_send(sc, bits, cnt) 520 struct dc_softc *sc; 521 u_int32_t bits; 522 int cnt; 523 { 524 int i; 525 526 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 527 dc_mii_writebit(sc, bits & i); 528 } 529 530 /* 531 * Read an PHY register through the MII. 532 */ 533 int dc_mii_readreg(sc, frame) 534 struct dc_softc *sc; 535 struct dc_mii_frame *frame; 536 537 { 538 int i, ack, s; 539 540 s = splimp(); 541 542 /* 543 * Set up frame for RX. 544 */ 545 frame->mii_stdelim = DC_MII_STARTDELIM; 546 frame->mii_opcode = DC_MII_READOP; 547 frame->mii_turnaround = 0; 548 frame->mii_data = 0; 549 550 /* 551 * Sync the PHYs. 552 */ 553 dc_mii_sync(sc); 554 555 /* 556 * Send command/address info. 557 */ 558 dc_mii_send(sc, frame->mii_stdelim, 2); 559 dc_mii_send(sc, frame->mii_opcode, 2); 560 dc_mii_send(sc, frame->mii_phyaddr, 5); 561 dc_mii_send(sc, frame->mii_regaddr, 5); 562 563 #ifdef notdef 564 /* Idle bit */ 565 dc_mii_writebit(sc, 1); 566 dc_mii_writebit(sc, 0); 567 #endif 568 569 /* Check for ack */ 570 ack = dc_mii_readbit(sc); 571 572 /* 573 * Now try reading data bits. If the ack failed, we still 574 * need to clock through 16 cycles to keep the PHY(s) in sync. 575 */ 576 if (ack) { 577 for(i = 0; i < 16; i++) { 578 dc_mii_readbit(sc); 579 } 580 goto fail; 581 } 582 583 for (i = 0x8000; i; i >>= 1) { 584 if (!ack) { 585 if (dc_mii_readbit(sc)) 586 frame->mii_data |= i; 587 } 588 } 589 590 fail: 591 592 dc_mii_writebit(sc, 0); 593 dc_mii_writebit(sc, 0); 594 595 splx(s); 596 597 if (ack) 598 return(1); 599 return(0); 600 } 601 602 /* 603 * Write to a PHY register through the MII. 604 */ 605 int dc_mii_writereg(sc, frame) 606 struct dc_softc *sc; 607 struct dc_mii_frame *frame; 608 609 { 610 int s; 611 612 s = splimp(); 613 /* 614 * Set up frame for TX. 615 */ 616 617 frame->mii_stdelim = DC_MII_STARTDELIM; 618 frame->mii_opcode = DC_MII_WRITEOP; 619 frame->mii_turnaround = DC_MII_TURNAROUND; 620 621 /* 622 * Sync the PHYs. 623 */ 624 dc_mii_sync(sc); 625 626 dc_mii_send(sc, frame->mii_stdelim, 2); 627 dc_mii_send(sc, frame->mii_opcode, 2); 628 dc_mii_send(sc, frame->mii_phyaddr, 5); 629 dc_mii_send(sc, frame->mii_regaddr, 5); 630 dc_mii_send(sc, frame->mii_turnaround, 2); 631 dc_mii_send(sc, frame->mii_data, 16); 632 633 /* Idle bit. */ 634 dc_mii_writebit(sc, 0); 635 dc_mii_writebit(sc, 0); 636 637 splx(s); 638 639 return(0); 640 } 641 642 int dc_miibus_readreg(self, phy, reg) 643 struct device *self; 644 int phy, reg; 645 { 646 struct dc_mii_frame frame; 647 struct dc_softc *sc = (struct dc_softc *)self; 648 int i, rval, phy_reg; 649 650 bzero((char *)&frame, sizeof(frame)); 651 652 /* 653 * Note: both the AL981 and AN983 have internal PHYs, 654 * however the AL981 provides direct access to the PHY 655 * registers while the AN983 uses a serial MII interface. 656 * The AN983's MII interface is also buggy in that you 657 * can read from any MII address (0 to 31), but only address 1 658 * behaves normally. To deal with both cases, we pretend 659 * that the PHY is at MII address 1. 660 */ 661 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 662 return(0); 663 664 if (sc->dc_pmode != DC_PMODE_MII) { 665 if (phy == (MII_NPHY - 1)) { 666 switch(reg) { 667 case MII_BMSR: 668 /* 669 * Fake something to make the probe 670 * code think there's a PHY here. 671 */ 672 return(BMSR_MEDIAMASK); 673 break; 674 case MII_PHYIDR1: 675 if (DC_IS_PNIC(sc)) 676 return(PCI_VENDOR_LITEON); 677 return(PCI_VENDOR_DEC); 678 break; 679 case MII_PHYIDR2: 680 if (DC_IS_PNIC(sc)) 681 return(PCI_PRODUCT_LITEON_PNIC); 682 return(PCI_PRODUCT_DEC_21142); 683 break; 684 default: 685 return(0); 686 break; 687 } 688 } else 689 return(0); 690 } 691 692 if (DC_IS_PNIC(sc)) { 693 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 694 (phy << 23) | (reg << 18)); 695 for (i = 0; i < DC_TIMEOUT; i++) { 696 DELAY(1); 697 rval = CSR_READ_4(sc, DC_PN_MII); 698 if (!(rval & DC_PN_MII_BUSY)) { 699 rval &= 0xFFFF; 700 return(rval == 0xFFFF ? 0 : rval); 701 } 702 } 703 return(0); 704 } 705 706 if (DC_IS_COMET(sc)) { 707 switch(reg) { 708 case MII_BMCR: 709 phy_reg = DC_AL_BMCR; 710 break; 711 case MII_BMSR: 712 phy_reg = DC_AL_BMSR; 713 break; 714 case MII_PHYIDR1: 715 phy_reg = DC_AL_VENID; 716 break; 717 case MII_PHYIDR2: 718 phy_reg = DC_AL_DEVID; 719 break; 720 case MII_ANAR: 721 phy_reg = DC_AL_ANAR; 722 break; 723 case MII_ANLPAR: 724 phy_reg = DC_AL_LPAR; 725 break; 726 case MII_ANER: 727 phy_reg = DC_AL_ANER; 728 break; 729 default: 730 printf("dc%d: phy_read: bad phy register %x\n", 731 sc->dc_unit, reg); 732 return(0); 733 break; 734 } 735 736 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 737 738 if (rval == 0xFFFF) 739 return(0); 740 return(rval); 741 } 742 743 frame.mii_phyaddr = phy; 744 frame.mii_regaddr = reg; 745 if (sc->dc_type == DC_TYPE_98713) { 746 phy_reg = CSR_READ_4(sc, DC_NETCFG); 747 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 748 } 749 dc_mii_readreg(sc, &frame); 750 if (sc->dc_type == DC_TYPE_98713) 751 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 752 753 return(frame.mii_data); 754 } 755 756 void dc_miibus_writereg(self, phy, reg, data) 757 struct device *self; 758 int phy, reg, data; 759 { 760 struct dc_softc *sc = (struct dc_softc *)self; 761 struct dc_mii_frame frame; 762 int i, phy_reg; 763 764 bzero((char *)&frame, sizeof(frame)); 765 766 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 767 return; 768 769 if (DC_IS_PNIC(sc)) { 770 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 771 (phy << 23) | (reg << 10) | data); 772 for (i = 0; i < DC_TIMEOUT; i++) { 773 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 774 break; 775 } 776 return; 777 } 778 779 if (DC_IS_COMET(sc)) { 780 switch(reg) { 781 case MII_BMCR: 782 phy_reg = DC_AL_BMCR; 783 break; 784 case MII_BMSR: 785 phy_reg = DC_AL_BMSR; 786 break; 787 case MII_PHYIDR1: 788 phy_reg = DC_AL_VENID; 789 break; 790 case MII_PHYIDR2: 791 phy_reg = DC_AL_DEVID; 792 break; 793 case MII_ANAR: 794 phy_reg = DC_AL_ANAR; 795 break; 796 case MII_ANLPAR: 797 phy_reg = DC_AL_LPAR; 798 break; 799 case MII_ANER: 800 phy_reg = DC_AL_ANER; 801 break; 802 default: 803 printf("dc%d: phy_write: bad phy register %x\n", 804 sc->dc_unit, reg); 805 return; 806 break; 807 } 808 809 CSR_WRITE_4(sc, phy_reg, data); 810 return; 811 } 812 813 frame.mii_phyaddr = phy; 814 frame.mii_regaddr = reg; 815 frame.mii_data = data; 816 817 if (sc->dc_type == DC_TYPE_98713) { 818 phy_reg = CSR_READ_4(sc, DC_NETCFG); 819 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 820 } 821 dc_mii_writereg(sc, &frame); 822 if (sc->dc_type == DC_TYPE_98713) 823 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 824 825 return; 826 } 827 828 void dc_miibus_statchg(self) 829 struct device *self; 830 { 831 struct dc_softc *sc = (struct dc_softc *)self; 832 struct mii_data *mii; 833 struct ifmedia *ifm; 834 835 if (DC_IS_ADMTEK(sc)) 836 return; 837 838 mii = &sc->sc_mii; 839 ifm = &mii->mii_media; 840 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 841 dc_setcfg(sc, ifm->ifm_media); 842 sc->dc_if_media = ifm->ifm_media; 843 } else { 844 dc_setcfg(sc, mii->mii_media_active); 845 sc->dc_if_media = mii->mii_media_active; 846 } 847 848 return; 849 } 850 851 #define DC_POLY 0xEDB88320 852 #define DC_BITS_512 9 853 #define DC_BITS_128 7 854 #define DC_BITS_64 6 855 856 u_int32_t dc_crc_le(sc, addr) 857 struct dc_softc *sc; 858 caddr_t addr; 859 { 860 u_int32_t idx, bit, data, crc; 861 862 /* Compute CRC for the address value. */ 863 crc = 0xFFFFFFFF; /* initial value */ 864 865 for (idx = 0; idx < 6; idx++) { 866 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 867 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 868 } 869 870 /* 871 * The hash table on the PNIC II and the MX98715AEC-C/D/E 872 * chips is only 128 bits wide. 873 */ 874 if (sc->dc_flags & DC_128BIT_HASH) 875 return (crc & ((1 << DC_BITS_128) - 1)); 876 877 /* The hash table on the MX98715BEC is only 64 bits wide. */ 878 if (sc->dc_flags & DC_64BIT_HASH) 879 return (crc & ((1 << DC_BITS_64) - 1)); 880 881 /* Xircom's hash filtering table is different (read: weird) */ 882 /* Xircom uses the LEAST significant bits */ 883 if (DC_IS_XIRCOM(sc)) { 884 if ((crc & 0x180) == 0x180) 885 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 886 else 887 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 888 } 889 890 return (crc & ((1 << DC_BITS_512) - 1)); 891 } 892 893 /* 894 * Calculate CRC of a multicast group address, return the lower 6 bits. 895 */ 896 u_int32_t dc_crc_be(addr) 897 caddr_t addr; 898 { 899 u_int32_t crc, carry; 900 int i, j; 901 u_int8_t c; 902 903 /* Compute CRC for the address value. */ 904 crc = 0xFFFFFFFF; /* initial value */ 905 906 for (i = 0; i < 6; i++) { 907 c = *(addr + i); 908 for (j = 0; j < 8; j++) { 909 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 910 crc <<= 1; 911 c >>= 1; 912 if (carry) 913 crc = (crc ^ 0x04c11db6) | carry; 914 } 915 } 916 917 /* return the filter bit position */ 918 return((crc >> 26) & 0x0000003F); 919 } 920 921 /* 922 * 21143-style RX filter setup routine. Filter programming is done by 923 * downloading a special setup frame into the TX engine. 21143, Macronix, 924 * PNIC, PNIC II and Davicom chips are programmed this way. 925 * 926 * We always program the chip using 'hash perfect' mode, i.e. one perfect 927 * address (our node address) and a 512-bit hash filter for multicast 928 * frames. We also sneak the broadcast address into the hash filter since 929 * we need that too. 930 */ 931 void dc_setfilt_21143(sc) 932 struct dc_softc *sc; 933 { 934 struct dc_desc *sframe; 935 u_int32_t h, *sp; 936 struct arpcom *ac = &sc->arpcom; 937 struct ether_multi *enm; 938 struct ether_multistep step; 939 struct ifnet *ifp; 940 int i; 941 942 ifp = &sc->arpcom.ac_if; 943 944 i = sc->dc_cdata.dc_tx_prod; 945 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 946 sc->dc_cdata.dc_tx_cnt++; 947 sframe = &sc->dc_ldata->dc_tx_list[i]; 948 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 949 bzero((char *)sp, DC_SFRAME_LEN); 950 951 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 952 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 953 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 954 955 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 956 957 /* If we want promiscuous mode, set the allframes bit. */ 958 if (ifp->if_flags & IFF_PROMISC) 959 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 960 else 961 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 962 963 if (ifp->if_flags & IFF_ALLMULTI) 964 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 965 else 966 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 967 968 ETHER_FIRST_MULTI(step, ac, enm); 969 while (enm != NULL) { 970 h = dc_crc_le(sc, enm->enm_addrlo); 971 sp[h >> 4] |= 1 << (h & 0xF); 972 ETHER_NEXT_MULTI(step, enm); 973 } 974 975 if (ifp->if_flags & IFF_BROADCAST) { 976 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 977 sp[h >> 4] |= 1 << (h & 0xF); 978 } 979 980 /* Set our MAC address */ 981 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 982 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 983 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 984 985 sframe->dc_status = DC_TXSTAT_OWN; 986 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 987 988 /* 989 * The PNIC takes an exceedingly long time to process its 990 * setup frame; wait 10ms after posting the setup frame 991 * before proceeding, just so it has time to swallow its 992 * medicine. 993 */ 994 DELAY(10000); 995 996 ifp->if_timer = 5; 997 998 return; 999 } 1000 1001 void dc_setfilt_admtek(sc) 1002 struct dc_softc *sc; 1003 { 1004 struct ifnet *ifp; 1005 struct arpcom *ac = &sc->arpcom; 1006 struct ether_multi *enm; 1007 struct ether_multistep step; 1008 int h = 0; 1009 u_int32_t hashes[2] = { 0, 0 }; 1010 1011 ifp = &sc->arpcom.ac_if; 1012 1013 /* Init our MAC address */ 1014 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1015 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1016 1017 /* If we want promiscuous mode, set the allframes bit. */ 1018 if (ifp->if_flags & IFF_PROMISC) 1019 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1020 else 1021 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1022 1023 if (ifp->if_flags & IFF_ALLMULTI) 1024 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1025 else 1026 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1027 1028 /* first, zot all the existing hash bits */ 1029 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1030 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1031 1032 /* 1033 * If we're already in promisc or allmulti mode, we 1034 * don't have to bother programming the multicast filter. 1035 */ 1036 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1037 return; 1038 1039 /* now program new ones */ 1040 ETHER_FIRST_MULTI(step, ac, enm); 1041 while (enm != NULL) { 1042 h = dc_crc_be(enm->enm_addrlo); 1043 if (h < 32) 1044 hashes[0] |= (1 << h); 1045 else 1046 hashes[1] |= (1 << (h - 32)); 1047 ETHER_NEXT_MULTI(step, enm); 1048 } 1049 1050 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1051 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1052 1053 return; 1054 } 1055 1056 void dc_setfilt_asix(sc) 1057 struct dc_softc *sc; 1058 { 1059 struct ifnet *ifp; 1060 struct arpcom *ac = &sc->arpcom; 1061 struct ether_multi *enm; 1062 struct ether_multistep step; 1063 int h = 0; 1064 u_int32_t hashes[2] = { 0, 0 }; 1065 1066 ifp = &sc->arpcom.ac_if; 1067 1068 /* Init our MAC address */ 1069 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1070 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1071 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1072 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1073 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1074 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1075 1076 /* If we want promiscuous mode, set the allframes bit. */ 1077 if (ifp->if_flags & IFF_PROMISC) 1078 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1079 else 1080 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1081 1082 if (ifp->if_flags & IFF_ALLMULTI) 1083 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1084 else 1085 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1086 1087 /* 1088 * The ASIX chip has a special bit to enable reception 1089 * of broadcast frames. 1090 */ 1091 if (ifp->if_flags & IFF_BROADCAST) 1092 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1093 else 1094 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1095 1096 /* first, zot all the existing hash bits */ 1097 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1098 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1099 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1100 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1101 1102 /* 1103 * If we're already in promisc or allmulti mode, we 1104 * don't have to bother programming the multicast filter. 1105 */ 1106 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1107 return; 1108 1109 /* now program new ones */ 1110 ETHER_FIRST_MULTI(step, ac, enm); 1111 while (enm != NULL) { 1112 h = dc_crc_be(enm->enm_addrlo); 1113 if (h < 32) 1114 hashes[0] |= (1 << h); 1115 else 1116 hashes[1] |= (1 << (h - 32)); 1117 ETHER_NEXT_MULTI(step, enm); 1118 } 1119 1120 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1121 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1122 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1123 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1124 1125 return; 1126 } 1127 1128 void dc_setfilt_xircom(sc) 1129 struct dc_softc *sc; 1130 { 1131 struct dc_desc *sframe; 1132 struct arpcom *ac = &sc->arpcom; 1133 struct ether_multi *enm; 1134 struct ether_multistep step; 1135 u_int32_t h, *sp; 1136 struct ifnet *ifp; 1137 int i; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1141 1142 i = sc->dc_cdata.dc_tx_prod; 1143 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1144 sc->dc_cdata.dc_tx_cnt++; 1145 sframe = &sc->dc_ldata->dc_tx_list[i]; 1146 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1147 bzero((char *)sp, DC_SFRAME_LEN); 1148 1149 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1150 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1151 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1152 1153 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1154 1155 /* If we want promiscuous mode, set the allframes bit. */ 1156 if (ifp->if_flags & IFF_PROMISC) 1157 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1158 else 1159 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1160 1161 if (ifp->if_flags & IFF_ALLMULTI) 1162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1163 else 1164 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1165 1166 /* now program new ones */ 1167 ETHER_FIRST_MULTI(step, ac, enm); 1168 while (enm != NULL) { 1169 h = dc_crc_le(sc, enm->enm_addrlo); 1170 sp[h >> 4] |= 1 << (h & 0xF); 1171 ETHER_NEXT_MULTI(step, enm); 1172 } 1173 1174 if (ifp->if_flags & IFF_BROADCAST) { 1175 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1176 sp[h >> 4] |= 1 << (h & 0xF); 1177 } 1178 1179 /* Set our MAC address */ 1180 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1181 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1182 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1183 1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1185 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1186 ifp->if_flags |= IFF_RUNNING; 1187 sframe->dc_status = DC_TXSTAT_OWN; 1188 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1189 1190 /* 1191 * wait some time... 1192 */ 1193 DELAY(1000); 1194 1195 ifp->if_timer = 5; 1196 1197 return; 1198 } 1199 1200 void dc_setfilt(sc) 1201 struct dc_softc *sc; 1202 { 1203 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1204 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1205 dc_setfilt_21143(sc); 1206 1207 if (DC_IS_ASIX(sc)) 1208 dc_setfilt_asix(sc); 1209 1210 if (DC_IS_ADMTEK(sc)) 1211 dc_setfilt_admtek(sc); 1212 1213 if (DC_IS_XIRCOM(sc)) 1214 dc_setfilt_xircom(sc); 1215 1216 return; 1217 } 1218 1219 /* 1220 * In order to fiddle with the 1221 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1222 * first have to put the transmit and/or receive logic in the idle state. 1223 */ 1224 void dc_setcfg(sc, media) 1225 struct dc_softc *sc; 1226 int media; 1227 { 1228 int i, restart = 0; 1229 u_int32_t isr; 1230 1231 if (IFM_SUBTYPE(media) == IFM_NONE) 1232 return; 1233 1234 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1235 restart = 1; 1236 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1237 1238 for (i = 0; i < DC_TIMEOUT; i++) { 1239 DELAY(10); 1240 isr = CSR_READ_4(sc, DC_ISR); 1241 if (isr & DC_ISR_TX_IDLE || 1242 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1243 break; 1244 } 1245 1246 if (i == DC_TIMEOUT) 1247 printf("dc%d: failed to force tx and " 1248 "rx to idle state\n", sc->dc_unit); 1249 1250 } 1251 1252 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1253 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1254 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1255 if (sc->dc_pmode == DC_PMODE_MII) { 1256 int watchdogreg; 1257 1258 if (DC_IS_INTEL(sc)) { 1259 /* there's a write enable bit here that reads as 1 */ 1260 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1261 watchdogreg &= ~DC_WDOG_CTLWREN; 1262 watchdogreg |= DC_WDOG_JABBERDIS; 1263 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1264 } else { 1265 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1266 } 1267 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1268 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1269 if (sc->dc_type == DC_TYPE_98713) 1270 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1271 DC_NETCFG_SCRAMBLER)); 1272 if (!DC_IS_DAVICOM(sc)) 1273 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1274 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1275 if (DC_IS_INTEL(sc)) 1276 dc_apply_fixup(sc, IFM_AUTO); 1277 } else { 1278 if (DC_IS_PNIC(sc)) { 1279 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1280 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1281 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1282 } 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1284 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1285 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1286 if (DC_IS_INTEL(sc)) 1287 dc_apply_fixup(sc, 1288 (media & IFM_GMASK) == IFM_FDX ? 1289 IFM_100_TX|IFM_FDX : IFM_100_TX); 1290 } 1291 } 1292 1293 if (IFM_SUBTYPE(media) == IFM_10_T) { 1294 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1295 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1296 if (sc->dc_pmode == DC_PMODE_MII) { 1297 int watchdogreg; 1298 1299 if (DC_IS_INTEL(sc)) { 1300 /* there's a write enable bit here that reads as 1 */ 1301 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1302 watchdogreg &= ~DC_WDOG_CTLWREN; 1303 watchdogreg |= DC_WDOG_JABBERDIS; 1304 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1305 } else { 1306 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1307 } 1308 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1309 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1310 if (sc->dc_type == DC_TYPE_98713) 1311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1312 if (!DC_IS_DAVICOM(sc)) 1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1314 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1315 if (DC_IS_INTEL(sc)) 1316 dc_apply_fixup(sc, IFM_AUTO); 1317 } else { 1318 if (DC_IS_PNIC(sc)) { 1319 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1320 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1321 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1322 } 1323 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1324 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1325 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1326 if (DC_IS_INTEL(sc)) { 1327 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1328 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1329 if ((media & IFM_GMASK) == IFM_FDX) 1330 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1331 else 1332 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1333 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1334 DC_CLRBIT(sc, DC_10BTCTRL, 1335 DC_TCTL_AUTONEGENBL); 1336 dc_apply_fixup(sc, 1337 (media & IFM_GMASK) == IFM_FDX ? 1338 IFM_10_T|IFM_FDX : IFM_10_T); 1339 DELAY(20000); 1340 } 1341 } 1342 } 1343 1344 /* 1345 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1346 * PHY and we want HomePNA mode, set the portsel bit to turn 1347 * on the external MII port. 1348 */ 1349 if (DC_IS_DAVICOM(sc)) { 1350 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1352 sc->dc_link = 1; 1353 } else { 1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1355 } 1356 } 1357 1358 if ((media & IFM_GMASK) == IFM_FDX) { 1359 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1360 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1361 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1362 } else { 1363 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1364 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1365 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1366 } 1367 1368 if (restart) 1369 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1370 1371 return; 1372 } 1373 1374 void dc_reset(sc) 1375 struct dc_softc *sc; 1376 { 1377 register int i; 1378 1379 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1380 1381 for (i = 0; i < DC_TIMEOUT; i++) { 1382 DELAY(10); 1383 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1384 break; 1385 } 1386 1387 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) || 1388 DC_IS_INTEL(sc)) { 1389 DELAY(10000); 1390 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1391 i = 0; 1392 } 1393 1394 if (i == DC_TIMEOUT) 1395 printf("dc%d: reset never completed!\n", sc->dc_unit); 1396 1397 /* Wait a little while for the chip to get its brains in order. */ 1398 DELAY(1000); 1399 1400 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1401 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1402 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1403 1404 /* 1405 * Bring the SIA out of reset. In some cases, it looks 1406 * like failing to unreset the SIA soon enough gets it 1407 * into a state where it will never come out of reset 1408 * until we reset the whole chip again. 1409 */ 1410 if (DC_IS_INTEL(sc)) { 1411 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1412 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1413 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1414 } 1415 1416 return; 1417 } 1418 1419 void dc_apply_fixup(sc, media) 1420 struct dc_softc *sc; 1421 int media; 1422 { 1423 struct dc_mediainfo *m; 1424 u_int8_t *p; 1425 int i; 1426 u_int32_t reg; 1427 1428 m = sc->dc_mi; 1429 1430 while (m != NULL) { 1431 if (m->dc_media == media) 1432 break; 1433 m = m->dc_next; 1434 } 1435 1436 if (m == NULL) 1437 return; 1438 1439 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1440 reg = (p[0] | (p[1] << 8)) << 16; 1441 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1442 } 1443 1444 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1445 reg = (p[0] | (p[1] << 8)) << 16; 1446 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1447 } 1448 1449 return; 1450 } 1451 1452 void dc_decode_leaf_sia(sc, l) 1453 struct dc_softc *sc; 1454 struct dc_eblock_sia *l; 1455 { 1456 struct dc_mediainfo *m; 1457 1458 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1459 bzero(m, sizeof(struct dc_mediainfo)); 1460 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1461 m->dc_media = IFM_10_T; 1462 1463 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1464 m->dc_media = IFM_10_T|IFM_FDX; 1465 1466 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1467 m->dc_media = IFM_10_2; 1468 1469 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1470 m->dc_media = IFM_10_5; 1471 1472 m->dc_gp_len = 2; 1473 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1474 1475 m->dc_next = sc->dc_mi; 1476 sc->dc_mi = m; 1477 1478 sc->dc_pmode = DC_PMODE_SIA; 1479 1480 return; 1481 } 1482 1483 void dc_decode_leaf_sym(sc, l) 1484 struct dc_softc *sc; 1485 struct dc_eblock_sym *l; 1486 { 1487 struct dc_mediainfo *m; 1488 1489 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1490 bzero(m, sizeof(struct dc_mediainfo)); 1491 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1492 m->dc_media = IFM_100_TX; 1493 1494 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1495 m->dc_media = IFM_100_TX|IFM_FDX; 1496 1497 m->dc_gp_len = 2; 1498 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1499 1500 m->dc_next = sc->dc_mi; 1501 sc->dc_mi = m; 1502 1503 sc->dc_pmode = DC_PMODE_SYM; 1504 1505 return; 1506 } 1507 1508 void dc_decode_leaf_mii(sc, l) 1509 struct dc_softc *sc; 1510 struct dc_eblock_mii *l; 1511 { 1512 u_int8_t *p; 1513 struct dc_mediainfo *m; 1514 1515 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1516 bzero(m, sizeof(struct dc_mediainfo)); 1517 /* We abuse IFM_AUTO to represent MII. */ 1518 m->dc_media = IFM_AUTO; 1519 m->dc_gp_len = l->dc_gpr_len; 1520 1521 p = (u_int8_t *)l; 1522 p += sizeof(struct dc_eblock_mii); 1523 m->dc_gp_ptr = p; 1524 p += 2 * l->dc_gpr_len; 1525 m->dc_reset_len = *p; 1526 p++; 1527 m->dc_reset_ptr = p; 1528 1529 m->dc_next = sc->dc_mi; 1530 sc->dc_mi = m; 1531 1532 return; 1533 } 1534 1535 void dc_read_srom(sc, bits) 1536 struct dc_softc *sc; 1537 int bits; 1538 { 1539 int size; 1540 1541 size = 2 << bits; 1542 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1543 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1544 } 1545 1546 void dc_parse_21143_srom(sc) 1547 struct dc_softc *sc; 1548 { 1549 struct dc_leaf_hdr *lhdr; 1550 struct dc_eblock_hdr *hdr; 1551 int i, loff; 1552 char *ptr; 1553 1554 loff = sc->dc_srom[27]; 1555 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1556 1557 ptr = (char *)lhdr; 1558 ptr += sizeof(struct dc_leaf_hdr) - 1; 1559 for (i = 0; i < lhdr->dc_mcnt; i++) { 1560 hdr = (struct dc_eblock_hdr *)ptr; 1561 switch(hdr->dc_type) { 1562 case DC_EBLOCK_MII: 1563 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1564 break; 1565 case DC_EBLOCK_SIA: 1566 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1567 break; 1568 case DC_EBLOCK_SYM: 1569 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1570 break; 1571 default: 1572 /* Don't care. Yet. */ 1573 break; 1574 } 1575 ptr += (hdr->dc_len & 0x7F); 1576 ptr++; 1577 } 1578 1579 return; 1580 } 1581 1582 /* 1583 * Attach the interface. Allocate softc structures, do ifmedia 1584 * setup and ethernet/BPF attach. 1585 */ 1586 void dc_attach(sc) 1587 struct dc_softc *sc; 1588 { 1589 struct ifnet *ifp; 1590 int error = 0, mac_offset, tmp; 1591 1592 /* 1593 * Get station address from the EEPROM. 1594 */ 1595 switch(sc->dc_type) { 1596 case DC_TYPE_98713: 1597 case DC_TYPE_98713A: 1598 case DC_TYPE_987x5: 1599 case DC_TYPE_PNICII: 1600 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1601 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1602 dc_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1603 (mac_offset / 2), 3, 0); 1604 break; 1605 case DC_TYPE_PNIC: 1606 dc_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 1); 1607 break; 1608 case DC_TYPE_DM9102: 1609 case DC_TYPE_21143: 1610 case DC_TYPE_ASIX: 1611 dc_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1612 DC_EE_NODEADDR, 3, 0); 1613 break; 1614 case DC_TYPE_AL981: 1615 case DC_TYPE_AN983: 1616 dc_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1617 DC_AL_EE_NODEADDR, 3, 0); 1618 break; 1619 case DC_TYPE_XIRCOM: 1620 break; 1621 default: 1622 dc_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1623 DC_EE_NODEADDR, 3, 0); 1624 break; 1625 } 1626 1627 /* 1628 * A 21143 or clone chip was detected. Inform the world. 1629 */ 1630 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 1631 1632 sc->dc_ldata_ptr = malloc(sizeof(struct dc_list_data), M_DEVBUF, 1633 M_NOWAIT); 1634 if (sc->dc_ldata_ptr == NULL) { 1635 printf("%s: no memory for list buffers!\n", sc->dc_unit); 1636 goto fail; 1637 } 1638 1639 sc->dc_ldata = (struct dc_list_data *)sc->dc_ldata_ptr; 1640 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1641 1642 ifp = &sc->arpcom.ac_if; 1643 ifp->if_softc = sc; 1644 ifp->if_mtu = ETHERMTU; 1645 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1646 ifp->if_ioctl = dc_ioctl; 1647 ifp->if_output = ether_output; 1648 ifp->if_start = dc_start; 1649 ifp->if_watchdog = dc_watchdog; 1650 ifp->if_baudrate = 10000000; 1651 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 1652 IFQ_SET_READY(&ifp->if_snd); 1653 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1654 1655 #if NVLAN > 0 1656 ifp->if_capabilities = IFCAP_VLAN_MTU; 1657 #endif 1658 1659 /* Do MII setup. If this is a 21143, check for a PHY on the 1660 * MII bus after applying any necessary fixups to twiddle the 1661 * GPIO bits. If we don't end up finding a PHY, restore the 1662 * old selection (SIA only or SIA/SYM) and attach the dcphy 1663 * driver instead. 1664 */ 1665 if (DC_IS_INTEL(sc)) { 1666 dc_apply_fixup(sc, IFM_AUTO); 1667 tmp = sc->dc_pmode; 1668 sc->dc_pmode = DC_PMODE_MII; 1669 } 1670 1671 sc->sc_mii.mii_ifp = ifp; 1672 sc->sc_mii.mii_readreg = dc_miibus_readreg; 1673 sc->sc_mii.mii_writereg = dc_miibus_writereg; 1674 sc->sc_mii.mii_statchg = dc_miibus_statchg; 1675 ifmedia_init(&sc->sc_mii.mii_media, 0, dc_ifmedia_upd, dc_ifmedia_sts); 1676 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1677 MII_OFFSET_ANY, 0); 1678 1679 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1680 error = ENXIO; 1681 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1682 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1683 } else 1684 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1685 1686 if (DC_IS_DAVICOM(sc) && sc->dc_revision >= DC_REVISION_DM9102A) 1687 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_HPNA_1,0,NULL); 1688 1689 if (DC_IS_INTEL(sc)) { 1690 if (error) { 1691 sc->dc_pmode = tmp; 1692 if (sc->dc_pmode != DC_PMODE_SIA) 1693 sc->dc_pmode = DC_PMODE_SYM; 1694 sc->dc_flags |= DC_21143_NWAY; 1695 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 1696 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1697 error = 0; 1698 } else { 1699 /* we have a PHY, so we must clear this bit */ 1700 sc->dc_flags &= ~DC_TULIP_LEDS; 1701 } 1702 } 1703 1704 if (error) { 1705 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1706 error = ENXIO; 1707 goto fail; 1708 } 1709 1710 if (DC_IS_XIRCOM(sc)) { 1711 /* 1712 * setup General Purpose Port mode and data so the tulip 1713 * can talk to the MII. 1714 */ 1715 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 1716 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 1717 DELAY(10); 1718 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 1719 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 1720 DELAY(10); 1721 } 1722 1723 /* 1724 * Call MI attach routines. 1725 */ 1726 if_attach(ifp); 1727 ether_ifattach(ifp); 1728 1729 sc->sc_dhook = shutdownhook_establish(dc_shutdown, sc); 1730 1731 fail: 1732 return; 1733 } 1734 1735 int dc_detach(sc) 1736 struct dc_softc *sc; 1737 { 1738 struct ifnet *ifp = &sc->arpcom.ac_if; 1739 1740 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL) 1741 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1742 1743 if (sc->dc_srom) 1744 free(sc->dc_srom, M_DEVBUF); 1745 1746 timeout_del(&sc->dc_tick_tmo); 1747 1748 ether_ifdetach(ifp); 1749 if_detach(ifp); 1750 1751 shutdownhook_disestablish(sc->sc_dhook); 1752 1753 return (0); 1754 } 1755 1756 /* 1757 * Initialize the transmit descriptors. 1758 */ 1759 int dc_list_tx_init(sc) 1760 struct dc_softc *sc; 1761 { 1762 struct dc_chain_data *cd; 1763 struct dc_list_data *ld; 1764 int i; 1765 1766 cd = &sc->dc_cdata; 1767 ld = sc->dc_ldata; 1768 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1769 if (i == (DC_TX_LIST_CNT - 1)) { 1770 ld->dc_tx_list[i].dc_next = 1771 vtophys(&ld->dc_tx_list[0]); 1772 } else { 1773 ld->dc_tx_list[i].dc_next = 1774 vtophys(&ld->dc_tx_list[i + 1]); 1775 } 1776 cd->dc_tx_chain[i] = NULL; 1777 ld->dc_tx_list[i].dc_data = 0; 1778 ld->dc_tx_list[i].dc_ctl = 0; 1779 } 1780 1781 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1782 1783 return(0); 1784 } 1785 1786 1787 /* 1788 * Initialize the RX descriptors and allocate mbufs for them. Note that 1789 * we arrange the descriptors in a closed ring, so that the last descriptor 1790 * points back to the first. 1791 */ 1792 int dc_list_rx_init(sc) 1793 struct dc_softc *sc; 1794 { 1795 struct dc_chain_data *cd; 1796 struct dc_list_data *ld; 1797 int i; 1798 1799 cd = &sc->dc_cdata; 1800 ld = sc->dc_ldata; 1801 1802 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1803 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1804 return(ENOBUFS); 1805 if (i == (DC_RX_LIST_CNT - 1)) { 1806 ld->dc_rx_list[i].dc_next = 1807 vtophys(&ld->dc_rx_list[0]); 1808 } else { 1809 ld->dc_rx_list[i].dc_next = 1810 vtophys(&ld->dc_rx_list[i + 1]); 1811 } 1812 } 1813 1814 cd->dc_rx_prod = 0; 1815 1816 return(0); 1817 } 1818 1819 /* 1820 * Initialize an RX descriptor and attach an MBUF cluster. 1821 */ 1822 int dc_newbuf(sc, i, m) 1823 struct dc_softc *sc; 1824 int i; 1825 struct mbuf *m; 1826 { 1827 struct mbuf *m_new = NULL; 1828 struct dc_desc *c; 1829 1830 c = &sc->dc_ldata->dc_rx_list[i]; 1831 1832 if (m == NULL) { 1833 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1834 if (m_new == NULL) { 1835 printf("dc%d: no memory for rx list " 1836 "-- packet dropped!\n", sc->dc_unit); 1837 return(ENOBUFS); 1838 } 1839 1840 MCLGET(m_new, M_DONTWAIT); 1841 if (!(m_new->m_flags & M_EXT)) { 1842 printf("dc%d: no memory for rx list " 1843 "-- packet dropped!\n", sc->dc_unit); 1844 m_freem(m_new); 1845 return(ENOBUFS); 1846 } 1847 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1848 } else { 1849 m_new = m; 1850 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1851 m_new->m_data = m_new->m_ext.ext_buf; 1852 } 1853 1854 m_adj(m_new, sizeof(u_int64_t)); 1855 1856 /* 1857 * If this is a PNIC chip, zero the buffer. This is part 1858 * of the workaround for the receive bug in the 82c168 and 1859 * 82c169 chips. 1860 */ 1861 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1862 bzero((char *)mtod(m_new, char *), m_new->m_len); 1863 1864 sc->dc_cdata.dc_rx_chain[i] = m_new; 1865 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1866 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1867 c->dc_status = DC_RXSTAT_OWN; 1868 1869 return(0); 1870 } 1871 1872 /* 1873 * Grrrrr. 1874 * The PNIC chip has a terrible bug in it that manifests itself during 1875 * periods of heavy activity. The exact mode of failure if difficult to 1876 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1877 * will happen on slow machines. The bug is that sometimes instead of 1878 * uploading one complete frame during reception, it uploads what looks 1879 * like the entire contents of its FIFO memory. The frame we want is at 1880 * the end of the whole mess, but we never know exactly how much data has 1881 * been uploaded, so salvaging the frame is hard. 1882 * 1883 * There is only one way to do it reliably, and it's disgusting. 1884 * Here's what we know: 1885 * 1886 * - We know there will always be somewhere between one and three extra 1887 * descriptors uploaded. 1888 * 1889 * - We know the desired received frame will always be at the end of the 1890 * total data upload. 1891 * 1892 * - We know the size of the desired received frame because it will be 1893 * provided in the length field of the status word in the last descriptor. 1894 * 1895 * Here's what we do: 1896 * 1897 * - When we allocate buffers for the receive ring, we bzero() them. 1898 * This means that we know that the buffer contents should be all 1899 * zeros, except for data uploaded by the chip. 1900 * 1901 * - We also force the PNIC chip to upload frames that include the 1902 * ethernet CRC at the end. 1903 * 1904 * - We gather all of the bogus frame data into a single buffer. 1905 * 1906 * - We then position a pointer at the end of this buffer and scan 1907 * backwards until we encounter the first non-zero byte of data. 1908 * This is the end of the received frame. We know we will encounter 1909 * some data at the end of the frame because the CRC will always be 1910 * there, so even if the sender transmits a packet of all zeros, 1911 * we won't be fooled. 1912 * 1913 * - We know the size of the actual received frame, so we subtract 1914 * that value from the current pointer location. This brings us 1915 * to the start of the actual received packet. 1916 * 1917 * - We copy this into an mbuf and pass it on, along with the actual 1918 * frame length. 1919 * 1920 * The performance hit is tremendous, but it beats dropping frames all 1921 * the time. 1922 */ 1923 1924 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1925 void dc_pnic_rx_bug_war(sc, idx) 1926 struct dc_softc *sc; 1927 int idx; 1928 { 1929 struct dc_desc *cur_rx; 1930 struct dc_desc *c = NULL; 1931 struct mbuf *m = NULL; 1932 unsigned char *ptr; 1933 int i, total_len; 1934 u_int32_t rxstat = 0; 1935 1936 i = sc->dc_pnic_rx_bug_save; 1937 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1938 ptr = sc->dc_pnic_rx_buf; 1939 bzero(ptr, sizeof(DC_RXLEN * 5)); 1940 1941 /* Copy all the bytes from the bogus buffers. */ 1942 while (1) { 1943 c = &sc->dc_ldata->dc_rx_list[i]; 1944 rxstat = c->dc_status; 1945 m = sc->dc_cdata.dc_rx_chain[i]; 1946 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1947 ptr += DC_RXLEN; 1948 /* If this is the last buffer, break out. */ 1949 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1950 break; 1951 dc_newbuf(sc, i, m); 1952 DC_INC(i, DC_RX_LIST_CNT); 1953 } 1954 1955 /* Find the length of the actual receive frame. */ 1956 total_len = DC_RXBYTES(rxstat); 1957 1958 /* Scan backwards until we hit a non-zero byte. */ 1959 while(*ptr == 0x00) 1960 ptr--; 1961 1962 /* Round off. */ 1963 if ((unsigned long)(ptr) & 0x3) 1964 ptr -= 1; 1965 1966 /* Now find the start of the frame. */ 1967 ptr -= total_len; 1968 if (ptr < sc->dc_pnic_rx_buf) 1969 ptr = sc->dc_pnic_rx_buf; 1970 1971 /* 1972 * Now copy the salvaged frame to the last mbuf and fake up 1973 * the status word to make it look like a successful 1974 * frame reception. 1975 */ 1976 dc_newbuf(sc, i, m); 1977 bcopy(ptr, mtod(m, char *), total_len); 1978 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 1979 1980 return; 1981 } 1982 1983 /* 1984 * This routine searches the RX ring for dirty descriptors in the 1985 * event that the rxeof routine falls out of sync with the chip's 1986 * current descriptor pointer. This may happen sometimes as a result 1987 * of a "no RX buffer available" condition that happens when the chip 1988 * consumes all of the RX buffers before the driver has a chance to 1989 * process the RX ring. This routine may need to be called more than 1990 * once to bring the driver back in sync with the chip, however we 1991 * should still be getting RX DONE interrupts to drive the search 1992 * for new packets in the RX ring, so we should catch up eventually. 1993 */ 1994 int dc_rx_resync(sc) 1995 struct dc_softc *sc; 1996 { 1997 int i, pos; 1998 struct dc_desc *cur_rx; 1999 2000 pos = sc->dc_cdata.dc_rx_prod; 2001 2002 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2003 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2004 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2005 break; 2006 DC_INC(pos, DC_RX_LIST_CNT); 2007 } 2008 2009 /* If the ring really is empty, then just return. */ 2010 if (i == DC_RX_LIST_CNT) 2011 return(0); 2012 2013 /* We've fallen behing the chip: catch it. */ 2014 sc->dc_cdata.dc_rx_prod = pos; 2015 2016 return(EAGAIN); 2017 } 2018 2019 /* 2020 * A frame has been uploaded: pass the resulting mbuf chain up to 2021 * the higher level protocols. 2022 */ 2023 void dc_rxeof(sc) 2024 struct dc_softc *sc; 2025 { 2026 struct mbuf *m; 2027 struct ifnet *ifp; 2028 struct dc_desc *cur_rx; 2029 int i, total_len = 0; 2030 u_int32_t rxstat; 2031 2032 ifp = &sc->arpcom.ac_if; 2033 i = sc->dc_cdata.dc_rx_prod; 2034 2035 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2036 struct mbuf *m0 = NULL; 2037 2038 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2039 rxstat = cur_rx->dc_status; 2040 m = sc->dc_cdata.dc_rx_chain[i]; 2041 total_len = DC_RXBYTES(rxstat); 2042 2043 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2044 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2045 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2046 sc->dc_pnic_rx_bug_save = i; 2047 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2048 DC_INC(i, DC_RX_LIST_CNT); 2049 continue; 2050 } 2051 dc_pnic_rx_bug_war(sc, i); 2052 rxstat = cur_rx->dc_status; 2053 total_len = DC_RXBYTES(rxstat); 2054 } 2055 } 2056 2057 sc->dc_cdata.dc_rx_chain[i] = NULL; 2058 2059 /* 2060 * If an error occurs, update stats, clear the 2061 * status word and leave the mbuf cluster in place: 2062 * it should simply get re-used next time this descriptor 2063 * comes up in the ring. 2064 */ 2065 if (rxstat & DC_RXSTAT_RXERR 2066 #if NVLAN > 0 2067 /* 2068 * If VLANs are enabled, allow frames up to 4 bytes 2069 * longer than the MTU. This should really check if 2070 * the giant packet has a vlan tag 2071 */ 2072 && ((rxstat & (DC_RXSTAT_GIANT|DC_RXSTAT_LASTFRAG)) == 0 2073 && total_len <= ifp->if_mtu + 4) 2074 #endif 2075 ) { 2076 ifp->if_ierrors++; 2077 if (rxstat & DC_RXSTAT_COLLSEEN) 2078 ifp->if_collisions++; 2079 dc_newbuf(sc, i, m); 2080 if (rxstat & DC_RXSTAT_CRCERR) { 2081 DC_INC(i, DC_RX_LIST_CNT); 2082 continue; 2083 } else { 2084 dc_init(sc); 2085 return; 2086 } 2087 } 2088 2089 /* No errors; receive the packet. */ 2090 total_len -= ETHER_CRC_LEN; 2091 2092 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2093 total_len + ETHER_ALIGN, 0, ifp, NULL); 2094 dc_newbuf(sc, i, m); 2095 DC_INC(i, DC_RX_LIST_CNT); 2096 if (m0 == NULL) { 2097 ifp->if_ierrors++; 2098 continue; 2099 } 2100 m_adj(m0, ETHER_ALIGN); 2101 m = m0; 2102 2103 ifp->if_ipackets++; 2104 2105 #if NBPFILTER > 0 2106 if (ifp->if_bpf) 2107 bpf_mtap(ifp->if_bpf, m); 2108 #endif 2109 ether_input_mbuf(ifp, m); 2110 } 2111 2112 sc->dc_cdata.dc_rx_prod = i; 2113 2114 return; 2115 } 2116 2117 /* 2118 * A frame was downloaded to the chip. It's safe for us to clean up 2119 * the list buffers. 2120 */ 2121 2122 void dc_txeof(sc) 2123 struct dc_softc *sc; 2124 { 2125 struct dc_desc *cur_tx = NULL; 2126 struct ifnet *ifp; 2127 int idx; 2128 2129 ifp = &sc->arpcom.ac_if; 2130 2131 /* Clear the timeout timer. */ 2132 ifp->if_timer = 0; 2133 2134 /* 2135 * Go through our tx list and free mbufs for those 2136 * frames that have been transmitted. 2137 */ 2138 idx = sc->dc_cdata.dc_tx_cons; 2139 while(idx != sc->dc_cdata.dc_tx_prod) { 2140 u_int32_t txstat; 2141 2142 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2143 txstat = cur_tx->dc_status; 2144 2145 if (txstat & DC_TXSTAT_OWN) 2146 break; 2147 2148 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2149 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2150 sc->dc_cdata.dc_tx_cnt--; 2151 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2152 /* 2153 * Yes, the PNIC is so brain damaged 2154 * that it will sometimes generate a TX 2155 * underrun error while DMAing the RX 2156 * filter setup frame. If we detect this, 2157 * we have to send the setup frame again, 2158 * or else the filter won't be programmed 2159 * correctly. 2160 */ 2161 if (DC_IS_PNIC(sc)) { 2162 if (txstat & DC_TXSTAT_ERRSUM) 2163 dc_setfilt(sc); 2164 } 2165 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2166 } 2167 DC_INC(idx, DC_TX_LIST_CNT); 2168 continue; 2169 } 2170 2171 if (DC_IS_XIRCOM(sc)) { 2172 /* 2173 * XXX: Why does my Xircom taunt me so? 2174 * For some reason it likes setting the CARRLOST flag 2175 * even when the carrier is there. wtf?! */ 2176 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2177 sc->dc_pmode == DC_PMODE_MII && 2178 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2179 DC_TXSTAT_NOCARRIER))) 2180 txstat &= ~DC_TXSTAT_ERRSUM; 2181 } else { 2182 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2183 sc->dc_pmode == DC_PMODE_MII && 2184 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2185 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2186 txstat &= ~DC_TXSTAT_ERRSUM; 2187 } 2188 2189 if (txstat & DC_TXSTAT_ERRSUM) { 2190 ifp->if_oerrors++; 2191 if (txstat & DC_TXSTAT_EXCESSCOLL) 2192 ifp->if_collisions++; 2193 if (txstat & DC_TXSTAT_LATECOLL) 2194 ifp->if_collisions++; 2195 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2196 dc_init(sc); 2197 return; 2198 } 2199 } 2200 2201 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2202 2203 ifp->if_opackets++; 2204 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2205 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2206 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2207 } 2208 2209 sc->dc_cdata.dc_tx_cnt--; 2210 DC_INC(idx, DC_TX_LIST_CNT); 2211 } 2212 2213 sc->dc_cdata.dc_tx_cons = idx; 2214 if (cur_tx != NULL) 2215 ifp->if_flags &= ~IFF_OACTIVE; 2216 2217 return; 2218 } 2219 2220 void dc_tick(xsc) 2221 void *xsc; 2222 { 2223 struct dc_softc *sc = (struct dc_softc *)xsc; 2224 struct mii_data *mii; 2225 struct ifnet *ifp; 2226 int s; 2227 u_int32_t r; 2228 2229 s = splimp(); 2230 2231 ifp = &sc->arpcom.ac_if; 2232 mii = &sc->sc_mii; 2233 2234 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2235 if (sc->dc_flags & DC_21143_NWAY) { 2236 r = CSR_READ_4(sc, DC_10BTSTAT); 2237 if (IFM_SUBTYPE(mii->mii_media_active) == 2238 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2239 sc->dc_link = 0; 2240 mii_mediachg(mii); 2241 } 2242 if (IFM_SUBTYPE(mii->mii_media_active) == 2243 IFM_10_T && (r & DC_TSTAT_LS10)) { 2244 sc->dc_link = 0; 2245 mii_mediachg(mii); 2246 } 2247 if (sc->dc_link == 0) 2248 mii_tick(mii); 2249 } else { 2250 r = CSR_READ_4(sc, DC_ISR); 2251 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2252 sc->dc_cdata.dc_tx_cnt == 0 && !DC_IS_ASIX(sc)) 2253 mii_tick(mii); 2254 if (!(mii->mii_media_status & IFM_ACTIVE)) 2255 sc->dc_link = 0; 2256 } 2257 } else 2258 mii_tick(mii); 2259 2260 /* 2261 * When the init routine completes, we expect to be able to send 2262 * packets right away, and in fact the network code will send a 2263 * gratuitous ARP the moment the init routine marks the interface 2264 * as running. However, even though the MAC may have been initialized, 2265 * there may be a delay of a few seconds before the PHY completes 2266 * autonegotiation and the link is brought up. Any transmissions 2267 * made during that delay will be lost. Dealing with this is tricky: 2268 * we can't just pause in the init routine while waiting for the 2269 * PHY to come ready since that would bring the whole system to 2270 * a screeching halt for several seconds. 2271 * 2272 * What we do here is prevent the TX start routine from sending 2273 * any packets until a link has been established. After the 2274 * interface has been initialized, the tick routine will poll 2275 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2276 * that time, packets will stay in the send queue, and once the 2277 * link comes up, they will be flushed out to the wire. 2278 */ 2279 if (!sc->dc_link) { 2280 mii_pollstat(mii); 2281 if (mii->mii_media_status & IFM_ACTIVE && 2282 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2283 sc->dc_link++; 2284 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2285 dc_start(ifp); 2286 } 2287 } 2288 2289 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2290 timeout_add(&sc->dc_tick_tmo, hz / 10); 2291 else 2292 timeout_add(&sc->dc_tick_tmo, hz); 2293 2294 splx(s); 2295 2296 return; 2297 } 2298 2299 int dc_intr(arg) 2300 void *arg; 2301 { 2302 struct dc_softc *sc; 2303 struct ifnet *ifp; 2304 u_int32_t status; 2305 int claimed = 0; 2306 2307 sc = arg; 2308 ifp = &sc->arpcom.ac_if; 2309 2310 /* Supress unwanted interrupts */ 2311 if (!(ifp->if_flags & IFF_UP)) { 2312 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2313 dc_stop(sc); 2314 return claimed; 2315 } 2316 2317 /* Disable interrupts. */ 2318 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2319 2320 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 2321 status != 0xFFFFFFFF) { 2322 2323 claimed = 1; 2324 2325 CSR_WRITE_4(sc, DC_ISR, status); 2326 if ((status & DC_INTRS) == 0) { 2327 claimed = 0; 2328 break; 2329 } 2330 2331 if (status & DC_ISR_RX_OK) { 2332 int curpkts; 2333 curpkts = ifp->if_ipackets; 2334 dc_rxeof(sc); 2335 if (curpkts == ifp->if_ipackets) { 2336 while(dc_rx_resync(sc)) 2337 dc_rxeof(sc); 2338 } 2339 } 2340 2341 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2342 dc_txeof(sc); 2343 2344 if (status & DC_ISR_TX_IDLE) { 2345 dc_txeof(sc); 2346 if (sc->dc_cdata.dc_tx_cnt) { 2347 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2348 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2349 } 2350 } 2351 2352 if (status & DC_ISR_TX_UNDERRUN) { 2353 u_int32_t cfg; 2354 2355 printf("dc%d: TX underrun -- ", sc->dc_unit); 2356 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2357 dc_init(sc); 2358 cfg = CSR_READ_4(sc, DC_NETCFG); 2359 cfg &= ~DC_NETCFG_TX_THRESH; 2360 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2361 printf("using store and forward mode\n"); 2362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2363 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2364 printf("resetting\n"); 2365 } else { 2366 sc->dc_txthresh += 0x4000; 2367 printf("increasing TX threshold\n"); 2368 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2369 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2370 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2371 } 2372 } 2373 2374 if ((status & DC_ISR_RX_WATDOGTIMEO) 2375 || (status & DC_ISR_RX_NOBUF)) { 2376 int curpkts; 2377 curpkts = ifp->if_ipackets; 2378 dc_rxeof(sc); 2379 if (curpkts == ifp->if_ipackets) { 2380 while(dc_rx_resync(sc)) 2381 dc_rxeof(sc); 2382 } 2383 } 2384 2385 if (status & DC_ISR_BUS_ERR) { 2386 dc_reset(sc); 2387 dc_init(sc); 2388 } 2389 } 2390 2391 /* Re-enable interrupts. */ 2392 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2393 2394 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2395 dc_start(ifp); 2396 2397 return (claimed); 2398 } 2399 2400 /* 2401 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2402 * pointers to the fragment pointers. 2403 */ 2404 int dc_encap(sc, m_head, txidx) 2405 struct dc_softc *sc; 2406 struct mbuf *m_head; 2407 u_int32_t *txidx; 2408 { 2409 struct dc_desc *f = NULL; 2410 struct mbuf *m; 2411 int frag, cur, cnt = 0; 2412 2413 /* 2414 * Start packing the mbufs in this chain into 2415 * the fragment pointers. Stop when we run out 2416 * of fragments or hit the end of the mbuf chain. 2417 */ 2418 m = m_head; 2419 cur = frag = *txidx; 2420 2421 for (m = m_head; m != NULL; m = m->m_next) { 2422 if (m->m_len != 0) { 2423 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2424 if (*txidx != sc->dc_cdata.dc_tx_prod && 2425 frag == (DC_TX_LIST_CNT - 1)) 2426 return(ENOBUFS); 2427 } 2428 if ((DC_TX_LIST_CNT - 2429 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2430 return(ENOBUFS); 2431 2432 f = &sc->dc_ldata->dc_tx_list[frag]; 2433 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2434 if (cnt == 0) { 2435 f->dc_status = 0; 2436 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2437 } else 2438 f->dc_status = DC_TXSTAT_OWN; 2439 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2440 cur = frag; 2441 DC_INC(frag, DC_TX_LIST_CNT); 2442 cnt++; 2443 } 2444 } 2445 2446 if (m != NULL) 2447 return(ENOBUFS); 2448 2449 sc->dc_cdata.dc_tx_cnt += cnt; 2450 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2451 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2452 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2453 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2454 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2455 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2456 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2457 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2458 #ifdef ALTQ 2459 else if ((sc->dc_flags & DC_TX_USE_TX_INTR) && 2460 TBR_IS_ENABLED(&sc->arpcom.ac_if.if_snd)) 2461 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2462 #endif 2463 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2464 *txidx = frag; 2465 2466 return(0); 2467 } 2468 2469 /* 2470 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2471 * Needed for some really badly behaved chips that just can't 2472 * do scatter/gather correctly. 2473 */ 2474 int dc_coal(sc, m_head) 2475 struct dc_softc *sc; 2476 struct mbuf **m_head; 2477 { 2478 struct mbuf *m_new, *m; 2479 2480 m = *m_head; 2481 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2482 if (m_new == NULL) { 2483 printf("dc%d: no memory for tx list", sc->dc_unit); 2484 return(ENOBUFS); 2485 } 2486 if (m->m_pkthdr.len > MHLEN) { 2487 MCLGET(m_new, M_DONTWAIT); 2488 if (!(m_new->m_flags & M_EXT)) { 2489 m_freem(m_new); 2490 printf("dc%d: no memory for tx list", sc->dc_unit); 2491 return(ENOBUFS); 2492 } 2493 } 2494 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2495 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2496 m_freem(m); 2497 *m_head = m_new; 2498 2499 return(0); 2500 } 2501 2502 /* 2503 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2504 * to the mbuf data regions directly in the transmit lists. We also save a 2505 * copy of the pointers since the transmit list fragment pointers are 2506 * physical addresses. 2507 */ 2508 2509 void dc_start(ifp) 2510 struct ifnet *ifp; 2511 { 2512 struct dc_softc *sc; 2513 struct mbuf *m_head = NULL; 2514 int idx; 2515 2516 sc = ifp->if_softc; 2517 2518 if (!sc->dc_link) 2519 return; 2520 2521 if (ifp->if_flags & IFF_OACTIVE) 2522 return; 2523 2524 idx = sc->dc_cdata.dc_tx_prod; 2525 2526 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2527 IFQ_POLL(&ifp->if_snd, m_head); 2528 if (m_head == NULL) 2529 break; 2530 2531 if (sc->dc_flags & DC_TX_COALESCE) { 2532 #ifdef ALTQ 2533 /* note: dc_coal breaks the poll-and-dequeue rule. 2534 * if dc_coal fails, we lose the packet. 2535 */ 2536 #endif 2537 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2538 if (dc_coal(sc, &m_head)) { 2539 ifp->if_flags |= IFF_OACTIVE; 2540 break; 2541 } 2542 } 2543 2544 if (dc_encap(sc, m_head, &idx)) { 2545 ifp->if_flags |= IFF_OACTIVE; 2546 break; 2547 } 2548 2549 /* now we are committed to transmit the packet */ 2550 if (sc->dc_flags & DC_TX_COALESCE) { 2551 /* if mbuf is coalesced, it is already dequeued */ 2552 } else 2553 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2554 2555 /* 2556 * If there's a BPF listener, bounce a copy of this frame 2557 * to him. 2558 */ 2559 #if NBPFILTER > 0 2560 if (ifp->if_bpf) 2561 bpf_mtap(ifp->if_bpf, m_head); 2562 #endif 2563 if (sc->dc_flags & DC_TX_ONE) { 2564 ifp->if_flags |= IFF_OACTIVE; 2565 break; 2566 } 2567 } 2568 if (idx == sc->dc_cdata.dc_tx_prod) 2569 return; 2570 2571 /* Transmit */ 2572 sc->dc_cdata.dc_tx_prod = idx; 2573 if (!(sc->dc_flags & DC_TX_POLL)) 2574 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2575 2576 /* 2577 * Set a timeout in case the chip goes out to lunch. 2578 */ 2579 ifp->if_timer = 5; 2580 2581 return; 2582 } 2583 2584 void dc_init(xsc) 2585 void *xsc; 2586 { 2587 struct dc_softc *sc = xsc; 2588 struct ifnet *ifp = &sc->arpcom.ac_if; 2589 struct mii_data *mii; 2590 int s; 2591 2592 s = splimp(); 2593 2594 mii = &sc->sc_mii; 2595 2596 /* 2597 * Cancel pending I/O and free all RX/TX buffers. 2598 */ 2599 dc_stop(sc); 2600 dc_reset(sc); 2601 2602 /* 2603 * Set cache alignment and burst length. 2604 */ 2605 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2606 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2607 else 2608 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2609 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2610 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2611 } else { 2612 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2613 } 2614 if (sc->dc_flags & DC_TX_POLL) 2615 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2616 switch(sc->dc_cachesize) { 2617 case 32: 2618 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2619 break; 2620 case 16: 2621 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2622 break; 2623 case 8: 2624 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2625 break; 2626 case 0: 2627 default: 2628 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2629 break; 2630 } 2631 2632 if (sc->dc_flags & DC_TX_STORENFWD) 2633 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2634 else { 2635 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2636 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2637 } else { 2638 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2639 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2640 } 2641 } 2642 2643 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2644 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2645 2646 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2647 /* 2648 * The app notes for the 98713 and 98715A say that 2649 * in order to have the chips operate properly, a magic 2650 * number must be written to CSR16. Macronix does not 2651 * document the meaning of these bits so there's no way 2652 * to know exactly what they do. The 98713 has a magic 2653 * number all its own; the rest all use a different one. 2654 */ 2655 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2656 if (sc->dc_type == DC_TYPE_98713) 2657 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2658 else 2659 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2660 } 2661 2662 if (DC_IS_XIRCOM(sc)) { 2663 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2664 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2665 DELAY(10); 2666 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2667 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2668 DELAY(10); 2669 } 2670 2671 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2672 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2673 2674 /* Init circular RX list. */ 2675 if (dc_list_rx_init(sc) == ENOBUFS) { 2676 printf("dc%d: initialization failed: no " 2677 "memory for rx buffers\n", sc->dc_unit); 2678 dc_stop(sc); 2679 (void)splx(s); 2680 return; 2681 } 2682 2683 /* 2684 * Init tx descriptors. 2685 */ 2686 dc_list_tx_init(sc); 2687 2688 /* 2689 * Load the address of the RX list. 2690 */ 2691 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2692 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2693 2694 /* 2695 * Enable interrupts. 2696 */ 2697 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2698 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2699 2700 /* Enable transmitter. */ 2701 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2702 2703 /* 2704 * If this is an Intel 21143 and we're not using the 2705 * MII port, program the LED control pins so we get 2706 * link and activity indications. 2707 */ 2708 if (sc->dc_flags & DC_TULIP_LEDS) { 2709 CSR_WRITE_4(sc, DC_WATCHDOG, 2710 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 2711 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 2712 } 2713 2714 /* 2715 * Load the RX/multicast filter. We do this sort of late 2716 * because the filter programming scheme on the 21143 and 2717 * some clones requires DMAing a setup frame via the TX 2718 * engine, and we need the transmitter enabled for that. 2719 */ 2720 dc_setfilt(sc); 2721 2722 /* Enable receiver. */ 2723 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2724 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2725 2726 mii_mediachg(mii); 2727 dc_setcfg(sc, sc->dc_if_media); 2728 2729 ifp->if_flags |= IFF_RUNNING; 2730 ifp->if_flags &= ~IFF_OACTIVE; 2731 2732 (void)splx(s); 2733 2734 timeout_set(&sc->dc_tick_tmo, dc_tick, sc); 2735 2736 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 2737 sc->dc_link = 1; 2738 else { 2739 if (sc->dc_flags & DC_21143_NWAY) 2740 timeout_add(&sc->dc_tick_tmo, hz / 10); 2741 else 2742 timeout_add(&sc->dc_tick_tmo, hz); 2743 } 2744 2745 #ifdef SRM_MEDIA 2746 if(sc->dc_srm_media) { 2747 struct ifreq ifr; 2748 2749 ifr.ifr_media = sc->dc_srm_media; 2750 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2751 sc->dc_srm_media = 0; 2752 } 2753 #endif 2754 2755 return; 2756 } 2757 2758 /* 2759 * Set media options. 2760 */ 2761 int dc_ifmedia_upd(ifp) 2762 struct ifnet *ifp; 2763 { 2764 struct dc_softc *sc; 2765 struct mii_data *mii; 2766 struct ifmedia *ifm; 2767 2768 sc = ifp->if_softc; 2769 mii = &sc->sc_mii; 2770 mii_mediachg(mii); 2771 2772 ifm = &mii->mii_media; 2773 2774 if (DC_IS_DAVICOM(sc) && 2775 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 2776 dc_setcfg(sc, ifm->ifm_media); 2777 else 2778 sc->dc_link = 0; 2779 2780 return(0); 2781 } 2782 2783 /* 2784 * Report current media status. 2785 */ 2786 void dc_ifmedia_sts(ifp, ifmr) 2787 struct ifnet *ifp; 2788 struct ifmediareq *ifmr; 2789 { 2790 struct dc_softc *sc; 2791 struct mii_data *mii; 2792 struct ifmedia *ifm; 2793 2794 sc = ifp->if_softc; 2795 mii = &sc->sc_mii; 2796 mii_pollstat(mii); 2797 ifm = &mii->mii_media; 2798 if (DC_IS_DAVICOM(sc)) { 2799 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 2800 ifmr->ifm_active = ifm->ifm_media; 2801 ifmr->ifm_status = 0; 2802 return; 2803 } 2804 } 2805 ifmr->ifm_active = mii->mii_media_active; 2806 ifmr->ifm_status = mii->mii_media_status; 2807 2808 return; 2809 } 2810 2811 int dc_ioctl(ifp, command, data) 2812 struct ifnet *ifp; 2813 u_long command; 2814 caddr_t data; 2815 { 2816 struct dc_softc *sc = ifp->if_softc; 2817 struct ifreq *ifr = (struct ifreq *) data; 2818 struct ifaddr *ifa = (struct ifaddr *)data; 2819 struct mii_data *mii; 2820 int s, error = 0; 2821 2822 s = splimp(); 2823 2824 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 2825 splx(s); 2826 return error; 2827 } 2828 2829 switch(command) { 2830 case SIOCSIFADDR: 2831 ifp->if_flags |= IFF_UP; 2832 switch (ifa->ifa_addr->sa_family) { 2833 case AF_INET: 2834 dc_init(sc); 2835 arp_ifinit(&sc->arpcom, ifa); 2836 break; 2837 default: 2838 dc_init(sc); 2839 break; 2840 } 2841 break; 2842 case SIOCSIFFLAGS: 2843 if (ifp->if_flags & IFF_UP) { 2844 if (ifp->if_flags & IFF_RUNNING && 2845 ifp->if_flags & IFF_PROMISC && 2846 !(sc->dc_if_flags & IFF_PROMISC)) { 2847 dc_setfilt(sc); 2848 } else if (ifp->if_flags & IFF_RUNNING && 2849 !(ifp->if_flags & IFF_PROMISC) && 2850 sc->dc_if_flags & IFF_PROMISC) { 2851 dc_setfilt(sc); 2852 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2853 sc->dc_txthresh = 0; 2854 dc_init(sc); 2855 } 2856 } else { 2857 if (ifp->if_flags & IFF_RUNNING) 2858 dc_stop(sc); 2859 } 2860 sc->dc_if_flags = ifp->if_flags; 2861 error = 0; 2862 break; 2863 case SIOCADDMULTI: 2864 case SIOCDELMULTI: 2865 error = (command == SIOCADDMULTI) ? 2866 ether_addmulti(ifr, &sc->arpcom) : 2867 ether_delmulti(ifr, &sc->arpcom); 2868 2869 if (error == ENETRESET) { 2870 /* 2871 * Multicast list has changed; set the hardware 2872 * filter accordingly. 2873 */ 2874 dc_setfilt(sc); 2875 error = 0; 2876 } 2877 break; 2878 case SIOCGIFMEDIA: 2879 case SIOCSIFMEDIA: 2880 mii = &sc->sc_mii; 2881 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2882 #ifdef SRM_MEDIA 2883 if (sc->dc_srm_media) 2884 sc->dc_srm_media = 0; 2885 #endif 2886 break; 2887 default: 2888 error = EINVAL; 2889 break; 2890 } 2891 2892 (void)splx(s); 2893 2894 return(error); 2895 } 2896 2897 void dc_watchdog(ifp) 2898 struct ifnet *ifp; 2899 { 2900 struct dc_softc *sc; 2901 2902 sc = ifp->if_softc; 2903 2904 ifp->if_oerrors++; 2905 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2906 2907 dc_stop(sc); 2908 dc_reset(sc); 2909 dc_init(sc); 2910 2911 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2912 dc_start(ifp); 2913 2914 return; 2915 } 2916 2917 /* 2918 * Stop the adapter and free any mbufs allocated to the 2919 * RX and TX lists. 2920 */ 2921 void dc_stop(sc) 2922 struct dc_softc *sc; 2923 { 2924 register int i; 2925 struct ifnet *ifp; 2926 2927 ifp = &sc->arpcom.ac_if; 2928 ifp->if_timer = 0; 2929 2930 timeout_del(&sc->dc_tick_tmo); 2931 2932 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2933 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2934 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2935 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2936 sc->dc_link = 0; 2937 2938 /* 2939 * Free data in the RX lists. 2940 */ 2941 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2942 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2943 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2944 sc->dc_cdata.dc_rx_chain[i] = NULL; 2945 } 2946 } 2947 bzero((char *)&sc->dc_ldata->dc_rx_list, 2948 sizeof(sc->dc_ldata->dc_rx_list)); 2949 2950 /* 2951 * Free the TX list buffers. 2952 */ 2953 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2954 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2955 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2956 DC_TXCTL_SETUP) { 2957 sc->dc_cdata.dc_tx_chain[i] = NULL; 2958 continue; 2959 } 2960 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2961 sc->dc_cdata.dc_tx_chain[i] = NULL; 2962 } 2963 } 2964 2965 bzero((char *)&sc->dc_ldata->dc_tx_list, 2966 sizeof(sc->dc_ldata->dc_tx_list)); 2967 2968 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2969 2970 return; 2971 } 2972 2973 /* 2974 * Stop all chip I/O so that the kernel's probe routines don't 2975 * get confused by errant DMAs when rebooting. 2976 */ 2977 void dc_shutdown(v) 2978 void *v; 2979 { 2980 struct dc_softc *sc = (struct dc_softc *)v; 2981 2982 dc_stop(sc); 2983 } 2984 2985 struct cfdriver dc_cd = { 2986 0, "dc", DV_IFNET 2987 }; 2988 2989