1 /* $OpenBSD: com.c,v 1.148 2011/07/03 15:47:16 matthew Exp $ */ 2 /* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */ 3 4 /* 5 * Copyright (c) 1997 - 1999, Jason Downs. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /*- 29 * Copyright (c) 1993, 1994, 1995, 1996 30 * Charles M. Hannum. All rights reserved. 31 * Copyright (c) 1991 The Regents of the University of California. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. Neither the name of the University nor the names of its contributors 43 * may be used to endorse or promote products derived from this software 44 * without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * @(#)com.c 7.5 (Berkeley) 5/16/91 59 */ 60 61 /* 62 * COM driver, based on HP dca driver 63 * uses National Semiconductor NS16450/NS16550AF UART 64 */ 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/ioctl.h> 68 #include <sys/selinfo.h> 69 #include <sys/tty.h> 70 #include <sys/proc.h> 71 #include <sys/conf.h> 72 #include <sys/file.h> 73 #include <sys/uio.h> 74 #include <sys/kernel.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/vnode.h> 78 #ifdef DDB 79 #include <ddb/db_var.h> 80 #endif 81 82 #include <machine/bus.h> 83 #if !defined(__sparc__) || defined(__sparc64__) 84 #include <machine/intr.h> 85 #endif 86 87 #if !defined(__sparc__) || defined(__sparc64__) 88 #define COM_CONSOLE 89 #include <dev/cons.h> 90 #endif 91 92 #include <dev/ic/comreg.h> 93 #include <dev/ic/comvar.h> 94 #include <dev/ic/ns16550reg.h> 95 #define com_lcr com_cfcr 96 97 #ifdef COM_PXA2X0 98 #define com_isr 8 99 #define ISR_SEND (ISR_RXPL | ISR_XMODE | ISR_XMITIR) 100 #define ISR_RECV (ISR_RXPL | ISR_XMODE | ISR_RCVEIR) 101 #endif 102 103 #ifdef __zaurus__ 104 #include <arch/zaurus/dev/zaurus_scoopvar.h> 105 #endif 106 107 cdev_decl(com); 108 109 static u_char tiocm_xxx2mcr(int); 110 111 void compwroff(struct com_softc *); 112 void cominit(bus_space_tag_t, bus_space_handle_t, int, int); 113 int com_is_console(bus_space_tag_t, bus_addr_t); 114 115 struct cfdriver com_cd = { 116 NULL, "com", DV_TTY 117 }; 118 119 int comdefaultrate = TTYDEF_SPEED; 120 #ifdef COM_PXA2X0 121 bus_addr_t comsiraddr; 122 #endif 123 #ifdef COM_CONSOLE 124 int comconsfreq; 125 int comconsrate = TTYDEF_SPEED; 126 int comconsinit; 127 bus_addr_t comconsaddr = 0; 128 int comconsattached; 129 bus_space_tag_t comconsiot; 130 bus_space_handle_t comconsioh; 131 int comconsunit; 132 tcflag_t comconscflag = TTYDEF_CFLAG; 133 #endif 134 135 int commajor; 136 137 #ifdef KGDB 138 #include <sys/kgdb.h> 139 140 bus_addr_t com_kgdb_addr; 141 bus_space_tag_t com_kgdb_iot; 142 bus_space_handle_t com_kgdb_ioh; 143 144 int com_kgdb_getc(void *); 145 void com_kgdb_putc(void *, int); 146 #endif /* KGDB */ 147 148 #define DEVUNIT(x) (minor(x) & 0x7f) 149 #define DEVCUA(x) (minor(x) & 0x80) 150 151 int 152 comspeed(long freq, long speed) 153 { 154 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 155 156 int x, err; 157 158 if (speed == 0) 159 return 0; 160 if (speed < 0) 161 return -1; 162 x = divrnd((freq / 16), speed); 163 if (x <= 0) 164 return -1; 165 err = divrnd((quad_t)freq * 1000 / 16, speed * x) - 1000; 166 if (err < 0) 167 err = -err; 168 if (err > COM_TOLERANCE) 169 return -1; 170 return x; 171 172 #undef divrnd 173 } 174 175 #ifdef COM_CONSOLE 176 int 177 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 178 { 179 int i, k; 180 181 /* force access to id reg */ 182 bus_space_write_1(iot, ioh, com_lcr, 0); 183 bus_space_write_1(iot, ioh, com_iir, 0); 184 for (i = 0; i < 32; i++) { 185 k = bus_space_read_1(iot, ioh, com_iir); 186 if (k & 0x38) { 187 bus_space_read_1(iot, ioh, com_data); /* cleanup */ 188 } else 189 break; 190 } 191 if (i >= 32) 192 return 0; 193 194 return 1; 195 } 196 #endif 197 198 int 199 com_detach(struct device *self, int flags) 200 { 201 struct com_softc *sc = (struct com_softc *)self; 202 int maj, mn; 203 204 sc->sc_swflags |= COM_SW_DEAD; 205 206 /* Locate the major number. */ 207 for (maj = 0; maj < nchrdev; maj++) 208 if (cdevsw[maj].d_open == comopen) 209 break; 210 211 /* Nuke the vnodes for any open instances. */ 212 mn = self->dv_unit; 213 vdevgone(maj, mn, mn, VCHR); 214 215 /* XXX a symbolic constant for the cua bit would be nicer. */ 216 mn |= 0x80; 217 vdevgone(maj, mn, mn, VCHR); 218 219 /* Detach and free the tty. */ 220 if (sc->sc_tty) { 221 ttyfree(sc->sc_tty); 222 } 223 224 timeout_del(&sc->sc_dtr_tmo); 225 timeout_del(&sc->sc_diag_tmo); 226 softintr_disestablish(sc->sc_si); 227 228 return (0); 229 } 230 231 int 232 com_activate(struct device *self, int act) 233 { 234 struct com_softc *sc = (struct com_softc *)self; 235 int s, rv = 0; 236 237 s = spltty(); 238 switch (act) { 239 case DVACT_DEACTIVATE: 240 #ifdef KGDB 241 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 242 #else 243 if (sc->sc_hwflags & COM_HW_CONSOLE) { 244 #endif /* KGDB */ 245 rv = EBUSY; 246 break; 247 } 248 249 if (sc->disable != NULL && sc->enabled != 0) { 250 (*sc->disable)(sc); 251 sc->enabled = 0; 252 } 253 break; 254 } 255 splx(s); 256 return (rv); 257 } 258 259 int 260 comopen(dev_t dev, int flag, int mode, struct proc *p) 261 { 262 int unit = DEVUNIT(dev); 263 struct com_softc *sc; 264 bus_space_tag_t iot; 265 bus_space_handle_t ioh; 266 struct tty *tp; 267 int s; 268 int error = 0; 269 270 if (unit >= com_cd.cd_ndevs) 271 return ENXIO; 272 sc = com_cd.cd_devs[unit]; 273 if (!sc) 274 return ENXIO; 275 276 #ifdef KGDB 277 /* 278 * If this is the kgdb port, no other use is permitted. 279 */ 280 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 281 return (EBUSY); 282 #endif /* KGDB */ 283 284 s = spltty(); 285 if (!sc->sc_tty) { 286 tp = sc->sc_tty = ttymalloc(1000000); 287 } else 288 tp = sc->sc_tty; 289 splx(s); 290 291 tp->t_oproc = comstart; 292 tp->t_param = comparam; 293 tp->t_dev = dev; 294 if (!ISSET(tp->t_state, TS_ISOPEN)) { 295 SET(tp->t_state, TS_WOPEN); 296 ttychars(tp); 297 tp->t_iflag = TTYDEF_IFLAG; 298 tp->t_oflag = TTYDEF_OFLAG; 299 #ifdef COM_CONSOLE 300 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 301 tp->t_cflag = comconscflag; 302 tp->t_ispeed = tp->t_ospeed = comconsrate; 303 } else 304 #endif 305 { 306 tp->t_cflag = TTYDEF_CFLAG; 307 tp->t_ispeed = tp->t_ospeed = comdefaultrate; 308 } 309 if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)) 310 SET(tp->t_cflag, CLOCAL); 311 if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)) 312 SET(tp->t_cflag, CRTSCTS); 313 if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)) 314 SET(tp->t_cflag, MDMBUF); 315 tp->t_lflag = TTYDEF_LFLAG; 316 317 s = spltty(); 318 319 sc->sc_initialize = 1; 320 comparam(tp, &tp->t_termios); 321 ttsetwater(tp); 322 323 sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; 324 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 325 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 326 327 iot = sc->sc_iot; 328 ioh = sc->sc_ioh; 329 330 /* 331 * Wake up the sleepy heads. 332 */ 333 switch (sc->sc_uarttype) { 334 case COM_UART_ST16650: 335 case COM_UART_ST16650V2: 336 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 337 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 338 bus_space_write_1(iot, ioh, com_ier, 0); 339 bus_space_write_1(iot, ioh, com_efr, 0); 340 bus_space_write_1(iot, ioh, com_lcr, 0); 341 break; 342 case COM_UART_TI16750: 343 bus_space_write_1(iot, ioh, com_ier, 0); 344 break; 345 case COM_UART_PXA2X0: 346 bus_space_write_1(iot, ioh, com_ier, IER_EUART); 347 break; 348 } 349 350 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 351 u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST; 352 u_int8_t lcr; 353 354 if (tp->t_ispeed <= 1200) 355 fifo |= FIFO_TRIGGER_1; 356 else if (tp->t_ispeed <= 38400) 357 fifo |= FIFO_TRIGGER_4; 358 else 359 fifo |= FIFO_TRIGGER_8; 360 if (sc->sc_uarttype == COM_UART_TI16750) { 361 fifo |= FIFO_ENABLE_64BYTE; 362 lcr = bus_space_read_1(iot, ioh, com_lcr); 363 bus_space_write_1(iot, ioh, com_lcr, 364 lcr | LCR_DLAB); 365 } 366 367 /* 368 * (Re)enable and drain FIFOs. 369 * 370 * Certain SMC chips cause problems if the FIFOs are 371 * enabled while input is ready. Turn off the FIFO 372 * if necessary to clear the input. Test the input 373 * ready bit after enabling the FIFOs to handle races 374 * between enabling and fresh input. 375 * 376 * Set the FIFO threshold based on the receive speed. 377 */ 378 for (;;) { 379 bus_space_write_1(iot, ioh, com_fifo, 0); 380 delay(100); 381 (void) bus_space_read_1(iot, ioh, com_data); 382 bus_space_write_1(iot, ioh, com_fifo, fifo | 383 FIFO_RCV_RST | FIFO_XMT_RST); 384 delay(100); 385 if(!ISSET(bus_space_read_1(iot, ioh, 386 com_lsr), LSR_RXRDY)) 387 break; 388 } 389 if (sc->sc_uarttype == COM_UART_TI16750) 390 bus_space_write_1(iot, ioh, com_lcr, lcr); 391 } 392 393 /* Flush any pending I/O. */ 394 while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 395 (void) bus_space_read_1(iot, ioh, com_data); 396 397 /* You turn me on, baby! */ 398 sc->sc_mcr = MCR_DTR | MCR_RTS; 399 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 400 SET(sc->sc_mcr, MCR_IENABLE); 401 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 402 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 403 #ifdef COM_PXA2X0 404 if (sc->sc_uarttype == COM_UART_PXA2X0) 405 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 406 #endif 407 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 408 409 sc->sc_msr = bus_space_read_1(iot, ioh, com_msr); 410 if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) || 411 ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF)) 412 SET(tp->t_state, TS_CARR_ON); 413 else 414 CLR(tp->t_state, TS_CARR_ON); 415 #ifdef COM_PXA2X0 416 if (sc->sc_uarttype == COM_UART_PXA2X0 && 417 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 418 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 419 #ifdef __zaurus__ 420 scoop_set_irled(1); 421 #endif 422 } 423 #endif 424 } else if (ISSET(tp->t_state, TS_XCLUDE) && suser(p, 0) != 0) 425 return EBUSY; 426 else 427 s = spltty(); 428 429 if (DEVCUA(dev)) { 430 if (ISSET(tp->t_state, TS_ISOPEN)) { 431 /* Ah, but someone already is dialed in... */ 432 splx(s); 433 return EBUSY; 434 } 435 sc->sc_cua = 1; /* We go into CUA mode. */ 436 } else { 437 /* tty (not cua) device; wait for carrier if necessary. */ 438 if (ISSET(flag, O_NONBLOCK)) { 439 if (sc->sc_cua) { 440 /* Opening TTY non-blocking... but the CUA is busy. */ 441 splx(s); 442 return EBUSY; 443 } 444 } else { 445 while (sc->sc_cua || 446 (!ISSET(tp->t_cflag, CLOCAL) && 447 !ISSET(tp->t_state, TS_CARR_ON))) { 448 SET(tp->t_state, TS_WOPEN); 449 error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, ttopen, 0); 450 /* 451 * If TS_WOPEN has been reset, that means the cua device 452 * has been closed. We don't want to fail in that case, 453 * so just go around again. 454 */ 455 if (error && ISSET(tp->t_state, TS_WOPEN)) { 456 CLR(tp->t_state, TS_WOPEN); 457 if (!sc->sc_cua && !ISSET(tp->t_state, TS_ISOPEN)) 458 compwroff(sc); 459 splx(s); 460 return error; 461 } 462 } 463 } 464 } 465 splx(s); 466 467 return (*linesw[tp->t_line].l_open)(dev, tp, p); 468 } 469 470 int 471 comclose(dev_t dev, int flag, int mode, struct proc *p) 472 { 473 int unit = DEVUNIT(dev); 474 struct com_softc *sc = com_cd.cd_devs[unit]; 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 struct tty *tp = sc->sc_tty; 478 int s; 479 480 #ifdef COM_CONSOLE 481 /* XXX This is for cons.c. */ 482 if (!ISSET(tp->t_state, TS_ISOPEN)) 483 return 0; 484 #endif 485 486 if(sc->sc_swflags & COM_SW_DEAD) 487 return 0; 488 489 (*linesw[tp->t_line].l_close)(tp, flag, p); 490 s = spltty(); 491 if (ISSET(tp->t_state, TS_WOPEN)) { 492 /* tty device is waiting for carrier; drop dtr then re-raise */ 493 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 494 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 495 timeout_add_sec(&sc->sc_dtr_tmo, 2); 496 } else { 497 /* no one else waiting; turn off the uart */ 498 compwroff(sc); 499 } 500 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 501 sc->sc_cua = 0; 502 splx(s); 503 ttyclose(tp); 504 505 #ifdef COM_CONSOLE 506 #ifdef notyet /* XXXX */ 507 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 508 ttyfree(tp); 509 sc->sc_tty = 0; 510 } 511 #endif 512 #endif 513 return 0; 514 } 515 516 void 517 compwroff(struct com_softc *sc) 518 { 519 bus_space_tag_t iot = sc->sc_iot; 520 bus_space_handle_t ioh = sc->sc_ioh; 521 struct tty *tp = sc->sc_tty; 522 523 CLR(sc->sc_lcr, LCR_SBREAK); 524 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 525 bus_space_write_1(iot, ioh, com_ier, 0); 526 if (ISSET(tp->t_cflag, HUPCL) && 527 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 528 /* XXX perhaps only clear DTR */ 529 sc->sc_mcr = 0; 530 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 531 } 532 533 /* 534 * Turn FIFO off; enter sleep mode if possible. 535 */ 536 bus_space_write_1(iot, ioh, com_fifo, 0); 537 delay(100); 538 if (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 539 (void) bus_space_read_1(iot, ioh, com_data); 540 delay(100); 541 bus_space_write_1(iot, ioh, com_fifo, 542 FIFO_RCV_RST | FIFO_XMT_RST); 543 544 switch (sc->sc_uarttype) { 545 case COM_UART_ST16650: 546 case COM_UART_ST16650V2: 547 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 548 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 549 bus_space_write_1(iot, ioh, com_ier, IER_SLEEP); 550 bus_space_write_1(iot, ioh, com_lcr, 0); 551 break; 552 case COM_UART_TI16750: 553 bus_space_write_1(iot, ioh, com_ier, IER_SLEEP); 554 break; 555 #ifdef COM_PXA2X0 556 case COM_UART_PXA2X0: 557 bus_space_write_1(iot, ioh, com_ier, 0); 558 #ifdef __zaurus__ 559 if (ISSET(sc->sc_hwflags, COM_HW_SIR)) 560 scoop_set_irled(0); 561 #endif 562 break; 563 #endif 564 } 565 } 566 567 void 568 com_resume(struct com_softc *sc) 569 { 570 struct tty *tp = sc->sc_tty; 571 bus_space_tag_t iot = sc->sc_iot; 572 bus_space_handle_t ioh = sc->sc_ioh; 573 int ospeed; 574 575 if (!tp || !ISSET(tp->t_state, TS_ISOPEN)) { 576 #ifdef COM_CONSOLE 577 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 578 cominit(iot, ioh, comconsrate, comconsfreq); 579 #endif 580 return; 581 } 582 583 /* 584 * Wake up the sleepy heads. 585 */ 586 switch (sc->sc_uarttype) { 587 case COM_UART_ST16650: 588 case COM_UART_ST16650V2: 589 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 590 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 591 bus_space_write_1(iot, ioh, com_ier, 0); 592 bus_space_write_1(iot, ioh, com_efr, 0); 593 bus_space_write_1(iot, ioh, com_lcr, 0); 594 break; 595 case COM_UART_TI16750: 596 bus_space_write_1(iot, ioh, com_ier, 0); 597 break; 598 case COM_UART_PXA2X0: 599 bus_space_write_1(iot, ioh, com_ier, IER_EUART); 600 break; 601 } 602 603 ospeed = comspeed(sc->sc_frequency, tp->t_ospeed); 604 605 if (ospeed != 0) { 606 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr | LCR_DLAB); 607 bus_space_write_1(iot, ioh, com_dlbl, ospeed); 608 bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8); 609 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 610 } else { 611 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 612 } 613 614 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 615 u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST; 616 u_int8_t lcr; 617 618 if (tp->t_ispeed <= 1200) 619 fifo |= FIFO_TRIGGER_1; 620 else if (tp->t_ispeed <= 38400) 621 fifo |= FIFO_TRIGGER_4; 622 else 623 fifo |= FIFO_TRIGGER_8; 624 if (sc->sc_uarttype == COM_UART_TI16750) { 625 fifo |= FIFO_ENABLE_64BYTE; 626 lcr = bus_space_read_1(iot, ioh, com_lcr); 627 bus_space_write_1(iot, ioh, com_lcr, 628 lcr | LCR_DLAB); 629 } 630 631 /* 632 * (Re)enable and drain FIFOs. 633 * 634 * Certain SMC chips cause problems if the FIFOs are 635 * enabled while input is ready. Turn off the FIFO 636 * if necessary to clear the input. Test the input 637 * ready bit after enabling the FIFOs to handle races 638 * between enabling and fresh input. 639 * 640 * Set the FIFO threshold based on the receive speed. 641 */ 642 for (;;) { 643 bus_space_write_1(iot, ioh, com_fifo, 0); 644 delay(100); 645 (void) bus_space_read_1(iot, ioh, com_data); 646 bus_space_write_1(iot, ioh, com_fifo, fifo | 647 FIFO_RCV_RST | FIFO_XMT_RST); 648 delay(100); 649 if(!ISSET(bus_space_read_1(iot, ioh, 650 com_lsr), LSR_RXRDY)) 651 break; 652 } 653 if (sc->sc_uarttype == COM_UART_TI16750) 654 bus_space_write_1(iot, ioh, com_lcr, lcr); 655 } 656 657 /* Flush any pending I/O. */ 658 while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 659 (void) bus_space_read_1(iot, ioh, com_data); 660 661 /* You turn me on, baby! */ 662 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 663 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 664 665 #ifdef COM_PXA2X0 666 if (sc->sc_uarttype == COM_UART_PXA2X0 && 667 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 668 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 669 #ifdef __zaurus__ 670 scoop_set_irled(1); 671 #endif 672 } 673 #endif 674 } 675 676 void 677 com_raisedtr(void *arg) 678 { 679 struct com_softc *sc = arg; 680 681 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 682 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, sc->sc_mcr); 683 } 684 685 int 686 comread(dev_t dev, struct uio *uio, int flag) 687 { 688 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 689 struct tty *tp = sc->sc_tty; 690 691 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 692 } 693 694 int 695 comwrite(dev_t dev, struct uio *uio, int flag) 696 { 697 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 698 struct tty *tp = sc->sc_tty; 699 700 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 701 } 702 703 struct tty * 704 comtty(dev_t dev) 705 { 706 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 707 struct tty *tp = sc->sc_tty; 708 709 return (tp); 710 } 711 712 static u_char 713 tiocm_xxx2mcr(int data) 714 { 715 u_char m = 0; 716 717 if (ISSET(data, TIOCM_DTR)) 718 SET(m, MCR_DTR); 719 if (ISSET(data, TIOCM_RTS)) 720 SET(m, MCR_RTS); 721 return m; 722 } 723 724 int 725 comioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 726 { 727 int unit = DEVUNIT(dev); 728 struct com_softc *sc = com_cd.cd_devs[unit]; 729 struct tty *tp = sc->sc_tty; 730 bus_space_tag_t iot = sc->sc_iot; 731 bus_space_handle_t ioh = sc->sc_ioh; 732 int error; 733 734 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 735 if (error >= 0) 736 return error; 737 error = ttioctl(tp, cmd, data, flag, p); 738 if (error >= 0) 739 return error; 740 741 switch (cmd) { 742 case TIOCSBRK: 743 SET(sc->sc_lcr, LCR_SBREAK); 744 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 745 break; 746 case TIOCCBRK: 747 CLR(sc->sc_lcr, LCR_SBREAK); 748 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 749 break; 750 case TIOCSDTR: 751 SET(sc->sc_mcr, sc->sc_dtr); 752 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 753 break; 754 case TIOCCDTR: 755 CLR(sc->sc_mcr, sc->sc_dtr); 756 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 757 break; 758 case TIOCMSET: 759 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 760 case TIOCMBIS: 761 SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 762 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 763 break; 764 case TIOCMBIC: 765 CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 766 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 767 break; 768 case TIOCMGET: { 769 u_char m; 770 int bits = 0; 771 772 m = sc->sc_mcr; 773 if (ISSET(m, MCR_DTR)) 774 SET(bits, TIOCM_DTR); 775 if (ISSET(m, MCR_RTS)) 776 SET(bits, TIOCM_RTS); 777 m = sc->sc_msr; 778 if (ISSET(m, MSR_DCD)) 779 SET(bits, TIOCM_CD); 780 if (ISSET(m, MSR_CTS)) 781 SET(bits, TIOCM_CTS); 782 if (ISSET(m, MSR_DSR)) 783 SET(bits, TIOCM_DSR); 784 if (ISSET(m, MSR_RI | MSR_TERI)) 785 SET(bits, TIOCM_RI); 786 if (bus_space_read_1(iot, ioh, com_ier)) 787 SET(bits, TIOCM_LE); 788 *(int *)data = bits; 789 break; 790 } 791 case TIOCGFLAGS: { 792 int driverbits, userbits = 0; 793 794 driverbits = sc->sc_swflags; 795 if (ISSET(driverbits, COM_SW_SOFTCAR)) 796 SET(userbits, TIOCFLAG_SOFTCAR); 797 if (ISSET(driverbits, COM_SW_CLOCAL)) 798 SET(userbits, TIOCFLAG_CLOCAL); 799 if (ISSET(driverbits, COM_SW_CRTSCTS)) 800 SET(userbits, TIOCFLAG_CRTSCTS); 801 if (ISSET(driverbits, COM_SW_MDMBUF)) 802 SET(userbits, TIOCFLAG_MDMBUF); 803 if (ISSET(driverbits, COM_SW_PPS)) 804 SET(userbits, TIOCFLAG_PPS); 805 806 *(int *)data = userbits; 807 break; 808 } 809 case TIOCSFLAGS: { 810 int userbits, driverbits = 0; 811 812 error = suser(p, 0); 813 if (error != 0) 814 return(EPERM); 815 816 userbits = *(int *)data; 817 if (ISSET(userbits, TIOCFLAG_SOFTCAR) || 818 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 819 SET(driverbits, COM_SW_SOFTCAR); 820 if (ISSET(userbits, TIOCFLAG_CLOCAL)) 821 SET(driverbits, COM_SW_CLOCAL); 822 if (ISSET(userbits, TIOCFLAG_CRTSCTS)) 823 SET(driverbits, COM_SW_CRTSCTS); 824 if (ISSET(userbits, TIOCFLAG_MDMBUF)) 825 SET(driverbits, COM_SW_MDMBUF); 826 if (ISSET(userbits, TIOCFLAG_PPS)) 827 SET(driverbits, COM_SW_PPS); 828 829 sc->sc_swflags = driverbits; 830 break; 831 } 832 default: 833 return ENOTTY; 834 } 835 836 return 0; 837 } 838 839 /* already called at spltty */ 840 int 841 comparam(struct tty *tp, struct termios *t) 842 { 843 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)]; 844 bus_space_tag_t iot = sc->sc_iot; 845 bus_space_handle_t ioh = sc->sc_ioh; 846 int ospeed = comspeed(sc->sc_frequency, t->c_ospeed); 847 u_char lcr; 848 tcflag_t oldcflag; 849 850 /* Check requested parameters. */ 851 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) 852 return EINVAL; 853 854 lcr = ISSET(sc->sc_lcr, LCR_SBREAK); 855 856 switch (ISSET(t->c_cflag, CSIZE)) { 857 case CS5: 858 SET(lcr, LCR_5BITS); 859 break; 860 case CS6: 861 SET(lcr, LCR_6BITS); 862 break; 863 case CS7: 864 SET(lcr, LCR_7BITS); 865 break; 866 case CS8: 867 SET(lcr, LCR_8BITS); 868 break; 869 } 870 if (ISSET(t->c_cflag, PARENB)) { 871 SET(lcr, LCR_PENAB); 872 if (!ISSET(t->c_cflag, PARODD)) 873 SET(lcr, LCR_PEVEN); 874 } 875 if (ISSET(t->c_cflag, CSTOPB)) 876 SET(lcr, LCR_STOPB); 877 878 sc->sc_lcr = lcr; 879 880 if (ospeed == 0) { 881 CLR(sc->sc_mcr, MCR_DTR); 882 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 883 } 884 885 /* 886 * Set the FIFO threshold based on the receive speed, if we are 887 * changing it. 888 */ 889 if (sc->sc_initialize || (tp->t_ispeed != t->c_ispeed)) { 890 sc->sc_initialize = 0; 891 892 if (ospeed != 0) { 893 /* 894 * Make sure the transmit FIFO is empty before 895 * proceeding. If we don't do this, some revisions 896 * of the UART will hang. Interestingly enough, 897 * even if we do this while the last character is 898 * still being pushed out, they don't hang. This 899 * seems good enough. 900 */ 901 while (ISSET(tp->t_state, TS_BUSY)) { 902 int error; 903 904 ++sc->sc_halt; 905 error = ttysleep(tp, &tp->t_outq, 906 TTOPRI | PCATCH, "comprm", 0); 907 --sc->sc_halt; 908 if (error) { 909 comstart(tp); 910 return (error); 911 } 912 } 913 914 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 915 bus_space_write_1(iot, ioh, com_dlbl, ospeed); 916 bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8); 917 bus_space_write_1(iot, ioh, com_lcr, lcr); 918 SET(sc->sc_mcr, MCR_DTR); 919 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 920 } else 921 bus_space_write_1(iot, ioh, com_lcr, lcr); 922 923 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 924 if (sc->sc_uarttype == COM_UART_TI16750) { 925 bus_space_write_1(iot, ioh, com_lcr, 926 lcr | LCR_DLAB); 927 bus_space_write_1(iot, ioh, com_fifo, 928 FIFO_ENABLE | FIFO_ENABLE_64BYTE | 929 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 930 bus_space_write_1(iot, ioh, com_lcr, lcr); 931 } else 932 bus_space_write_1(iot, ioh, com_fifo, 933 FIFO_ENABLE | 934 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 935 } 936 } else 937 bus_space_write_1(iot, ioh, com_lcr, lcr); 938 939 /* When not using CRTSCTS, RTS follows DTR. */ 940 if (!ISSET(t->c_cflag, CRTSCTS)) { 941 if (ISSET(sc->sc_mcr, MCR_DTR)) { 942 if (!ISSET(sc->sc_mcr, MCR_RTS)) { 943 SET(sc->sc_mcr, MCR_RTS); 944 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 945 } 946 } else { 947 if (ISSET(sc->sc_mcr, MCR_RTS)) { 948 CLR(sc->sc_mcr, MCR_RTS); 949 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 950 } 951 } 952 sc->sc_dtr = MCR_DTR | MCR_RTS; 953 } else 954 sc->sc_dtr = MCR_DTR; 955 956 /* and copy to tty */ 957 tp->t_ispeed = t->c_ispeed; 958 tp->t_ospeed = t->c_ospeed; 959 oldcflag = tp->t_cflag; 960 tp->t_cflag = t->c_cflag; 961 962 /* 963 * If DCD is off and MDMBUF is changed, ask the tty layer if we should 964 * stop the device. 965 */ 966 if (!ISSET(sc->sc_msr, MSR_DCD) && 967 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 968 ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) && 969 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 970 CLR(sc->sc_mcr, sc->sc_dtr); 971 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 972 } 973 974 /* Just to be sure... */ 975 comstart(tp); 976 return 0; 977 } 978 979 void 980 comstart(struct tty *tp) 981 { 982 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)]; 983 bus_space_tag_t iot = sc->sc_iot; 984 bus_space_handle_t ioh = sc->sc_ioh; 985 int s; 986 987 s = spltty(); 988 if (ISSET(tp->t_state, TS_BUSY)) 989 goto out; 990 if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) || sc->sc_halt > 0) 991 goto stopped; 992 if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS)) 993 goto stopped; 994 ttwakeupwr(tp); 995 if (tp->t_outq.c_cc == 0) 996 goto stopped; 997 SET(tp->t_state, TS_BUSY); 998 999 #ifdef COM_PXA2X0 1000 /* Enable transmitter slow infrared mode. */ 1001 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1002 ISSET(sc->sc_hwflags, COM_HW_SIR)) 1003 bus_space_write_1(iot, ioh, com_isr, ISR_SEND); 1004 #endif 1005 1006 /* Enable transmit completion interrupts. */ 1007 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1008 SET(sc->sc_ier, IER_ETXRDY); 1009 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1010 } 1011 1012 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1013 u_char buffer[128]; /* largest fifo */ 1014 int i, n; 1015 1016 n = q_to_b(&tp->t_outq, buffer, 1017 min(sc->sc_fifolen, sizeof buffer)); 1018 for (i = 0; i < n; i++) { 1019 bus_space_write_1(iot, ioh, com_data, buffer[i]); 1020 } 1021 bzero(buffer, n); 1022 } else if (tp->t_outq.c_cc != 0) 1023 bus_space_write_1(iot, ioh, com_data, getc(&tp->t_outq)); 1024 out: 1025 splx(s); 1026 return; 1027 stopped: 1028 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1029 CLR(sc->sc_ier, IER_ETXRDY); 1030 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1031 #ifdef COM_PXA2X0 1032 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1033 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 1034 int timo; 1035 1036 /* Wait for empty transmit shift register. */ 1037 timo = 20000; 1038 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1039 LSR_TSRE) && --timo) 1040 delay(1); 1041 1042 /* Enable receiver slow infrared mode. */ 1043 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1044 } 1045 #endif 1046 } 1047 splx(s); 1048 } 1049 1050 /* 1051 * Stop output on a line. 1052 */ 1053 int 1054 comstop(struct tty *tp, int flag) 1055 { 1056 int s; 1057 1058 s = spltty(); 1059 if (ISSET(tp->t_state, TS_BUSY)) 1060 if (!ISSET(tp->t_state, TS_TTSTOP)) 1061 SET(tp->t_state, TS_FLUSH); 1062 splx(s); 1063 return 0; 1064 } 1065 1066 void 1067 comdiag(void *arg) 1068 { 1069 struct com_softc *sc = arg; 1070 int overflows, floods; 1071 int s; 1072 1073 s = spltty(); 1074 sc->sc_errors = 0; 1075 overflows = sc->sc_overflows; 1076 sc->sc_overflows = 0; 1077 floods = sc->sc_floods; 1078 sc->sc_floods = 0; 1079 splx(s); 1080 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s\n", 1081 sc->sc_dev.dv_xname, 1082 overflows, overflows == 1 ? "" : "s", 1083 floods, floods == 1 ? "" : "s"); 1084 } 1085 1086 void 1087 comsoft(void *arg) 1088 { 1089 struct com_softc *sc = (struct com_softc *)arg; 1090 struct tty *tp; 1091 u_char *ibufp; 1092 u_char *ibufend; 1093 int c; 1094 int s; 1095 static int lsrmap[8] = { 1096 0, TTY_PE, 1097 TTY_FE, TTY_PE|TTY_FE, 1098 TTY_FE, TTY_PE|TTY_FE, 1099 TTY_FE, TTY_PE|TTY_FE 1100 }; 1101 1102 if (sc == NULL || sc->sc_ibufp == sc->sc_ibuf) 1103 return; 1104 1105 tp = sc->sc_tty; 1106 1107 s = spltty(); 1108 1109 ibufp = sc->sc_ibuf; 1110 ibufend = sc->sc_ibufp; 1111 1112 if (ibufp == ibufend) { 1113 splx(s); 1114 return; 1115 } 1116 1117 sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? 1118 sc->sc_ibufs[1] : sc->sc_ibufs[0]; 1119 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 1120 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 1121 1122 if (tp == NULL || !ISSET(tp->t_state, TS_ISOPEN)) { 1123 splx(s); 1124 return; 1125 } 1126 1127 if (ISSET(tp->t_cflag, CRTSCTS) && 1128 !ISSET(sc->sc_mcr, MCR_RTS)) { 1129 /* XXX */ 1130 SET(sc->sc_mcr, MCR_RTS); 1131 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, 1132 sc->sc_mcr); 1133 } 1134 1135 splx(s); 1136 1137 while (ibufp < ibufend) { 1138 c = *ibufp++; 1139 if (ISSET(*ibufp, LSR_OE)) { 1140 sc->sc_overflows++; 1141 if (sc->sc_errors++ == 0) 1142 timeout_add_sec(&sc->sc_diag_tmo, 60); 1143 } 1144 /* This is ugly, but fast. */ 1145 c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2]; 1146 (*linesw[tp->t_line].l_rint)(c, tp); 1147 } 1148 } 1149 1150 #ifdef KGDB 1151 1152 /* 1153 * If a line break is set, or data matches one of the characters 1154 * gdb uses to signal a connection, then start up kgdb. Just gobble 1155 * any other data. Done in a stand alone function because comintr 1156 * does tty stuff and we don't have one. 1157 */ 1158 1159 int 1160 kgdbintr(void *arg) 1161 { 1162 struct com_softc *sc = arg; 1163 bus_space_tag_t iot = sc->sc_iot; 1164 bus_space_handle_t ioh = sc->sc_ioh; 1165 u_char lsr, data, msr, delta; 1166 1167 if (!ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1168 return(0); 1169 1170 for (;;) { 1171 lsr = bus_space_read_1(iot, ioh, com_lsr); 1172 if (ISSET(lsr, LSR_RXRDY)) { 1173 do { 1174 data = bus_space_read_1(iot, ioh, com_data); 1175 if (data == 3 || data == '$' || data == '+' || 1176 ISSET(lsr, LSR_BI)) { 1177 kgdb_connect(1); 1178 data = 0; 1179 } 1180 lsr = bus_space_read_1(iot, ioh, com_lsr); 1181 } while (ISSET(lsr, LSR_RXRDY)); 1182 1183 } 1184 if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE)) 1185 printf("weird lsr %02x\n", lsr); 1186 1187 msr = bus_space_read_1(iot, ioh, com_msr); 1188 1189 if (msr != sc->sc_msr) { 1190 delta = msr ^ sc->sc_msr; 1191 sc->sc_msr = msr; 1192 if (ISSET(delta, MSR_DCD)) { 1193 if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 1194 CLR(sc->sc_mcr, sc->sc_dtr); 1195 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1196 } 1197 } 1198 } 1199 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1200 return (1); 1201 } 1202 } 1203 #endif /* KGDB */ 1204 1205 int 1206 comintr(void *arg) 1207 { 1208 struct com_softc *sc = arg; 1209 bus_space_tag_t iot = sc->sc_iot; 1210 bus_space_handle_t ioh = sc->sc_ioh; 1211 struct tty *tp; 1212 u_char lsr, data, msr, delta; 1213 1214 if (!sc->sc_tty) 1215 return (0); /* Can't do squat. */ 1216 1217 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1218 return (0); 1219 1220 tp = sc->sc_tty; 1221 1222 for (;;) { 1223 lsr = bus_space_read_1(iot, ioh, com_lsr); 1224 1225 if (ISSET(lsr, LSR_RXRDY)) { 1226 u_char *p = sc->sc_ibufp; 1227 1228 softintr_schedule(sc->sc_si); 1229 do { 1230 data = bus_space_read_1(iot, ioh, com_data); 1231 if (ISSET(lsr, LSR_BI)) { 1232 #if defined(COM_CONSOLE) && defined(DDB) 1233 if (ISSET(sc->sc_hwflags, 1234 COM_HW_CONSOLE)) { 1235 if (db_console) 1236 Debugger(); 1237 goto next; 1238 } 1239 #endif 1240 data = 0; 1241 } 1242 if (p >= sc->sc_ibufend) { 1243 sc->sc_floods++; 1244 if (sc->sc_errors++ == 0) 1245 timeout_add_sec(&sc->sc_diag_tmo, 60); 1246 } else { 1247 *p++ = data; 1248 *p++ = lsr; 1249 if (p == sc->sc_ibufhigh && 1250 ISSET(tp->t_cflag, CRTSCTS)) { 1251 /* XXX */ 1252 CLR(sc->sc_mcr, MCR_RTS); 1253 bus_space_write_1(iot, ioh, com_mcr, 1254 sc->sc_mcr); 1255 } 1256 } 1257 #if defined(COM_CONSOLE) && defined(DDB) 1258 next: 1259 #endif 1260 lsr = bus_space_read_1(iot, ioh, com_lsr); 1261 } while (ISSET(lsr, LSR_RXRDY)); 1262 1263 sc->sc_ibufp = p; 1264 } 1265 msr = bus_space_read_1(iot, ioh, com_msr); 1266 1267 if (msr != sc->sc_msr) { 1268 delta = msr ^ sc->sc_msr; 1269 1270 ttytstamp(tp, sc->sc_msr & MSR_CTS, msr & MSR_CTS, 1271 sc->sc_msr & MSR_DCD, msr & MSR_DCD); 1272 1273 sc->sc_msr = msr; 1274 if (ISSET(delta, MSR_DCD)) { 1275 if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 1276 (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) { 1277 CLR(sc->sc_mcr, sc->sc_dtr); 1278 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1279 } 1280 } 1281 if (ISSET(delta & msr, MSR_CTS) && 1282 ISSET(tp->t_cflag, CRTSCTS)) { 1283 /* the line is up and we want to do rts/cts flow control */ 1284 (*linesw[tp->t_line].l_start)(tp); 1285 } 1286 } 1287 1288 if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) { 1289 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 1290 if (sc->sc_halt > 0) 1291 wakeup(&tp->t_outq); 1292 (*linesw[tp->t_line].l_start)(tp); 1293 } 1294 1295 #ifdef COM_PXA2X0 1296 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1297 ISSET(sc->sc_hwflags, COM_HW_SIR) && 1298 ISSET(lsr, LSR_TXRDY) && ISSET(lsr, LSR_TSRE)) 1299 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1300 #endif 1301 1302 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1303 return (1); 1304 } 1305 } 1306 1307 /* 1308 * The following functions are polled getc and putc routines, shared 1309 * by the console and kgdb glue. 1310 */ 1311 1312 int 1313 com_common_getc(bus_space_tag_t iot, bus_space_handle_t ioh) 1314 { 1315 int s = splhigh(); 1316 u_char stat, c; 1317 1318 #ifdef COM_PXA2X0 1319 if (com_is_console(iot, comsiraddr)) 1320 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1321 #endif 1322 1323 /* Block until a character becomes available. */ 1324 while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 1325 continue; 1326 1327 c = bus_space_read_1(iot, ioh, com_data); 1328 1329 /* Clear any interrupts generated by this transmission. */ 1330 stat = bus_space_read_1(iot, ioh, com_iir); 1331 splx(s); 1332 return (c); 1333 } 1334 1335 void 1336 com_common_putc(bus_space_tag_t iot, bus_space_handle_t ioh, int c) 1337 { 1338 int s = spltty(); 1339 int timo; 1340 1341 /* Wait for any pending transmission to finish. */ 1342 timo = 2000; 1343 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo) 1344 delay(1); 1345 1346 #ifdef COM_PXA2X0 1347 if (com_is_console(iot, comsiraddr)) 1348 bus_space_write_1(iot, ioh, com_isr, ISR_SEND); 1349 #endif 1350 bus_space_write_1(iot, ioh, com_data, (u_int8_t)(c & 0xff)); 1351 bus_space_barrier(iot, ioh, 0, COM_NPORTS, 1352 (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)); 1353 1354 /* Wait for this transmission to complete. */ 1355 timo = 2000; 1356 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo) 1357 delay(1); 1358 1359 #ifdef COM_PXA2X0 1360 if (com_is_console(iot, comsiraddr)) { 1361 /* Wait for transmit shift register to become empty. */ 1362 timo = 20000; 1363 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TSRE) 1364 && --timo) 1365 delay(1); 1366 1367 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1368 } 1369 #endif 1370 1371 splx(s); 1372 } 1373 1374 void 1375 cominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int frequency) 1376 { 1377 int s = splhigh(); 1378 u_char stat; 1379 1380 bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB); 1381 rate = comspeed(frequency, rate); /* XXX not comdefaultrate? */ 1382 bus_space_write_1(iot, ioh, com_dlbl, rate); 1383 bus_space_write_1(iot, ioh, com_dlbh, rate >> 8); 1384 bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS); 1385 bus_space_write_1(iot, ioh, com_mcr, MCR_DTR | MCR_RTS); 1386 #ifdef COM_PXA2X0 1387 /* XXX */ 1388 bus_space_write_1(iot, ioh, com_ier, IER_EUART); /* Make sure they are off */ 1389 #else 1390 bus_space_write_1(iot, ioh, com_ier, 0); /* Make sure they are off */ 1391 #endif 1392 bus_space_write_1(iot, ioh, com_fifo, 1393 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 1394 stat = bus_space_read_1(iot, ioh, com_iir); 1395 splx(s); 1396 } 1397 1398 #ifdef COM_CONSOLE 1399 void 1400 comcnprobe(struct consdev *cp) 1401 { 1402 bus_space_handle_t ioh; 1403 int found; 1404 1405 if (comconsaddr == 0) 1406 return; 1407 1408 if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS, 0, &ioh)) 1409 return; 1410 found = comprobe1(comconsiot, ioh); 1411 bus_space_unmap(comconsiot, ioh, COM_NPORTS); 1412 if (!found) 1413 return; 1414 1415 /* Locate the major number. */ 1416 for (commajor = 0; commajor < nchrdev; commajor++) 1417 if (cdevsw[commajor].d_open == comopen) 1418 break; 1419 1420 /* Initialize required fields. */ 1421 cp->cn_dev = makedev(commajor, comconsunit); 1422 #if defined(COMCONSOLE) || !defined(__amd64__) 1423 cp->cn_pri = CN_HIGHPRI; 1424 #else 1425 cp->cn_pri = CN_LOWPRI; 1426 #endif 1427 } 1428 1429 void 1430 comcninit(struct consdev *cp) 1431 { 1432 if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS, 0, &comconsioh)) 1433 panic("comcninit: mapping failed"); 1434 1435 if (comconsfreq == 0) 1436 comconsfreq = COM_FREQ; 1437 1438 cominit(comconsiot, comconsioh, comconsrate, comconsfreq); 1439 comconsinit = 0; 1440 } 1441 1442 int 1443 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, tcflag_t cflag) 1444 { 1445 static struct consdev comcons = { 1446 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, 1447 NODEV, CN_LOWPRI 1448 }; 1449 1450 #ifndef __sparc64__ 1451 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &comconsioh)) 1452 return ENOMEM; 1453 #endif 1454 1455 cominit(iot, comconsioh, rate, frequency); 1456 1457 cn_tab = &comcons; 1458 1459 comconsiot = iot; 1460 comconsaddr = iobase; 1461 comconscflag = cflag; 1462 comconsfreq = frequency; 1463 comconsrate = rate; 1464 1465 return (0); 1466 } 1467 1468 int 1469 comcngetc(dev_t dev) 1470 { 1471 return (com_common_getc(comconsiot, comconsioh)); 1472 } 1473 1474 /* 1475 * Console kernel output character routine. 1476 */ 1477 void 1478 comcnputc(dev_t dev, int c) 1479 { 1480 com_common_putc(comconsiot, comconsioh, c); 1481 } 1482 1483 void 1484 comcnpollc(dev_t dev, int on) 1485 { 1486 1487 } 1488 #endif /* COM_CONSOLE */ 1489 1490 #ifdef KGDB 1491 int 1492 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 1493 int frequency, tcflag_t cflag) 1494 { 1495 #ifdef COM_CONSOLE 1496 if (iot == comconsiot && iobase == comconsaddr) { 1497 return (EBUSY); /* cannot share with console */ 1498 } 1499 #endif 1500 1501 com_kgdb_iot = iot; 1502 com_kgdb_addr = iobase; 1503 1504 if (bus_space_map(com_kgdb_iot, com_kgdb_addr, COM_NPORTS, 0, 1505 &com_kgdb_ioh)) 1506 panic("com_kgdb_attach: mapping failed"); 1507 1508 /* XXX We currently don't respect KGDBMODE? */ 1509 cominit(com_kgdb_iot, com_kgdb_ioh, rate, frequency); 1510 1511 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 1512 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1513 1514 return (0); 1515 } 1516 1517 /* ARGSUSED */ 1518 int 1519 com_kgdb_getc(void *arg) 1520 { 1521 1522 return (com_common_getc(com_kgdb_iot, com_kgdb_ioh)); 1523 } 1524 1525 /* ARGSUSED */ 1526 void 1527 com_kgdb_putc(void *arg, int c) 1528 { 1529 1530 return (com_common_putc(com_kgdb_iot, com_kgdb_ioh, c)); 1531 } 1532 #endif /* KGDB */ 1533 1534 #ifdef COM_PXA2X0 1535 int 1536 com_is_console(bus_space_tag_t iot, bus_addr_t iobase) 1537 { 1538 1539 if (comconsiot == iot && comconsaddr == iobase) 1540 return (1); 1541 #ifdef KGDB 1542 else if (com_kgdb_iot == iot && com_kgdb_addr == iobase) 1543 return (1); 1544 #endif 1545 return (0); 1546 } 1547 #endif /* COM_PXA2X0 */ 1548 1549 void com_enable_debugport(struct com_softc *); 1550 void com_fifo_probe(struct com_softc *); 1551 1552 #if defined(COM_CONSOLE) || defined(KGDB) 1553 void 1554 com_enable_debugport(struct com_softc *sc) 1555 { 1556 int s; 1557 1558 /* Turn on line break interrupt, set carrier. */ 1559 s = splhigh(); 1560 #ifdef KGDB 1561 SET(sc->sc_ier, IER_ERXRDY); 1562 #ifdef COM_PXA2X0 1563 if (sc->sc_uarttype == COM_UART_PXA2X0) 1564 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1565 #endif 1566 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_ier, sc->sc_ier); 1567 #endif 1568 SET(sc->sc_mcr, MCR_DTR | MCR_RTS | MCR_IENABLE); 1569 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, sc->sc_mcr); 1570 1571 splx(s); 1572 } 1573 #endif /* COM_CONSOLE || KGDB */ 1574 1575 void 1576 com_attach_subr(struct com_softc *sc) 1577 { 1578 bus_space_tag_t iot = sc->sc_iot; 1579 bus_space_handle_t ioh = sc->sc_ioh; 1580 u_int8_t lcr; 1581 1582 sc->sc_ier = 0; 1583 #ifdef COM_PXA2X0 1584 if (sc->sc_uarttype == COM_UART_PXA2X0) 1585 sc->sc_ier |= IER_EUART; 1586 #endif 1587 /* disable interrupts */ 1588 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1589 1590 #ifdef COM_CONSOLE 1591 if (sc->sc_iot == comconsiot && sc->sc_iobase == comconsaddr) { 1592 comconsattached = 1; 1593 delay(10000); /* wait for output to finish */ 1594 SET(sc->sc_hwflags, COM_HW_CONSOLE); 1595 SET(sc->sc_swflags, COM_SW_SOFTCAR); 1596 } 1597 #endif 1598 1599 /* 1600 * Probe for all known forms of UART. 1601 */ 1602 lcr = bus_space_read_1(iot, ioh, com_lcr); 1603 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 1604 bus_space_write_1(iot, ioh, com_efr, 0); 1605 bus_space_write_1(iot, ioh, com_lcr, 0); 1606 1607 bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE); 1608 delay(100); 1609 1610 /* 1611 * Skip specific probes if attachment code knows it already. 1612 */ 1613 if (sc->sc_uarttype == COM_UART_UNKNOWN) 1614 switch (bus_space_read_1(iot, ioh, com_iir) >> 6) { 1615 case 0: 1616 sc->sc_uarttype = COM_UART_16450; 1617 break; 1618 case 2: 1619 sc->sc_uarttype = COM_UART_16550; 1620 break; 1621 case 3: 1622 sc->sc_uarttype = COM_UART_16550A; 1623 break; 1624 default: 1625 sc->sc_uarttype = COM_UART_UNKNOWN; 1626 break; 1627 } 1628 1629 if (sc->sc_uarttype == COM_UART_16550A) { /* Probe for ST16650s */ 1630 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1631 if (bus_space_read_1(iot, ioh, com_efr) == 0) { 1632 sc->sc_uarttype = COM_UART_ST16650; 1633 } else { 1634 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 1635 if (bus_space_read_1(iot, ioh, com_efr) == 0) 1636 sc->sc_uarttype = COM_UART_ST16650V2; 1637 } 1638 } 1639 1640 #if 0 /* until com works with large FIFOs */ 1641 if (sc->sc_uarttype == COM_UART_ST16650V2) { /* Probe for XR16850s */ 1642 u_int8_t dlbl, dlbh; 1643 1644 /* Enable latch access and get the current values. */ 1645 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1646 dlbl = bus_space_read_1(iot, ioh, com_dlbl); 1647 dlbh = bus_space_read_1(iot, ioh, com_dlbh); 1648 1649 /* Zero out the latch divisors */ 1650 bus_space_write_1(iot, ioh, com_dlbl, 0); 1651 bus_space_write_1(iot, ioh, com_dlbh, 0); 1652 1653 if (bus_space_read_1(iot, ioh, com_dlbh) == 0x10) { 1654 sc->sc_uarttype = COM_UART_XR16850; 1655 sc->sc_uartrev = bus_space_read_1(iot, ioh, com_dlbl); 1656 } 1657 1658 /* Reset to original. */ 1659 bus_space_write_1(iot, ioh, com_dlbl, dlbl); 1660 bus_space_write_1(iot, ioh, com_dlbh, dlbh); 1661 } 1662 #endif 1663 1664 if (sc->sc_uarttype == COM_UART_16550A) { /* Probe for TI16750s */ 1665 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1666 bus_space_write_1(iot, ioh, com_fifo, 1667 FIFO_ENABLE | FIFO_ENABLE_64BYTE); 1668 if ((bus_space_read_1(iot, ioh, com_iir) >> 5) == 7) { 1669 #if 0 1670 bus_space_write_1(iot, ioh, com_lcr, 0); 1671 if ((bus_space_read_1(iot, ioh, com_iir) >> 5) == 6) 1672 #endif 1673 sc->sc_uarttype = COM_UART_TI16750; 1674 } 1675 bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE); 1676 } 1677 1678 /* Reset the LCR (latch access is probably enabled). */ 1679 bus_space_write_1(iot, ioh, com_lcr, lcr); 1680 if (sc->sc_uarttype == COM_UART_16450) { /* Probe for 8250 */ 1681 u_int8_t scr0, scr1, scr2; 1682 1683 scr0 = bus_space_read_1(iot, ioh, com_scratch); 1684 bus_space_write_1(iot, ioh, com_scratch, 0xa5); 1685 scr1 = bus_space_read_1(iot, ioh, com_scratch); 1686 bus_space_write_1(iot, ioh, com_scratch, 0x5a); 1687 scr2 = bus_space_read_1(iot, ioh, com_scratch); 1688 bus_space_write_1(iot, ioh, com_scratch, scr0); 1689 1690 if ((scr1 != 0xa5) || (scr2 != 0x5a)) 1691 sc->sc_uarttype = COM_UART_8250; 1692 } 1693 1694 /* 1695 * Print UART type and initialize ourself. 1696 */ 1697 switch (sc->sc_uarttype) { 1698 case COM_UART_UNKNOWN: 1699 printf(": unknown uart\n"); 1700 break; 1701 case COM_UART_8250: 1702 printf(": ns8250, no fifo\n"); 1703 break; 1704 case COM_UART_16450: 1705 printf(": ns16450, no fifo\n"); 1706 break; 1707 case COM_UART_16550: 1708 printf(": ns16550, no working fifo\n"); 1709 break; 1710 case COM_UART_16550A: 1711 if (sc->sc_fifolen == 0) 1712 sc->sc_fifolen = 16; 1713 printf(": ns16550a, %d byte fifo\n", sc->sc_fifolen); 1714 SET(sc->sc_hwflags, COM_HW_FIFO); 1715 break; 1716 #ifdef COM_PXA2X0 1717 case COM_UART_PXA2X0: 1718 printf(": pxa2x0, 32 byte fifo"); 1719 SET(sc->sc_hwflags, COM_HW_FIFO); 1720 sc->sc_fifolen = 32; 1721 if (sc->sc_iobase == comsiraddr) { 1722 SET(sc->sc_hwflags, COM_HW_SIR); 1723 printf(" (SIR)"); 1724 } 1725 printf("\n"); 1726 break; 1727 #endif 1728 case COM_UART_ST16650: 1729 printf(": st16650, no working fifo\n"); 1730 break; 1731 case COM_UART_ST16650V2: 1732 if (sc->sc_fifolen == 0) 1733 sc->sc_fifolen = 32; 1734 printf(": st16650, %d byte fifo\n", sc->sc_fifolen); 1735 SET(sc->sc_hwflags, COM_HW_FIFO); 1736 break; 1737 case COM_UART_ST16C654: 1738 printf(": st16c654, 64 byte fifo\n"); 1739 SET(sc->sc_hwflags, COM_HW_FIFO); 1740 sc->sc_fifolen = 64; 1741 break; 1742 case COM_UART_TI16750: 1743 printf(": ti16750, 64 byte fifo\n"); 1744 SET(sc->sc_hwflags, COM_HW_FIFO); 1745 sc->sc_fifolen = 64; 1746 break; 1747 #if 0 1748 case COM_UART_XR16850: 1749 printf(": xr16850 (rev %d), 128 byte fifo\n", sc->sc_uartrev); 1750 SET(sc->sc_hwflags, COM_HW_FIFO); 1751 sc->sc_fifolen = 128; 1752 break; 1753 #ifdef COM_UART_OX16C950 1754 case COM_UART_OX16C950: 1755 printf(": ox16c950 (rev %d), 128 byte fifo\n", sc->sc_uartrev); 1756 SET(sc->sc_hwflags, COM_HW_FIFO); 1757 sc->sc_fifolen = 128; 1758 break; 1759 #endif 1760 #endif 1761 default: 1762 panic("comattach: bad fifo type"); 1763 } 1764 1765 #ifdef KGDB 1766 /* 1767 * Allow kgdb to "take over" this port. If this is 1768 * the kgdb device, it has exclusive use. 1769 */ 1770 1771 if (iot == com_kgdb_iot && sc->sc_iobase == com_kgdb_addr && 1772 !ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1773 printf("%s: kgdb\n", sc->sc_dev.dv_xname); 1774 SET(sc->sc_hwflags, COM_HW_KGDB); 1775 } 1776 #endif /* KGDB */ 1777 1778 #if defined(COM_CONSOLE) || defined(KGDB) 1779 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 1780 #endif 1781 com_fifo_probe(sc); 1782 1783 if (sc->sc_fifolen == 0) { 1784 CLR(sc->sc_hwflags, COM_HW_FIFO); 1785 sc->sc_fifolen = 1; 1786 } 1787 1788 /* clear and disable fifo */ 1789 bus_space_write_1(iot, ioh, com_fifo, FIFO_RCV_RST | FIFO_XMT_RST); 1790 if (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 1791 (void)bus_space_read_1(iot, ioh, com_data); 1792 bus_space_write_1(iot, ioh, com_fifo, 0); 1793 1794 sc->sc_mcr = 0; 1795 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1796 1797 #ifdef COM_CONSOLE 1798 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1799 int maj; 1800 1801 /* locate the major number */ 1802 for (maj = 0; maj < nchrdev; maj++) 1803 if (cdevsw[maj].d_open == comopen) 1804 break; 1805 1806 if (maj < nchrdev && cn_tab->cn_dev == NODEV) 1807 cn_tab->cn_dev = makedev(maj, sc->sc_dev.dv_unit); 1808 1809 printf("%s: console\n", sc->sc_dev.dv_xname); 1810 } 1811 #endif 1812 1813 timeout_set(&sc->sc_diag_tmo, comdiag, sc); 1814 timeout_set(&sc->sc_dtr_tmo, com_raisedtr, sc); 1815 sc->sc_si = softintr_establish(IPL_TTY, comsoft, sc); 1816 if (sc->sc_si == NULL) 1817 panic("%s: can't establish soft interrupt", 1818 sc->sc_dev.dv_xname); 1819 1820 /* 1821 * If there are no enable/disable functions, assume the device 1822 * is always enabled. 1823 */ 1824 if (!sc->enable) 1825 sc->enabled = 1; 1826 1827 #if defined(COM_CONSOLE) || defined(KGDB) 1828 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 1829 com_enable_debugport(sc); 1830 #endif 1831 } 1832 1833 void 1834 com_fifo_probe(struct com_softc *sc) 1835 { 1836 bus_space_handle_t ioh = sc->sc_ioh; 1837 bus_space_tag_t iot = sc->sc_iot; 1838 u_int8_t fifo, ier; 1839 int timo, len; 1840 1841 if (!ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1842 return; 1843 1844 ier = 0; 1845 #ifdef COM_PXA2X0 1846 if (sc->sc_uarttype == COM_UART_PXA2X0) 1847 ier |= IER_EUART; 1848 #endif 1849 bus_space_write_1(iot, ioh, com_ier, ier); 1850 bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB); 1851 bus_space_write_1(iot, ioh, com_dlbl, 3); 1852 bus_space_write_1(iot, ioh, com_dlbh, 0); 1853 bus_space_write_1(iot, ioh, com_lcr, LCR_PNONE | LCR_8BITS); 1854 bus_space_write_1(iot, ioh, com_mcr, MCR_LOOPBACK); 1855 1856 fifo = FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST; 1857 if (sc->sc_uarttype == COM_UART_TI16750) 1858 fifo |= FIFO_ENABLE_64BYTE; 1859 1860 bus_space_write_1(iot, ioh, com_fifo, fifo); 1861 1862 for (len = 0; len < 256; len++) { 1863 bus_space_write_1(iot, ioh, com_data, (len + 1)); 1864 timo = 2000; 1865 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1866 LSR_TXRDY) && --timo) 1867 delay(1); 1868 if (!timo) 1869 break; 1870 } 1871 1872 delay(100); 1873 1874 for (len = 0; len < 256; len++) { 1875 timo = 2000; 1876 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1877 LSR_RXRDY) && --timo) 1878 delay(1); 1879 if (!timo || bus_space_read_1(iot, ioh, com_data) != (len + 1)) 1880 break; 1881 } 1882 1883 /* For safety, always use the smaller value. */ 1884 if (sc->sc_fifolen > len) { 1885 printf("%s: probed fifo depth: %d bytes\n", 1886 sc->sc_dev.dv_xname, len); 1887 sc->sc_fifolen = len; 1888 } 1889 } 1890