1 /* $OpenBSD: com.c,v 1.157 2014/04/13 15:42:32 deraadt Exp $ */ 2 /* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */ 3 4 /* 5 * Copyright (c) 1997 - 1999, Jason Downs. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /*- 29 * Copyright (c) 1993, 1994, 1995, 1996 30 * Charles M. Hannum. All rights reserved. 31 * Copyright (c) 1991 The Regents of the University of California. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. Neither the name of the University nor the names of its contributors 43 * may be used to endorse or promote products derived from this software 44 * without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * @(#)com.c 7.5 (Berkeley) 5/16/91 59 */ 60 61 /* 62 * COM driver, based on HP dca driver 63 * uses National Semiconductor NS16450/NS16550AF UART 64 */ 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/ioctl.h> 68 #include <sys/selinfo.h> 69 #include <sys/tty.h> 70 #include <sys/proc.h> 71 #include <sys/conf.h> 72 #include <sys/file.h> 73 #include <sys/uio.h> 74 #include <sys/kernel.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/vnode.h> 78 #ifdef DDB 79 #include <ddb/db_var.h> 80 #endif 81 82 #include <machine/bus.h> 83 #if !defined(__sparc__) || defined(__sparc64__) 84 #include <machine/intr.h> 85 #endif 86 87 #if !defined(__sparc__) || defined(__sparc64__) 88 #define COM_CONSOLE 89 #include <dev/cons.h> 90 #endif 91 92 #include <dev/ic/comreg.h> 93 #include <dev/ic/comvar.h> 94 #include <dev/ic/ns16550reg.h> 95 #define com_lcr com_cfcr 96 97 #ifdef COM_PXA2X0 98 #define com_isr 8 99 #define ISR_SEND (ISR_RXPL | ISR_XMODE | ISR_XMITIR) 100 #define ISR_RECV (ISR_RXPL | ISR_XMODE | ISR_RCVEIR) 101 #endif 102 103 #ifdef __zaurus__ 104 #include <arch/zaurus/dev/zaurus_scoopvar.h> 105 #endif 106 107 cdev_decl(com); 108 109 static u_char tiocm_xxx2mcr(int); 110 111 void compwroff(struct com_softc *); 112 void cominit(bus_space_tag_t, bus_space_handle_t, int, int); 113 int com_is_console(bus_space_tag_t, bus_addr_t); 114 115 struct cfdriver com_cd = { 116 NULL, "com", DV_TTY 117 }; 118 119 int comdefaultrate = TTYDEF_SPEED; 120 #ifdef COM_PXA2X0 121 bus_addr_t comsiraddr; 122 #endif 123 #ifdef COM_CONSOLE 124 int comconsfreq; 125 int comconsrate = TTYDEF_SPEED; 126 bus_addr_t comconsaddr = 0; 127 int comconsattached; 128 bus_space_tag_t comconsiot; 129 bus_space_handle_t comconsioh; 130 int comconsunit; 131 tcflag_t comconscflag = TTYDEF_CFLAG; 132 #endif 133 134 int commajor; 135 136 #ifdef KGDB 137 #include <sys/kgdb.h> 138 139 bus_addr_t com_kgdb_addr; 140 bus_space_tag_t com_kgdb_iot; 141 bus_space_handle_t com_kgdb_ioh; 142 143 int com_kgdb_getc(void *); 144 void com_kgdb_putc(void *, int); 145 #endif /* KGDB */ 146 147 #define DEVUNIT(x) (minor(x) & 0x7f) 148 #define DEVCUA(x) (minor(x) & 0x80) 149 150 int 151 comspeed(long freq, long speed) 152 { 153 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 154 155 int x, err; 156 157 if (speed == 0) 158 return 0; 159 if (speed < 0) 160 return -1; 161 x = divrnd((freq / 16), speed); 162 if (x <= 0) 163 return -1; 164 err = divrnd((quad_t)freq * 1000 / 16, speed * x) - 1000; 165 if (err < 0) 166 err = -err; 167 if (err > COM_TOLERANCE) 168 return -1; 169 return x; 170 171 #undef divrnd 172 } 173 174 #ifdef COM_CONSOLE 175 int 176 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 177 { 178 int i, k; 179 180 /* force access to id reg */ 181 bus_space_write_1(iot, ioh, com_lcr, 0); 182 bus_space_write_1(iot, ioh, com_iir, 0); 183 for (i = 0; i < 32; i++) { 184 k = bus_space_read_1(iot, ioh, com_iir); 185 if (k & 0x38) { 186 bus_space_read_1(iot, ioh, com_data); /* cleanup */ 187 } else 188 break; 189 } 190 if (i >= 32) 191 return 0; 192 193 return 1; 194 } 195 #endif 196 197 int 198 com_detach(struct device *self, int flags) 199 { 200 struct com_softc *sc = (struct com_softc *)self; 201 int maj, mn; 202 203 sc->sc_swflags |= COM_SW_DEAD; 204 205 /* Locate the major number. */ 206 for (maj = 0; maj < nchrdev; maj++) 207 if (cdevsw[maj].d_open == comopen) 208 break; 209 210 /* Nuke the vnodes for any open instances. */ 211 mn = self->dv_unit; 212 vdevgone(maj, mn, mn, VCHR); 213 214 /* XXX a symbolic constant for the cua bit would be nicer. */ 215 mn |= 0x80; 216 vdevgone(maj, mn, mn, VCHR); 217 218 /* Detach and free the tty. */ 219 if (sc->sc_tty) { 220 ttyfree(sc->sc_tty); 221 } 222 223 timeout_del(&sc->sc_dtr_tmo); 224 timeout_del(&sc->sc_diag_tmo); 225 softintr_disestablish(sc->sc_si); 226 227 return (0); 228 } 229 230 int 231 com_activate(struct device *self, int act) 232 { 233 struct com_softc *sc = (struct com_softc *)self; 234 int s, rv = 0; 235 236 switch (act) { 237 case DVACT_SUSPEND: 238 if (timeout_del(&sc->sc_dtr_tmo)) { 239 /* Make sure DTR gets raised upon resume. */ 240 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 241 } 242 timeout_del(&sc->sc_diag_tmo); 243 break; 244 case DVACT_RESUME: 245 com_resume(sc); 246 break; 247 case DVACT_DEACTIVATE: 248 #ifdef KGDB 249 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 250 #else 251 if (sc->sc_hwflags & COM_HW_CONSOLE) { 252 #endif /* KGDB */ 253 rv = EBUSY; 254 break; 255 } 256 257 s = spltty(); 258 if (sc->disable != NULL && sc->enabled != 0) { 259 (*sc->disable)(sc); 260 sc->enabled = 0; 261 } 262 splx(s); 263 break; 264 } 265 return (rv); 266 } 267 268 int 269 comopen(dev_t dev, int flag, int mode, struct proc *p) 270 { 271 int unit = DEVUNIT(dev); 272 struct com_softc *sc; 273 bus_space_tag_t iot; 274 bus_space_handle_t ioh; 275 struct tty *tp; 276 int s; 277 int error = 0; 278 279 if (unit >= com_cd.cd_ndevs) 280 return ENXIO; 281 sc = com_cd.cd_devs[unit]; 282 if (!sc) 283 return ENXIO; 284 285 #ifdef KGDB 286 /* 287 * If this is the kgdb port, no other use is permitted. 288 */ 289 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 290 return (EBUSY); 291 #endif /* KGDB */ 292 293 s = spltty(); 294 if (!sc->sc_tty) { 295 tp = sc->sc_tty = ttymalloc(1000000); 296 } else 297 tp = sc->sc_tty; 298 splx(s); 299 300 tp->t_oproc = comstart; 301 tp->t_param = comparam; 302 tp->t_dev = dev; 303 if (!ISSET(tp->t_state, TS_ISOPEN)) { 304 SET(tp->t_state, TS_WOPEN); 305 ttychars(tp); 306 tp->t_iflag = TTYDEF_IFLAG; 307 tp->t_oflag = TTYDEF_OFLAG; 308 #ifdef COM_CONSOLE 309 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 310 tp->t_cflag = comconscflag; 311 tp->t_ispeed = tp->t_ospeed = comconsrate; 312 } else 313 #endif 314 { 315 tp->t_cflag = TTYDEF_CFLAG; 316 tp->t_ispeed = tp->t_ospeed = comdefaultrate; 317 } 318 if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)) 319 SET(tp->t_cflag, CLOCAL); 320 if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)) 321 SET(tp->t_cflag, CRTSCTS); 322 if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)) 323 SET(tp->t_cflag, MDMBUF); 324 tp->t_lflag = TTYDEF_LFLAG; 325 326 s = spltty(); 327 328 sc->sc_initialize = 1; 329 comparam(tp, &tp->t_termios); 330 ttsetwater(tp); 331 332 sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; 333 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 334 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 335 336 iot = sc->sc_iot; 337 ioh = sc->sc_ioh; 338 339 /* 340 * Wake up the sleepy heads. 341 */ 342 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 343 switch (sc->sc_uarttype) { 344 case COM_UART_ST16650: 345 case COM_UART_ST16650V2: 346 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 347 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 348 bus_space_write_1(iot, ioh, com_ier, 0); 349 bus_space_write_1(iot, ioh, com_efr, 0); 350 bus_space_write_1(iot, ioh, com_lcr, 0); 351 break; 352 case COM_UART_TI16750: 353 bus_space_write_1(iot, ioh, com_ier, 0); 354 break; 355 case COM_UART_PXA2X0: 356 bus_space_write_1(iot, ioh, com_ier, IER_EUART); 357 break; 358 } 359 } 360 361 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 362 u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST; 363 u_int8_t lcr; 364 365 if (tp->t_ispeed <= 1200) 366 fifo |= FIFO_TRIGGER_1; 367 else if (tp->t_ispeed <= 38400) 368 fifo |= FIFO_TRIGGER_4; 369 else 370 fifo |= FIFO_TRIGGER_8; 371 if (sc->sc_uarttype == COM_UART_TI16750) { 372 fifo |= FIFO_ENABLE_64BYTE; 373 lcr = bus_space_read_1(iot, ioh, com_lcr); 374 bus_space_write_1(iot, ioh, com_lcr, 375 lcr | LCR_DLAB); 376 } 377 378 /* 379 * (Re)enable and drain FIFOs. 380 * 381 * Certain SMC chips cause problems if the FIFOs are 382 * enabled while input is ready. Turn off the FIFO 383 * if necessary to clear the input. Test the input 384 * ready bit after enabling the FIFOs to handle races 385 * between enabling and fresh input. 386 * 387 * Set the FIFO threshold based on the receive speed. 388 */ 389 for (;;) { 390 bus_space_write_1(iot, ioh, com_fifo, 0); 391 delay(100); 392 (void) bus_space_read_1(iot, ioh, com_data); 393 bus_space_write_1(iot, ioh, com_fifo, fifo | 394 FIFO_RCV_RST | FIFO_XMT_RST); 395 delay(100); 396 if(!ISSET(bus_space_read_1(iot, ioh, 397 com_lsr), LSR_RXRDY)) 398 break; 399 } 400 if (sc->sc_uarttype == COM_UART_TI16750) 401 bus_space_write_1(iot, ioh, com_lcr, lcr); 402 } 403 404 /* Flush any pending I/O. */ 405 while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 406 (void) bus_space_read_1(iot, ioh, com_data); 407 408 /* You turn me on, baby! */ 409 sc->sc_mcr = MCR_DTR | MCR_RTS; 410 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 411 SET(sc->sc_mcr, MCR_IENABLE); 412 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 413 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 414 #ifdef COM_PXA2X0 415 if (sc->sc_uarttype == COM_UART_PXA2X0) 416 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 417 #endif 418 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 419 420 sc->sc_msr = bus_space_read_1(iot, ioh, com_msr); 421 if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) || 422 ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF)) 423 SET(tp->t_state, TS_CARR_ON); 424 else 425 CLR(tp->t_state, TS_CARR_ON); 426 #ifdef COM_PXA2X0 427 if (sc->sc_uarttype == COM_UART_PXA2X0 && 428 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 429 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 430 #ifdef __zaurus__ 431 scoop_set_irled(1); 432 #endif 433 } 434 #endif 435 } else if (ISSET(tp->t_state, TS_XCLUDE) && suser(p, 0) != 0) 436 return EBUSY; 437 else 438 s = spltty(); 439 440 if (DEVCUA(dev)) { 441 if (ISSET(tp->t_state, TS_ISOPEN)) { 442 /* Ah, but someone already is dialed in... */ 443 splx(s); 444 return EBUSY; 445 } 446 sc->sc_cua = 1; /* We go into CUA mode. */ 447 } else { 448 /* tty (not cua) device; wait for carrier if necessary. */ 449 if (ISSET(flag, O_NONBLOCK)) { 450 if (sc->sc_cua) { 451 /* Opening TTY non-blocking... but the CUA is busy. */ 452 splx(s); 453 return EBUSY; 454 } 455 } else { 456 while (sc->sc_cua || 457 (!ISSET(tp->t_cflag, CLOCAL) && 458 !ISSET(tp->t_state, TS_CARR_ON))) { 459 SET(tp->t_state, TS_WOPEN); 460 error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, ttopen, 0); 461 /* 462 * If TS_WOPEN has been reset, that means the cua device 463 * has been closed. We don't want to fail in that case, 464 * so just go around again. 465 */ 466 if (error && ISSET(tp->t_state, TS_WOPEN)) { 467 CLR(tp->t_state, TS_WOPEN); 468 if (!sc->sc_cua && !ISSET(tp->t_state, TS_ISOPEN)) 469 compwroff(sc); 470 splx(s); 471 return error; 472 } 473 } 474 } 475 } 476 splx(s); 477 478 return (*linesw[tp->t_line].l_open)(dev, tp, p); 479 } 480 481 int 482 comclose(dev_t dev, int flag, int mode, struct proc *p) 483 { 484 int unit = DEVUNIT(dev); 485 struct com_softc *sc = com_cd.cd_devs[unit]; 486 bus_space_tag_t iot = sc->sc_iot; 487 bus_space_handle_t ioh = sc->sc_ioh; 488 struct tty *tp = sc->sc_tty; 489 int s; 490 491 #ifdef COM_CONSOLE 492 /* XXX This is for cons.c. */ 493 if (!ISSET(tp->t_state, TS_ISOPEN)) 494 return 0; 495 #endif 496 497 if(sc->sc_swflags & COM_SW_DEAD) 498 return 0; 499 500 (*linesw[tp->t_line].l_close)(tp, flag, p); 501 s = spltty(); 502 if (ISSET(tp->t_state, TS_WOPEN)) { 503 /* tty device is waiting for carrier; drop dtr then re-raise */ 504 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 505 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 506 timeout_add_sec(&sc->sc_dtr_tmo, 2); 507 } else { 508 /* no one else waiting; turn off the uart */ 509 compwroff(sc); 510 } 511 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 512 sc->sc_cua = 0; 513 splx(s); 514 ttyclose(tp); 515 516 #ifdef COM_CONSOLE 517 #ifdef notyet /* XXXX */ 518 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 519 ttyfree(tp); 520 sc->sc_tty = 0; 521 } 522 #endif 523 #endif 524 return 0; 525 } 526 527 void 528 compwroff(struct com_softc *sc) 529 { 530 bus_space_tag_t iot = sc->sc_iot; 531 bus_space_handle_t ioh = sc->sc_ioh; 532 struct tty *tp = sc->sc_tty; 533 534 CLR(sc->sc_lcr, LCR_SBREAK); 535 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 536 bus_space_write_1(iot, ioh, com_ier, 0); 537 if (ISSET(tp->t_cflag, HUPCL) && 538 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 539 /* XXX perhaps only clear DTR */ 540 sc->sc_mcr = 0; 541 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 542 } 543 544 /* 545 * Turn FIFO off; enter sleep mode if possible. 546 */ 547 bus_space_write_1(iot, ioh, com_fifo, 0); 548 delay(100); 549 if (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 550 (void) bus_space_read_1(iot, ioh, com_data); 551 delay(100); 552 bus_space_write_1(iot, ioh, com_fifo, 553 FIFO_RCV_RST | FIFO_XMT_RST); 554 555 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 556 switch (sc->sc_uarttype) { 557 case COM_UART_ST16650: 558 case COM_UART_ST16650V2: 559 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 560 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 561 bus_space_write_1(iot, ioh, com_ier, IER_SLEEP); 562 bus_space_write_1(iot, ioh, com_lcr, 0); 563 break; 564 case COM_UART_TI16750: 565 bus_space_write_1(iot, ioh, com_ier, IER_SLEEP); 566 break; 567 #ifdef COM_PXA2X0 568 case COM_UART_PXA2X0: 569 bus_space_write_1(iot, ioh, com_ier, 0); 570 #ifdef __zaurus__ 571 if (ISSET(sc->sc_hwflags, COM_HW_SIR)) 572 scoop_set_irled(0); 573 #endif 574 break; 575 #endif 576 } 577 } 578 } 579 580 void 581 com_resume(struct com_softc *sc) 582 { 583 struct tty *tp = sc->sc_tty; 584 bus_space_tag_t iot = sc->sc_iot; 585 bus_space_handle_t ioh = sc->sc_ioh; 586 int ospeed; 587 588 if (!tp || !ISSET(tp->t_state, TS_ISOPEN)) { 589 #ifdef COM_CONSOLE 590 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 591 cominit(iot, ioh, comconsrate, comconsfreq); 592 #endif 593 return; 594 } 595 596 /* 597 * Wake up the sleepy heads. 598 */ 599 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 600 switch (sc->sc_uarttype) { 601 case COM_UART_ST16650: 602 case COM_UART_ST16650V2: 603 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 604 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 605 bus_space_write_1(iot, ioh, com_ier, 0); 606 bus_space_write_1(iot, ioh, com_efr, 0); 607 bus_space_write_1(iot, ioh, com_lcr, 0); 608 break; 609 case COM_UART_TI16750: 610 bus_space_write_1(iot, ioh, com_ier, 0); 611 break; 612 case COM_UART_PXA2X0: 613 bus_space_write_1(iot, ioh, com_ier, IER_EUART); 614 break; 615 } 616 } 617 618 ospeed = comspeed(sc->sc_frequency, tp->t_ospeed); 619 620 if (ospeed != 0) { 621 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr | LCR_DLAB); 622 bus_space_write_1(iot, ioh, com_dlbl, ospeed); 623 bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8); 624 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 625 } else { 626 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 627 } 628 629 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 630 u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST; 631 u_int8_t lcr; 632 633 if (tp->t_ispeed <= 1200) 634 fifo |= FIFO_TRIGGER_1; 635 else if (tp->t_ispeed <= 38400) 636 fifo |= FIFO_TRIGGER_4; 637 else 638 fifo |= FIFO_TRIGGER_8; 639 if (sc->sc_uarttype == COM_UART_TI16750) { 640 fifo |= FIFO_ENABLE_64BYTE; 641 lcr = bus_space_read_1(iot, ioh, com_lcr); 642 bus_space_write_1(iot, ioh, com_lcr, 643 lcr | LCR_DLAB); 644 } 645 646 /* 647 * (Re)enable and drain FIFOs. 648 * 649 * Certain SMC chips cause problems if the FIFOs are 650 * enabled while input is ready. Turn off the FIFO 651 * if necessary to clear the input. Test the input 652 * ready bit after enabling the FIFOs to handle races 653 * between enabling and fresh input. 654 * 655 * Set the FIFO threshold based on the receive speed. 656 */ 657 for (;;) { 658 bus_space_write_1(iot, ioh, com_fifo, 0); 659 delay(100); 660 (void) bus_space_read_1(iot, ioh, com_data); 661 bus_space_write_1(iot, ioh, com_fifo, fifo | 662 FIFO_RCV_RST | FIFO_XMT_RST); 663 delay(100); 664 if(!ISSET(bus_space_read_1(iot, ioh, 665 com_lsr), LSR_RXRDY)) 666 break; 667 } 668 if (sc->sc_uarttype == COM_UART_TI16750) 669 bus_space_write_1(iot, ioh, com_lcr, lcr); 670 } 671 672 /* You turn me on, baby! */ 673 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 674 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 675 676 #ifdef COM_PXA2X0 677 if (sc->sc_uarttype == COM_UART_PXA2X0 && 678 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 679 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 680 #ifdef __zaurus__ 681 scoop_set_irled(1); 682 #endif 683 } 684 #endif 685 } 686 687 void 688 com_raisedtr(void *arg) 689 { 690 struct com_softc *sc = arg; 691 692 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 693 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, sc->sc_mcr); 694 } 695 696 int 697 comread(dev_t dev, struct uio *uio, int flag) 698 { 699 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 700 struct tty *tp = sc->sc_tty; 701 702 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 703 } 704 705 int 706 comwrite(dev_t dev, struct uio *uio, int flag) 707 { 708 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 709 struct tty *tp = sc->sc_tty; 710 711 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 712 } 713 714 struct tty * 715 comtty(dev_t dev) 716 { 717 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 718 struct tty *tp = sc->sc_tty; 719 720 return (tp); 721 } 722 723 static u_char 724 tiocm_xxx2mcr(int data) 725 { 726 u_char m = 0; 727 728 if (ISSET(data, TIOCM_DTR)) 729 SET(m, MCR_DTR); 730 if (ISSET(data, TIOCM_RTS)) 731 SET(m, MCR_RTS); 732 return m; 733 } 734 735 int 736 comioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 737 { 738 int unit = DEVUNIT(dev); 739 struct com_softc *sc = com_cd.cd_devs[unit]; 740 struct tty *tp = sc->sc_tty; 741 bus_space_tag_t iot = sc->sc_iot; 742 bus_space_handle_t ioh = sc->sc_ioh; 743 int error; 744 745 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 746 if (error >= 0) 747 return error; 748 error = ttioctl(tp, cmd, data, flag, p); 749 if (error >= 0) 750 return error; 751 752 switch (cmd) { 753 case TIOCSBRK: 754 SET(sc->sc_lcr, LCR_SBREAK); 755 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 756 break; 757 case TIOCCBRK: 758 CLR(sc->sc_lcr, LCR_SBREAK); 759 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 760 break; 761 case TIOCSDTR: 762 SET(sc->sc_mcr, sc->sc_dtr); 763 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 764 break; 765 case TIOCCDTR: 766 CLR(sc->sc_mcr, sc->sc_dtr); 767 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 768 break; 769 case TIOCMSET: 770 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 771 case TIOCMBIS: 772 SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 773 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 774 break; 775 case TIOCMBIC: 776 CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 777 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 778 break; 779 case TIOCMGET: { 780 u_char m; 781 int bits = 0; 782 783 m = sc->sc_mcr; 784 if (ISSET(m, MCR_DTR)) 785 SET(bits, TIOCM_DTR); 786 if (ISSET(m, MCR_RTS)) 787 SET(bits, TIOCM_RTS); 788 m = sc->sc_msr; 789 if (ISSET(m, MSR_DCD)) 790 SET(bits, TIOCM_CD); 791 if (ISSET(m, MSR_CTS)) 792 SET(bits, TIOCM_CTS); 793 if (ISSET(m, MSR_DSR)) 794 SET(bits, TIOCM_DSR); 795 if (ISSET(m, MSR_RI | MSR_TERI)) 796 SET(bits, TIOCM_RI); 797 if (bus_space_read_1(iot, ioh, com_ier)) 798 SET(bits, TIOCM_LE); 799 *(int *)data = bits; 800 break; 801 } 802 case TIOCGFLAGS: { 803 int driverbits, userbits = 0; 804 805 driverbits = sc->sc_swflags; 806 if (ISSET(driverbits, COM_SW_SOFTCAR)) 807 SET(userbits, TIOCFLAG_SOFTCAR); 808 if (ISSET(driverbits, COM_SW_CLOCAL)) 809 SET(userbits, TIOCFLAG_CLOCAL); 810 if (ISSET(driverbits, COM_SW_CRTSCTS)) 811 SET(userbits, TIOCFLAG_CRTSCTS); 812 if (ISSET(driverbits, COM_SW_MDMBUF)) 813 SET(userbits, TIOCFLAG_MDMBUF); 814 if (ISSET(driverbits, COM_SW_PPS)) 815 SET(userbits, TIOCFLAG_PPS); 816 817 *(int *)data = userbits; 818 break; 819 } 820 case TIOCSFLAGS: { 821 int userbits, driverbits = 0; 822 823 error = suser(p, 0); 824 if (error != 0) 825 return(EPERM); 826 827 userbits = *(int *)data; 828 if (ISSET(userbits, TIOCFLAG_SOFTCAR) || 829 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 830 SET(driverbits, COM_SW_SOFTCAR); 831 if (ISSET(userbits, TIOCFLAG_CLOCAL)) 832 SET(driverbits, COM_SW_CLOCAL); 833 if (ISSET(userbits, TIOCFLAG_CRTSCTS)) 834 SET(driverbits, COM_SW_CRTSCTS); 835 if (ISSET(userbits, TIOCFLAG_MDMBUF)) 836 SET(driverbits, COM_SW_MDMBUF); 837 if (ISSET(userbits, TIOCFLAG_PPS)) 838 SET(driverbits, COM_SW_PPS); 839 840 sc->sc_swflags = driverbits; 841 break; 842 } 843 default: 844 return ENOTTY; 845 } 846 847 return 0; 848 } 849 850 /* already called at spltty */ 851 int 852 comparam(struct tty *tp, struct termios *t) 853 { 854 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)]; 855 bus_space_tag_t iot = sc->sc_iot; 856 bus_space_handle_t ioh = sc->sc_ioh; 857 int ospeed = comspeed(sc->sc_frequency, t->c_ospeed); 858 u_char lcr; 859 tcflag_t oldcflag; 860 861 /* Check requested parameters. */ 862 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) 863 return EINVAL; 864 865 lcr = ISSET(sc->sc_lcr, LCR_SBREAK); 866 867 switch (ISSET(t->c_cflag, CSIZE)) { 868 case CS5: 869 SET(lcr, LCR_5BITS); 870 break; 871 case CS6: 872 SET(lcr, LCR_6BITS); 873 break; 874 case CS7: 875 SET(lcr, LCR_7BITS); 876 break; 877 case CS8: 878 SET(lcr, LCR_8BITS); 879 break; 880 } 881 if (ISSET(t->c_cflag, PARENB)) { 882 SET(lcr, LCR_PENAB); 883 if (!ISSET(t->c_cflag, PARODD)) 884 SET(lcr, LCR_PEVEN); 885 } 886 if (ISSET(t->c_cflag, CSTOPB)) 887 SET(lcr, LCR_STOPB); 888 889 sc->sc_lcr = lcr; 890 891 if (ospeed == 0) { 892 CLR(sc->sc_mcr, MCR_DTR); 893 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 894 } 895 896 /* 897 * Set the FIFO threshold based on the receive speed, if we are 898 * changing it. 899 */ 900 if (sc->sc_initialize || (tp->t_ispeed != t->c_ispeed)) { 901 sc->sc_initialize = 0; 902 903 if (ospeed != 0) { 904 /* 905 * Make sure the transmit FIFO is empty before 906 * proceeding. If we don't do this, some revisions 907 * of the UART will hang. Interestingly enough, 908 * even if we do this while the last character is 909 * still being pushed out, they don't hang. This 910 * seems good enough. 911 */ 912 while (ISSET(tp->t_state, TS_BUSY)) { 913 int error; 914 915 ++sc->sc_halt; 916 error = ttysleep(tp, &tp->t_outq, 917 TTOPRI | PCATCH, "comprm", 0); 918 --sc->sc_halt; 919 if (error) { 920 comstart(tp); 921 return (error); 922 } 923 } 924 925 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 926 bus_space_write_1(iot, ioh, com_dlbl, ospeed); 927 bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8); 928 bus_space_write_1(iot, ioh, com_lcr, lcr); 929 SET(sc->sc_mcr, MCR_DTR); 930 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 931 } else 932 bus_space_write_1(iot, ioh, com_lcr, lcr); 933 934 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 935 if (sc->sc_uarttype == COM_UART_TI16750) { 936 bus_space_write_1(iot, ioh, com_lcr, 937 lcr | LCR_DLAB); 938 bus_space_write_1(iot, ioh, com_fifo, 939 FIFO_ENABLE | FIFO_ENABLE_64BYTE | 940 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 941 bus_space_write_1(iot, ioh, com_lcr, lcr); 942 } else 943 bus_space_write_1(iot, ioh, com_fifo, 944 FIFO_ENABLE | 945 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 946 } 947 } else 948 bus_space_write_1(iot, ioh, com_lcr, lcr); 949 950 /* When not using CRTSCTS, RTS follows DTR. */ 951 if (!ISSET(t->c_cflag, CRTSCTS)) { 952 if (ISSET(sc->sc_mcr, MCR_DTR)) { 953 if (!ISSET(sc->sc_mcr, MCR_RTS)) { 954 SET(sc->sc_mcr, MCR_RTS); 955 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 956 } 957 } else { 958 if (ISSET(sc->sc_mcr, MCR_RTS)) { 959 CLR(sc->sc_mcr, MCR_RTS); 960 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 961 } 962 } 963 sc->sc_dtr = MCR_DTR | MCR_RTS; 964 } else 965 sc->sc_dtr = MCR_DTR; 966 967 /* and copy to tty */ 968 tp->t_ispeed = t->c_ispeed; 969 tp->t_ospeed = t->c_ospeed; 970 oldcflag = tp->t_cflag; 971 tp->t_cflag = t->c_cflag; 972 973 /* 974 * If DCD is off and MDMBUF is changed, ask the tty layer if we should 975 * stop the device. 976 */ 977 if (!ISSET(sc->sc_msr, MSR_DCD) && 978 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 979 ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) && 980 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 981 CLR(sc->sc_mcr, sc->sc_dtr); 982 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 983 } 984 985 /* Just to be sure... */ 986 comstart(tp); 987 return 0; 988 } 989 990 void 991 comstart(struct tty *tp) 992 { 993 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)]; 994 bus_space_tag_t iot = sc->sc_iot; 995 bus_space_handle_t ioh = sc->sc_ioh; 996 int s; 997 998 s = spltty(); 999 if (ISSET(tp->t_state, TS_BUSY)) 1000 goto out; 1001 if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) || sc->sc_halt > 0) 1002 goto stopped; 1003 if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS)) 1004 goto stopped; 1005 ttwakeupwr(tp); 1006 if (tp->t_outq.c_cc == 0) 1007 goto stopped; 1008 SET(tp->t_state, TS_BUSY); 1009 1010 #ifdef COM_PXA2X0 1011 /* Enable transmitter slow infrared mode. */ 1012 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1013 ISSET(sc->sc_hwflags, COM_HW_SIR)) 1014 bus_space_write_1(iot, ioh, com_isr, ISR_SEND); 1015 #endif 1016 1017 /* Enable transmit completion interrupts. */ 1018 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1019 SET(sc->sc_ier, IER_ETXRDY); 1020 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1021 } 1022 1023 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1024 u_char buffer[128]; /* largest fifo */ 1025 int i, n; 1026 1027 n = q_to_b(&tp->t_outq, buffer, 1028 min(sc->sc_fifolen, sizeof buffer)); 1029 for (i = 0; i < n; i++) { 1030 bus_space_write_1(iot, ioh, com_data, buffer[i]); 1031 } 1032 bzero(buffer, n); 1033 } else if (tp->t_outq.c_cc != 0) 1034 bus_space_write_1(iot, ioh, com_data, getc(&tp->t_outq)); 1035 out: 1036 splx(s); 1037 return; 1038 stopped: 1039 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1040 CLR(sc->sc_ier, IER_ETXRDY); 1041 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1042 #ifdef COM_PXA2X0 1043 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1044 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 1045 int timo; 1046 1047 /* Wait for empty transmit shift register. */ 1048 timo = 20000; 1049 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1050 LSR_TSRE) && --timo) 1051 delay(1); 1052 1053 /* Enable receiver slow infrared mode. */ 1054 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1055 } 1056 #endif 1057 } 1058 splx(s); 1059 } 1060 1061 /* 1062 * Stop output on a line. 1063 */ 1064 int 1065 comstop(struct tty *tp, int flag) 1066 { 1067 int s; 1068 1069 s = spltty(); 1070 if (ISSET(tp->t_state, TS_BUSY)) 1071 if (!ISSET(tp->t_state, TS_TTSTOP)) 1072 SET(tp->t_state, TS_FLUSH); 1073 splx(s); 1074 return 0; 1075 } 1076 1077 void 1078 comdiag(void *arg) 1079 { 1080 struct com_softc *sc = arg; 1081 int overflows, floods; 1082 int s; 1083 1084 s = spltty(); 1085 sc->sc_errors = 0; 1086 overflows = sc->sc_overflows; 1087 sc->sc_overflows = 0; 1088 floods = sc->sc_floods; 1089 sc->sc_floods = 0; 1090 splx(s); 1091 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s\n", 1092 sc->sc_dev.dv_xname, 1093 overflows, overflows == 1 ? "" : "s", 1094 floods, floods == 1 ? "" : "s"); 1095 } 1096 1097 void 1098 comsoft(void *arg) 1099 { 1100 struct com_softc *sc = (struct com_softc *)arg; 1101 struct tty *tp; 1102 u_char *ibufp; 1103 u_char *ibufend; 1104 int c; 1105 int s; 1106 static int lsrmap[8] = { 1107 0, TTY_PE, 1108 TTY_FE, TTY_PE|TTY_FE, 1109 TTY_FE, TTY_PE|TTY_FE, 1110 TTY_FE, TTY_PE|TTY_FE 1111 }; 1112 1113 if (sc == NULL || sc->sc_ibufp == sc->sc_ibuf) 1114 return; 1115 1116 tp = sc->sc_tty; 1117 1118 s = spltty(); 1119 1120 ibufp = sc->sc_ibuf; 1121 ibufend = sc->sc_ibufp; 1122 1123 if (ibufp == ibufend) { 1124 splx(s); 1125 return; 1126 } 1127 1128 sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? 1129 sc->sc_ibufs[1] : sc->sc_ibufs[0]; 1130 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 1131 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 1132 1133 if (tp == NULL || !ISSET(tp->t_state, TS_ISOPEN)) { 1134 splx(s); 1135 return; 1136 } 1137 1138 if (ISSET(tp->t_cflag, CRTSCTS) && 1139 !ISSET(sc->sc_mcr, MCR_RTS)) { 1140 /* XXX */ 1141 SET(sc->sc_mcr, MCR_RTS); 1142 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, 1143 sc->sc_mcr); 1144 } 1145 1146 splx(s); 1147 1148 while (ibufp < ibufend) { 1149 c = *ibufp++; 1150 if (ISSET(*ibufp, LSR_OE)) { 1151 sc->sc_overflows++; 1152 if (sc->sc_errors++ == 0) 1153 timeout_add_sec(&sc->sc_diag_tmo, 60); 1154 } 1155 /* This is ugly, but fast. */ 1156 c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2]; 1157 (*linesw[tp->t_line].l_rint)(c, tp); 1158 } 1159 } 1160 1161 #ifdef KGDB 1162 1163 /* 1164 * If a line break is set, or data matches one of the characters 1165 * gdb uses to signal a connection, then start up kgdb. Just gobble 1166 * any other data. Done in a stand alone function because comintr 1167 * does tty stuff and we don't have one. 1168 */ 1169 1170 int 1171 kgdbintr(void *arg) 1172 { 1173 struct com_softc *sc = arg; 1174 bus_space_tag_t iot = sc->sc_iot; 1175 bus_space_handle_t ioh = sc->sc_ioh; 1176 u_char lsr, data, msr, delta; 1177 1178 if (!ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1179 return(0); 1180 1181 for (;;) { 1182 lsr = bus_space_read_1(iot, ioh, com_lsr); 1183 if (ISSET(lsr, LSR_RXRDY)) { 1184 do { 1185 data = bus_space_read_1(iot, ioh, com_data); 1186 if (data == 3 || data == '$' || data == '+' || 1187 ISSET(lsr, LSR_BI)) { 1188 kgdb_connect(1); 1189 data = 0; 1190 } 1191 lsr = bus_space_read_1(iot, ioh, com_lsr); 1192 } while (ISSET(lsr, LSR_RXRDY)); 1193 1194 } 1195 if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE)) 1196 printf("weird lsr %02x\n", lsr); 1197 1198 msr = bus_space_read_1(iot, ioh, com_msr); 1199 1200 if (msr != sc->sc_msr) { 1201 delta = msr ^ sc->sc_msr; 1202 sc->sc_msr = msr; 1203 if (ISSET(delta, MSR_DCD)) { 1204 if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 1205 CLR(sc->sc_mcr, sc->sc_dtr); 1206 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1207 } 1208 } 1209 } 1210 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1211 return (1); 1212 } 1213 } 1214 #endif /* KGDB */ 1215 1216 int 1217 comintr(void *arg) 1218 { 1219 struct com_softc *sc = arg; 1220 bus_space_tag_t iot = sc->sc_iot; 1221 bus_space_handle_t ioh = sc->sc_ioh; 1222 struct tty *tp; 1223 u_char lsr, data, msr, delta; 1224 1225 if (!sc->sc_tty) 1226 return (0); /* Can't do squat. */ 1227 1228 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1229 return (0); 1230 1231 tp = sc->sc_tty; 1232 1233 for (;;) { 1234 lsr = bus_space_read_1(iot, ioh, com_lsr); 1235 1236 if (ISSET(lsr, LSR_RXRDY)) { 1237 u_char *p = sc->sc_ibufp; 1238 1239 softintr_schedule(sc->sc_si); 1240 do { 1241 data = bus_space_read_1(iot, ioh, com_data); 1242 if (ISSET(lsr, LSR_BI)) { 1243 #if defined(COM_CONSOLE) && defined(DDB) 1244 if (ISSET(sc->sc_hwflags, 1245 COM_HW_CONSOLE)) { 1246 if (db_console) 1247 Debugger(); 1248 goto next; 1249 } 1250 #endif 1251 data = 0; 1252 } 1253 if (p >= sc->sc_ibufend) { 1254 sc->sc_floods++; 1255 if (sc->sc_errors++ == 0) 1256 timeout_add_sec(&sc->sc_diag_tmo, 60); 1257 } else { 1258 *p++ = data; 1259 *p++ = lsr; 1260 if (p == sc->sc_ibufhigh && 1261 ISSET(tp->t_cflag, CRTSCTS)) { 1262 /* XXX */ 1263 CLR(sc->sc_mcr, MCR_RTS); 1264 bus_space_write_1(iot, ioh, com_mcr, 1265 sc->sc_mcr); 1266 } 1267 } 1268 #if defined(COM_CONSOLE) && defined(DDB) 1269 next: 1270 #endif 1271 lsr = bus_space_read_1(iot, ioh, com_lsr); 1272 } while (ISSET(lsr, LSR_RXRDY)); 1273 1274 sc->sc_ibufp = p; 1275 } 1276 msr = bus_space_read_1(iot, ioh, com_msr); 1277 1278 if (msr != sc->sc_msr) { 1279 delta = msr ^ sc->sc_msr; 1280 1281 ttytstamp(tp, sc->sc_msr & MSR_CTS, msr & MSR_CTS, 1282 sc->sc_msr & MSR_DCD, msr & MSR_DCD); 1283 1284 sc->sc_msr = msr; 1285 if (ISSET(delta, MSR_DCD)) { 1286 if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 1287 (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) { 1288 CLR(sc->sc_mcr, sc->sc_dtr); 1289 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1290 } 1291 } 1292 if (ISSET(delta & msr, MSR_CTS) && 1293 ISSET(tp->t_cflag, CRTSCTS)) { 1294 /* the line is up and we want to do rts/cts flow control */ 1295 (*linesw[tp->t_line].l_start)(tp); 1296 } 1297 } 1298 1299 if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) { 1300 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 1301 if (sc->sc_halt > 0) 1302 wakeup(&tp->t_outq); 1303 (*linesw[tp->t_line].l_start)(tp); 1304 } 1305 1306 #ifdef COM_PXA2X0 1307 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1308 ISSET(sc->sc_hwflags, COM_HW_SIR) && 1309 ISSET(lsr, LSR_TXRDY) && ISSET(lsr, LSR_TSRE)) 1310 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1311 #endif 1312 1313 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1314 return (1); 1315 } 1316 } 1317 1318 /* 1319 * The following functions are polled getc and putc routines, shared 1320 * by the console and kgdb glue. 1321 */ 1322 1323 int 1324 com_common_getc(bus_space_tag_t iot, bus_space_handle_t ioh) 1325 { 1326 int s = splhigh(); 1327 u_char stat, c; 1328 1329 #ifdef COM_PXA2X0 1330 if (com_is_console(iot, comsiraddr)) 1331 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1332 #endif 1333 1334 /* Block until a character becomes available. */ 1335 while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 1336 continue; 1337 1338 c = bus_space_read_1(iot, ioh, com_data); 1339 1340 /* Clear any interrupts generated by this transmission. */ 1341 stat = bus_space_read_1(iot, ioh, com_iir); 1342 splx(s); 1343 return (c); 1344 } 1345 1346 void 1347 com_common_putc(bus_space_tag_t iot, bus_space_handle_t ioh, int c) 1348 { 1349 int s = spltty(); 1350 int timo; 1351 1352 /* Wait for any pending transmission to finish. */ 1353 timo = 2000; 1354 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo) 1355 delay(1); 1356 1357 #ifdef COM_PXA2X0 1358 if (com_is_console(iot, comsiraddr)) 1359 bus_space_write_1(iot, ioh, com_isr, ISR_SEND); 1360 #endif 1361 bus_space_write_1(iot, ioh, com_data, (u_int8_t)(c & 0xff)); 1362 bus_space_barrier(iot, ioh, 0, COM_NPORTS, 1363 (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)); 1364 1365 /* Wait for this transmission to complete. */ 1366 timo = 2000; 1367 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo) 1368 delay(1); 1369 1370 #ifdef COM_PXA2X0 1371 if (com_is_console(iot, comsiraddr)) { 1372 /* Wait for transmit shift register to become empty. */ 1373 timo = 20000; 1374 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TSRE) 1375 && --timo) 1376 delay(1); 1377 1378 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1379 } 1380 #endif 1381 1382 splx(s); 1383 } 1384 1385 void 1386 cominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int frequency) 1387 { 1388 int s = splhigh(); 1389 u_char stat; 1390 1391 bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB); 1392 rate = comspeed(frequency, rate); /* XXX not comdefaultrate? */ 1393 bus_space_write_1(iot, ioh, com_dlbl, rate); 1394 bus_space_write_1(iot, ioh, com_dlbh, rate >> 8); 1395 bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS); 1396 bus_space_write_1(iot, ioh, com_mcr, MCR_DTR | MCR_RTS); 1397 #ifdef COM_PXA2X0 1398 /* XXX */ 1399 bus_space_write_1(iot, ioh, com_ier, IER_EUART); /* Make sure they are off */ 1400 #else 1401 bus_space_write_1(iot, ioh, com_ier, 0); /* Make sure they are off */ 1402 #endif 1403 bus_space_write_1(iot, ioh, com_fifo, 1404 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 1405 stat = bus_space_read_1(iot, ioh, com_iir); 1406 splx(s); 1407 } 1408 1409 #ifdef COM_CONSOLE 1410 void 1411 comcnprobe(struct consdev *cp) 1412 { 1413 bus_space_handle_t ioh; 1414 int found; 1415 1416 if (comconsaddr == 0) 1417 return; 1418 1419 if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS, 0, &ioh)) 1420 return; 1421 found = comprobe1(comconsiot, ioh); 1422 bus_space_unmap(comconsiot, ioh, COM_NPORTS); 1423 if (!found) 1424 return; 1425 1426 /* Locate the major number. */ 1427 for (commajor = 0; commajor < nchrdev; commajor++) 1428 if (cdevsw[commajor].d_open == comopen) 1429 break; 1430 1431 /* Initialize required fields. */ 1432 cp->cn_dev = makedev(commajor, comconsunit); 1433 cp->cn_pri = CN_HIGHPRI; 1434 } 1435 1436 void 1437 comcninit(struct consdev *cp) 1438 { 1439 if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS, 0, &comconsioh)) 1440 panic("comcninit: mapping failed"); 1441 1442 if (comconsfreq == 0) 1443 comconsfreq = COM_FREQ; 1444 1445 cominit(comconsiot, comconsioh, comconsrate, comconsfreq); 1446 } 1447 1448 int 1449 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 1450 int frequency, tcflag_t cflag) 1451 { 1452 static struct consdev comcons = { 1453 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, 1454 NODEV, CN_LOWPRI 1455 }; 1456 1457 #ifndef __sparc64__ 1458 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &comconsioh)) 1459 return ENOMEM; 1460 #endif 1461 1462 cominit(iot, comconsioh, rate, frequency); 1463 1464 cn_tab = &comcons; 1465 1466 comconsiot = iot; 1467 comconsaddr = iobase; 1468 comconscflag = cflag; 1469 comconsfreq = frequency; 1470 comconsrate = rate; 1471 1472 return (0); 1473 } 1474 1475 int 1476 comcngetc(dev_t dev) 1477 { 1478 return (com_common_getc(comconsiot, comconsioh)); 1479 } 1480 1481 /* 1482 * Console kernel output character routine. 1483 */ 1484 void 1485 comcnputc(dev_t dev, int c) 1486 { 1487 com_common_putc(comconsiot, comconsioh, c); 1488 } 1489 1490 void 1491 comcnpollc(dev_t dev, int on) 1492 { 1493 1494 } 1495 #endif /* COM_CONSOLE */ 1496 1497 #ifdef KGDB 1498 int 1499 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 1500 int frequency, tcflag_t cflag) 1501 { 1502 #ifdef COM_CONSOLE 1503 if (iot == comconsiot && iobase == comconsaddr) { 1504 return (EBUSY); /* cannot share with console */ 1505 } 1506 #endif 1507 1508 com_kgdb_iot = iot; 1509 com_kgdb_addr = iobase; 1510 1511 if (bus_space_map(com_kgdb_iot, com_kgdb_addr, COM_NPORTS, 0, 1512 &com_kgdb_ioh)) 1513 panic("com_kgdb_attach: mapping failed"); 1514 1515 /* XXX We currently don't respect KGDBMODE? */ 1516 cominit(com_kgdb_iot, com_kgdb_ioh, rate, frequency); 1517 1518 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 1519 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1520 1521 return (0); 1522 } 1523 1524 /* ARGSUSED */ 1525 int 1526 com_kgdb_getc(void *arg) 1527 { 1528 1529 return (com_common_getc(com_kgdb_iot, com_kgdb_ioh)); 1530 } 1531 1532 /* ARGSUSED */ 1533 void 1534 com_kgdb_putc(void *arg, int c) 1535 { 1536 1537 return (com_common_putc(com_kgdb_iot, com_kgdb_ioh, c)); 1538 } 1539 #endif /* KGDB */ 1540 1541 #ifdef COM_PXA2X0 1542 int 1543 com_is_console(bus_space_tag_t iot, bus_addr_t iobase) 1544 { 1545 1546 if (comconsiot == iot && comconsaddr == iobase) 1547 return (1); 1548 #ifdef KGDB 1549 else if (com_kgdb_iot == iot && com_kgdb_addr == iobase) 1550 return (1); 1551 #endif 1552 return (0); 1553 } 1554 #endif /* COM_PXA2X0 */ 1555 1556 void com_enable_debugport(struct com_softc *); 1557 void com_fifo_probe(struct com_softc *); 1558 1559 #if defined(COM_CONSOLE) || defined(KGDB) 1560 void 1561 com_enable_debugport(struct com_softc *sc) 1562 { 1563 int s; 1564 1565 /* Turn on line break interrupt, set carrier. */ 1566 s = splhigh(); 1567 #ifdef KGDB 1568 SET(sc->sc_ier, IER_ERXRDY); 1569 #ifdef COM_PXA2X0 1570 if (sc->sc_uarttype == COM_UART_PXA2X0) 1571 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1572 #endif 1573 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_ier, sc->sc_ier); 1574 #endif 1575 SET(sc->sc_mcr, MCR_DTR | MCR_RTS | MCR_IENABLE); 1576 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, sc->sc_mcr); 1577 1578 splx(s); 1579 } 1580 #endif /* COM_CONSOLE || KGDB */ 1581 1582 void 1583 com_attach_subr(struct com_softc *sc) 1584 { 1585 bus_space_tag_t iot = sc->sc_iot; 1586 bus_space_handle_t ioh = sc->sc_ioh; 1587 u_int8_t lcr; 1588 1589 sc->sc_ier = 0; 1590 #ifdef COM_PXA2X0 1591 if (sc->sc_uarttype == COM_UART_PXA2X0) 1592 sc->sc_ier |= IER_EUART; 1593 #endif 1594 /* disable interrupts */ 1595 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1596 1597 #ifdef COM_CONSOLE 1598 if (sc->sc_iot == comconsiot && sc->sc_iobase == comconsaddr) { 1599 comconsattached = 1; 1600 delay(10000); /* wait for output to finish */ 1601 SET(sc->sc_hwflags, COM_HW_CONSOLE); 1602 SET(sc->sc_swflags, COM_SW_SOFTCAR); 1603 } 1604 #endif 1605 1606 /* 1607 * Probe for all known forms of UART. 1608 */ 1609 lcr = bus_space_read_1(iot, ioh, com_lcr); 1610 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 1611 bus_space_write_1(iot, ioh, com_efr, 0); 1612 bus_space_write_1(iot, ioh, com_lcr, 0); 1613 1614 bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE); 1615 delay(100); 1616 1617 /* 1618 * Skip specific probes if attachment code knows it already. 1619 */ 1620 if (sc->sc_uarttype == COM_UART_UNKNOWN) 1621 switch (bus_space_read_1(iot, ioh, com_iir) >> 6) { 1622 case 0: 1623 sc->sc_uarttype = COM_UART_16450; 1624 break; 1625 case 2: 1626 sc->sc_uarttype = COM_UART_16550; 1627 break; 1628 case 3: 1629 sc->sc_uarttype = COM_UART_16550A; 1630 break; 1631 default: 1632 sc->sc_uarttype = COM_UART_UNKNOWN; 1633 break; 1634 } 1635 1636 if (sc->sc_uarttype == COM_UART_16550A) { /* Probe for ST16650s */ 1637 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1638 if (bus_space_read_1(iot, ioh, com_efr) == 0) { 1639 bus_space_write_1(iot, ioh, com_efr, EFR_CTS); 1640 if (bus_space_read_1(iot, ioh, com_efr) != 0) 1641 sc->sc_uarttype = COM_UART_ST16650; 1642 bus_space_write_1(iot, ioh, com_efr, 0); 1643 } else { 1644 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 1645 if (bus_space_read_1(iot, ioh, com_efr) == 0) 1646 sc->sc_uarttype = COM_UART_ST16650V2; 1647 } 1648 } 1649 1650 #if 0 /* until com works with large FIFOs */ 1651 if (sc->sc_uarttype == COM_UART_ST16650V2) { /* Probe for XR16850s */ 1652 u_int8_t dlbl, dlbh; 1653 1654 /* Enable latch access and get the current values. */ 1655 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1656 dlbl = bus_space_read_1(iot, ioh, com_dlbl); 1657 dlbh = bus_space_read_1(iot, ioh, com_dlbh); 1658 1659 /* Zero out the latch divisors */ 1660 bus_space_write_1(iot, ioh, com_dlbl, 0); 1661 bus_space_write_1(iot, ioh, com_dlbh, 0); 1662 1663 if (bus_space_read_1(iot, ioh, com_dlbh) == 0x10) { 1664 sc->sc_uarttype = COM_UART_XR16850; 1665 sc->sc_uartrev = bus_space_read_1(iot, ioh, com_dlbl); 1666 } 1667 1668 /* Reset to original. */ 1669 bus_space_write_1(iot, ioh, com_dlbl, dlbl); 1670 bus_space_write_1(iot, ioh, com_dlbh, dlbh); 1671 } 1672 #endif 1673 1674 if (sc->sc_uarttype == COM_UART_16550A) { /* Probe for TI16750s */ 1675 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1676 bus_space_write_1(iot, ioh, com_fifo, 1677 FIFO_ENABLE | FIFO_ENABLE_64BYTE); 1678 if ((bus_space_read_1(iot, ioh, com_iir) >> 5) == 7) { 1679 #if 0 1680 bus_space_write_1(iot, ioh, com_lcr, 0); 1681 if ((bus_space_read_1(iot, ioh, com_iir) >> 5) == 6) 1682 #endif 1683 sc->sc_uarttype = COM_UART_TI16750; 1684 } 1685 bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE); 1686 } 1687 1688 /* Reset the LCR (latch access is probably enabled). */ 1689 bus_space_write_1(iot, ioh, com_lcr, lcr); 1690 if (sc->sc_uarttype == COM_UART_16450) { /* Probe for 8250 */ 1691 u_int8_t scr0, scr1, scr2; 1692 1693 scr0 = bus_space_read_1(iot, ioh, com_scratch); 1694 bus_space_write_1(iot, ioh, com_scratch, 0xa5); 1695 scr1 = bus_space_read_1(iot, ioh, com_scratch); 1696 bus_space_write_1(iot, ioh, com_scratch, 0x5a); 1697 scr2 = bus_space_read_1(iot, ioh, com_scratch); 1698 bus_space_write_1(iot, ioh, com_scratch, scr0); 1699 1700 if ((scr1 != 0xa5) || (scr2 != 0x5a)) 1701 sc->sc_uarttype = COM_UART_8250; 1702 } 1703 1704 /* 1705 * Print UART type and initialize ourself. 1706 */ 1707 switch (sc->sc_uarttype) { 1708 case COM_UART_UNKNOWN: 1709 printf(": unknown uart\n"); 1710 break; 1711 case COM_UART_8250: 1712 printf(": ns8250, no fifo\n"); 1713 break; 1714 case COM_UART_16450: 1715 printf(": ns16450, no fifo\n"); 1716 break; 1717 case COM_UART_16550: 1718 printf(": ns16550, no working fifo\n"); 1719 break; 1720 case COM_UART_16550A: 1721 if (sc->sc_fifolen == 0) 1722 sc->sc_fifolen = 16; 1723 printf(": ns16550a, %d byte fifo\n", sc->sc_fifolen); 1724 SET(sc->sc_hwflags, COM_HW_FIFO); 1725 break; 1726 #ifdef COM_PXA2X0 1727 case COM_UART_PXA2X0: 1728 printf(": pxa2x0, 32 byte fifo"); 1729 SET(sc->sc_hwflags, COM_HW_FIFO); 1730 sc->sc_fifolen = 32; 1731 if (sc->sc_iobase == comsiraddr) { 1732 SET(sc->sc_hwflags, COM_HW_SIR); 1733 printf(" (SIR)"); 1734 } 1735 printf("\n"); 1736 break; 1737 #endif 1738 case COM_UART_ST16650: 1739 printf(": st16650, no working fifo\n"); 1740 break; 1741 case COM_UART_ST16650V2: 1742 if (sc->sc_fifolen == 0) 1743 sc->sc_fifolen = 32; 1744 printf(": st16650, %d byte fifo\n", sc->sc_fifolen); 1745 SET(sc->sc_hwflags, COM_HW_FIFO); 1746 break; 1747 case COM_UART_ST16C654: 1748 printf(": st16c654, 64 byte fifo\n"); 1749 SET(sc->sc_hwflags, COM_HW_FIFO); 1750 sc->sc_fifolen = 64; 1751 break; 1752 case COM_UART_TI16750: 1753 printf(": ti16750, 64 byte fifo\n"); 1754 SET(sc->sc_hwflags, COM_HW_FIFO); 1755 sc->sc_fifolen = 64; 1756 break; 1757 #if 0 1758 case COM_UART_XR16850: 1759 printf(": xr16850 (rev %d), 128 byte fifo\n", sc->sc_uartrev); 1760 SET(sc->sc_hwflags, COM_HW_FIFO); 1761 sc->sc_fifolen = 128; 1762 break; 1763 #ifdef COM_UART_OX16C950 1764 case COM_UART_OX16C950: 1765 printf(": ox16c950 (rev %d), 128 byte fifo\n", sc->sc_uartrev); 1766 SET(sc->sc_hwflags, COM_HW_FIFO); 1767 sc->sc_fifolen = 128; 1768 break; 1769 #endif 1770 #endif 1771 default: 1772 panic("comattach: bad fifo type"); 1773 } 1774 1775 #ifdef KGDB 1776 /* 1777 * Allow kgdb to "take over" this port. If this is 1778 * the kgdb device, it has exclusive use. 1779 */ 1780 1781 if (iot == com_kgdb_iot && sc->sc_iobase == com_kgdb_addr && 1782 !ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1783 printf("%s: kgdb\n", sc->sc_dev.dv_xname); 1784 SET(sc->sc_hwflags, COM_HW_KGDB); 1785 } 1786 #endif /* KGDB */ 1787 1788 #if defined(COM_CONSOLE) || defined(KGDB) 1789 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 1790 #endif 1791 com_fifo_probe(sc); 1792 1793 if (sc->sc_fifolen == 0) { 1794 CLR(sc->sc_hwflags, COM_HW_FIFO); 1795 sc->sc_fifolen = 1; 1796 } 1797 1798 /* clear and disable fifo */ 1799 bus_space_write_1(iot, ioh, com_fifo, FIFO_RCV_RST | FIFO_XMT_RST); 1800 if (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 1801 (void)bus_space_read_1(iot, ioh, com_data); 1802 bus_space_write_1(iot, ioh, com_fifo, 0); 1803 1804 sc->sc_mcr = 0; 1805 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1806 1807 #ifdef COM_CONSOLE 1808 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1809 int maj; 1810 1811 /* locate the major number */ 1812 for (maj = 0; maj < nchrdev; maj++) 1813 if (cdevsw[maj].d_open == comopen) 1814 break; 1815 1816 if (maj < nchrdev && cn_tab->cn_dev == NODEV) 1817 cn_tab->cn_dev = makedev(maj, sc->sc_dev.dv_unit); 1818 1819 printf("%s: console\n", sc->sc_dev.dv_xname); 1820 } 1821 #endif 1822 1823 timeout_set(&sc->sc_diag_tmo, comdiag, sc); 1824 timeout_set(&sc->sc_dtr_tmo, com_raisedtr, sc); 1825 sc->sc_si = softintr_establish(IPL_TTY, comsoft, sc); 1826 if (sc->sc_si == NULL) 1827 panic("%s: can't establish soft interrupt", 1828 sc->sc_dev.dv_xname); 1829 1830 /* 1831 * If there are no enable/disable functions, assume the device 1832 * is always enabled. 1833 */ 1834 if (!sc->enable) 1835 sc->enabled = 1; 1836 1837 #if defined(COM_CONSOLE) || defined(KGDB) 1838 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 1839 com_enable_debugport(sc); 1840 #endif 1841 } 1842 1843 void 1844 com_fifo_probe(struct com_softc *sc) 1845 { 1846 bus_space_handle_t ioh = sc->sc_ioh; 1847 bus_space_tag_t iot = sc->sc_iot; 1848 u_int8_t fifo, ier; 1849 int timo, len; 1850 1851 if (!ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1852 return; 1853 1854 ier = 0; 1855 #ifdef COM_PXA2X0 1856 if (sc->sc_uarttype == COM_UART_PXA2X0) 1857 ier |= IER_EUART; 1858 #endif 1859 bus_space_write_1(iot, ioh, com_ier, ier); 1860 bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB); 1861 bus_space_write_1(iot, ioh, com_dlbl, 3); 1862 bus_space_write_1(iot, ioh, com_dlbh, 0); 1863 bus_space_write_1(iot, ioh, com_lcr, LCR_PNONE | LCR_8BITS); 1864 bus_space_write_1(iot, ioh, com_mcr, MCR_LOOPBACK); 1865 1866 fifo = FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST; 1867 if (sc->sc_uarttype == COM_UART_TI16750) 1868 fifo |= FIFO_ENABLE_64BYTE; 1869 1870 bus_space_write_1(iot, ioh, com_fifo, fifo); 1871 1872 for (len = 0; len < 256; len++) { 1873 bus_space_write_1(iot, ioh, com_data, (len + 1)); 1874 timo = 2000; 1875 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1876 LSR_TXRDY) && --timo) 1877 delay(1); 1878 if (!timo) 1879 break; 1880 } 1881 1882 delay(100); 1883 1884 for (len = 0; len < 256; len++) { 1885 timo = 2000; 1886 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1887 LSR_RXRDY) && --timo) 1888 delay(1); 1889 if (!timo || bus_space_read_1(iot, ioh, com_data) != (len + 1)) 1890 break; 1891 } 1892 1893 /* For safety, always use the smaller value. */ 1894 if (sc->sc_fifolen > len) { 1895 printf("%s: probed fifo depth: %d bytes\n", 1896 sc->sc_dev.dv_xname, len); 1897 sc->sc_fifolen = len; 1898 } 1899 } 1900