1 /* $OpenBSD: com.c,v 1.149 2012/05/12 18:02:33 kettenis Exp $ */ 2 /* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */ 3 4 /* 5 * Copyright (c) 1997 - 1999, Jason Downs. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /*- 29 * Copyright (c) 1993, 1994, 1995, 1996 30 * Charles M. Hannum. All rights reserved. 31 * Copyright (c) 1991 The Regents of the University of California. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. Neither the name of the University nor the names of its contributors 43 * may be used to endorse or promote products derived from this software 44 * without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * @(#)com.c 7.5 (Berkeley) 5/16/91 59 */ 60 61 /* 62 * COM driver, based on HP dca driver 63 * uses National Semiconductor NS16450/NS16550AF UART 64 */ 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/ioctl.h> 68 #include <sys/selinfo.h> 69 #include <sys/tty.h> 70 #include <sys/proc.h> 71 #include <sys/conf.h> 72 #include <sys/file.h> 73 #include <sys/uio.h> 74 #include <sys/kernel.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/vnode.h> 78 #ifdef DDB 79 #include <ddb/db_var.h> 80 #endif 81 82 #include <machine/bus.h> 83 #if !defined(__sparc__) || defined(__sparc64__) 84 #include <machine/intr.h> 85 #endif 86 87 #if !defined(__sparc__) || defined(__sparc64__) 88 #define COM_CONSOLE 89 #include <dev/cons.h> 90 #endif 91 92 #include <dev/ic/comreg.h> 93 #include <dev/ic/comvar.h> 94 #include <dev/ic/ns16550reg.h> 95 #define com_lcr com_cfcr 96 97 #ifdef COM_PXA2X0 98 #define com_isr 8 99 #define ISR_SEND (ISR_RXPL | ISR_XMODE | ISR_XMITIR) 100 #define ISR_RECV (ISR_RXPL | ISR_XMODE | ISR_RCVEIR) 101 #endif 102 103 #ifdef __zaurus__ 104 #include <arch/zaurus/dev/zaurus_scoopvar.h> 105 #endif 106 107 cdev_decl(com); 108 109 static u_char tiocm_xxx2mcr(int); 110 111 void compwroff(struct com_softc *); 112 void cominit(bus_space_tag_t, bus_space_handle_t, int, int); 113 int com_is_console(bus_space_tag_t, bus_addr_t); 114 115 struct cfdriver com_cd = { 116 NULL, "com", DV_TTY 117 }; 118 119 int comdefaultrate = TTYDEF_SPEED; 120 #ifdef COM_PXA2X0 121 bus_addr_t comsiraddr; 122 #endif 123 #ifdef COM_CONSOLE 124 int comconsfreq; 125 int comconsrate = TTYDEF_SPEED; 126 bus_addr_t comconsaddr = 0; 127 int comconsattached; 128 bus_space_tag_t comconsiot; 129 bus_space_handle_t comconsioh; 130 int comconsunit; 131 tcflag_t comconscflag = TTYDEF_CFLAG; 132 #endif 133 134 int commajor; 135 136 #ifdef KGDB 137 #include <sys/kgdb.h> 138 139 bus_addr_t com_kgdb_addr; 140 bus_space_tag_t com_kgdb_iot; 141 bus_space_handle_t com_kgdb_ioh; 142 143 int com_kgdb_getc(void *); 144 void com_kgdb_putc(void *, int); 145 #endif /* KGDB */ 146 147 #define DEVUNIT(x) (minor(x) & 0x7f) 148 #define DEVCUA(x) (minor(x) & 0x80) 149 150 int 151 comspeed(long freq, long speed) 152 { 153 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 154 155 int x, err; 156 157 if (speed == 0) 158 return 0; 159 if (speed < 0) 160 return -1; 161 x = divrnd((freq / 16), speed); 162 if (x <= 0) 163 return -1; 164 err = divrnd((quad_t)freq * 1000 / 16, speed * x) - 1000; 165 if (err < 0) 166 err = -err; 167 if (err > COM_TOLERANCE) 168 return -1; 169 return x; 170 171 #undef divrnd 172 } 173 174 #ifdef COM_CONSOLE 175 int 176 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 177 { 178 int i, k; 179 180 /* force access to id reg */ 181 bus_space_write_1(iot, ioh, com_lcr, 0); 182 bus_space_write_1(iot, ioh, com_iir, 0); 183 for (i = 0; i < 32; i++) { 184 k = bus_space_read_1(iot, ioh, com_iir); 185 if (k & 0x38) { 186 bus_space_read_1(iot, ioh, com_data); /* cleanup */ 187 } else 188 break; 189 } 190 if (i >= 32) 191 return 0; 192 193 return 1; 194 } 195 #endif 196 197 int 198 com_detach(struct device *self, int flags) 199 { 200 struct com_softc *sc = (struct com_softc *)self; 201 int maj, mn; 202 203 sc->sc_swflags |= COM_SW_DEAD; 204 205 /* Locate the major number. */ 206 for (maj = 0; maj < nchrdev; maj++) 207 if (cdevsw[maj].d_open == comopen) 208 break; 209 210 /* Nuke the vnodes for any open instances. */ 211 mn = self->dv_unit; 212 vdevgone(maj, mn, mn, VCHR); 213 214 /* XXX a symbolic constant for the cua bit would be nicer. */ 215 mn |= 0x80; 216 vdevgone(maj, mn, mn, VCHR); 217 218 /* Detach and free the tty. */ 219 if (sc->sc_tty) { 220 ttyfree(sc->sc_tty); 221 } 222 223 timeout_del(&sc->sc_dtr_tmo); 224 timeout_del(&sc->sc_diag_tmo); 225 softintr_disestablish(sc->sc_si); 226 227 return (0); 228 } 229 230 int 231 com_activate(struct device *self, int act) 232 { 233 struct com_softc *sc = (struct com_softc *)self; 234 int s, rv = 0; 235 236 s = spltty(); 237 switch (act) { 238 case DVACT_DEACTIVATE: 239 #ifdef KGDB 240 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 241 #else 242 if (sc->sc_hwflags & COM_HW_CONSOLE) { 243 #endif /* KGDB */ 244 rv = EBUSY; 245 break; 246 } 247 248 if (sc->disable != NULL && sc->enabled != 0) { 249 (*sc->disable)(sc); 250 sc->enabled = 0; 251 } 252 break; 253 } 254 splx(s); 255 return (rv); 256 } 257 258 int 259 comopen(dev_t dev, int flag, int mode, struct proc *p) 260 { 261 int unit = DEVUNIT(dev); 262 struct com_softc *sc; 263 bus_space_tag_t iot; 264 bus_space_handle_t ioh; 265 struct tty *tp; 266 int s; 267 int error = 0; 268 269 if (unit >= com_cd.cd_ndevs) 270 return ENXIO; 271 sc = com_cd.cd_devs[unit]; 272 if (!sc) 273 return ENXIO; 274 275 #ifdef KGDB 276 /* 277 * If this is the kgdb port, no other use is permitted. 278 */ 279 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 280 return (EBUSY); 281 #endif /* KGDB */ 282 283 s = spltty(); 284 if (!sc->sc_tty) { 285 tp = sc->sc_tty = ttymalloc(1000000); 286 } else 287 tp = sc->sc_tty; 288 splx(s); 289 290 tp->t_oproc = comstart; 291 tp->t_param = comparam; 292 tp->t_dev = dev; 293 if (!ISSET(tp->t_state, TS_ISOPEN)) { 294 SET(tp->t_state, TS_WOPEN); 295 ttychars(tp); 296 tp->t_iflag = TTYDEF_IFLAG; 297 tp->t_oflag = TTYDEF_OFLAG; 298 #ifdef COM_CONSOLE 299 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 300 tp->t_cflag = comconscflag; 301 tp->t_ispeed = tp->t_ospeed = comconsrate; 302 } else 303 #endif 304 { 305 tp->t_cflag = TTYDEF_CFLAG; 306 tp->t_ispeed = tp->t_ospeed = comdefaultrate; 307 } 308 if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)) 309 SET(tp->t_cflag, CLOCAL); 310 if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)) 311 SET(tp->t_cflag, CRTSCTS); 312 if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)) 313 SET(tp->t_cflag, MDMBUF); 314 tp->t_lflag = TTYDEF_LFLAG; 315 316 s = spltty(); 317 318 sc->sc_initialize = 1; 319 comparam(tp, &tp->t_termios); 320 ttsetwater(tp); 321 322 sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; 323 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 324 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 325 326 iot = sc->sc_iot; 327 ioh = sc->sc_ioh; 328 329 /* 330 * Wake up the sleepy heads. 331 */ 332 switch (sc->sc_uarttype) { 333 case COM_UART_ST16650: 334 case COM_UART_ST16650V2: 335 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 336 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 337 bus_space_write_1(iot, ioh, com_ier, 0); 338 bus_space_write_1(iot, ioh, com_efr, 0); 339 bus_space_write_1(iot, ioh, com_lcr, 0); 340 break; 341 case COM_UART_TI16750: 342 bus_space_write_1(iot, ioh, com_ier, 0); 343 break; 344 case COM_UART_PXA2X0: 345 bus_space_write_1(iot, ioh, com_ier, IER_EUART); 346 break; 347 } 348 349 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 350 u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST; 351 u_int8_t lcr; 352 353 if (tp->t_ispeed <= 1200) 354 fifo |= FIFO_TRIGGER_1; 355 else if (tp->t_ispeed <= 38400) 356 fifo |= FIFO_TRIGGER_4; 357 else 358 fifo |= FIFO_TRIGGER_8; 359 if (sc->sc_uarttype == COM_UART_TI16750) { 360 fifo |= FIFO_ENABLE_64BYTE; 361 lcr = bus_space_read_1(iot, ioh, com_lcr); 362 bus_space_write_1(iot, ioh, com_lcr, 363 lcr | LCR_DLAB); 364 } 365 366 /* 367 * (Re)enable and drain FIFOs. 368 * 369 * Certain SMC chips cause problems if the FIFOs are 370 * enabled while input is ready. Turn off the FIFO 371 * if necessary to clear the input. Test the input 372 * ready bit after enabling the FIFOs to handle races 373 * between enabling and fresh input. 374 * 375 * Set the FIFO threshold based on the receive speed. 376 */ 377 for (;;) { 378 bus_space_write_1(iot, ioh, com_fifo, 0); 379 delay(100); 380 (void) bus_space_read_1(iot, ioh, com_data); 381 bus_space_write_1(iot, ioh, com_fifo, fifo | 382 FIFO_RCV_RST | FIFO_XMT_RST); 383 delay(100); 384 if(!ISSET(bus_space_read_1(iot, ioh, 385 com_lsr), LSR_RXRDY)) 386 break; 387 } 388 if (sc->sc_uarttype == COM_UART_TI16750) 389 bus_space_write_1(iot, ioh, com_lcr, lcr); 390 } 391 392 /* Flush any pending I/O. */ 393 while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 394 (void) bus_space_read_1(iot, ioh, com_data); 395 396 /* You turn me on, baby! */ 397 sc->sc_mcr = MCR_DTR | MCR_RTS; 398 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 399 SET(sc->sc_mcr, MCR_IENABLE); 400 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 401 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 402 #ifdef COM_PXA2X0 403 if (sc->sc_uarttype == COM_UART_PXA2X0) 404 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 405 #endif 406 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 407 408 sc->sc_msr = bus_space_read_1(iot, ioh, com_msr); 409 if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) || 410 ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF)) 411 SET(tp->t_state, TS_CARR_ON); 412 else 413 CLR(tp->t_state, TS_CARR_ON); 414 #ifdef COM_PXA2X0 415 if (sc->sc_uarttype == COM_UART_PXA2X0 && 416 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 417 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 418 #ifdef __zaurus__ 419 scoop_set_irled(1); 420 #endif 421 } 422 #endif 423 } else if (ISSET(tp->t_state, TS_XCLUDE) && suser(p, 0) != 0) 424 return EBUSY; 425 else 426 s = spltty(); 427 428 if (DEVCUA(dev)) { 429 if (ISSET(tp->t_state, TS_ISOPEN)) { 430 /* Ah, but someone already is dialed in... */ 431 splx(s); 432 return EBUSY; 433 } 434 sc->sc_cua = 1; /* We go into CUA mode. */ 435 } else { 436 /* tty (not cua) device; wait for carrier if necessary. */ 437 if (ISSET(flag, O_NONBLOCK)) { 438 if (sc->sc_cua) { 439 /* Opening TTY non-blocking... but the CUA is busy. */ 440 splx(s); 441 return EBUSY; 442 } 443 } else { 444 while (sc->sc_cua || 445 (!ISSET(tp->t_cflag, CLOCAL) && 446 !ISSET(tp->t_state, TS_CARR_ON))) { 447 SET(tp->t_state, TS_WOPEN); 448 error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, ttopen, 0); 449 /* 450 * If TS_WOPEN has been reset, that means the cua device 451 * has been closed. We don't want to fail in that case, 452 * so just go around again. 453 */ 454 if (error && ISSET(tp->t_state, TS_WOPEN)) { 455 CLR(tp->t_state, TS_WOPEN); 456 if (!sc->sc_cua && !ISSET(tp->t_state, TS_ISOPEN)) 457 compwroff(sc); 458 splx(s); 459 return error; 460 } 461 } 462 } 463 } 464 splx(s); 465 466 return (*linesw[tp->t_line].l_open)(dev, tp, p); 467 } 468 469 int 470 comclose(dev_t dev, int flag, int mode, struct proc *p) 471 { 472 int unit = DEVUNIT(dev); 473 struct com_softc *sc = com_cd.cd_devs[unit]; 474 bus_space_tag_t iot = sc->sc_iot; 475 bus_space_handle_t ioh = sc->sc_ioh; 476 struct tty *tp = sc->sc_tty; 477 int s; 478 479 #ifdef COM_CONSOLE 480 /* XXX This is for cons.c. */ 481 if (!ISSET(tp->t_state, TS_ISOPEN)) 482 return 0; 483 #endif 484 485 if(sc->sc_swflags & COM_SW_DEAD) 486 return 0; 487 488 (*linesw[tp->t_line].l_close)(tp, flag, p); 489 s = spltty(); 490 if (ISSET(tp->t_state, TS_WOPEN)) { 491 /* tty device is waiting for carrier; drop dtr then re-raise */ 492 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 493 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 494 timeout_add_sec(&sc->sc_dtr_tmo, 2); 495 } else { 496 /* no one else waiting; turn off the uart */ 497 compwroff(sc); 498 } 499 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 500 sc->sc_cua = 0; 501 splx(s); 502 ttyclose(tp); 503 504 #ifdef COM_CONSOLE 505 #ifdef notyet /* XXXX */ 506 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 507 ttyfree(tp); 508 sc->sc_tty = 0; 509 } 510 #endif 511 #endif 512 return 0; 513 } 514 515 void 516 compwroff(struct com_softc *sc) 517 { 518 bus_space_tag_t iot = sc->sc_iot; 519 bus_space_handle_t ioh = sc->sc_ioh; 520 struct tty *tp = sc->sc_tty; 521 522 CLR(sc->sc_lcr, LCR_SBREAK); 523 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 524 bus_space_write_1(iot, ioh, com_ier, 0); 525 if (ISSET(tp->t_cflag, HUPCL) && 526 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 527 /* XXX perhaps only clear DTR */ 528 sc->sc_mcr = 0; 529 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 530 } 531 532 /* 533 * Turn FIFO off; enter sleep mode if possible. 534 */ 535 bus_space_write_1(iot, ioh, com_fifo, 0); 536 delay(100); 537 if (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 538 (void) bus_space_read_1(iot, ioh, com_data); 539 delay(100); 540 bus_space_write_1(iot, ioh, com_fifo, 541 FIFO_RCV_RST | FIFO_XMT_RST); 542 543 switch (sc->sc_uarttype) { 544 case COM_UART_ST16650: 545 case COM_UART_ST16650V2: 546 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 547 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 548 bus_space_write_1(iot, ioh, com_ier, IER_SLEEP); 549 bus_space_write_1(iot, ioh, com_lcr, 0); 550 break; 551 case COM_UART_TI16750: 552 bus_space_write_1(iot, ioh, com_ier, IER_SLEEP); 553 break; 554 #ifdef COM_PXA2X0 555 case COM_UART_PXA2X0: 556 bus_space_write_1(iot, ioh, com_ier, 0); 557 #ifdef __zaurus__ 558 if (ISSET(sc->sc_hwflags, COM_HW_SIR)) 559 scoop_set_irled(0); 560 #endif 561 break; 562 #endif 563 } 564 } 565 566 void 567 com_resume(struct com_softc *sc) 568 { 569 struct tty *tp = sc->sc_tty; 570 bus_space_tag_t iot = sc->sc_iot; 571 bus_space_handle_t ioh = sc->sc_ioh; 572 int ospeed; 573 574 if (!tp || !ISSET(tp->t_state, TS_ISOPEN)) { 575 #ifdef COM_CONSOLE 576 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 577 cominit(iot, ioh, comconsrate, comconsfreq); 578 #endif 579 return; 580 } 581 582 /* 583 * Wake up the sleepy heads. 584 */ 585 switch (sc->sc_uarttype) { 586 case COM_UART_ST16650: 587 case COM_UART_ST16650V2: 588 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 589 bus_space_write_1(iot, ioh, com_efr, EFR_ECB); 590 bus_space_write_1(iot, ioh, com_ier, 0); 591 bus_space_write_1(iot, ioh, com_efr, 0); 592 bus_space_write_1(iot, ioh, com_lcr, 0); 593 break; 594 case COM_UART_TI16750: 595 bus_space_write_1(iot, ioh, com_ier, 0); 596 break; 597 case COM_UART_PXA2X0: 598 bus_space_write_1(iot, ioh, com_ier, IER_EUART); 599 break; 600 } 601 602 ospeed = comspeed(sc->sc_frequency, tp->t_ospeed); 603 604 if (ospeed != 0) { 605 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr | LCR_DLAB); 606 bus_space_write_1(iot, ioh, com_dlbl, ospeed); 607 bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8); 608 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 609 } else { 610 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 611 } 612 613 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 614 u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST; 615 u_int8_t lcr; 616 617 if (tp->t_ispeed <= 1200) 618 fifo |= FIFO_TRIGGER_1; 619 else if (tp->t_ispeed <= 38400) 620 fifo |= FIFO_TRIGGER_4; 621 else 622 fifo |= FIFO_TRIGGER_8; 623 if (sc->sc_uarttype == COM_UART_TI16750) { 624 fifo |= FIFO_ENABLE_64BYTE; 625 lcr = bus_space_read_1(iot, ioh, com_lcr); 626 bus_space_write_1(iot, ioh, com_lcr, 627 lcr | LCR_DLAB); 628 } 629 630 /* 631 * (Re)enable and drain FIFOs. 632 * 633 * Certain SMC chips cause problems if the FIFOs are 634 * enabled while input is ready. Turn off the FIFO 635 * if necessary to clear the input. Test the input 636 * ready bit after enabling the FIFOs to handle races 637 * between enabling and fresh input. 638 * 639 * Set the FIFO threshold based on the receive speed. 640 */ 641 for (;;) { 642 bus_space_write_1(iot, ioh, com_fifo, 0); 643 delay(100); 644 (void) bus_space_read_1(iot, ioh, com_data); 645 bus_space_write_1(iot, ioh, com_fifo, fifo | 646 FIFO_RCV_RST | FIFO_XMT_RST); 647 delay(100); 648 if(!ISSET(bus_space_read_1(iot, ioh, 649 com_lsr), LSR_RXRDY)) 650 break; 651 } 652 if (sc->sc_uarttype == COM_UART_TI16750) 653 bus_space_write_1(iot, ioh, com_lcr, lcr); 654 } 655 656 /* Flush any pending I/O. */ 657 while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 658 (void) bus_space_read_1(iot, ioh, com_data); 659 660 /* You turn me on, baby! */ 661 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 662 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 663 664 #ifdef COM_PXA2X0 665 if (sc->sc_uarttype == COM_UART_PXA2X0 && 666 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 667 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 668 #ifdef __zaurus__ 669 scoop_set_irled(1); 670 #endif 671 } 672 #endif 673 } 674 675 void 676 com_raisedtr(void *arg) 677 { 678 struct com_softc *sc = arg; 679 680 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 681 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, sc->sc_mcr); 682 } 683 684 int 685 comread(dev_t dev, struct uio *uio, int flag) 686 { 687 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 688 struct tty *tp = sc->sc_tty; 689 690 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 691 } 692 693 int 694 comwrite(dev_t dev, struct uio *uio, int flag) 695 { 696 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 697 struct tty *tp = sc->sc_tty; 698 699 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 700 } 701 702 struct tty * 703 comtty(dev_t dev) 704 { 705 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)]; 706 struct tty *tp = sc->sc_tty; 707 708 return (tp); 709 } 710 711 static u_char 712 tiocm_xxx2mcr(int data) 713 { 714 u_char m = 0; 715 716 if (ISSET(data, TIOCM_DTR)) 717 SET(m, MCR_DTR); 718 if (ISSET(data, TIOCM_RTS)) 719 SET(m, MCR_RTS); 720 return m; 721 } 722 723 int 724 comioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 725 { 726 int unit = DEVUNIT(dev); 727 struct com_softc *sc = com_cd.cd_devs[unit]; 728 struct tty *tp = sc->sc_tty; 729 bus_space_tag_t iot = sc->sc_iot; 730 bus_space_handle_t ioh = sc->sc_ioh; 731 int error; 732 733 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 734 if (error >= 0) 735 return error; 736 error = ttioctl(tp, cmd, data, flag, p); 737 if (error >= 0) 738 return error; 739 740 switch (cmd) { 741 case TIOCSBRK: 742 SET(sc->sc_lcr, LCR_SBREAK); 743 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 744 break; 745 case TIOCCBRK: 746 CLR(sc->sc_lcr, LCR_SBREAK); 747 bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr); 748 break; 749 case TIOCSDTR: 750 SET(sc->sc_mcr, sc->sc_dtr); 751 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 752 break; 753 case TIOCCDTR: 754 CLR(sc->sc_mcr, sc->sc_dtr); 755 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 756 break; 757 case TIOCMSET: 758 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 759 case TIOCMBIS: 760 SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 761 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 762 break; 763 case TIOCMBIC: 764 CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 765 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 766 break; 767 case TIOCMGET: { 768 u_char m; 769 int bits = 0; 770 771 m = sc->sc_mcr; 772 if (ISSET(m, MCR_DTR)) 773 SET(bits, TIOCM_DTR); 774 if (ISSET(m, MCR_RTS)) 775 SET(bits, TIOCM_RTS); 776 m = sc->sc_msr; 777 if (ISSET(m, MSR_DCD)) 778 SET(bits, TIOCM_CD); 779 if (ISSET(m, MSR_CTS)) 780 SET(bits, TIOCM_CTS); 781 if (ISSET(m, MSR_DSR)) 782 SET(bits, TIOCM_DSR); 783 if (ISSET(m, MSR_RI | MSR_TERI)) 784 SET(bits, TIOCM_RI); 785 if (bus_space_read_1(iot, ioh, com_ier)) 786 SET(bits, TIOCM_LE); 787 *(int *)data = bits; 788 break; 789 } 790 case TIOCGFLAGS: { 791 int driverbits, userbits = 0; 792 793 driverbits = sc->sc_swflags; 794 if (ISSET(driverbits, COM_SW_SOFTCAR)) 795 SET(userbits, TIOCFLAG_SOFTCAR); 796 if (ISSET(driverbits, COM_SW_CLOCAL)) 797 SET(userbits, TIOCFLAG_CLOCAL); 798 if (ISSET(driverbits, COM_SW_CRTSCTS)) 799 SET(userbits, TIOCFLAG_CRTSCTS); 800 if (ISSET(driverbits, COM_SW_MDMBUF)) 801 SET(userbits, TIOCFLAG_MDMBUF); 802 if (ISSET(driverbits, COM_SW_PPS)) 803 SET(userbits, TIOCFLAG_PPS); 804 805 *(int *)data = userbits; 806 break; 807 } 808 case TIOCSFLAGS: { 809 int userbits, driverbits = 0; 810 811 error = suser(p, 0); 812 if (error != 0) 813 return(EPERM); 814 815 userbits = *(int *)data; 816 if (ISSET(userbits, TIOCFLAG_SOFTCAR) || 817 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 818 SET(driverbits, COM_SW_SOFTCAR); 819 if (ISSET(userbits, TIOCFLAG_CLOCAL)) 820 SET(driverbits, COM_SW_CLOCAL); 821 if (ISSET(userbits, TIOCFLAG_CRTSCTS)) 822 SET(driverbits, COM_SW_CRTSCTS); 823 if (ISSET(userbits, TIOCFLAG_MDMBUF)) 824 SET(driverbits, COM_SW_MDMBUF); 825 if (ISSET(userbits, TIOCFLAG_PPS)) 826 SET(driverbits, COM_SW_PPS); 827 828 sc->sc_swflags = driverbits; 829 break; 830 } 831 default: 832 return ENOTTY; 833 } 834 835 return 0; 836 } 837 838 /* already called at spltty */ 839 int 840 comparam(struct tty *tp, struct termios *t) 841 { 842 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)]; 843 bus_space_tag_t iot = sc->sc_iot; 844 bus_space_handle_t ioh = sc->sc_ioh; 845 int ospeed = comspeed(sc->sc_frequency, t->c_ospeed); 846 u_char lcr; 847 tcflag_t oldcflag; 848 849 /* Check requested parameters. */ 850 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) 851 return EINVAL; 852 853 lcr = ISSET(sc->sc_lcr, LCR_SBREAK); 854 855 switch (ISSET(t->c_cflag, CSIZE)) { 856 case CS5: 857 SET(lcr, LCR_5BITS); 858 break; 859 case CS6: 860 SET(lcr, LCR_6BITS); 861 break; 862 case CS7: 863 SET(lcr, LCR_7BITS); 864 break; 865 case CS8: 866 SET(lcr, LCR_8BITS); 867 break; 868 } 869 if (ISSET(t->c_cflag, PARENB)) { 870 SET(lcr, LCR_PENAB); 871 if (!ISSET(t->c_cflag, PARODD)) 872 SET(lcr, LCR_PEVEN); 873 } 874 if (ISSET(t->c_cflag, CSTOPB)) 875 SET(lcr, LCR_STOPB); 876 877 sc->sc_lcr = lcr; 878 879 if (ospeed == 0) { 880 CLR(sc->sc_mcr, MCR_DTR); 881 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 882 } 883 884 /* 885 * Set the FIFO threshold based on the receive speed, if we are 886 * changing it. 887 */ 888 if (sc->sc_initialize || (tp->t_ispeed != t->c_ispeed)) { 889 sc->sc_initialize = 0; 890 891 if (ospeed != 0) { 892 /* 893 * Make sure the transmit FIFO is empty before 894 * proceeding. If we don't do this, some revisions 895 * of the UART will hang. Interestingly enough, 896 * even if we do this while the last character is 897 * still being pushed out, they don't hang. This 898 * seems good enough. 899 */ 900 while (ISSET(tp->t_state, TS_BUSY)) { 901 int error; 902 903 ++sc->sc_halt; 904 error = ttysleep(tp, &tp->t_outq, 905 TTOPRI | PCATCH, "comprm", 0); 906 --sc->sc_halt; 907 if (error) { 908 comstart(tp); 909 return (error); 910 } 911 } 912 913 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 914 bus_space_write_1(iot, ioh, com_dlbl, ospeed); 915 bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8); 916 bus_space_write_1(iot, ioh, com_lcr, lcr); 917 SET(sc->sc_mcr, MCR_DTR); 918 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 919 } else 920 bus_space_write_1(iot, ioh, com_lcr, lcr); 921 922 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 923 if (sc->sc_uarttype == COM_UART_TI16750) { 924 bus_space_write_1(iot, ioh, com_lcr, 925 lcr | LCR_DLAB); 926 bus_space_write_1(iot, ioh, com_fifo, 927 FIFO_ENABLE | FIFO_ENABLE_64BYTE | 928 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 929 bus_space_write_1(iot, ioh, com_lcr, lcr); 930 } else 931 bus_space_write_1(iot, ioh, com_fifo, 932 FIFO_ENABLE | 933 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 934 } 935 } else 936 bus_space_write_1(iot, ioh, com_lcr, lcr); 937 938 /* When not using CRTSCTS, RTS follows DTR. */ 939 if (!ISSET(t->c_cflag, CRTSCTS)) { 940 if (ISSET(sc->sc_mcr, MCR_DTR)) { 941 if (!ISSET(sc->sc_mcr, MCR_RTS)) { 942 SET(sc->sc_mcr, MCR_RTS); 943 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 944 } 945 } else { 946 if (ISSET(sc->sc_mcr, MCR_RTS)) { 947 CLR(sc->sc_mcr, MCR_RTS); 948 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 949 } 950 } 951 sc->sc_dtr = MCR_DTR | MCR_RTS; 952 } else 953 sc->sc_dtr = MCR_DTR; 954 955 /* and copy to tty */ 956 tp->t_ispeed = t->c_ispeed; 957 tp->t_ospeed = t->c_ospeed; 958 oldcflag = tp->t_cflag; 959 tp->t_cflag = t->c_cflag; 960 961 /* 962 * If DCD is off and MDMBUF is changed, ask the tty layer if we should 963 * stop the device. 964 */ 965 if (!ISSET(sc->sc_msr, MSR_DCD) && 966 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 967 ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) && 968 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 969 CLR(sc->sc_mcr, sc->sc_dtr); 970 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 971 } 972 973 /* Just to be sure... */ 974 comstart(tp); 975 return 0; 976 } 977 978 void 979 comstart(struct tty *tp) 980 { 981 struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)]; 982 bus_space_tag_t iot = sc->sc_iot; 983 bus_space_handle_t ioh = sc->sc_ioh; 984 int s; 985 986 s = spltty(); 987 if (ISSET(tp->t_state, TS_BUSY)) 988 goto out; 989 if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) || sc->sc_halt > 0) 990 goto stopped; 991 if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS)) 992 goto stopped; 993 ttwakeupwr(tp); 994 if (tp->t_outq.c_cc == 0) 995 goto stopped; 996 SET(tp->t_state, TS_BUSY); 997 998 #ifdef COM_PXA2X0 999 /* Enable transmitter slow infrared mode. */ 1000 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1001 ISSET(sc->sc_hwflags, COM_HW_SIR)) 1002 bus_space_write_1(iot, ioh, com_isr, ISR_SEND); 1003 #endif 1004 1005 /* Enable transmit completion interrupts. */ 1006 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1007 SET(sc->sc_ier, IER_ETXRDY); 1008 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1009 } 1010 1011 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1012 u_char buffer[128]; /* largest fifo */ 1013 int i, n; 1014 1015 n = q_to_b(&tp->t_outq, buffer, 1016 min(sc->sc_fifolen, sizeof buffer)); 1017 for (i = 0; i < n; i++) { 1018 bus_space_write_1(iot, ioh, com_data, buffer[i]); 1019 } 1020 bzero(buffer, n); 1021 } else if (tp->t_outq.c_cc != 0) 1022 bus_space_write_1(iot, ioh, com_data, getc(&tp->t_outq)); 1023 out: 1024 splx(s); 1025 return; 1026 stopped: 1027 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1028 CLR(sc->sc_ier, IER_ETXRDY); 1029 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1030 #ifdef COM_PXA2X0 1031 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1032 ISSET(sc->sc_hwflags, COM_HW_SIR)) { 1033 int timo; 1034 1035 /* Wait for empty transmit shift register. */ 1036 timo = 20000; 1037 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1038 LSR_TSRE) && --timo) 1039 delay(1); 1040 1041 /* Enable receiver slow infrared mode. */ 1042 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1043 } 1044 #endif 1045 } 1046 splx(s); 1047 } 1048 1049 /* 1050 * Stop output on a line. 1051 */ 1052 int 1053 comstop(struct tty *tp, int flag) 1054 { 1055 int s; 1056 1057 s = spltty(); 1058 if (ISSET(tp->t_state, TS_BUSY)) 1059 if (!ISSET(tp->t_state, TS_TTSTOP)) 1060 SET(tp->t_state, TS_FLUSH); 1061 splx(s); 1062 return 0; 1063 } 1064 1065 void 1066 comdiag(void *arg) 1067 { 1068 struct com_softc *sc = arg; 1069 int overflows, floods; 1070 int s; 1071 1072 s = spltty(); 1073 sc->sc_errors = 0; 1074 overflows = sc->sc_overflows; 1075 sc->sc_overflows = 0; 1076 floods = sc->sc_floods; 1077 sc->sc_floods = 0; 1078 splx(s); 1079 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s\n", 1080 sc->sc_dev.dv_xname, 1081 overflows, overflows == 1 ? "" : "s", 1082 floods, floods == 1 ? "" : "s"); 1083 } 1084 1085 void 1086 comsoft(void *arg) 1087 { 1088 struct com_softc *sc = (struct com_softc *)arg; 1089 struct tty *tp; 1090 u_char *ibufp; 1091 u_char *ibufend; 1092 int c; 1093 int s; 1094 static int lsrmap[8] = { 1095 0, TTY_PE, 1096 TTY_FE, TTY_PE|TTY_FE, 1097 TTY_FE, TTY_PE|TTY_FE, 1098 TTY_FE, TTY_PE|TTY_FE 1099 }; 1100 1101 if (sc == NULL || sc->sc_ibufp == sc->sc_ibuf) 1102 return; 1103 1104 tp = sc->sc_tty; 1105 1106 s = spltty(); 1107 1108 ibufp = sc->sc_ibuf; 1109 ibufend = sc->sc_ibufp; 1110 1111 if (ibufp == ibufend) { 1112 splx(s); 1113 return; 1114 } 1115 1116 sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? 1117 sc->sc_ibufs[1] : sc->sc_ibufs[0]; 1118 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 1119 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 1120 1121 if (tp == NULL || !ISSET(tp->t_state, TS_ISOPEN)) { 1122 splx(s); 1123 return; 1124 } 1125 1126 if (ISSET(tp->t_cflag, CRTSCTS) && 1127 !ISSET(sc->sc_mcr, MCR_RTS)) { 1128 /* XXX */ 1129 SET(sc->sc_mcr, MCR_RTS); 1130 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, 1131 sc->sc_mcr); 1132 } 1133 1134 splx(s); 1135 1136 while (ibufp < ibufend) { 1137 c = *ibufp++; 1138 if (ISSET(*ibufp, LSR_OE)) { 1139 sc->sc_overflows++; 1140 if (sc->sc_errors++ == 0) 1141 timeout_add_sec(&sc->sc_diag_tmo, 60); 1142 } 1143 /* This is ugly, but fast. */ 1144 c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2]; 1145 (*linesw[tp->t_line].l_rint)(c, tp); 1146 } 1147 } 1148 1149 #ifdef KGDB 1150 1151 /* 1152 * If a line break is set, or data matches one of the characters 1153 * gdb uses to signal a connection, then start up kgdb. Just gobble 1154 * any other data. Done in a stand alone function because comintr 1155 * does tty stuff and we don't have one. 1156 */ 1157 1158 int 1159 kgdbintr(void *arg) 1160 { 1161 struct com_softc *sc = arg; 1162 bus_space_tag_t iot = sc->sc_iot; 1163 bus_space_handle_t ioh = sc->sc_ioh; 1164 u_char lsr, data, msr, delta; 1165 1166 if (!ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1167 return(0); 1168 1169 for (;;) { 1170 lsr = bus_space_read_1(iot, ioh, com_lsr); 1171 if (ISSET(lsr, LSR_RXRDY)) { 1172 do { 1173 data = bus_space_read_1(iot, ioh, com_data); 1174 if (data == 3 || data == '$' || data == '+' || 1175 ISSET(lsr, LSR_BI)) { 1176 kgdb_connect(1); 1177 data = 0; 1178 } 1179 lsr = bus_space_read_1(iot, ioh, com_lsr); 1180 } while (ISSET(lsr, LSR_RXRDY)); 1181 1182 } 1183 if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE)) 1184 printf("weird lsr %02x\n", lsr); 1185 1186 msr = bus_space_read_1(iot, ioh, com_msr); 1187 1188 if (msr != sc->sc_msr) { 1189 delta = msr ^ sc->sc_msr; 1190 sc->sc_msr = msr; 1191 if (ISSET(delta, MSR_DCD)) { 1192 if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 1193 CLR(sc->sc_mcr, sc->sc_dtr); 1194 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1195 } 1196 } 1197 } 1198 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1199 return (1); 1200 } 1201 } 1202 #endif /* KGDB */ 1203 1204 int 1205 comintr(void *arg) 1206 { 1207 struct com_softc *sc = arg; 1208 bus_space_tag_t iot = sc->sc_iot; 1209 bus_space_handle_t ioh = sc->sc_ioh; 1210 struct tty *tp; 1211 u_char lsr, data, msr, delta; 1212 1213 if (!sc->sc_tty) 1214 return (0); /* Can't do squat. */ 1215 1216 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1217 return (0); 1218 1219 tp = sc->sc_tty; 1220 1221 for (;;) { 1222 lsr = bus_space_read_1(iot, ioh, com_lsr); 1223 1224 if (ISSET(lsr, LSR_RXRDY)) { 1225 u_char *p = sc->sc_ibufp; 1226 1227 softintr_schedule(sc->sc_si); 1228 do { 1229 data = bus_space_read_1(iot, ioh, com_data); 1230 if (ISSET(lsr, LSR_BI)) { 1231 #if defined(COM_CONSOLE) && defined(DDB) 1232 if (ISSET(sc->sc_hwflags, 1233 COM_HW_CONSOLE)) { 1234 if (db_console) 1235 Debugger(); 1236 goto next; 1237 } 1238 #endif 1239 data = 0; 1240 } 1241 if (p >= sc->sc_ibufend) { 1242 sc->sc_floods++; 1243 if (sc->sc_errors++ == 0) 1244 timeout_add_sec(&sc->sc_diag_tmo, 60); 1245 } else { 1246 *p++ = data; 1247 *p++ = lsr; 1248 if (p == sc->sc_ibufhigh && 1249 ISSET(tp->t_cflag, CRTSCTS)) { 1250 /* XXX */ 1251 CLR(sc->sc_mcr, MCR_RTS); 1252 bus_space_write_1(iot, ioh, com_mcr, 1253 sc->sc_mcr); 1254 } 1255 } 1256 #if defined(COM_CONSOLE) && defined(DDB) 1257 next: 1258 #endif 1259 lsr = bus_space_read_1(iot, ioh, com_lsr); 1260 } while (ISSET(lsr, LSR_RXRDY)); 1261 1262 sc->sc_ibufp = p; 1263 } 1264 msr = bus_space_read_1(iot, ioh, com_msr); 1265 1266 if (msr != sc->sc_msr) { 1267 delta = msr ^ sc->sc_msr; 1268 1269 ttytstamp(tp, sc->sc_msr & MSR_CTS, msr & MSR_CTS, 1270 sc->sc_msr & MSR_DCD, msr & MSR_DCD); 1271 1272 sc->sc_msr = msr; 1273 if (ISSET(delta, MSR_DCD)) { 1274 if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 1275 (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) { 1276 CLR(sc->sc_mcr, sc->sc_dtr); 1277 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1278 } 1279 } 1280 if (ISSET(delta & msr, MSR_CTS) && 1281 ISSET(tp->t_cflag, CRTSCTS)) { 1282 /* the line is up and we want to do rts/cts flow control */ 1283 (*linesw[tp->t_line].l_start)(tp); 1284 } 1285 } 1286 1287 if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) { 1288 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 1289 if (sc->sc_halt > 0) 1290 wakeup(&tp->t_outq); 1291 (*linesw[tp->t_line].l_start)(tp); 1292 } 1293 1294 #ifdef COM_PXA2X0 1295 if (sc->sc_uarttype == COM_UART_PXA2X0 && 1296 ISSET(sc->sc_hwflags, COM_HW_SIR) && 1297 ISSET(lsr, LSR_TXRDY) && ISSET(lsr, LSR_TSRE)) 1298 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1299 #endif 1300 1301 if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND)) 1302 return (1); 1303 } 1304 } 1305 1306 /* 1307 * The following functions are polled getc and putc routines, shared 1308 * by the console and kgdb glue. 1309 */ 1310 1311 int 1312 com_common_getc(bus_space_tag_t iot, bus_space_handle_t ioh) 1313 { 1314 int s = splhigh(); 1315 u_char stat, c; 1316 1317 #ifdef COM_PXA2X0 1318 if (com_is_console(iot, comsiraddr)) 1319 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1320 #endif 1321 1322 /* Block until a character becomes available. */ 1323 while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 1324 continue; 1325 1326 c = bus_space_read_1(iot, ioh, com_data); 1327 1328 /* Clear any interrupts generated by this transmission. */ 1329 stat = bus_space_read_1(iot, ioh, com_iir); 1330 splx(s); 1331 return (c); 1332 } 1333 1334 void 1335 com_common_putc(bus_space_tag_t iot, bus_space_handle_t ioh, int c) 1336 { 1337 int s = spltty(); 1338 int timo; 1339 1340 /* Wait for any pending transmission to finish. */ 1341 timo = 2000; 1342 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo) 1343 delay(1); 1344 1345 #ifdef COM_PXA2X0 1346 if (com_is_console(iot, comsiraddr)) 1347 bus_space_write_1(iot, ioh, com_isr, ISR_SEND); 1348 #endif 1349 bus_space_write_1(iot, ioh, com_data, (u_int8_t)(c & 0xff)); 1350 bus_space_barrier(iot, ioh, 0, COM_NPORTS, 1351 (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)); 1352 1353 /* Wait for this transmission to complete. */ 1354 timo = 2000; 1355 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo) 1356 delay(1); 1357 1358 #ifdef COM_PXA2X0 1359 if (com_is_console(iot, comsiraddr)) { 1360 /* Wait for transmit shift register to become empty. */ 1361 timo = 20000; 1362 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_TSRE) 1363 && --timo) 1364 delay(1); 1365 1366 bus_space_write_1(iot, ioh, com_isr, ISR_RECV); 1367 } 1368 #endif 1369 1370 splx(s); 1371 } 1372 1373 void 1374 cominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int frequency) 1375 { 1376 int s = splhigh(); 1377 u_char stat; 1378 1379 bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB); 1380 rate = comspeed(frequency, rate); /* XXX not comdefaultrate? */ 1381 bus_space_write_1(iot, ioh, com_dlbl, rate); 1382 bus_space_write_1(iot, ioh, com_dlbh, rate >> 8); 1383 bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS); 1384 bus_space_write_1(iot, ioh, com_mcr, MCR_DTR | MCR_RTS); 1385 #ifdef COM_PXA2X0 1386 /* XXX */ 1387 bus_space_write_1(iot, ioh, com_ier, IER_EUART); /* Make sure they are off */ 1388 #else 1389 bus_space_write_1(iot, ioh, com_ier, 0); /* Make sure they are off */ 1390 #endif 1391 bus_space_write_1(iot, ioh, com_fifo, 1392 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 1393 stat = bus_space_read_1(iot, ioh, com_iir); 1394 splx(s); 1395 } 1396 1397 #ifdef COM_CONSOLE 1398 void 1399 comcnprobe(struct consdev *cp) 1400 { 1401 bus_space_handle_t ioh; 1402 int found; 1403 1404 if (comconsaddr == 0) 1405 return; 1406 1407 if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS, 0, &ioh)) 1408 return; 1409 found = comprobe1(comconsiot, ioh); 1410 bus_space_unmap(comconsiot, ioh, COM_NPORTS); 1411 if (!found) 1412 return; 1413 1414 /* Locate the major number. */ 1415 for (commajor = 0; commajor < nchrdev; commajor++) 1416 if (cdevsw[commajor].d_open == comopen) 1417 break; 1418 1419 /* Initialize required fields. */ 1420 cp->cn_dev = makedev(commajor, comconsunit); 1421 #if defined(COMCONSOLE) || !defined(__amd64__) 1422 cp->cn_pri = CN_HIGHPRI; 1423 #else 1424 cp->cn_pri = CN_LOWPRI; 1425 #endif 1426 } 1427 1428 void 1429 comcninit(struct consdev *cp) 1430 { 1431 if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS, 0, &comconsioh)) 1432 panic("comcninit: mapping failed"); 1433 1434 if (comconsfreq == 0) 1435 comconsfreq = COM_FREQ; 1436 1437 cominit(comconsiot, comconsioh, comconsrate, comconsfreq); 1438 } 1439 1440 int 1441 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, tcflag_t cflag) 1442 { 1443 static struct consdev comcons = { 1444 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, 1445 NODEV, CN_LOWPRI 1446 }; 1447 1448 #ifndef __sparc64__ 1449 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &comconsioh)) 1450 return ENOMEM; 1451 #endif 1452 1453 cominit(iot, comconsioh, rate, frequency); 1454 1455 cn_tab = &comcons; 1456 1457 comconsiot = iot; 1458 comconsaddr = iobase; 1459 comconscflag = cflag; 1460 comconsfreq = frequency; 1461 comconsrate = rate; 1462 1463 return (0); 1464 } 1465 1466 int 1467 comcngetc(dev_t dev) 1468 { 1469 return (com_common_getc(comconsiot, comconsioh)); 1470 } 1471 1472 /* 1473 * Console kernel output character routine. 1474 */ 1475 void 1476 comcnputc(dev_t dev, int c) 1477 { 1478 com_common_putc(comconsiot, comconsioh, c); 1479 } 1480 1481 void 1482 comcnpollc(dev_t dev, int on) 1483 { 1484 1485 } 1486 #endif /* COM_CONSOLE */ 1487 1488 #ifdef KGDB 1489 int 1490 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 1491 int frequency, tcflag_t cflag) 1492 { 1493 #ifdef COM_CONSOLE 1494 if (iot == comconsiot && iobase == comconsaddr) { 1495 return (EBUSY); /* cannot share with console */ 1496 } 1497 #endif 1498 1499 com_kgdb_iot = iot; 1500 com_kgdb_addr = iobase; 1501 1502 if (bus_space_map(com_kgdb_iot, com_kgdb_addr, COM_NPORTS, 0, 1503 &com_kgdb_ioh)) 1504 panic("com_kgdb_attach: mapping failed"); 1505 1506 /* XXX We currently don't respect KGDBMODE? */ 1507 cominit(com_kgdb_iot, com_kgdb_ioh, rate, frequency); 1508 1509 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 1510 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1511 1512 return (0); 1513 } 1514 1515 /* ARGSUSED */ 1516 int 1517 com_kgdb_getc(void *arg) 1518 { 1519 1520 return (com_common_getc(com_kgdb_iot, com_kgdb_ioh)); 1521 } 1522 1523 /* ARGSUSED */ 1524 void 1525 com_kgdb_putc(void *arg, int c) 1526 { 1527 1528 return (com_common_putc(com_kgdb_iot, com_kgdb_ioh, c)); 1529 } 1530 #endif /* KGDB */ 1531 1532 #ifdef COM_PXA2X0 1533 int 1534 com_is_console(bus_space_tag_t iot, bus_addr_t iobase) 1535 { 1536 1537 if (comconsiot == iot && comconsaddr == iobase) 1538 return (1); 1539 #ifdef KGDB 1540 else if (com_kgdb_iot == iot && com_kgdb_addr == iobase) 1541 return (1); 1542 #endif 1543 return (0); 1544 } 1545 #endif /* COM_PXA2X0 */ 1546 1547 void com_enable_debugport(struct com_softc *); 1548 void com_fifo_probe(struct com_softc *); 1549 1550 #if defined(COM_CONSOLE) || defined(KGDB) 1551 void 1552 com_enable_debugport(struct com_softc *sc) 1553 { 1554 int s; 1555 1556 /* Turn on line break interrupt, set carrier. */ 1557 s = splhigh(); 1558 #ifdef KGDB 1559 SET(sc->sc_ier, IER_ERXRDY); 1560 #ifdef COM_PXA2X0 1561 if (sc->sc_uarttype == COM_UART_PXA2X0) 1562 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1563 #endif 1564 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_ier, sc->sc_ier); 1565 #endif 1566 SET(sc->sc_mcr, MCR_DTR | MCR_RTS | MCR_IENABLE); 1567 bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr, sc->sc_mcr); 1568 1569 splx(s); 1570 } 1571 #endif /* COM_CONSOLE || KGDB */ 1572 1573 void 1574 com_attach_subr(struct com_softc *sc) 1575 { 1576 bus_space_tag_t iot = sc->sc_iot; 1577 bus_space_handle_t ioh = sc->sc_ioh; 1578 u_int8_t lcr; 1579 1580 sc->sc_ier = 0; 1581 #ifdef COM_PXA2X0 1582 if (sc->sc_uarttype == COM_UART_PXA2X0) 1583 sc->sc_ier |= IER_EUART; 1584 #endif 1585 /* disable interrupts */ 1586 bus_space_write_1(iot, ioh, com_ier, sc->sc_ier); 1587 1588 #ifdef COM_CONSOLE 1589 if (sc->sc_iot == comconsiot && sc->sc_iobase == comconsaddr) { 1590 comconsattached = 1; 1591 delay(10000); /* wait for output to finish */ 1592 SET(sc->sc_hwflags, COM_HW_CONSOLE); 1593 SET(sc->sc_swflags, COM_SW_SOFTCAR); 1594 } 1595 #endif 1596 1597 /* 1598 * Probe for all known forms of UART. 1599 */ 1600 lcr = bus_space_read_1(iot, ioh, com_lcr); 1601 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 1602 bus_space_write_1(iot, ioh, com_efr, 0); 1603 bus_space_write_1(iot, ioh, com_lcr, 0); 1604 1605 bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE); 1606 delay(100); 1607 1608 /* 1609 * Skip specific probes if attachment code knows it already. 1610 */ 1611 if (sc->sc_uarttype == COM_UART_UNKNOWN) 1612 switch (bus_space_read_1(iot, ioh, com_iir) >> 6) { 1613 case 0: 1614 sc->sc_uarttype = COM_UART_16450; 1615 break; 1616 case 2: 1617 sc->sc_uarttype = COM_UART_16550; 1618 break; 1619 case 3: 1620 sc->sc_uarttype = COM_UART_16550A; 1621 break; 1622 default: 1623 sc->sc_uarttype = COM_UART_UNKNOWN; 1624 break; 1625 } 1626 1627 if (sc->sc_uarttype == COM_UART_16550A) { /* Probe for ST16650s */ 1628 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1629 if (bus_space_read_1(iot, ioh, com_efr) == 0) { 1630 sc->sc_uarttype = COM_UART_ST16650; 1631 } else { 1632 bus_space_write_1(iot, ioh, com_lcr, LCR_EFR); 1633 if (bus_space_read_1(iot, ioh, com_efr) == 0) 1634 sc->sc_uarttype = COM_UART_ST16650V2; 1635 } 1636 } 1637 1638 #if 0 /* until com works with large FIFOs */ 1639 if (sc->sc_uarttype == COM_UART_ST16650V2) { /* Probe for XR16850s */ 1640 u_int8_t dlbl, dlbh; 1641 1642 /* Enable latch access and get the current values. */ 1643 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1644 dlbl = bus_space_read_1(iot, ioh, com_dlbl); 1645 dlbh = bus_space_read_1(iot, ioh, com_dlbh); 1646 1647 /* Zero out the latch divisors */ 1648 bus_space_write_1(iot, ioh, com_dlbl, 0); 1649 bus_space_write_1(iot, ioh, com_dlbh, 0); 1650 1651 if (bus_space_read_1(iot, ioh, com_dlbh) == 0x10) { 1652 sc->sc_uarttype = COM_UART_XR16850; 1653 sc->sc_uartrev = bus_space_read_1(iot, ioh, com_dlbl); 1654 } 1655 1656 /* Reset to original. */ 1657 bus_space_write_1(iot, ioh, com_dlbl, dlbl); 1658 bus_space_write_1(iot, ioh, com_dlbh, dlbh); 1659 } 1660 #endif 1661 1662 if (sc->sc_uarttype == COM_UART_16550A) { /* Probe for TI16750s */ 1663 bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB); 1664 bus_space_write_1(iot, ioh, com_fifo, 1665 FIFO_ENABLE | FIFO_ENABLE_64BYTE); 1666 if ((bus_space_read_1(iot, ioh, com_iir) >> 5) == 7) { 1667 #if 0 1668 bus_space_write_1(iot, ioh, com_lcr, 0); 1669 if ((bus_space_read_1(iot, ioh, com_iir) >> 5) == 6) 1670 #endif 1671 sc->sc_uarttype = COM_UART_TI16750; 1672 } 1673 bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE); 1674 } 1675 1676 /* Reset the LCR (latch access is probably enabled). */ 1677 bus_space_write_1(iot, ioh, com_lcr, lcr); 1678 if (sc->sc_uarttype == COM_UART_16450) { /* Probe for 8250 */ 1679 u_int8_t scr0, scr1, scr2; 1680 1681 scr0 = bus_space_read_1(iot, ioh, com_scratch); 1682 bus_space_write_1(iot, ioh, com_scratch, 0xa5); 1683 scr1 = bus_space_read_1(iot, ioh, com_scratch); 1684 bus_space_write_1(iot, ioh, com_scratch, 0x5a); 1685 scr2 = bus_space_read_1(iot, ioh, com_scratch); 1686 bus_space_write_1(iot, ioh, com_scratch, scr0); 1687 1688 if ((scr1 != 0xa5) || (scr2 != 0x5a)) 1689 sc->sc_uarttype = COM_UART_8250; 1690 } 1691 1692 /* 1693 * Print UART type and initialize ourself. 1694 */ 1695 switch (sc->sc_uarttype) { 1696 case COM_UART_UNKNOWN: 1697 printf(": unknown uart\n"); 1698 break; 1699 case COM_UART_8250: 1700 printf(": ns8250, no fifo\n"); 1701 break; 1702 case COM_UART_16450: 1703 printf(": ns16450, no fifo\n"); 1704 break; 1705 case COM_UART_16550: 1706 printf(": ns16550, no working fifo\n"); 1707 break; 1708 case COM_UART_16550A: 1709 if (sc->sc_fifolen == 0) 1710 sc->sc_fifolen = 16; 1711 printf(": ns16550a, %d byte fifo\n", sc->sc_fifolen); 1712 SET(sc->sc_hwflags, COM_HW_FIFO); 1713 break; 1714 #ifdef COM_PXA2X0 1715 case COM_UART_PXA2X0: 1716 printf(": pxa2x0, 32 byte fifo"); 1717 SET(sc->sc_hwflags, COM_HW_FIFO); 1718 sc->sc_fifolen = 32; 1719 if (sc->sc_iobase == comsiraddr) { 1720 SET(sc->sc_hwflags, COM_HW_SIR); 1721 printf(" (SIR)"); 1722 } 1723 printf("\n"); 1724 break; 1725 #endif 1726 case COM_UART_ST16650: 1727 printf(": st16650, no working fifo\n"); 1728 break; 1729 case COM_UART_ST16650V2: 1730 if (sc->sc_fifolen == 0) 1731 sc->sc_fifolen = 32; 1732 printf(": st16650, %d byte fifo\n", sc->sc_fifolen); 1733 SET(sc->sc_hwflags, COM_HW_FIFO); 1734 break; 1735 case COM_UART_ST16C654: 1736 printf(": st16c654, 64 byte fifo\n"); 1737 SET(sc->sc_hwflags, COM_HW_FIFO); 1738 sc->sc_fifolen = 64; 1739 break; 1740 case COM_UART_TI16750: 1741 printf(": ti16750, 64 byte fifo\n"); 1742 SET(sc->sc_hwflags, COM_HW_FIFO); 1743 sc->sc_fifolen = 64; 1744 break; 1745 #if 0 1746 case COM_UART_XR16850: 1747 printf(": xr16850 (rev %d), 128 byte fifo\n", sc->sc_uartrev); 1748 SET(sc->sc_hwflags, COM_HW_FIFO); 1749 sc->sc_fifolen = 128; 1750 break; 1751 #ifdef COM_UART_OX16C950 1752 case COM_UART_OX16C950: 1753 printf(": ox16c950 (rev %d), 128 byte fifo\n", sc->sc_uartrev); 1754 SET(sc->sc_hwflags, COM_HW_FIFO); 1755 sc->sc_fifolen = 128; 1756 break; 1757 #endif 1758 #endif 1759 default: 1760 panic("comattach: bad fifo type"); 1761 } 1762 1763 #ifdef KGDB 1764 /* 1765 * Allow kgdb to "take over" this port. If this is 1766 * the kgdb device, it has exclusive use. 1767 */ 1768 1769 if (iot == com_kgdb_iot && sc->sc_iobase == com_kgdb_addr && 1770 !ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1771 printf("%s: kgdb\n", sc->sc_dev.dv_xname); 1772 SET(sc->sc_hwflags, COM_HW_KGDB); 1773 } 1774 #endif /* KGDB */ 1775 1776 #if defined(COM_CONSOLE) || defined(KGDB) 1777 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 1778 #endif 1779 com_fifo_probe(sc); 1780 1781 if (sc->sc_fifolen == 0) { 1782 CLR(sc->sc_hwflags, COM_HW_FIFO); 1783 sc->sc_fifolen = 1; 1784 } 1785 1786 /* clear and disable fifo */ 1787 bus_space_write_1(iot, ioh, com_fifo, FIFO_RCV_RST | FIFO_XMT_RST); 1788 if (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY)) 1789 (void)bus_space_read_1(iot, ioh, com_data); 1790 bus_space_write_1(iot, ioh, com_fifo, 0); 1791 1792 sc->sc_mcr = 0; 1793 bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr); 1794 1795 #ifdef COM_CONSOLE 1796 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1797 int maj; 1798 1799 /* locate the major number */ 1800 for (maj = 0; maj < nchrdev; maj++) 1801 if (cdevsw[maj].d_open == comopen) 1802 break; 1803 1804 if (maj < nchrdev && cn_tab->cn_dev == NODEV) 1805 cn_tab->cn_dev = makedev(maj, sc->sc_dev.dv_unit); 1806 1807 printf("%s: console\n", sc->sc_dev.dv_xname); 1808 } 1809 #endif 1810 1811 timeout_set(&sc->sc_diag_tmo, comdiag, sc); 1812 timeout_set(&sc->sc_dtr_tmo, com_raisedtr, sc); 1813 sc->sc_si = softintr_establish(IPL_TTY, comsoft, sc); 1814 if (sc->sc_si == NULL) 1815 panic("%s: can't establish soft interrupt", 1816 sc->sc_dev.dv_xname); 1817 1818 /* 1819 * If there are no enable/disable functions, assume the device 1820 * is always enabled. 1821 */ 1822 if (!sc->enable) 1823 sc->enabled = 1; 1824 1825 #if defined(COM_CONSOLE) || defined(KGDB) 1826 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 1827 com_enable_debugport(sc); 1828 #endif 1829 } 1830 1831 void 1832 com_fifo_probe(struct com_softc *sc) 1833 { 1834 bus_space_handle_t ioh = sc->sc_ioh; 1835 bus_space_tag_t iot = sc->sc_iot; 1836 u_int8_t fifo, ier; 1837 int timo, len; 1838 1839 if (!ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1840 return; 1841 1842 ier = 0; 1843 #ifdef COM_PXA2X0 1844 if (sc->sc_uarttype == COM_UART_PXA2X0) 1845 ier |= IER_EUART; 1846 #endif 1847 bus_space_write_1(iot, ioh, com_ier, ier); 1848 bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB); 1849 bus_space_write_1(iot, ioh, com_dlbl, 3); 1850 bus_space_write_1(iot, ioh, com_dlbh, 0); 1851 bus_space_write_1(iot, ioh, com_lcr, LCR_PNONE | LCR_8BITS); 1852 bus_space_write_1(iot, ioh, com_mcr, MCR_LOOPBACK); 1853 1854 fifo = FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST; 1855 if (sc->sc_uarttype == COM_UART_TI16750) 1856 fifo |= FIFO_ENABLE_64BYTE; 1857 1858 bus_space_write_1(iot, ioh, com_fifo, fifo); 1859 1860 for (len = 0; len < 256; len++) { 1861 bus_space_write_1(iot, ioh, com_data, (len + 1)); 1862 timo = 2000; 1863 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1864 LSR_TXRDY) && --timo) 1865 delay(1); 1866 if (!timo) 1867 break; 1868 } 1869 1870 delay(100); 1871 1872 for (len = 0; len < 256; len++) { 1873 timo = 2000; 1874 while (!ISSET(bus_space_read_1(iot, ioh, com_lsr), 1875 LSR_RXRDY) && --timo) 1876 delay(1); 1877 if (!timo || bus_space_read_1(iot, ioh, com_data) != (len + 1)) 1878 break; 1879 } 1880 1881 /* For safety, always use the smaller value. */ 1882 if (sc->sc_fifolen > len) { 1883 printf("%s: probed fifo depth: %d bytes\n", 1884 sc->sc_dev.dv_xname, len); 1885 sc->sc_fifolen = len; 1886 } 1887 } 1888