1 /* $OpenBSD: bwireg.h,v 1.9 2014/06/07 11:55:02 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.1 2007/09/08 06:15:54 sephe Exp $ 37 */ 38 39 #ifndef _IF_BWIREG_H 40 #define _IF_BWIREG_H 41 42 /* 43 * Registers for all of the register windows 44 */ 45 #define BWI_FLAGS 0x00000f18 46 #define BWI_FLAGS_INTR_MASK 0x0000003f 47 48 #define BWI_IMSTATE 0x00000f90 49 #define BWI_IMSTATE_INBAND_ERR (1 << 17) 50 #define BWI_IMSTATE_TIMEOUT (1 << 18) 51 52 #define BWI_INTRVEC 0x00000f94 53 54 #define BWI_STATE_LO 0x00000f98 55 #define BWI_STATE_LO_RESET (1 << 0) 56 #define BWI_STATE_LO_DISABLE1 (1 << 1) 57 #define BWI_STATE_LO_DISABLE2 (1 << 2) 58 #define BWI_STATE_LO_CLOCK (1 << 16) 59 #define BWI_STATE_LO_GATED_CLOCK (1 << 17) 60 #define BWI_STATE_LO_FLAG_PHYCLKEN (1 << 0) 61 #define BWI_STATE_LO_FLAG_PHYRST (1 << 1) 62 #define BWI_STATE_LO_FLAG_PHYLNK (1 << 11) 63 #define BWI_STATE_LO_FLAGS_MASK 0x3ffc0000 64 65 #define BWI_STATE_HI 0x00000f9c 66 #define BWI_STATE_HI_SERROR (1 << 0) 67 #define BWI_STATE_HI_BUSY (1 << 2) 68 #define BWI_STATE_HI_FLAG_MAGIC1 0x1 69 #define BWI_STATE_HI_FLAG_MAGIC2 0x2 70 #define BWI_STATE_HI_FLAG_64BIT 0x1000 71 #define BWI_STATE_HI_FLAGS_MASK 0x1fff0000 72 73 #define BWI_CONF_LO 0x00000fa8 74 #define BWI_CONF_LO_SERVTO_MASK 0x00000007 /* service timeout */ 75 #define BWI_CONF_LO_SERVTO 2 76 #define BWI_CONF_LO_REQTO_MASK 0x00000070 /* request timeout */ 77 #define BWI_CONF_LO_REQTO 3 78 79 #define BWI_ID_LO 0x00000ff8 80 #define BWI_ID_LO_BUSREV_MASK 0xf0000000 81 /* Bus revision */ 82 #define BWI_BUSREV_0 0 83 #define BWI_BUSREV_1 1 84 85 #define BWI_ID_HI 0x00000ffc 86 #define BWI_ID_HI_REGWIN_REV(v) (((v) & 0xf) | (((v) & 0x7000) >> 8)) 87 #define BWI_ID_HI_REGWIN_TYPE(v) (((v) & 0x8ff0) >> 4) 88 #define BWI_ID_HI_REGWIN_VENDOR_MASK 0xffff0000 89 90 /* 91 * Registers for common register window 92 */ 93 #define BWI_INFO 0x00000000 94 #define BWI_INFO_BBPID_MASK 0x0000ffff 95 #define BWI_INFO_BBPREV_MASK 0x000f0000 96 #define BWI_INFO_BBPPKG_MASK 0x00f00000 97 #define BWI_INFO_NREGWIN_MASK 0x0f000000 98 99 #define BWI_CAPABILITY 0x00000004 100 #define BWI_CAP_CLKMODE (1 << 18) 101 102 #define BWI_CONTROL 0x00000028 103 #define BWI_CONTROL_MAGIC0 0x3a4 104 #define BWI_CONTROL_MAGIC1 0xa4 105 #define BWI_PLL_ON_DELAY 0xb0 106 #define BWI_FREQ_SEL_DELAY 0xb4 107 108 #define BWI_CLOCK_CTRL 0x000000b8 109 #define BWI_CLOCK_CTRL_CLKSRC (7 << 0) 110 #define BWI_CLOCK_CTRL_SLOW (1 << 11) 111 #define BWI_CLOCK_CTRL_IGNPLL (1 << 12) 112 #define BWI_CLOCK_CTRL_NODYN (1 << 13) 113 #define BWI_CLOCK_CTRL_FDIV (0xffff << 16) /* freq divisor */ 114 115 /* Possible values for BWI_CLOCK_CTRL_CLKSRC */ 116 #define BWI_CLKSRC_LP_OSC 0 /* Low power oscillator */ 117 #define BWI_CLKSRC_CS_OSC 1 /* Crystal oscillator */ 118 #define BWI_CLKSRC_PCI 2 119 #define BWI_CLKSRC_MAX 3 /* Maximum of clock source */ 120 /* Min/Max frequency for given clock source */ 121 #define BWI_CLKSRC_LP_OSC_FMIN 25000 122 #define BWI_CLKSRC_LP_OSC_FMAX 43000 123 #define BWI_CLKSRC_CS_OSC_FMIN 19800000 124 #define BWI_CLKSRC_CS_OSC_FMAX 20200000 125 #define BWI_CLKSRC_PCI_FMIN 25000000 126 #define BWI_CLKSRC_PCI_FMAX 34000000 127 128 #define BWI_CLOCK_INFO 0x000000c0 129 #define BWI_CLOCK_INFO_FDIV (0xffff << 16) /* freq divisor */ 130 131 /* 132 * Registers for bus register window 133 */ 134 #define BWI_BUS_ADDR 0x00000050 135 #define BWI_BUS_ADDR_MAGIC 0xfd8 136 137 #define BWI_BUS_DATA 0x00000054 138 139 #define BWI_BUS_CONFIG 0x00000108 140 #define BWI_BUS_CONFIG_PREFETCH (1 << 2) 141 #define BWI_BUS_CONFIG_BURST (1 << 3) 142 #define BWI_BUS_CONFIG_MRM (1 << 5) 143 144 /* 145 * Register for MAC 146 */ 147 #define BWI_TXRX_INTR_STATUS_BASE 0x20 148 #define BWI_TXRX_INTR_MASK_BASE 0x24 149 #define BWI_TXRX_INTR_STATUS(i) (BWI_TXRX_INTR_STATUS_BASE + ((i) * 8)) 150 #define BWI_TXRX_INTR_MASK(i) (BWI_TXRX_INTR_MASK_BASE + ((i) * 8)) 151 152 #define BWI_MAC_STATUS 0x00000120 153 #define BWI_MAC_STATUS_ENABLE (1U << 0) 154 #define BWI_MAC_STATUS_UCODE_START (1U << 1) 155 #define BWI_MAC_STATUS_UCODE_JUMP0 (1U << 2) 156 #define BWI_MAC_STATUS_IHREN (1U << 10) 157 #define BWI_MAC_STATUS_GPOSEL_MASK (3U << 14) 158 #define BWI_MAC_STATUS_BSWAP (1U << 16) 159 #define BWI_MAC_STATUS_INFRA (1U << 17) 160 #define BWI_MAC_STATUS_OPMODE_HOSTAP (1U << 18) 161 #define BWI_MAC_STATUS_RFLOCK (1U << 19) 162 #define BWI_MAC_STATUS_PASS_BCN (1U << 20) 163 #define BWI_MAC_STATUS_PASS_BADPLCP (1U << 21) 164 #define BWI_MAC_STATUS_PASS_CTL (1U << 22) 165 #define BWI_MAC_STATUS_PASS_BADFCS (1U << 23) 166 #define BWI_MAC_STATUS_PROMISC (1U << 24) 167 #define BWI_MAC_STATUS_HW_PS (1U << 25) 168 #define BWI_MAC_STATUS_WAKEUP (1U << 26) 169 #define BWI_MAC_STATUS_PHYLNK (1U << 31) 170 171 #define BWI_MAC_INTR_STATUS 0x00000128 172 #define BWI_MAC_INTR_MASK 0x0000012c 173 174 #define BWI_MAC_TMPLT_CTRL 0x00000130 175 #define BWI_MAC_TMPLT_DATA 0x00000134 176 177 #define BWI_MAC_PS_STATUS 0x00000140 178 179 #define BWI_MOBJ_CTRL 0x00000160 180 #define BWI_MOBJ_CTRL_VAL(objid, ofs) ((objid) << 16 | (ofs)) 181 #define BWI_MOBJ_DATA 0x00000164 182 #define BWI_MOBJ_DATA_UNALIGN 0x0166 183 184 /* 185 * Memory object IDs 186 */ 187 #define BWI_WR_MOBJ_AUTOINC 0x100 /* Auto-increment wr */ 188 #define BWI_RD_MOBJ_AUTOINC 0x200 /* Auto-increment rd */ 189 /* Firmware ucode object */ 190 #define BWI_FW_UCODE_MOBJ 0x0 191 /* Common object */ 192 #define BWI_COMM_MOBJ 0x1 193 #define BWI_COMM_MOBJ_FWREV 0x0 194 #define BWI_COMM_MOBJ_FWPATCHLV 0x2 195 #define BWI_COMM_MOBJ_SLOTTIME 0x10 196 #define BWI_COMM_MOBJ_MACREV 0x16 197 #define BWI_COMM_MOBJ_TX_ACK 0x22 198 #define BWI_COMM_MOBJ_UCODE_STATE 0x40 199 #define BWI_COMM_MOBJ_SHRETRY_FB 0x44 200 #define BWI_COMM_MOBJ_LGRETEY_FB 0x46 201 #define BWI_COMM_MOBJ_TX_BEACON 0x54 202 #define BWI_COMM_MOBJ_KEYTABLE_OFS 0x56 203 #define BWI_COMM_MOBJ_TSSI_DS 0x58 204 #define BWI_COMM_MOBJ_HFLAGS_LO 0x5e 205 #define BWI_COMM_MOBJ_HFLAGS_MI 0x60 206 #define BWI_COMM_MOBJ_HFLAGS_HI 0x62 207 #define BWI_COMM_MOBJ_RF_ATTEN 0x64 208 #define BWI_COMM_MOBJ_TSSI_OFDM 0x70 209 #define BWI_COMM_MOBJ_PROBE_RESP_TO 0x74 210 #define BWI_COMM_MOBJ_CHAN 0xa0 211 #define BWI_COMM_MOBJ_KEY_ALGO 0x100 212 #define BWI_COMM_MOBJ_TX_PROBE_RESP 0x188 213 #define BWI_HFLAG_AUTO_ANTDIV 0x1ULL 214 #define BWI_HFLAG_SYM_WA 0x2ULL /* ??? SYM work around */ 215 #define BWI_HFLAG_PWR_BOOST_DS 0x8ULL 216 #define BWI_HFLAG_GDC_WA 0x20ULL /* ??? GDC work around */ 217 #define BWI_HFLAG_OFDM_PA 0x40ULL 218 #define BWI_HFLAG_NOT_JAPAN 0x80ULL 219 #define BWI_HFLAG_MAGIC1 0x200ULL 220 #define BWI_UCODE_STATE_PS 4 221 #define BWI_LO_TSSI_MASK 0x00ff 222 #define BWI_HI_TSSI_MASK 0xff00 223 #define BWI_INVALID_TSSI 0x7f 224 /* 802.11 object */ 225 #define BWI_80211_MOBJ 0x2 226 #define BWI_80211_MOBJ_CWMIN 0xc 227 #define BWI_80211_MOBJ_CWMAX 0x10 228 #define BWI_80211_MOBJ_SHRETRY 0x18 229 #define BWI_80211_MOBJ_LGRETRY 0x1c 230 /* Firmware PCM object */ 231 #define BWI_FW_PCM_MOBJ 0x3 232 /* MAC address of pairwise keys */ 233 #define BWI_PKEY_ADDR_MOBJ 0x4 234 235 #define BWI_TXSTATUS_0 0x00000170 236 #define BWI_TXSTATUS_0_MORE (1 << 0) 237 #define BWI_TXSTATUS_0_TXID_MASK 0xffff0000 238 #define BWI_TXSTATUS_0_INFO(st) (((st) & 0xfff0) | (((st) & 0xf) >> 1)) 239 #define BWI_TXSTATUS_1 0x00000174 240 241 #define BWI_TXRX_CTRL_BASE 0x200 242 #define BWI_TX32_CTRL 0x0 243 #define BWI_TX32_RINGINFO 0x4 244 #define BWI_TX32_INDEX 0x8 245 #define BWI_TX32_STATUS 0xc 246 #define BWI_TX32_STATUS_STATE_MASK 0xf000 247 #define BWI_TX32_STATUS_STATE_DISABLED 0 248 #define BWI_TX32_STATUS_STATE_IDLE 2 249 #define BWI_TX32_STATUS_STATE_STOPPED 3 250 #define BWI_RX32_CTRL 0x10 251 #define BWI_RX32_CTRL_HDRSZ_MASK 0x00fe 252 #define BWI_RX32_RINGINFO 0x14 253 #define BWI_RX32_INDEX 0x18 254 #define BWI_RX32_STATUS 0x1c 255 #define BWI_RX32_STATUS_INDEX_MASK 0x0fff 256 #define BWI_RX32_STATUS_STATE_MASK 0xf000 257 #define BWI_RX32_STATUS_STATE_DISABLED 0 258 /* Shared by 32bit TX/RX CTRL */ 259 #define BWI_TXRX32_CTRL_ENABLE (1 << 0) 260 #define BWI_TXRX32_CTRL_ADDRHI_MASK 0x00030000 261 /* Shared by 32bit TX/RX RINGINFO */ 262 #define BWI_TXRX32_RINGINFO_FUNC_TXRX 0x1 263 #define BWI_TXRX32_RINGINFO_FUNC_MASK 0xc0000000 264 #define BWI_TXRX32_RINGINFO_ADDR_MASK 0x3fffffff 265 266 #define BWI_PHYINFO 0x03e0 267 #define BWI_PHYINFO_REV_MASK 0x000f 268 #define BWI_PHYINFO_TYPE_MASK 0x0f00 269 #define BWI_PHYINFO_TYPE_11A 0 270 #define BWI_PHYINFO_TYPE_11B 1 271 #define BWI_PHYINFO_TYPE_11G 2 272 #define BWI_PHYINFO_TYPE_11N 5 273 #define BWI_PHYINFO_VER_MASK 0xf000 274 275 #define BWI_RF_ANTDIV 0x03e2 /* Antenna Diversity ?? */ 276 277 #define BWI_PHY_MAGIC_REG1 0x03e4 278 #define BWI_PHY_MAGIC_REG1_VAL1 0x3000 279 #define BWI_PHY_MAGIC_REG1_VAL2 0x0009 280 281 #define BWI_BBP_ATTEN 0x03e6 282 #define BWI_BBP_ATTEN_MAGIC 0x00f4 283 #define BWI_BBP_ATTEN_MAGIC2 0x8140 284 285 #define BWI_BPHY_CTRL 0x03ec 286 #define BWI_BPHY_CTRL_INIT 0x3f22 287 288 #define BWI_RF_CHAN 0x03f0 289 #define BWI_RF_CHAN_EX 0x03f4 290 291 #define BWI_RF_CTRL 0x03f6 292 /* Register values for BWI_RF_CTRL */ 293 #define BWI_RF_CTRL_RFINFO 0x1 294 /* XXX extra bits for reading from radio */ 295 #define BWI_RF_CTRL_RD_11A 0x40 296 #define BWI_RF_CTRL_RD_11BG 0x80 297 #define BWI_RF_DATA_HI 0x3f8 298 #define BWI_RF_DATA_LO 0x3fa 299 /* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */ 300 #define BWI_RFINFO_MANUFACT_MASK 0x0fff 301 #define BWI_RF_MANUFACT_BCM 0x17f /* XXX */ 302 #define BWI_RFINFO_TYPE_MASK 0x0ffff000 303 #define BWI_RF_T_BCM2050 0x2050 304 #define BWI_RF_T_BCM2053 0x2053 305 #define BWI_RF_T_BCM2060 0x2060 306 #define BWI_RFINFO_REV_MASK 0xf0000000 307 308 #define BWI_PHY_CTRL 0x03fc 309 #define BWI_PHY_DATA 0x03fe 310 311 #define BWI_ADDR_FILTER_CTRL 0x0420 312 #define BWI_ADDR_FILTER_CTRL_SET 0x0020 313 #define BWI_ADDR_FILTER_MYADDR 0 314 #define BWI_ADDR_FILTER_BSSID 3 315 #define BWI_ADDR_FILTER_DATA 0x422 316 317 #define BWI_MAC_GPIO_CTRL 0x049c 318 #define BWI_MAC_GPIO_MASK 0x049e 319 #define BWI_MAC_PRE_TBTT 0x0612 320 #define BWI_MAC_SLOTTIME 0x0684 321 #define BWI_MAC_SLOTTIME_ADJUST 510 322 #define BWI_MAC_POWERUP_DELAY 0x06a8 323 324 /* 325 * Special registers 326 */ 327 /* 328 * GPIO control 329 * If common regwin exists, then it is within common regwin, 330 * else it is in bus regwin. 331 */ 332 #define BWI_GPIO_CTRL 0x0000006c 333 334 /* 335 * Extended PCI registers 336 */ 337 #define BWI_PCIR_BAR PCIR_BAR(0) 338 #define BWI_PCIR_SEL_REGWIN 0x00000080 339 /* Register value for BWI_PCIR_SEL_REGWIN */ 340 #define BWI_PCIM_REGWIN(id) (((id) * 0x1000) + 0x18000000) 341 #define BWI_PCIR_GPIO_IN 0x000000b0 342 #define BWI_PCIR_GPIO_OUT 0x000000b4 343 #define BWI_PCIM_GPIO_OUT_CLKSRC (1 << 4) 344 #define BWI_PCIR_GPIO_ENABLE 0x000000b8 345 /* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */ 346 #define BWI_PCIM_GPIO_PWR_ON (1 << 6) 347 #define BWI_PCIM_GPIO_PLL_PWR_OFF (1 << 7) 348 #define BWI_PCIR_INTCTL 0x00000094 349 350 /* 351 * PCI subdevice IDs 352 */ 353 #define BWI_PCI_SUBDEVICE_BU4306 0x416 354 #define BWI_PCI_SUBDEVICE_BCM4309G 0x421 355 356 #define BWI_IS_BRCM_BU4306(sc) \ 357 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 358 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306) 359 #define BWI_IS_BRCM_BCM4309G(sc) \ 360 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 361 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G) 362 363 /* 364 * EEPROM start address 365 */ 366 #define BWI_SPROM_START 0x1000 367 #define BWI_SPROM_11BG_EADDR 0x48 368 #define BWI_SPROM_11A_EADDR 0x54 369 #define BWI_SPROM_CARD_INFO 0x5c 370 #define BWI_SPROM_CARD_INFO_LOCALE (0x0f << 8) 371 #define BWI_SPROM_LOCALE_JAPAN 5 372 #define BWI_SPROM_PA_PARAM_11BG 0x5e 373 #define BWI_SPROM_GPIO01 0x64 374 #define BWI_SPROM_GPIO_0 0x00ff 375 #define BWI_SPROM_GPIO_1 0xff00 376 #define BWI_SPROM_GPIO23 0x0066 377 #define BWI_SPROM_GPIO_2 0x00ff 378 #define BWI_SPROM_GPIO_3 0xff00 379 #define BWI_SPROM_MAX_TXPWR 0x68 380 #define BWI_SPROM_MAX_TXPWR_MASK_11BG 0x00ff /* XXX */ 381 #define BWI_SPROM_MAX_TXPWR_MASK_11A 0xff00 /* XXX */ 382 #define BWI_SPROM_PA_PARAM_11A 0x6a 383 #define BWI_SPROM_IDLE_TSSI 0x70 384 #define BWI_SPROM_IDLE_TSSI_MASK_11BG 0x00ff /* XXX */ 385 #define BWI_SPROM_IDLE_TSSI_MASK_11A 0xff00 /* XXX */ 386 #define BWI_SPROM_CARD_FLAGS 0x72 387 #define BWI_SPROM_ANT_GAIN 0x74 388 #define BWI_SPROM_ANT_GAIN_MASK_11A 0x00ff 389 #define BWI_SPROM_ANT_GAIN_MASK_11BG 0xff00 390 391 /* 392 * SPROM card flags 393 */ 394 #define BWI_CARD_F_PA_GPIO9 (1 << 1) /* GPIO 9 controls PA */ 395 #define BWI_CARD_F_SW_NRSSI (1 << 3) 396 #define BWI_CARD_F_NO_SLOWCLK (1 << 5) /* no slow clock */ 397 #define BWI_CARD_F_EXT_LNA (1 << 12) /* external LNA */ 398 #define BWI_CARD_F_ALT_IQ (1 << 15) /* alternate I/Q */ 399 400 /* 401 * PROM GPIO 402 */ 403 #define BWI_LED_ACT_LOW (1 << 7) 404 #define BWI_LED_ACT_MASK 0x7f 405 #define BWI_LED_ACT_OFF 0 406 #define BWI_LED_ACT_ON 1 407 #define BWI_LED_ACT_BLINK 2 408 #define BWI_LED_ACT_RF_ENABLED 3 409 #define BWI_LED_ACT_5GHZ 4 410 #define BWI_LED_ACT_2GHZ 5 411 #define BWI_LED_ACT_11G 6 412 #define BWI_LED_ACT_BLINK_SLOW 7 413 #define BWI_LED_ACT_BLINK_POLL 8 414 #define BWI_LED_ACT_UNKN 9 415 #define BWI_LED_ACT_ASSOC 10 416 #define BWI_LED_ACT_NULL 11 417 418 #define BWI_VENDOR_LED_ACT_COMPAQ \ 419 BWI_LED_ACT_RF_ENABLED, \ 420 BWI_LED_ACT_2GHZ, \ 421 BWI_LED_ACT_5GHZ, \ 422 BWI_LED_ACT_OFF 423 424 #define BWI_VENDOR_LED_ACT_LINKSYS \ 425 BWI_LED_ACT_ASSOC, \ 426 BWI_LED_ACT_2GHZ, \ 427 BWI_LED_ACT_5GHZ, \ 428 BWI_LED_ACT_OFF 429 430 #define BWI_VENDOR_LED_ACT_DEFAULT \ 431 BWI_LED_ACT_BLINK, \ 432 BWI_LED_ACT_2GHZ, \ 433 BWI_LED_ACT_5GHZ, \ 434 BWI_LED_ACT_OFF 435 436 /* 437 * BBP IDs 438 */ 439 #define BWI_BBPID_BCM4301 0x4301 440 #define BWI_BBPID_BCM4306 0x4306 441 #define BWI_BBPID_BCM4317 0x4317 442 #define BWI_BBPID_BCM4320 0x4320 443 #define BWI_BBPID_BCM4321 0x4321 444 445 /* 446 * Register window types 447 */ 448 #define BWI_REGWIN_T_COM 0x800 449 #define BWI_REGWIN_T_BUSPCI 0x804 450 #define BWI_REGWIN_T_MAC 0x812 451 #define BWI_REGWIN_T_BUSPCIE 0x820 452 453 /* 454 * MAC interrupts 455 */ 456 #define BWI_INTR_READY (1 << 0) 457 #define BWI_INTR_BEACON (1 << 1) 458 #define BWI_INTR_TBTT (1 << 2) 459 #define BWI_INTR_EO_ATIM (1 << 5) /* End of ATIM */ 460 #define BWI_INTR_PMQ (1 << 6) /* XXX?? */ 461 #define BWI_INTR_MAC_TXERR (1 << 9) 462 #define BWI_INTR_PHY_TXERR (1 << 11) 463 #define BWI_INTR_TIMER1 (1 << 14) 464 #define BWI_INTR_RX_DONE (1 << 15) 465 #define BWI_INTR_TX_FIFO (1 << 16) /* XXX?? */ 466 #define BWI_INTR_NOISE (1 << 18) 467 #define BWI_INTR_RF_DISABLED (1 << 28) 468 #define BWI_INTR_TX_DONE (1 << 29) 469 470 #define BWI_INIT_INTRS \ 471 (BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \ 472 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \ 473 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \ 474 BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE) 475 #define BWI_ALL_INTRS 0xffffffff 476 477 /* 478 * TX/RX interrupts 479 */ 480 481 /* from brcmsmac */ 482 #define BWI_I_PC (1 << 10) /* pci descriptor error */ 483 #define BWI_I_PD (1 << 11) /* pci data error */ 484 #define BWI_I_DE (1 << 12) /* descriptor protocol error */ 485 #define BWI_I_RU (1 << 13) /* receive descriptor underflow */ 486 #define BWI_I_RO (1 << 14) /* receive fifo overflow */ 487 #define BWI_I_XU (1 << 15) /* transmit fifo underflow */ 488 #define BWI_I_RI (1 << 16) /* receive interrupt */ 489 #define BWI_I_XI (1 << 24) /* transmit interrupt */ 490 491 #define BWI_TXRX_INTR_ERROR (BWI_I_XU | BWI_I_RO | BWI_I_DE | \ 492 BWI_I_PD | BWI_I_PC) 493 #define BWI_TXRX_INTR_RX BWI_I_RI 494 #define BWI_TXRX_TX_INTRS BWI_TXRX_INTR_ERROR 495 #define BWI_TXRX_RX_INTRS (BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX) 496 #define BWI_TXRX_IS_RX(i) ((i) % 3 == 0) 497 498 /* PHY */ 499 500 #define BWI_PHYR_NRSSI_THR_11B 0x020 501 #define BWI_PHYR_BBP_ATTEN 0x060 502 #define BWI_PHYR_TBL_CTRL_11A 0x072 503 #define BWI_PHYR_TBL_DATA_LO_11A 0x073 504 #define BWI_PHYR_TBL_DATA_HI_11A 0x074 505 #define BWI_PHYR_TBL_CTRL_11G 0x472 506 #define BWI_PHYR_TBL_DATA_LO_11G 0x473 507 #define BWI_PHYR_TBL_DATA_HI_11G 0x474 508 #define BWI_PHYR_NRSSI_THR_11G 0x48a 509 #define BWI_PHYR_NRSSI_CTRL 0x803 510 #define BWI_PHYR_NRSSI_DATA 0x804 511 #define BWI_PHYR_RF_LO 0x810 512 513 /* 514 * PHY Tables 515 */ 516 /* 517 * http://bcm-specs.sipsolutions.net/APHYSetup/FineFrequency 518 * G PHY 519 */ 520 #define BWI_PHY_FREQ_11G_REV1 \ 521 0x0089, 0x02e9, 0x0409, 0x04e9, 0x05a9, 0x0669, 0x0709, 0x0789, \ 522 0x0829, 0x08a9, 0x0929, 0x0989, 0x0a09, 0x0a69, 0x0ac9, 0x0b29, \ 523 0x0ba9, 0x0be9, 0x0c49, 0x0ca9, 0x0d09, 0x0d69, 0x0da9, 0x0e09, \ 524 0x0e69, 0x0ea9, 0x0f09, 0x0f49, 0x0fa9, 0x0fe9, 0x1029, 0x1089, \ 525 0x10c9, 0x1109, 0x1169, 0x11a9, 0x11e9, 0x1229, 0x1289, 0x12c9, \ 526 0x1309, 0x1349, 0x1389, 0x13c9, 0x1409, 0x1449, 0x14a9, 0x14e9, \ 527 0x1529, 0x1569, 0x15a9, 0x15e9, 0x1629, 0x1669, 0x16a9, 0x16e8, \ 528 0x1728, 0x1768, 0x17a8, 0x17e8, 0x1828, 0x1868, 0x18a8, 0x18e8, \ 529 0x1928, 0x1968, 0x19a8, 0x19e8, 0x1a28, 0x1a68, 0x1aa8, 0x1ae8, \ 530 0x1b28, 0x1b68, 0x1ba8, 0x1be8, 0x1c28, 0x1c68, 0x1ca8, 0x1ce8, \ 531 0x1d28, 0x1d68, 0x1dc8, 0x1e08, 0x1e48, 0x1e88, 0x1ec8, 0x1f08, \ 532 0x1f48, 0x1f88, 0x1fe8, 0x2028, 0x2068, 0x20a8, 0x2108, 0x2148, \ 533 0x2188, 0x21c8, 0x2228, 0x2268, 0x22c8, 0x2308, 0x2348, 0x23a8, \ 534 0x23e8, 0x2448, 0x24a8, 0x24e8, 0x2548, 0x25a8, 0x2608, 0x2668, \ 535 0x26c8, 0x2728, 0x2787, 0x27e7, 0x2847, 0x28c7, 0x2947, 0x29a7, \ 536 0x2a27, 0x2ac7, 0x2b47, 0x2be7, 0x2ca7, 0x2d67, 0x2e47, 0x2f67, \ 537 0x3247, 0x3526, 0x3646, 0x3726, 0x3806, 0x38a6, 0x3946, 0x39e6, \ 538 0x3a66, 0x3ae6, 0x3b66, 0x3bc6, 0x3c45, 0x3ca5, 0x3d05, 0x3d85, \ 539 0x3de5, 0x3e45, 0x3ea5, 0x3ee5, 0x3f45, 0x3fa5, 0x4005, 0x4045, \ 540 0x40a5, 0x40e5, 0x4145, 0x4185, 0x41e5, 0x4225, 0x4265, 0x42c5, \ 541 0x4305, 0x4345, 0x43a5, 0x43e5, 0x4424, 0x4464, 0x44c4, 0x4504, \ 542 0x4544, 0x4584, 0x45c4, 0x4604, 0x4644, 0x46a4, 0x46e4, 0x4724, \ 543 0x4764, 0x47a4, 0x47e4, 0x4824, 0x4864, 0x48a4, 0x48e4, 0x4924, \ 544 0x4964, 0x49a4, 0x49e4, 0x4a24, 0x4a64, 0x4aa4, 0x4ae4, 0x4b23, \ 545 0x4b63, 0x4ba3, 0x4be3, 0x4c23, 0x4c63, 0x4ca3, 0x4ce3, 0x4d23, \ 546 0x4d63, 0x4da3, 0x4de3, 0x4e23, 0x4e63, 0x4ea3, 0x4ee3, 0x4f23, \ 547 0x4f63, 0x4fc3, 0x5003, 0x5043, 0x5083, 0x50c3, 0x5103, 0x5143, \ 548 0x5183, 0x51e2, 0x5222, 0x5262, 0x52a2, 0x52e2, 0x5342, 0x5382, \ 549 0x53c2, 0x5402, 0x5462, 0x54a2, 0x5502, 0x5542, 0x55a2, 0x55e2, \ 550 0x5642, 0x5682, 0x56e2, 0x5722, 0x5782, 0x57e1, 0x5841, 0x58a1, \ 551 0x5901, 0x5961, 0x59c1, 0x5a21, 0x5aa1, 0x5b01, 0x5b81, 0x5be1, \ 552 0x5c61, 0x5d01, 0x5d80, 0x5e20, 0x5ee0, 0x5fa0, 0x6080, 0x61c0 553 554 /* 555 * http://bcm-specs.sipsolutions.net/APHYSetup/noise_table 556 */ 557 /* G PHY Revision 1 */ 558 #define BWI_PHY_NOISE_11G_REV1 \ 559 0x013c, 0x01f5, 0x031a, 0x0631, 0x0001, 0x0001, 0x0001, 0x0001 560 /* G PHY generic */ 561 #define BWI_PHY_NOISE_11G \ 562 0x5484, 0x3c40, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 563 564 /* 565 * http://bcm-specs.sipsolutions.net/APHYSetup/rotor_table 566 * G PHY Revision 1 567 */ 568 #define BWI_PHY_ROTOR_11G_REV1 \ 569 0xfeb93ffd, 0xfec63ffd, 0xfed23ffd, 0xfedf3ffd, \ 570 0xfeec3ffe, 0xfef83ffe, 0xff053ffe, 0xff113ffe, \ 571 0xff1e3ffe, 0xff2a3fff, 0xff373fff, 0xff443fff, \ 572 0xff503fff, 0xff5d3fff, 0xff693fff, 0xff763fff, \ 573 0xff824000, 0xff8f4000, 0xff9b4000, 0xffa84000, \ 574 0xffb54000, 0xffc14000, 0xffce4000, 0xffda4000, \ 575 0xffe74000, 0xfff34000, 0x00004000, 0x000d4000, \ 576 0x00194000, 0x00264000, 0x00324000, 0x003f4000, \ 577 0x004b4000, 0x00584000, 0x00654000, 0x00714000, \ 578 0x007e4000, 0x008a3fff, 0x00973fff, 0x00a33fff, \ 579 0x00b03fff, 0x00bc3fff, 0x00c93fff, 0x00d63fff, \ 580 0x00e23ffe, 0x00ef3ffe, 0x00fb3ffe, 0x01083ffe, \ 581 0x01143ffe, 0x01213ffd, 0x012e3ffd, 0x013a3ffd, \ 582 0x01473ffd 583 584 /* 585 * http://bcm-specs.sipsolutions.net/APHYSetup/noise_scale_table 586 */ 587 /* G PHY Revision [0,2] */ 588 #define BWI_PHY_NOISE_SCALE_11G_REV2 \ 589 0x6c77, 0x5162, 0x3b40, 0x3335, 0x2f2d, 0x2a2a, 0x2527, 0x1f21, \ 590 0x1a1d, 0x1719, 0x1616, 0x1414, 0x1414, 0x1400, 0x1414, 0x1614, \ 591 0x1716, 0x1a19, 0x1f1d, 0x2521, 0x2a27, 0x2f2a, 0x332d, 0x3b35, \ 592 0x5140, 0x6c62, 0x0077 593 /* G PHY Revsion 7 */ 594 #define BWI_PHY_NOISE_SCALE_11G_REV7 \ 595 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, \ 596 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa400, 0xa4a4, 0xa4a4, \ 597 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, \ 598 0xa4a4, 0xa4a4, 0x00a4 599 /* G PHY generic */ 600 #define BWI_PHY_NOISE_SCALE_11G \ 601 0xd8dd, 0xcbd4, 0xbcc0, 0xb6b7, 0xb2b0, 0xadad, 0xa7a9, 0x9fa1, \ 602 0x969b, 0x9195, 0x8f8f, 0x8a8a, 0x8a8a, 0x8a00, 0x8a8a, 0x8f8a, \ 603 0x918f, 0x9695, 0x9f9b, 0xa7a1, 0xada9, 0xb2ad, 0xb6b0, 0xbcb7, \ 604 0xcbc0, 0xd8d4, 0x00dd 605 606 /* 607 * http://bcm-specs.sipsolutions.net/APHYSetup/sigma_square_table 608 */ 609 /* G PHY Revision 2 */ 610 #define BWI_PHY_SIGMA_SQ_11G_REV2 \ 611 0x007a, 0x0075, 0x0071, 0x006c, 0x0067, 0x0063, 0x005e, 0x0059, \ 612 0x0054, 0x0050, 0x004b, 0x0046, 0x0042, 0x003d, 0x003d, 0x003d, \ 613 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, \ 614 0x003d, 0x003d, 0x0000, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, \ 615 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, 0x003d, \ 616 0x0042, 0x0046, 0x004b, 0x0050, 0x0054, 0x0059, 0x005e, 0x0063, \ 617 0x0067, 0x006c, 0x0071, 0x0075, 0x007a 618 /* G PHY Revision (2,7] */ 619 #define BWI_PHY_SIGMA_SQ_11G_REV7 \ 620 0x00de, 0x00dc, 0x00da, 0x00d8, 0x00d6, 0x00d4, 0x00d2, 0x00cf, \ 621 0x00cd, 0x00ca, 0x00c7, 0x00c4, 0x00c1, 0x00be, 0x00be, 0x00be, \ 622 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \ 623 0x00be, 0x00be, 0x0000, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \ 624 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \ 625 0x00c1, 0x00c4, 0x00c7, 0x00ca, 0x00cd, 0x00cf, 0x00d2, 0x00d4, \ 626 0x00d6, 0x00d8, 0x00da, 0x00dc, 0x00de 627 628 /* 629 * http://bcm-specs.sipsolutions.net/APHYSetup/retard_table 630 * G PHY 631 */ 632 #define BWI_PHY_DELAY_11G_REV1 \ 633 0xdb93cb87, 0xd666cf64, 0xd1fdd358, 0xcda6d826, \ 634 0xca38dd9f, 0xc729e2b4, 0xc469e88e, 0xc26aee2b, \ 635 0xc0def46c, 0xc073fa62, 0xc01d00d5, 0xc0760743, \ 636 0xc1560d1e, 0xc2e51369, 0xc4ed18ff, 0xc7ac1ed7, \ 637 0xcb2823b2, 0xcefa28d9, 0xd2f62d3f, 0xd7bb3197, \ 638 0xdce53568, 0xe1fe3875, 0xe7d13b35, 0xed663d35, \ 639 0xf39b3ec4, 0xf98e3fa7, 0x00004000, 0x06723fa7, \ 640 0x0c653ec4, 0x129a3d35, 0x182f3b35, 0x1e023875, \ 641 0x231b3568, 0x28453197, 0x2d0a2d3f, 0x310628d9, \ 642 0x34d823b2, 0x38541ed7, 0x3b1318ff, 0x3d1b1369, \ 643 0x3eaa0d1e, 0x3f8a0743, 0x3fe300d5, 0x3f8dfa62, \ 644 0x3f22f46c, 0x3d96ee2b, 0x3b97e88e, 0x38d7e2b4, \ 645 0x35c8dd9f, 0x325ad826, 0x2e03d358, 0x299acf64, \ 646 0x246dcb87 647 648 /* RF */ 649 650 #define BWI_RFR_ATTEN 0x43 651 652 #define BWI_RFR_TXPWR 0x52 653 #define BWI_RFR_TXPWR1_MASK 0x0070 654 655 #define BWI_RFR_BBP_ATTEN 0x60 656 #define BWI_RFR_BBP_ATTEN_CALIB_BIT (1 << 0) 657 #define BWI_RFR_BBP_ATTEN_CALIB_IDX (0x0f << 1) 658 659 /* 660 * TSSI -- TX power maps 661 */ 662 /* 663 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table 664 * B PHY 665 */ 666 #define BWI_TXPOWER_MAP_11B \ 667 0x4d, 0x4c, 0x4b, 0x4a, 0x4a, 0x49, 0x48, 0x47, \ 668 0x47, 0x46, 0x45, 0x45, 0x44, 0x43, 0x42, 0x42, \ 669 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, \ 670 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x32, 0x31, \ 671 0x30, 0x2f, 0x2d, 0x2c, 0x2b, 0x29, 0x28, 0x26, \ 672 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, 0x17, 0x14, \ 673 0x10, 0x0c, 0x06, 0x00, -7, -7, -7, -7, \ 674 -7, -7, -7, -7, -7, -7, -7, -7 675 /* 676 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table 677 * G PHY 678 */ 679 #define BWI_TXPOWER_MAP_11G \ 680 77, 77, 77, 76, 76, 76, 75, 75, \ 681 74, 74, 73, 73, 73, 72, 72, 71, \ 682 71, 70, 70, 69, 68, 68, 67, 67, \ 683 66, 65, 65, 64, 63, 63, 62, 61, \ 684 60, 59, 58, 57, 56, 55, 54, 53, \ 685 52, 50, 49, 47, 45, 43, 40, 37, \ 686 33, 28, 22, 14, 5, -7, -20, -20, \ 687 -20, -20, -20, -20, -20, -20, -20, -20 688 689 /* Find least significant bit that is set */ 690 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 691 692 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 693 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 694 #define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask)) 695 696 #endif /* !_IF_BWIREG_H */ 697