1 /* $OpenBSD: athnvar.h,v 1.36 2016/01/05 18:41:15 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifdef notyet 20 #define ATHN_BT_COEXISTENCE 1 21 #endif 22 23 #ifdef ATHN_DEBUG 24 #define DPRINTF(x) do { if (athn_debug > 0) printf x; } while (0) 25 #define DPRINTFN(n, x) do { if (athn_debug >= (n)) printf x; } while (0) 26 extern int athn_debug; 27 #else 28 #define DPRINTF(x) 29 #define DPRINTFN(n, x) 30 #endif 31 32 #define LE_READ_4(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 33 #define LE_READ_2(p) ((p)[0] | (p)[1] << 8) 34 35 #define ATHN_RXBUFSZ 3872 36 #define ATHN_TXBUFSZ 4096 37 38 #define ATHN_NRXBUFS 64 39 #define ATHN_NTXBUFS 64 /* Shared between all Tx queues. */ 40 41 struct athn_rx_radiotap_header { 42 struct ieee80211_radiotap_header wr_ihdr; 43 uint64_t wr_tsft; 44 uint8_t wr_flags; 45 uint8_t wr_rate; 46 uint16_t wr_chan_freq; 47 uint16_t wr_chan_flags; 48 int8_t wr_dbm_antsignal; 49 uint8_t wr_antenna; 50 } __packed; 51 52 #define ATHN_RX_RADIOTAP_PRESENT \ 53 (1 << IEEE80211_RADIOTAP_TSFT | \ 54 1 << IEEE80211_RADIOTAP_FLAGS | \ 55 1 << IEEE80211_RADIOTAP_RATE | \ 56 1 << IEEE80211_RADIOTAP_CHANNEL | \ 57 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \ 58 1 << IEEE80211_RADIOTAP_ANTENNA) 59 60 struct athn_tx_radiotap_header { 61 struct ieee80211_radiotap_header wt_ihdr; 62 uint8_t wt_flags; 63 uint8_t wt_rate; 64 uint16_t wt_chan_freq; 65 uint16_t wt_chan_flags; 66 uint8_t wt_hwqueue; 67 } __packed; 68 69 #define ATHN_TX_RADIOTAP_PRESENT \ 70 (1 << IEEE80211_RADIOTAP_FLAGS | \ 71 1 << IEEE80211_RADIOTAP_RATE | \ 72 1 << IEEE80211_RADIOTAP_CHANNEL | \ 73 1 << IEEE80211_RADIOTAP_HWQUEUE) 74 75 struct athn_tx_buf { 76 SIMPLEQ_ENTRY(athn_tx_buf) bf_list; 77 78 void *bf_descs; 79 bus_dmamap_t bf_map; 80 bus_addr_t bf_daddr; 81 82 struct mbuf *bf_m; 83 struct ieee80211_node *bf_ni; 84 int bf_txflags; 85 #define ATHN_TXFLAG_PAPRD (1 << 0) 86 #define ATHN_TXFLAG_CAB (1 << 1) 87 }; 88 89 struct athn_txq { 90 SIMPLEQ_HEAD(, athn_tx_buf) head; 91 void *lastds; 92 struct athn_tx_buf *wait; 93 int queued; 94 }; 95 96 struct athn_rx_buf { 97 SIMPLEQ_ENTRY(athn_rx_buf) bf_list; 98 99 void *bf_desc; 100 bus_dmamap_t bf_map; 101 102 struct mbuf *bf_m; 103 bus_addr_t bf_daddr; 104 }; 105 106 struct athn_rxq { 107 struct athn_rx_buf *bf; 108 109 void *descs; 110 void *lastds; 111 bus_dmamap_t map; 112 bus_dma_segment_t seg; 113 int count; 114 115 SIMPLEQ_HEAD(, athn_rx_buf) head; 116 }; 117 118 /* Software rate indexes. */ 119 #define ATHN_RIDX_CCK1 0 120 #define ATHN_RIDX_CCK2 1 121 #define ATHN_RIDX_OFDM6 4 122 #define ATHN_RIDX_MCS0 12 123 #define ATHN_RIDX_MCS15 27 124 #define ATHN_RIDX_MAX 27 125 #define ATHN_IS_HT_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS0) 126 127 static const struct athn_rate { 128 uint8_t rate; /* Rate in 500Kbps unit or MCS if 0x80. */ 129 uint8_t hwrate; /* HW representation. */ 130 uint8_t rspridx; /* Control Response Frame rate index. */ 131 enum ieee80211_phytype phy; 132 } athn_rates[] = { 133 { 2, 0x1b, 0, IEEE80211_T_DS }, 134 { 4, 0x1a, 1, IEEE80211_T_DS }, 135 { 11, 0x19, 1, IEEE80211_T_DS }, 136 { 22, 0x18, 1, IEEE80211_T_DS }, 137 { 12, 0x0b, 4, IEEE80211_T_OFDM }, 138 { 18, 0x0f, 4, IEEE80211_T_OFDM }, 139 { 24, 0x0a, 6, IEEE80211_T_OFDM }, 140 { 36, 0x0e, 6, IEEE80211_T_OFDM }, 141 { 48, 0x09, 8, IEEE80211_T_OFDM }, 142 { 72, 0x0d, 8, IEEE80211_T_OFDM }, 143 { 96, 0x08, 8, IEEE80211_T_OFDM }, 144 { 108, 0x0c, 8, IEEE80211_T_OFDM }, 145 { 0x80, 0x80, 8, IEEE80211_T_OFDM }, 146 { 0x81, 0x81, 8, IEEE80211_T_OFDM }, 147 { 0x82, 0x82, 8, IEEE80211_T_OFDM }, 148 { 0x83, 0x83, 8, IEEE80211_T_OFDM }, 149 { 0x84, 0x84, 8, IEEE80211_T_OFDM }, 150 { 0x85, 0x85, 8, IEEE80211_T_OFDM }, 151 { 0x86, 0x86, 8, IEEE80211_T_OFDM }, 152 { 0x87, 0x87, 8, IEEE80211_T_OFDM }, 153 { 0x88, 0x88, 8, IEEE80211_T_OFDM }, 154 { 0x89, 0x89, 8, IEEE80211_T_OFDM }, 155 { 0x8a, 0x8a, 8, IEEE80211_T_OFDM }, 156 { 0x8b, 0x8b, 8, IEEE80211_T_OFDM }, 157 { 0x8c, 0x8c, 8, IEEE80211_T_OFDM }, 158 { 0x8d, 0x8d, 8, IEEE80211_T_OFDM }, 159 { 0x8e, 0x8e, 8, IEEE80211_T_OFDM }, 160 { 0x8f, 0x8f, 8, IEEE80211_T_OFDM } 161 }; 162 163 struct athn_series { 164 uint16_t dur; 165 uint8_t hwrate; 166 }; 167 168 struct athn_pier { 169 uint8_t fbin; 170 const uint8_t *pwr[AR_PD_GAINS_IN_MASK]; 171 const uint8_t *vpd[AR_PD_GAINS_IN_MASK]; 172 }; 173 174 /* 175 * Structures used to store initialization values. 176 */ 177 struct athn_ini { 178 int nregs; 179 const uint16_t *regs; 180 const uint32_t *vals_5g20; 181 const uint32_t *vals_5g40; 182 const uint32_t *vals_2g40; 183 const uint32_t *vals_2g20; 184 int ncmregs; 185 const uint16_t *cmregs; 186 const uint32_t *cmvals; 187 int nfastregs; 188 const uint16_t *fastregs; 189 const uint32_t *fastvals_5g20; 190 const uint32_t *fastvals_5g40; 191 }; 192 193 struct athn_gain { 194 int nregs; 195 const uint16_t *regs; 196 const uint32_t *vals_5g; 197 const uint32_t *vals_2g; 198 }; 199 200 struct athn_addac { 201 int nvals; 202 const uint32_t *vals; 203 }; 204 205 struct athn_serdes { 206 int nvals; 207 const uint32_t *regs; 208 const uint32_t *vals; 209 }; 210 211 /* Rx queue software indexes. */ 212 #define ATHN_QID_LP 0 213 #define ATHN_QID_HP 1 214 215 /* Tx queue software indexes. */ 216 #define ATHN_QID_AC_BE 0 217 #define ATHN_QID_PSPOLL 1 218 #define ATHN_QID_AC_BK 2 219 #define ATHN_QID_AC_VI 3 220 #define ATHN_QID_AC_VO 4 221 #define ATHN_QID_UAPSD 5 222 #define ATHN_QID_CAB 6 223 #define ATHN_QID_BEACON 7 224 #define ATHN_QID_COUNT 8 225 226 /* Map Access Category to Tx queue Id. */ 227 static const uint8_t athn_ac2qid[EDCA_NUM_AC] = { 228 ATHN_QID_AC_BE, /* EDCA_AC_BE */ 229 ATHN_QID_AC_BK, /* EDCA_AC_BK */ 230 ATHN_QID_AC_VI, /* EDCA_AC_VI */ 231 ATHN_QID_AC_VO /* EDCA_AC_VO */ 232 }; 233 234 static const uint8_t athn_5ghz_chans[] = { 235 /* UNII 1. */ 236 36, 40, 44, 48, 237 /* UNII 2. */ 238 52, 56, 60, 64, 239 /* Middle band. */ 240 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 241 /* UNII 3. */ 242 149, 153, 157, 161, 165 243 }; 244 245 /* Number of data bits per OFDM symbol for MCS[0-15]. */ 246 /* See tables 20-29, 20-30, 20-33, 20-34. */ 247 static const uint16_t ar_mcs_ndbps[][2] = { 248 /* 20MHz 40MHz */ 249 { 26, 54 }, /* MCS0 */ 250 { 52, 108 }, /* MCS1 */ 251 { 78, 162 }, /* MCS2 */ 252 { 104, 216 }, /* MCS3 */ 253 { 156, 324 }, /* MCS4 */ 254 { 208, 432 }, /* MCS5 */ 255 { 234, 486 }, /* MCS6 */ 256 { 260, 540 }, /* MCS7 */ 257 { 26, 108 }, /* MCS8 */ 258 { 52, 216 }, /* MCS9 */ 259 { 78, 324 }, /* MCS10 */ 260 { 104, 432 }, /* MCS11 */ 261 { 156, 648 }, /* MCS12 */ 262 { 208, 864 }, /* MCS13 */ 263 { 234, 972 }, /* MCS14 */ 264 { 260, 1080 } /* MCS15 */ 265 }; 266 267 #define ATHN_POWER_OFDM6 0 268 #define ATHN_POWER_OFDM9 1 269 #define ATHN_POWER_OFDM12 2 270 #define ATHN_POWER_OFDM18 3 271 #define ATHN_POWER_OFDM24 4 272 #define ATHN_POWER_OFDM36 5 273 #define ATHN_POWER_OFDM48 6 274 #define ATHN_POWER_OFDM54 7 275 #define ATHN_POWER_CCK1_LP 8 276 #define ATHN_POWER_CCK2_LP 9 277 #define ATHN_POWER_CCK2_SP 10 278 #define ATHN_POWER_CCK55_LP 11 279 #define ATHN_POWER_CCK55_SP 12 280 #define ATHN_POWER_CCK11_LP 13 281 #define ATHN_POWER_CCK11_SP 14 282 #define ATHN_POWER_XR 15 283 #define ATHN_POWER_HT20(mcs) (16 + (mcs)) 284 #define ATHN_POWER_HT40(mcs) (40 + (mcs)) 285 #define ATHN_POWER_CCK_DUP 64 286 #define ATHN_POWER_OFDM_DUP 65 287 #define ATHN_POWER_CCK_EXT 66 288 #define ATHN_POWER_OFDM_EXT 67 289 #define ATHN_POWER_COUNT 68 290 291 struct athn_node { 292 struct ieee80211_node ni; 293 struct ieee80211_amrr_node amn; 294 uint8_t ridx[IEEE80211_RATE_MAXSIZE]; 295 uint8_t fallback[IEEE80211_RATE_MAXSIZE]; 296 uint8_t sta_index; 297 }; 298 299 /* 300 * Adaptive noise immunity state. 301 */ 302 #define ATHN_ANI_PERIOD 100 303 #define ATHN_ANI_RSSI_THR_HIGH 40 304 #define ATHN_ANI_RSSI_THR_LOW 7 305 struct athn_ani { 306 uint8_t noise_immunity_level; 307 uint8_t spur_immunity_level; 308 uint8_t firstep_level; 309 uint8_t ofdm_weak_signal; 310 uint8_t cck_weak_signal; 311 312 uint32_t listen_time; 313 314 uint32_t ofdm_trig_high; 315 uint32_t ofdm_trig_low; 316 317 int32_t cck_trig_high; 318 int32_t cck_trig_low; 319 320 uint32_t ofdm_phy_err_base; 321 uint32_t cck_phy_err_base; 322 uint32_t ofdm_phy_err_count; 323 uint32_t cck_phy_err_count; 324 325 uint32_t cyccnt; 326 uint32_t txfcnt; 327 uint32_t rxfcnt; 328 }; 329 330 struct athn_iq_cal { 331 uint32_t pwr_meas_i; 332 uint32_t pwr_meas_q; 333 int32_t iq_corr_meas; 334 }; 335 336 struct athn_adc_cal { 337 uint32_t pwr_meas_odd_i; 338 uint32_t pwr_meas_even_i; 339 uint32_t pwr_meas_odd_q; 340 uint32_t pwr_meas_even_q; 341 }; 342 343 struct athn_calib { 344 int nsamples; 345 struct athn_iq_cal iq[AR_MAX_CHAINS]; 346 struct athn_adc_cal adc_gain[AR_MAX_CHAINS]; 347 struct athn_adc_cal adc_dc_offset[AR_MAX_CHAINS]; 348 }; 349 350 #define ATHN_NF_CAL_HIST_MAX 5 351 352 struct athn_softc; 353 354 struct athn_ops { 355 /* Bus callbacks. */ 356 uint32_t (*read)(struct athn_softc *, uint32_t); 357 void (*write)(struct athn_softc *, uint32_t, uint32_t); 358 void (*write_barrier)(struct athn_softc *); 359 360 void (*setup)(struct athn_softc *); 361 void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *, 362 struct ieee80211_channel *); 363 void (*spur_mitigate)(struct athn_softc *, 364 struct ieee80211_channel *, struct ieee80211_channel *); 365 const struct ar_spur_chan * 366 (*get_spur_chans)(struct athn_softc *, int); 367 void (*init_from_rom)(struct athn_softc *, 368 struct ieee80211_channel *, struct ieee80211_channel *); 369 int (*set_synth)(struct athn_softc *, struct ieee80211_channel *, 370 struct ieee80211_channel *); 371 int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int); 372 const uint8_t * 373 (*get_rom_template)(struct athn_softc *, uint8_t); 374 void (*swap_rom)(struct athn_softc *); 375 void (*olpc_init)(struct athn_softc *); 376 void (*olpc_temp_compensation)(struct athn_softc *); 377 /* GPIO callbacks. */ 378 int (*gpio_read)(struct athn_softc *, int); 379 void (*gpio_write)(struct athn_softc *, int, int); 380 void (*gpio_config_input)(struct athn_softc *, int); 381 void (*gpio_config_output)(struct athn_softc *, int, int); 382 void (*rfsilent_init)(struct athn_softc *); 383 /* DMA callbacks. */ 384 int (*dma_alloc)(struct athn_softc *); 385 void (*dma_free)(struct athn_softc *); 386 void (*rx_enable)(struct athn_softc *); 387 int (*intr)(struct athn_softc *); 388 int (*tx)(struct athn_softc *, struct mbuf *, 389 struct ieee80211_node *, int); 390 /* PHY callbacks. */ 391 void (*set_rf_mode)(struct athn_softc *, 392 struct ieee80211_channel *); 393 int (*rf_bus_request)(struct athn_softc *); 394 void (*rf_bus_release)(struct athn_softc *); 395 void (*set_phy)(struct athn_softc *, struct ieee80211_channel *, 396 struct ieee80211_channel *); 397 void (*set_delta_slope)(struct athn_softc *, 398 struct ieee80211_channel *, struct ieee80211_channel *); 399 void (*enable_antenna_diversity)(struct athn_softc *); 400 void (*init_baseband)(struct athn_softc *); 401 void (*disable_phy)(struct athn_softc *); 402 void (*set_rxchains)(struct athn_softc *); 403 void (*noisefloor_calib)(struct athn_softc *); 404 void (*do_calib)(struct athn_softc *); 405 void (*next_calib)(struct athn_softc *); 406 void (*hw_init)(struct athn_softc *, struct ieee80211_channel *, 407 struct ieee80211_channel *); 408 void (*get_paprd_masks)(struct athn_softc *sc, 409 struct ieee80211_channel *, uint32_t *, uint32_t *); 410 /* ANI callbacks. */ 411 void (*set_noise_immunity_level)(struct athn_softc *, int); 412 void (*enable_ofdm_weak_signal)(struct athn_softc *); 413 void (*disable_ofdm_weak_signal)(struct athn_softc *); 414 void (*set_cck_weak_signal)(struct athn_softc *, int); 415 void (*set_firstep_level)(struct athn_softc *, int); 416 void (*set_spur_immunity_level)(struct athn_softc *, int); 417 }; 418 419 struct athn_softc { 420 struct device sc_dev; 421 struct ieee80211com sc_ic; 422 423 int (*sc_enable)(struct athn_softc *); 424 void (*sc_disable)(struct athn_softc *); 425 void (*sc_power)(struct athn_softc *, int); 426 void (*sc_disable_aspm)(struct athn_softc *); 427 void (*sc_enable_extsynch)( 428 struct athn_softc *); 429 430 int (*sc_newstate)(struct ieee80211com *, 431 enum ieee80211_state, int); 432 433 bus_dma_tag_t sc_dmat; 434 435 struct timeout scan_to; 436 struct timeout calib_to; 437 struct ieee80211_amrr amrr; 438 439 u_int flags; 440 #define ATHN_FLAG_PCIE (1 << 0) 441 #define ATHN_FLAG_USB (1 << 1) 442 #define ATHN_FLAG_OLPC (1 << 2) 443 #define ATHN_FLAG_PAPRD (1 << 3) 444 #define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4) 445 #define ATHN_FLAG_RFSILENT (1 << 5) 446 #define ATHN_FLAG_RFSILENT_REVERSED (1 << 6) 447 #define ATHN_FLAG_BTCOEX2WIRE (1 << 7) 448 #define ATHN_FLAG_BTCOEX3WIRE (1 << 8) 449 /* Shortcut. */ 450 #define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE) 451 #define ATHN_FLAG_11A (1 << 9) 452 #define ATHN_FLAG_11G (1 << 10) 453 #define ATHN_FLAG_11N (1 << 11) 454 #define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12) 455 #define ATHN_FLAG_NON_ENTERPRISE (1 << 13) 456 #define ATHN_FLAG_3TREDUCE_CHAIN (1 << 14) 457 458 uint8_t ngpiopins; 459 int led_pin; 460 int rfsilent_pin; 461 int led_state; 462 uint32_t isync; 463 uint32_t imask; 464 465 uint16_t mac_ver; 466 uint8_t mac_rev; 467 uint8_t rf_rev; 468 uint16_t eep_rev; 469 470 uint8_t txchainmask; 471 uint8_t rxchainmask; 472 uint8_t ntxchains; 473 uint8_t nrxchains; 474 475 uint8_t sup_calib_mask; 476 uint8_t cur_calib_mask; 477 #define ATHN_CAL_IQ (1 << 0) 478 #define ATHN_CAL_ADC_GAIN (1 << 1) 479 #define ATHN_CAL_ADC_DC (1 << 2) 480 #define ATHN_CAL_TEMP (1 << 3) 481 482 struct ieee80211_channel *curchan; 483 struct ieee80211_channel *curchanext; 484 485 /* Open Loop Power Control. */ 486 int8_t tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE]; 487 int8_t pdadc; 488 int8_t tcomp; 489 int olpc_ticks; 490 491 /* PA predistortion. */ 492 uint16_t gain1[AR_MAX_CHAINS]; 493 uint32_t txgain[AR9003_TX_GAIN_TABLE_SIZE]; 494 int16_t pa_in[AR_MAX_CHAINS] 495 [AR9003_PAPRD_MEM_TAB_SIZE]; 496 int16_t angle[AR_MAX_CHAINS] 497 [AR9003_PAPRD_MEM_TAB_SIZE]; 498 int32_t trainpow; 499 uint8_t paprd_curchain; 500 501 uint32_t rwbuf[64]; 502 503 int kc_entries; 504 505 void *eep; 506 const void *eep_def; 507 uint32_t eep_base; 508 uint32_t eep_size; 509 510 struct athn_rxq rxq[2]; 511 struct athn_txq txq[31]; 512 513 void *descs; 514 bus_dmamap_t map; 515 bus_dma_segment_t seg; 516 SIMPLEQ_HEAD(, athn_tx_buf) txbufs; 517 struct athn_tx_buf *bcnbuf; 518 struct athn_tx_buf txpool[ATHN_NTXBUFS]; 519 520 bus_dmamap_t txsmap; 521 bus_dma_segment_t txsseg; 522 void *txsring; 523 int txscur; 524 525 int sc_if_flags; 526 int sc_tx_timer; 527 528 const struct athn_ini *ini; 529 const struct athn_gain *rx_gain; 530 const struct athn_gain *tx_gain; 531 const struct athn_addac *addac; 532 const struct athn_serdes *serdes; 533 uint32_t workaround; 534 uint32_t obs_off; 535 uint32_t gpio_input_en_off; 536 537 struct athn_ops ops; 538 539 int fixed_ridx; 540 541 int16_t cca_min_2g; 542 int16_t cca_max_2g; 543 int16_t cca_min_5g; 544 int16_t cca_max_5g; 545 int16_t def_nf; 546 struct { 547 int16_t nf[AR_MAX_CHAINS]; 548 int16_t nf_ext[AR_MAX_CHAINS]; 549 } nf_hist[ATHN_NF_CAL_HIST_MAX]; 550 int nf_hist_cur; 551 int16_t nf_priv[AR_MAX_CHAINS]; 552 int16_t nf_ext_priv[AR_MAX_CHAINS]; 553 int pa_calib_ticks; 554 555 struct athn_calib calib; 556 struct athn_ani ani; 557 558 #if NBPFILTER > 0 559 caddr_t sc_drvbpf; 560 561 union { 562 struct athn_rx_radiotap_header th; 563 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 564 } sc_rxtapu; 565 #define sc_rxtap sc_rxtapu.th 566 int sc_rxtap_len; 567 568 union { 569 struct athn_tx_radiotap_header th; 570 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 571 } sc_txtapu; 572 #define sc_txtap sc_txtapu.th 573 int sc_txtap_len; 574 #endif 575 }; 576 577 extern int athn_attach(struct athn_softc *); 578 extern void athn_detach(struct athn_softc *); 579 extern void athn_suspend(struct athn_softc *); 580 extern void athn_wakeup(struct athn_softc *); 581 extern int athn_intr(void *); 582