1 /* $OpenBSD: athnreg.h,v 1.18 2012/06/10 21:23:36 kettenis Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * MAC registers. 22 */ 23 #define AR_CR 0x0008 24 #define AR_RXDP 0x000c 25 #define AR_CFG 0x0014 26 #define AR_RXBP_THRESH 0x0018 27 #define AR_MIRT 0x0020 28 #define AR_IER 0x0024 29 #define AR_TIMT 0x0028 30 #define AR_RIMT 0x002c 31 #define AR_TXCFG 0x0030 32 #define AR_RXCFG 0x0034 33 #define AR_MIBC 0x0040 34 #define AR_TOPS 0x0044 35 #define AR_RXNPTO 0x0048 36 #define AR_TXNPTO 0x004c 37 #define AR_RPGTO 0x0050 38 #define AR_RPCNT 0x0054 39 #define AR_MACMISC 0x0058 40 #define AR_DATABUF_SIZE 0x0060 41 #define AR_GTXTO 0x0064 42 #define AR_GTTM 0x0068 43 #define AR_CST 0x006c 44 #define AR_HP_RXDP 0x0074 45 #define AR_LP_RXDP 0x0078 46 #define AR_ISR 0x0080 47 #define AR_ISR_S0 0x0084 48 #define AR_ISR_S1 0x0088 49 #define AR_ISR_S2 0x008c 50 #define AR_ISR_S3 0x0090 51 #define AR_ISR_S4 0x0094 52 #define AR_ISR_S5 0x0098 53 #define AR_IMR 0x00a0 54 #define AR_IMR_S0 0x00a4 55 #define AR_IMR_S1 0x00a8 56 #define AR_IMR_S2 0x00ac 57 #define AR_IMR_S3 0x00b0 58 #define AR_IMR_S4 0x00b4 59 #define AR_IMR_S5 0x00b8 60 #define AR_ISR_RAC 0x00c0 61 #define AR_ISR_S0_S 0x00c4 62 #define AR_ISR_S1_S 0x00c8 63 #define AR_DMADBG(i) (0x00e0 + (i) * 4) 64 #define AR_QTXDP(i) (0x0800 + (i) * 4) 65 #define AR_Q_STATUS_RING_START 0x0830 66 #define AR_Q_STATUS_RING_END 0x0834 67 #define AR_Q_TXE 0x0840 68 #define AR_Q_TXD 0x0880 69 #define AR_QCBRCFG(i) (0x08c0 + (i) * 4) 70 #define AR_QRDYTIMECFG(i) (0x0900 + (i) * 4) 71 #define AR_Q_ONESHOTARM_SC 0x0940 72 #define AR_Q_ONESHOTARM_CC 0x0980 73 #define AR_QMISC(i) (0x09c0 + (i) * 4) 74 #define AR_QSTS(i) (0x0a00 + (i) * 4) 75 #define AR_Q_RDYTIMESHDN 0x0a40 76 #define AR_Q_DESC_CRCCHK 0x0a44 77 #define AR_DQCUMASK(i) (0x1000 + (i) * 4) 78 #define AR_D_GBL_IFS_SIFS 0x1030 79 #define AR_D_TXBLK_CMD 0x1038 80 #define AR_DLCL_IFS(i) (0x1040 + (i) * 4) 81 #define AR_D_GBL_IFS_SLOT 0x1070 82 #define AR_DRETRY_LIMIT(i) (0x1080 + (i) * 4) 83 #define AR_D_GBL_IFS_EIFS 0x10b0 84 #define AR_DCHNTIME(i) (0x10c0 + (i) * 4) 85 #define AR_D_GBL_IFS_MISC 0x10f0 86 #define AR_DMISC(i) (0x1100 + (i) * 4) 87 #define AR_D_SEQNUM 0x1140 88 #define AR_D_FPCTL 0x1230 89 #define AR_D_TXPSE 0x1270 90 #define AR_D_TXSLOTMASK 0x12f0 91 #define AR_MAC_SLEEP 0x1f00 92 #define AR_CFG_LED 0x1f04 93 #define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4) 94 #define AR_RC 0x4000 95 #define AR_WA 0x4004 96 #define AR_PM_STATE 0x4008 97 #define AR_PCIE_PM_CTRL 0x4014 98 #define AR_HOST_TIMEOUT 0x4018 99 #define AR_EEPROM 0x401c 100 #define AR_SREV 0x4020 101 #define AR_AHB_MODE 0x4024 102 #define AR_INTR_SYNC_CAUSE 0x4028 103 #define AR_INTR_SYNC_ENABLE 0x402c 104 #define AR_INTR_ASYNC_MASK 0x4030 105 #define AR_INTR_SYNC_MASK 0x4034 106 #define AR_INTR_ASYNC_CAUSE 0x4038 107 #define AR_INTR_ASYNC_ENABLE 0x403c 108 #define AR_PCIE_SERDES 0x4040 109 #define AR_PCIE_SERDES2 0x4044 110 #define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 111 #define AR_INTR_PRIO_ASYNC_MASK 0x40c8 112 #define AR_INTR_PRIO_SYNC_MASK 0x40cc 113 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 114 #define AR_RTC_RC 0x7000 115 #define AR_RTC_XTAL_CONTROL 0x7004 116 #define AR_RTC_REG_CONTROL0 0x7008 117 #define AR_RTC_REG_CONTROL1 0x700c 118 #define AR_RTC_PLL_CONTROL 0x7014 119 #define AR_RTC_PLL_CONTROL2 0x703c 120 #define AR_RTC_RESET 0x7040 121 #define AR_RTC_STATUS 0x7044 122 #define AR_RTC_SLEEP_CLK 0x7048 123 #define AR_RTC_FORCE_WAKE 0x704c 124 #define AR_RTC_INTR_CAUSE 0x7050 125 #define AR_RTC_INTR_ENABLE 0x7054 126 #define AR_RTC_INTR_MASK 0x7058 127 #define AR_STA_ID0 0x8000 128 #define AR_STA_ID1 0x8004 129 #define AR_BSS_ID0 0x8008 130 #define AR_BSS_ID1 0x800c 131 #define AR_BCN_RSSI_AVE 0x8010 132 #define AR_TIME_OUT 0x8014 133 #define AR_RSSI_THR 0x8018 134 #define AR_USEC 0x801c 135 #define AR_RESET_TSF 0x8020 136 #define AR_MAX_CFP_DUR 0x8038 137 #define AR_RX_FILTER 0x803c 138 #define AR_MCAST_FIL0 0x8040 139 #define AR_MCAST_FIL1 0x8044 140 #define AR_DIAG_SW 0x8048 141 #define AR_TSF_L32 0x804c 142 #define AR_TSF_U32 0x8050 143 #define AR_TST_ADDAC 0x8054 144 #define AR_DEF_ANTENNA 0x8058 145 #define AR_AES_MUTE_MASK0 0x805c 146 #define AR_AES_MUTE_MASK1 0x8060 147 #define AR_GATED_CLKS 0x8064 148 #define AR_OBS_BUS_CTRL 0x8068 149 #define AR_OBS_BUS_1 0x806c 150 #define AR_LAST_TSTP 0x8080 151 #define AR_NAV 0x8084 152 #define AR_RTS_OK 0x8088 153 #define AR_RTS_FAIL 0x808c 154 #define AR_ACK_FAIL 0x8090 155 #define AR_FCS_FAIL 0x8094 156 #define AR_BEACON_CNT 0x8098 157 #define AR_SLEEP1 0x80d4 158 #define AR_SLEEP2 0x80d8 159 #define AR_BSSMSKL 0x80e0 160 #define AR_BSSMSKU 0x80e4 161 #define AR_TPC 0x80e8 162 #define AR_TFCNT 0x80ec 163 #define AR_RFCNT 0x80f0 164 #define AR_RCCNT 0x80f4 165 #define AR_CCCNT 0x80f8 166 #define AR_QUIET1 0x80fc 167 #define AR_QUIET2 0x8100 168 #define AR_TSF_PARM 0x8104 169 #define AR_QOS_NO_ACK 0x8108 170 #define AR_PHY_ERR 0x810c 171 #define AR_RXFIFO_CFG 0x8114 172 #define AR_MIC_QOS_CONTROL 0x8118 173 #define AR_MIC_QOS_SELECT 0x811c 174 #define AR_PCU_MISC 0x8120 175 #define AR_FILT_OFDM 0x8124 176 #define AR_FILT_CCK 0x8128 177 #define AR_PHY_ERR_1 0x812c 178 #define AR_PHY_ERR_MASK_1 0x8130 179 #define AR_PHY_ERR_2 0x8134 180 #define AR_PHY_ERR_MASK_2 0x8138 181 #define AR_TSFOOR_THRESHOLD 0x813c 182 #define AR_PHY_ERR_EIFS_MASK 0x8144 183 #define AR_PHY_ERR_3 0x8168 184 #define AR_PHY_ERR_MASK_3 0x816c 185 #define AR_BT_COEX_MODE 0x8170 186 #define AR_BT_COEX_WEIGHT 0x8174 187 #define AR_BT_COEX_MODE2 0x817c 188 #define AR_NEXT_NDP2_TIMER(i) (0x8180 + (i) * 4) 189 #define AR_NDP2_PERIOD(i) (0x81a0 + (i) * 4) 190 #define AR_NDP2_TIMER_MODE 0x81c0 191 #define AR_TXSIFS 0x81d0 192 #define AR_TXOP_X 0x81ec 193 #define AR_TXOP_0_3 0x81f0 194 #define AR_TXOP_4_7 0x81f4 195 #define AR_TXOP_8_11 0x81f8 196 #define AR_TXOP_12_15 0x81fc 197 #define AR_GEN_TIMER(i) (0x8200 + (i) * 4) 198 #define AR_NEXT_TBTT_TIMER AR_GEN_TIMER(0) 199 #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMER(1) 200 #define AR_NEXT_CFP AR_GEN_TIMER(2) 201 #define AR_NEXT_HCF AR_GEN_TIMER(3) 202 #define AR_NEXT_TIM AR_GEN_TIMER(4) 203 #define AR_NEXT_DTIM AR_GEN_TIMER(5) 204 #define AR_NEXT_QUIET_TIMER AR_GEN_TIMER(6) 205 #define AR_NEXT_NDP_TIMER AR_GEN_TIMER(7) 206 #define AR_BEACON_PERIOD AR_GEN_TIMER(8) 207 #define AR_DMA_BEACON_PERIOD AR_GEN_TIMER(9) 208 #define AR_SWBA_PERIOD AR_GEN_TIMER(10) 209 #define AR_HCF_PERIOD AR_GEN_TIMER(11) 210 #define AR_TIM_PERIOD AR_GEN_TIMER(12) 211 #define AR_DTIM_PERIOD AR_GEN_TIMER(13) 212 #define AR_QUIET_PERIOD AR_GEN_TIMER(14) 213 #define AR_NDP_PERIOD AR_GEN_TIMER(15) 214 #define AR_TIMER_MODE 0x8240 215 #define AR_SLP32_MODE 0x8244 216 #define AR_SLP32_WAKE 0x8248 217 #define AR_SLP32_INC 0x824c 218 #define AR_SLP_CNT 0x8250 219 #define AR_SLP_CYCLE_CNT 0x8254 220 #define AR_SLP_MIB_CTRL 0x8258 221 #define AR_WOW_PATTERN_REG 0x825c 222 #define AR_WOW_COUNT_REG 0x8260 223 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 224 #define AR_WOW_BCN_EN_REG 0x8270 225 #define AR_WOW_BCN_TIMO_REG 0x8274 226 #define AR_WOW_KEEP_ALIVE_TIMO_REG 0x8278 227 #define AR_WOW_KEEP_ALIVE_REG 0x827c 228 #define AR_WOW_US_SCALAR_REG 0x8284 229 #define AR_WOW_KEEP_ALIVE_DELAY_REG 0x8288 230 #define AR_WOW_PATTERN_MATCH_REG 0x828c 231 #define AR_WOW_PATTERN_OFF1_REG 0x8290 232 #define AR_WOW_PATTERN_OFF2_REG 0x8294 233 #define AR_WOW_EXACT_REG 0x829c 234 #define AR_2040_MODE 0x8318 235 #define AR_EXTRCCNT 0x8328 236 #define AR_SELFGEN_MASK 0x832c 237 #define AR_PCU_TXBUF_CTRL 0x8340 238 #define AR_PCU_MISC_MODE2 0x8344 239 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 240 #define AR_WOW_LENGTH1_REG 0x8360 241 #define AR_WOW_LENGTH2_REG 0x8364 242 #define AR_WOW_PATTERN_MATCH_LT_256B 0x8368 243 #define AR_RATE_DURATION(i) (0x8700 + (i) * 4) 244 #define AR_KEYTABLE(i) (0x8800 + (i) * 32) 245 #define AR_KEYTABLE_KEY0(i) (AR_KEYTABLE(i) + 0) 246 #define AR_KEYTABLE_KEY1(i) (AR_KEYTABLE(i) + 4) 247 #define AR_KEYTABLE_KEY2(i) (AR_KEYTABLE(i) + 8) 248 #define AR_KEYTABLE_KEY3(i) (AR_KEYTABLE(i) + 12) 249 #define AR_KEYTABLE_KEY4(i) (AR_KEYTABLE(i) + 16) 250 #define AR_KEYTABLE_TYPE(i) (AR_KEYTABLE(i) + 20) 251 #define AR_KEYTABLE_MAC0(i) (AR_KEYTABLE(i) + 24) 252 #define AR_KEYTABLE_MAC1(i) (AR_KEYTABLE(i) + 28) 253 254 255 /* Bits for AR_CR. */ 256 #define AR_CR_RXE 0x00000004 257 #define AR_CR_RXD 0x00000020 258 #define AR_CR_SWI 0x00000040 259 260 /* Bits for AR_CFG. */ 261 #define AR_CFG_SWTD 0x00000001 262 #define AR_CFG_SWTB 0x00000002 263 #define AR_CFG_SWRD 0x00000004 264 #define AR_CFG_SWRB 0x00000008 265 #define AR_CFG_SWRG 0x00000010 266 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 267 #define AR_CFG_PHOK 0x00000100 268 #define AR_CFG_EEBS 0x00000200 269 #define AR_CFG_CLK_GATE_DIS 0x00000400 270 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 271 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 272 273 /* Bits for AR_RXBP_THRESH. */ 274 #define AR_RXBP_THRESH_HP_M 0x0000000f 275 #define AR_RXBP_THRESH_HP_S 0 276 #define AR_RXBP_THRESH_LP_M 0x00003f00 277 #define AR_RXBP_THRESH_LP_S 8 278 279 /* Bits for AR_IER. */ 280 #define AR_IER_ENABLE 0x00000001 281 282 /* Bits for AR_TIMT. */ 283 #define AR_TIMT_LAST_M 0x0000ffff 284 #define AR_TIMT_LAST_S 0 285 #define AR_TIMT_FIRST_M 0xffff0000 286 #define AR_TIMT_FIRST_S 16 287 288 /* Bits for AR_RIMT. */ 289 #define AR_RIMT_LAST_M 0x0000ffff 290 #define AR_RIMT_LAST_S 0 291 #define AR_RIMT_FIRST_M 0xffff0000 292 #define AR_RIMT_FIRST_S 16 293 294 /* Bits for AR_[TR]XCFG_DMASZ fields. */ 295 #define AR_DMASZ_4B 0 296 #define AR_DMASZ_8B 1 297 #define AR_DMASZ_16B 2 298 #define AR_DMASZ_32B 3 299 #define AR_DMASZ_64B 4 300 #define AR_DMASZ_128B 5 301 #define AR_DMASZ_256B 6 302 #define AR_DMASZ_512B 7 303 304 /* Bits for AR_TXCFG. */ 305 #define AR_TXCFG_DMASZ_M 0x00000007 306 #define AR_TXCFG_DMASZ_S 0 307 #define AR_TXCFG_FTRIG_M 0x000003f0 308 #define AR_TXCFG_FTRIG_S 4 309 #define AR_TXCFG_FTRIG_IMMED ( 0 / 64) 310 #define AR_TXCFG_FTRIG_64B ( 64 / 64) 311 #define AR_TXCFG_FTRIG_128B (128 / 64) 312 #define AR_TXCFG_FTRIG_192B (192 / 64) 313 #define AR_TXCFG_FTRIG_256B (256 / 64) 314 #define AR_TXCFG_FTRIG_512B (512 / 64) 315 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 316 317 /* Bits for AR_RXCFG. */ 318 #define AR_RXCFG_DMASZ_M 0x00000007 319 #define AR_RXCFG_DMASZ_S 0 320 #define AR_RXCFG_CHIRP 0x00000008 321 #define AR_RXCFG_ZLFDMA 0x00000010 322 323 /* Bits for AR_MIBC. */ 324 #define AR_MIBC_COW 0x00000001 325 #define AR_MIBC_FMC 0x00000002 326 #define AR_MIBC_CMC 0x00000004 327 #define AR_MIBC_MCS 0x00000008 328 329 /* Bits for AR_TOPS. */ 330 #define AR_TOPS_MASK 0x0000ffff 331 332 /* Bits for AR_RXNPTO. */ 333 #define AR_RXNPTO_MASK 0x000003ff 334 335 /* Bits for AR_TXNPTO. */ 336 #define AR_TXNPTO_MASK 0x000003ff 337 #define AR_TXNPTO_QCU_MASK 0x000ffc00 338 339 /* Bits for AR_RPGTO. */ 340 #define AR_RPGTO_MASK 0x000003ff 341 342 /* Bits for AR_RPCNT. */ 343 #define AR_RPCNT_MASK 0x0000001f 344 345 /* Bits for AR_MACMISC. */ 346 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 347 #define AR_MACMISC_DMA_OBS_M 0x000001e0 348 #define AR_MACMISC_DMA_OBS_S 5 349 #define AR_MACMISC_MISC_OBS_M 0x00000e00 350 #define AR_MACMISC_MISC_OBS_S 9 351 #define AR_MACMISC_MISC_OBS_BUS_LSB_M 0x00007000 352 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 353 #define AR_MACMISC_MISC_OBS_BUS_MSB_M 0x00038000 354 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 355 356 /* Bits for AR_GTXTO. */ 357 #define AR_GTXTO_TIMEOUT_COUNTER_M 0x0000ffff 358 #define AR_GTXTO_TIMEOUT_COUNTER_S 0 359 #define AR_GTXTO_TIMEOUT_LIMIT_M 0xffff0000 360 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 361 362 /* Bits for AR_GTTM. */ 363 #define AR_GTTM_USEC 0x00000001 364 #define AR_GTTM_IGNORE_IDLE 0x00000002 365 #define AR_GTTM_RESET_IDLE 0x00000004 366 #define AR_GTTM_CST_USEC 0x00000008 367 368 /* Bits for AR_CST. */ 369 #define AR_CST_TIMEOUT_COUNTER_M 0x0000ffff 370 #define AR_CST_TIMEOUT_COUNTER_S 0 371 #define AR_CST_TIMEOUT_LIMIT_M 0xffff0000 372 #define AR_CST_TIMEOUT_LIMIT_S 16 373 374 /* Bits for AR_ISR. */ 375 #define AR_ISR_RXOK 0x00000001 376 #define AR_ISR_HP_RXOK 0x00000001 377 #define AR_ISR_RXDESC 0x00000002 378 #define AR_ISR_LP_RXOK 0x00000002 379 #define AR_ISR_RXERR 0x00000004 380 #define AR_ISR_RXNOPKT 0x00000008 381 #define AR_ISR_RXEOL 0x00000010 382 #define AR_ISR_RXORN 0x00000020 383 #define AR_ISR_TXOK 0x00000040 384 #define AR_ISR_TXDESC 0x00000080 385 #define AR_ISR_TXERR 0x00000100 386 #define AR_ISR_TXNOPKT 0x00000200 387 #define AR_ISR_TXEOL 0x00000400 388 #define AR_ISR_TXURN 0x00000800 389 #define AR_ISR_MIB 0x00001000 390 #define AR_ISR_SWI 0x00002000 391 #define AR_ISR_RXPHY 0x00004000 392 #define AR_ISR_RXKCM 0x00008000 393 #define AR_ISR_SWBA 0x00010000 394 #define AR_ISR_BRSSI 0x00020000 395 #define AR_ISR_BMISS 0x00040000 396 #define AR_ISR_TXMINTR 0x00080000 397 #define AR_ISR_BNR 0x00100000 398 #define AR_ISR_RXCHIRP 0x00200000 399 #define AR_ISR_BCNMISC 0x00800000 400 #define AR_ISR_TIM 0x00800000 401 #define AR_ISR_RXMINTR 0x01000000 402 #define AR_ISR_QCBROVF 0x02000000 403 #define AR_ISR_QCBRURN 0x04000000 404 #define AR_ISR_QTRIG 0x08000000 405 #define AR_ISR_GENTMR 0x10000000 406 #define AR_ISR_TXINTM 0x40000000 407 #define AR_ISR_RXINTM 0x80000000 408 409 /* Bits for AR_ISR_S0. */ 410 #define AR_ISR_S0_QCU_TXOK_M 0x000003ff 411 #define AR_ISR_S0_QCU_TXOK_S 0 412 #define AR_ISR_S0_QCU_TXDESC_M 0x03ff0000 413 #define AR_ISR_S0_QCU_TXDESC_S 16 414 415 /* Bits for AR_ISR_S1. */ 416 #define AR_ISR_S1_QCU_TXERR_M 0x000003ff 417 #define AR_ISR_S1_QCU_TXERR_S 0 418 #define AR_ISR_S1_QCU_TXEOL_M 0x03ff0000 419 #define AR_ISR_S1_QCU_TXEOL_S 16 420 421 /* Bits for AR_ISR_S2. */ 422 #define AR_ISR_S2_QCU_TXURN_M 0x000003ff 423 #define AR_ISR_S2_QCU_TXURN_S 0 424 #define AR_ISR_S2_BB_WATCHDOG 0x00010000 425 #define AR_ISR_S2_CST 0x00400000 426 #define AR_ISR_S2_GTT 0x00800000 427 #define AR_ISR_S2_TIM 0x01000000 428 #define AR_ISR_S2_CABEND 0x02000000 429 #define AR_ISR_S2_DTIMSYNC 0x04000000 430 #define AR_ISR_S2_BCNTO 0x08000000 431 #define AR_ISR_S2_CABTO 0x10000000 432 #define AR_ISR_S2_DTIM 0x20000000 433 #define AR_ISR_S2_TSFOOR 0x40000000 434 #define AR_ISR_S2_TBTT_TIME 0x80000000 435 436 /* Bits for AR_ISR_S3. */ 437 #define AR_ISR_S3_QCU_QCBROVF_M 0x000003ff 438 #define AR_ISR_S3_QCU_QCBROVF_S 0 439 #define AR_ISR_S3_QCU_QCBRURN_M 0x03ff0000 440 #define AR_ISR_S3_QCU_QCBRURN_S 0 441 442 /* Bits for AR_ISR_S4. */ 443 #define AR_ISR_S4_QCU_QTRIG_M 0x000003ff 444 #define AR_ISR_S4_QCU_QTRIG_S 0 445 446 /* Bits for AR_ISR_S5. */ 447 #define AR_ISR_S5_TIMER_TRIG_M 0x000000ff 448 #define AR_ISR_S5_TIMER_TRIG_S 0 449 #define AR_ISR_S5_TIMER_THRESH_M 0x0007fe00 450 #define AR_ISR_S5_TIMER_THRESH_S 9 451 #define AR_ISR_S5_TIM_TIMER 0x00000010 452 #define AR_ISR_S5_DTIM_TIMER 0x00000020 453 #define AR_ISR_S5_GENTIMER_TRIG_M 0x0000ff80 454 #define AR_ISR_S5_GENTIMER_TRIG_S 0 455 #define AR_ISR_S5_GENTIMER_THRESH_M 0xff800000 456 #define AR_ISR_S5_GENTIMER_THRESH_S 16 457 458 /* Bits for AR_IMR. */ 459 #define AR_IMR_RXOK 0x00000001 460 #define AR_IMR_HP_RXOK 0x00000001 461 #define AR_IMR_RXDESC 0x00000002 462 #define AR_IMR_LP_RXOK 0x00000002 463 #define AR_IMR_RXERR 0x00000004 464 #define AR_IMR_RXNOPKT 0x00000008 465 #define AR_IMR_RXEOL 0x00000010 466 #define AR_IMR_RXORN 0x00000020 467 #define AR_IMR_TXOK 0x00000040 468 #define AR_IMR_TXDESC 0x00000080 469 #define AR_IMR_TXERR 0x00000100 470 #define AR_IMR_TXNOPKT 0x00000200 471 #define AR_IMR_TXEOL 0x00000400 472 #define AR_IMR_TXURN 0x00000800 473 #define AR_IMR_MIB 0x00001000 474 #define AR_IMR_SWI 0x00002000 475 #define AR_IMR_RXPHY 0x00004000 476 #define AR_IMR_RXKCM 0x00008000 477 #define AR_IMR_SWBA 0x00010000 478 #define AR_IMR_BRSSI 0x00020000 479 #define AR_IMR_BMISS 0x00040000 480 #define AR_IMR_TXMINTR 0x00080000 481 #define AR_IMR_BNR 0x00100000 482 #define AR_IMR_RXCHIRP 0x00200000 483 #define AR_IMR_BCNMISC 0x00800000 484 #define AR_IMR_TIM 0x00800000 485 #define AR_IMR_RXMINTR 0x01000000 486 #define AR_IMR_QCBROVF 0x02000000 487 #define AR_IMR_QCBRURN 0x04000000 488 #define AR_IMR_QTRIG 0x08000000 489 #define AR_IMR_GENTMR 0x10000000 490 #define AR_IMR_TXINTM 0x40000000 491 #define AR_IMR_RXINTM 0x80000000 492 493 #define AR_IMR_DEFAULT \ 494 (AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | \ 495 AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM | \ 496 AR_IMR_RXMINTR | AR_IMR_TXOK) 497 #define AR_IMR_HOSTAP (AR_IMR_DEFAULT | AR_IMR_MIB) 498 499 /* Bits for AR_IMR_S0. */ 500 #define AR_IMR_S0_QCU_TXOK(qid) (1 << (qid)) 501 #define AR_IMR_S0_QCU_TXDESC(qid) (1 << (16 + (qid))) 502 503 /* Bits for AR_IMR_S1. */ 504 #define AR_IMR_S1_QCU_TXERR(qid) (1 << (qid)) 505 #define AR_IMR_S1_QCU_TXEOL(qid) (1 << (16 + (qid))) 506 507 /* Bits for AR_IMR_S2. */ 508 #define AR_IMR_S2_QCU_TXURN(qid) (1 << (qid)) 509 #define AR_IMR_S2_CST 0x00400000 510 #define AR_IMR_S2_GTT 0x00800000 511 #define AR_IMR_S2_TIM 0x01000000 512 #define AR_IMR_S2_CABEND 0x02000000 513 #define AR_IMR_S2_DTIMSYNC 0x04000000 514 #define AR_IMR_S2_BCNTO 0x08000000 515 #define AR_IMR_S2_CABTO 0x10000000 516 #define AR_IMR_S2_DTIM 0x20000000 517 #define AR_IMR_S2_TSFOOR 0x40000000 518 519 /* Bits for AR_IMR_S3. */ 520 #define AR_IMR_S3_QCU_QCBROVF(qid) (1 << (qid)) 521 #define AR_IMR_S3_QCU_QCBRURN(qid) (1 << (16 + (qid))) 522 523 /* Bits for AR_IMR_S4. */ 524 #define AR_IMR_S4_QCU_QTRIG(qid) (1 << (qid)) 525 526 /* Bits for AR_IMR_S5. */ 527 #define AR_IMR_S5_TIM_TIMER 0x00000010 528 #define AR_IMR_S5_DTIM_TIMER 0x00000020 529 #define AR_IMR_S5_TIMER_TRIG_M 0x000000ff 530 #define AR_IMR_S5_TIMER_TRIG_S 0 531 #define AR_IMR_S5_TIMER_THRESH_M 0x0000ff00 532 #define AR_IMR_S5_TIMER_THRESH_S 0 533 534 #define AR_NUM_QCU 10 535 #define AR_QCU(x) (1 << (x)) 536 537 /* Bits for AR_Q_TXE. */ 538 #define AR_Q_TXE_M 0x000003ff 539 #define AR_Q_TXE_S 0 540 541 /* Bits for AR_Q_TXD. */ 542 #define AR_Q_TXD_M 0x000003ff 543 #define AR_Q_TXD_S 0 544 545 /* Bits for AR_QCBRCFG_*. */ 546 #define AR_Q_CBRCFG_INTERVAL_M 0x00ffffff 547 #define AR_Q_CBRCFG_INTERVAL_S 0 548 #define AR_Q_CBRCFG_OVF_THRESH_M 0xff000000 549 #define AR_Q_CBRCFG_OVF_THRESH_S 24 550 551 /* Bits for AR_QRDYTIMECFG_*. */ 552 #define AR_Q_RDYTIMECFG_DURATION_M 0x00ffffff 553 #define AR_Q_RDYTIMECFG_DURATION_S 0 554 #define AR_Q_RDYTIMECFG_EN 0x01000000 555 556 /* Bits for AR_QMISC_*. */ 557 #define AR_Q_MISC_FSP_M 0x0000000f 558 #define AR_Q_MISC_FSP_S 0 559 #define AR_Q_MISC_FSP_ASAP 0 560 #define AR_Q_MISC_FSP_CBR 1 561 #define AR_Q_MISC_FSP_DBA_GATED 2 562 #define AR_Q_MISC_FSP_TIM_GATED 3 563 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 564 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 565 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 566 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 567 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 568 #define AR_Q_MISC_BEACON_USE 0x00000080 569 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 570 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 571 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 572 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 573 574 /* Bits for AR_QSTS_*. */ 575 #define AR_Q_STS_PEND_FR_CNT_M 0x00000003 576 #define AR_Q_STS_PEND_FR_CNT_S 0 577 #define AR_Q_STS_CBR_EXP_CNT_M 0x0000ff00 578 #define AR_Q_STS_CBR_EXP_CNT_S 8 579 580 /* Bits for AR_Q_DESC_CRCCHK. */ 581 #define AR_Q_DESC_CRCCHK_EN 0x00000001 582 583 #define AR_NUM_DCU 10 584 #define AR_DCU(x) (1 << (x)) 585 586 /* Bits for AR_D_QCUMASK_*. */ 587 #define AR_D_QCUMASK_M 0x000003ff 588 #define AR_D_QCUMASK_S 0 589 590 /* Bits for AR_D_GBL_IFS_SIFS. */ 591 #define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003ab 592 593 /* Bits for AR_D_TXBLK_CMD. */ 594 #define AR_D_TXBLK_WRITE_BITMASK_M 0x0000ffff 595 #define AR_D_TXBLK_WRITE_BITMASK_S 0 596 #define AR_D_TXBLK_WRITE_SLICE_M 0x000f0000 597 #define AR_D_TXBLK_WRITE_SLICE_S 16 598 #define AR_D_TXBLK_WRITE_DCU_M 0x00f00000 599 #define AR_D_TXBLK_WRITE_DCU_S 20 600 #define AR_D_TXBLK_WRITE_COMMAND_M 0x0f000000 601 #define AR_D_TXBLK_WRITE_COMMAND_S 24 602 603 /* Bits for AR_DLCL_IFS. */ 604 #define AR_D_LCL_IFS_CWMIN_M 0x000003ff 605 #define AR_D_LCL_IFS_CWMIN_S 0 606 #define AR_D_LCL_IFS_CWMAX_M 0x000ffc00 607 #define AR_D_LCL_IFS_CWMAX_S 10 608 #define AR_D_LCL_IFS_AIFS_M 0x0ff00000 609 #define AR_D_LCL_IFS_AIFS_S 20 610 611 /* Bits for AR_D_GBL_IFS_SLOT. */ 612 #define AR_D_GBL_IFS_SLOT_M 0x0000ffff 613 #define AR_D_GBL_IFS_SLOT_S 0 614 #define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 615 616 /* Bits for AR_DRETRY_LIMIT_*. */ 617 #define AR_D_RETRY_LIMIT_FR_SH_M 0x0000000f 618 #define AR_D_RETRY_LIMIT_FR_SH_S 0 619 #define AR_D_RETRY_LIMIT_STA_SH_M 0x00003f00 620 #define AR_D_RETRY_LIMIT_STA_SH_S 8 621 #define AR_D_RETRY_LIMIT_STA_LG_M 0x000fc000 622 #define AR_D_RETRY_LIMIT_STA_LG_S 14 623 624 /* Bits for AR_D_GBL_IFS_EIFS. */ 625 #define AR_D_GBL_IFS_EIFS_M 0x0000ffff 626 #define AR_D_GBL_IFS_EIFS_S 0 627 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000a5eb 628 629 /* Bits for AR_DCHNTIME_*. */ 630 #define AR_D_CHNTIME_DUR_M 0x000fffff 631 #define AR_D_CHNTIME_DUR_S 0 632 #define AR_D_CHNTIME_EN 0x00100000 633 634 /* Bits for AR_D_GBL_IFS_MISC. */ 635 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 636 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 637 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000ffc00 638 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 639 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 640 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 641 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 642 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 643 644 /* Bits for AR_DMISC_*. */ 645 #define AR_D_MISC_BKOFF_THRESH_M 0x0000003f 646 #define AR_D_MISC_BKOFF_THRESH_S 0 647 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 648 #define AR_D_MISC_CW_RESET_EN 0x00000080 649 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 650 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 651 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 652 #define AR_D_MISC_VIR_COL_HANDLING_M 0x0000c000 653 #define AR_D_MISC_VIR_COL_HANDLING_S 14 654 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 655 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 656 #define AR_D_MISC_BEACON_USE 0x00010000 657 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000 658 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 659 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 660 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 661 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 662 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 663 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 664 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 665 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 666 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 667 668 /* Bits for AR_D_FPCTL. */ 669 #define AR_D_FPCTL_DCU_M 0x0000000f 670 #define AR_D_FPCTL_DCU_S 0 671 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 672 #define AR_D_FPCTL_BURST_PREFETCH_M 0x00007fe0 673 #define AR_D_FPCTL_BURST_PREFETCH_S 5 674 675 /* Bits for AR_D_TXPSE. */ 676 #define AR_D_TXPSE_CTRL_M 0x000003ff 677 #define AR_D_TXPSE_CTRL_S 0 678 #define AR_D_TXPSE_STATUS 0x00010000 679 680 /* Bits for AR_D_TXSLOTMASK. */ 681 #define AR_D_TXSLOTMASK_NUM 0x0000000f 682 683 /* Bits for AR_MAC_SLEEP. */ 684 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 685 686 /* Bits for AR_CFG_LED. */ 687 #define AR_CFG_SCLK_RATE_IND_M 0x00000003 688 #define AR_CFG_SCLK_RATE_IND_S 0 689 #define AR_CFG_SCLK_32MHZ 0 690 #define AR_CFG_SCLK_4MHZ 1 691 #define AR_CFG_SCLK_1MHZ 2 692 #define AR_CFG_SCLK_32KHZ 3 693 #define AR_CFG_LED_BLINK_SLOW 0x00000008 694 #define AR_CFG_LED_BLINK_THRESH_SEL_M 0x00000070 695 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 696 #define AR_CFG_LED_MODE_SEL_M 0x00000380 697 #define AR_CFG_LED_MODE_SEL_S 7 698 #define AR_CFG_LED_POWER_M 0x00000280 699 #define AR_CFG_LED_POWER_S 7 700 #define AR_CFG_LED_NETWORK_M 0x00000300 701 #define AR_CFG_LED_NETWORK_S 7 702 #define AR_CFG_LED_MODE_PROP 0 703 #define AR_CFG_LED_MODE_RPROP 1 704 #define AR_CFG_LED_MODE_SPLIT 2 705 #define AR_CFG_LED_MODE_RAND 3 706 #define AR_CFG_LED_MODE_POWER_OFF 4 707 #define AR_CFG_LED_MODE_POWER_ON 5 708 #define AR_CFG_LED_MODE_NETWORK_OFF 4 709 #define AR_CFG_LED_MODE_NETWORK_ON 6 710 #define AR_CFG_LED_ASSOC_CTL_M 0x00000c00 711 #define AR_CFG_LED_ASSOC_CTL_S 10 712 #define AR_CFG_LED_ASSOC_NONE 0 713 #define AR_CFG_LED_ASSOC_ACTIVE 1 714 #define AR_CFG_LED_ASSOC_PENDING 2 715 716 /* Bit for AR_RC. */ 717 #define AR_RC_AHB 0x00000001 718 #define AR_RC_APB 0x00000002 719 #define AR_RC_HOSTIF 0x00000100 720 721 /* Bits for AR_WA. */ 722 #define AR5416_WA_DEFAULT 0x0000073f 723 #define AR9280_WA_DEFAULT 0x0040073b 724 #define AR9285_WA_DEFAULT 0x004a050b 725 #define AR_WA_UNTIE_RESET_EN 0x00008000 726 #define AR_WA_RESET_EN 0x00040000 727 #define AR_WA_ANALOG_SHIFT 0x00100000 728 #define AR_WA_POR_SHORT 0x00200000 729 730 /* Bits for AR_PM_STATE. */ 731 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 732 733 /* Bits for AR_PCIE_PM_CTRL. */ 734 #define AR_PCIE_PM_CTRL_ENA 0x00080000 735 736 /* Bits for AR_HOST_TIMEOUT. */ 737 #define AR_HOST_TIMEOUT_APB_CNTR_M 0x0000ffff 738 #define AR_HOST_TIMEOUT_APB_CNTR_S 0 739 #define AR_HOST_TIMEOUT_LCL_CNTR_M 0xffff0000 740 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 741 742 /* Bits for AR_EEPROM. */ 743 #define AR_EEPROM_ABSENT 0x00000100 744 #define AR_EEPROM_CORRUPT 0x00000200 745 #define AR_EEPROM_PROT_MASK_M 0x03fffc00 746 #define AR_EEPROM_PROT_MASK_S 10 747 748 /* Bits for AR_SREV. */ 749 #define AR_SREV_ID_M 0x000000ff 750 #define AR_SREV_ID_S 0 751 #define AR_SREV_REVISION_M 0x00000007 752 #define AR_SREV_REVISION_S 0 753 #define AR_SREV_VERSION_M 0x000000f0 754 #define AR_SREV_VERSION_S 4 755 #define AR_SREV_VERSION2_M 0xfffc0000 756 #define AR_SREV_VERSION2_S 12 /* XXX Hack. */ 757 #define AR_SREV_TYPE2_M 0x0003f000 758 #define AR_SREV_TYPE2_S 12 759 #define AR_SREV_TYPE2_CHAIN 0x00001000 760 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 761 #define AR_SREV_REVISION2_M 0x00000f00 762 #define AR_SREV_REVISION2_S 8 763 #define AR_SREV_VERSION_5416_PCI 0x00d 764 #define AR_SREV_VERSION_5416_PCIE 0x00c 765 #define AR_SREV_REVISION_5416_10 0 766 #define AR_SREV_REVISION_5416_20 1 767 #define AR_SREV_REVISION_5416_22 2 768 #define AR_SREV_VERSION_9100 0x014 769 #define AR_SREV_VERSION_9160 0x040 770 #define AR_SREV_REVISION_9160_10 0 771 #define AR_SREV_REVISION_9160_11 1 772 #define AR_SREV_VERSION_9280 0x080 773 #define AR_SREV_REVISION_9280_10 0 774 #define AR_SREV_REVISION_9280_20 1 775 #define AR_SREV_REVISION_9280_21 2 776 #define AR_SREV_VERSION_9285 0x0c0 777 #define AR_SREV_REVISION_9285_10 0 778 #define AR_SREV_REVISION_9285_11 1 779 #define AR_SREV_REVISION_9285_12 2 780 #define AR_SREV_VERSION_9271 0x140 781 #define AR_SREV_REVISION_9271_10 0 782 #define AR_SREV_REVISION_9271_11 1 783 #define AR_SREV_VERSION_9287 0x180 784 #define AR_SREV_REVISION_9287_10 0 785 #define AR_SREV_REVISION_9287_11 1 786 #define AR_SREV_REVISION_9287_12 2 787 #define AR_SREV_REVISION_9287_13 3 788 #define AR_SREV_VERSION_9380 0x1c0 789 #define AR_SREV_REVISION_9380_10 0 790 #define AR_SREV_REVISION_9380_20 2 791 #define AR_SREV_VERSION_9485 0x240 792 #define AR_SREV_REVISION_9485_10 0 793 794 /* Bits for AR_AHB_MODE. */ 795 #define AR_AHB_EXACT_WR_EN 0x00000000 796 #define AR_AHB_BUF_WR_EN 0x00000001 797 #define AR_AHB_EXACT_RD_EN 0x00000000 798 #define AR_AHB_CACHELINE_RD_EN 0x00000002 799 #define AR_AHB_PREFETCH_RD_EN 0x00000004 800 #define AR_AHB_PAGE_SIZE_1K 0x00000000 801 #define AR_AHB_PAGE_SIZE_2K 0x00000008 802 #define AR_AHB_PAGE_SIZE_4K 0x00000010 803 #define AR_AHB_CUSTOM_BURST_M 0x000000c0 804 #define AR_AHB_CUSTOM_BURST_S 6 805 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 806 807 /* Bits for AR_INTR_SYNC_CAUSE. */ 808 #define AR_INTR_SYNC_RTC_IRQ 0x00000001 809 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 810 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 811 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 812 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 813 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 814 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 815 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 816 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 817 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 818 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 819 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 820 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 821 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 822 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 823 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 824 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 825 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 826 #define AR_INTR_SYNC_ALL 0x0003ffff 827 #define AR_INTR_SYNC_GPIO_PIN(i) (1 << (18 + (i))) 828 829 #define AR_INTR_SYNC_DEFAULT \ 830 (AR_INTR_SYNC_HOST1_FATAL | \ 831 AR_INTR_SYNC_HOST1_PERR | \ 832 AR_INTR_SYNC_RADM_CPL_EP | \ 833 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 834 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | \ 835 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 836 AR_INTR_SYNC_RADM_CPL_TIMEOUT | \ 837 AR_INTR_SYNC_LOCAL_TIMEOUT | \ 838 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 839 840 /* Bits for AR_INTR_ASYNC_CAUSE. */ 841 #define AR_INTR_RTC_IRQ 0x00000001 842 #define AR_INTR_MAC_IRQ 0x00000002 843 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 844 #define AR_INTR_MAC_AWAKE 0x00020000 845 #define AR_INTR_MAC_ASLEEP 0x00040000 846 #define AR_INTR_GPIO_PIN(i) (1 << (18 + (i))) 847 #define AR_INTR_SPURIOUS 0xffffffff 848 849 /* Bits for AR_GPIO_OE_OUT. */ 850 #define AR_GPIO_OE_OUT_DRV_M 0x00000003 851 #define AR_GPIO_OE_OUT_DRV_S 0 852 #define AR_GPIO_OE_OUT_DRV_NO 0 853 #define AR_GPIO_OE_OUT_DRV_LOW 1 854 #define AR_GPIO_OE_OUT_DRV_HI 2 855 #define AR_GPIO_OE_OUT_DRV_ALL 3 856 857 /* Bits for AR_GPIO_INTR_POL. */ 858 #define AR_GPIO_INTR_POL_PIN(i) (1 << (i)) 859 860 /* Bits for AR_GPIO_INPUT_EN_VAL. */ 861 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 862 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 863 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 864 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 865 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 866 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 867 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 868 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 869 #define AR_GPIO_JTAG_DISABLE 0x00020000 870 871 /* Bits for AR_GPIO_INPUT_MUX1. */ 872 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M 0x00000f00 873 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 874 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M 0x000f0000 875 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 876 877 /* Bits for AR_GPIO_INPUT_MUX2. */ 878 #define AR_GPIO_INPUT_MUX2_CLK25_M 0x0000000f 879 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 880 #define AR_GPIO_INPUT_MUX2_RFSILENT_M 0x000000f0 881 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 882 #define AR_GPIO_INPUT_MUX2_RTC_RESET_M 0x00000f00 883 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 884 885 /* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */ 886 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 887 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 888 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 889 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 890 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 891 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 892 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 893 894 /* Bits for AR_EEPROM_STATUS_DATA. */ 895 #define AR_EEPROM_STATUS_DATA_VAL_M 0x0000ffff 896 #define AR_EEPROM_STATUS_DATA_VAL_S 0 897 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 898 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 899 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 900 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 901 902 /* Bits for AR_PCIE_MSI. */ 903 #define AR_PCIE_MSI_ENABLE 0x00000001 904 905 /* Bits for AR_RTC_RC. */ 906 #define AR_RTC_RC_MAC_WARM 0x00000001 907 #define AR_RTC_RC_MAC_COLD 0x00000002 908 #define AR_RTC_RC_COLD_RESET 0x00000004 909 #define AR_RTC_RC_WARM_RESET 0x00000008 910 911 /* Bits for AR_RTC_REG_CONTROL1. */ 912 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 913 914 /* Bits for AR_RTC_PLL_CONTROL. */ 915 #define AR_RTC_PLL_DIV_M 0x0000001f 916 #define AR_RTC_PLL_DIV_S 0 917 #define AR_RTC_PLL_DIV2 0x00000020 918 #define AR_RTC_PLL_REFDIV_5 0x000000c0 919 #define AR_RTC_PLL_CLKSEL_M 0x00000300 920 #define AR_RTC_PLL_CLKSEL_S 8 921 #define AR_RTC_9160_PLL_DIV_M 0x000003ff 922 #define AR_RTC_9160_PLL_DIV_S 0 923 #define AR_RTC_9160_PLL_REFDIV_M 0x00003c00 924 #define AR_RTC_9160_PLL_REFDIV_S 10 925 #define AR_RTC_9160_PLL_CLKSEL_M 0x0000c000 926 #define AR_RTC_9160_PLL_CLKSEL_S 14 927 928 /* Bits for AR_RTC_RESET. */ 929 #define AR_RTC_RESET_EN 0x00000001 930 931 /* Bits for AR_RTC_STATUS. */ 932 #define AR_RTC_STATUS_M 0x0000000f 933 #define AR_RTC_STATUS_S 0 934 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 935 #define AR_RTC_STATUS_ON 0x00000002 936 #define AR_RTC_STATUS_SLEEP 0x00000004 937 #define AR_RTC_STATUS_WAKEUP 0x00000008 938 939 /* Bits for AR_RTC_SLEEP_CLK. */ 940 #define AR_RTC_FORCE_DERIVED_CLK 0x00000002 941 #define AR_RTC_FORCE_SWREG_PRD 0x00000004 942 943 /* Bits for AR_RTC_FORCE_WAKE. */ 944 #define AR_RTC_FORCE_WAKE_EN 0x00000001 945 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 946 947 /* Bits for AR_STA_ID1. */ 948 #define AR_STA_ID1_SADH_M 0x0000ffff 949 #define AR_STA_ID1_SADH_S 0 950 #define AR_STA_ID1_STA_AP 0x00010000 951 #define AR_STA_ID1_ADHOC 0x00020000 952 #define AR_STA_ID1_PWR_SAV 0x00040000 953 #define AR_STA_ID1_KSRCHDIS 0x00080000 954 #define AR_STA_ID1_PCF 0x00100000 955 #define AR_STA_ID1_USE_DEFANT 0x00200000 956 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 957 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 958 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 959 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 960 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 961 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 962 #define AR_STA_ID1_KSRCH_MODE 0x10000000 963 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 964 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 965 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 966 967 /* Bits for AR_BSS_ID1. */ 968 #define AR_BSS_ID1_U16_M 0x0000ffff 969 #define AR_BSS_ID1_U16_S 0 970 #define AR_BSS_ID1_AID_M 0x07ff0000 971 #define AR_BSS_ID1_AID_S 16 972 973 /* Bits for AR_TIME_OUT. */ 974 #define AR_TIME_OUT_ACK_M 0x00003fff 975 #define AR_TIME_OUT_ACK_S 0 976 #define AR_TIME_OUT_CTS_M 0x3fff0000 977 #define AR_TIME_OUT_CTS_S 16 978 #define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001d56 979 980 /* Bits for AR_RSSI_THR. */ 981 #define AR_RSSI_THR_M 0x000000ff 982 #define AR_RSSI_THR_S 0 983 #define AR_RSSI_THR_BM_THR_M 0x0000ff00 984 #define AR_RSSI_THR_BM_THR_S 8 985 #define AR_RSSI_BCN_WEIGHT_M 0x1f000000 986 #define AR_RSSI_BCN_WEIGHT_S 24 987 #define AR_RSSI_BCN_RSSI_RST 0x20000000 988 989 /* Bits for AR_USEC. */ 990 #define AR_USEC_USEC_M 0x0000007f 991 #define AR_USEC_USEC_S 0 992 #define AR_USEC_TX_LAT_M 0x007fc000 993 #define AR_USEC_TX_LAT_S 14 994 #define AR_USEC_RX_LAT_M 0x1f800000 995 #define AR_USEC_RX_LAT_S 23 996 #define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 997 998 /* Bits for AR_RESET_TSF. */ 999 #define AR_RESET_TSF_ONCE 0x01000000 1000 1001 /* Bits for AR_RX_FILTER. */ 1002 #define AR_RX_FILTER_UCAST 0x00000001 1003 #define AR_RX_FILTER_MCAST 0x00000002 1004 #define AR_RX_FILTER_BCAST 0x00000004 1005 #define AR_RX_FILTER_CONTROL 0x00000008 1006 #define AR_RX_FILTER_BEACON 0x00000010 1007 #define AR_RX_FILTER_PROM 0x00000020 1008 #define AR_RX_FILTER_PROBEREQ 0x00000080 1009 #define AR_RX_FILTER_MYBEACON 0x00000200 1010 #define AR_RX_FILTER_COMPR_BAR 0x00000400 1011 #define AR_RX_FILTER_PSPOLL 0x00004000 1012 1013 /* Bits for AR_DIAG_SW. */ 1014 #define AR_DIAG_CACHE_ACK 0x00000001 1015 #define AR_DIAG_ACK_DIS 0x00000002 1016 #define AR_DIAG_CTS_DIS 0x00000004 1017 #define AR_DIAG_ENCRYPT_DIS 0x00000008 1018 #define AR_DIAG_DECRYPT_DIS 0x00000010 1019 #define AR_DIAG_RX_DIS 0x00000020 1020 #define AR_DIAG_LOOP_BACK 0x00000040 1021 #define AR_DIAG_CORR_FCS 0x00000080 1022 #define AR_DIAG_CHAN_INFO 0x00000100 1023 #define AR_DIAG_SCRAM_SEED_M 0x0001fe00 1024 #define AR_DIAG_SCRAM_SEED_S 8 /* XXX should be 9? */ 1025 #define AR_DIAG_FRAME_NV0 0x00020000 1026 #define AR_DIAG_OBS_PT_SEL1_M 0x000c0000 1027 #define AR_DIAG_OBS_PT_SEL1_S 18 1028 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1029 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1030 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1031 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1032 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1033 #define AR_DIAG_RX_ABORT 0x02000000 1034 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1035 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1036 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1037 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1038 1039 /* Bits for AR_AES_MUTE_MASK0. */ 1040 #define AR_AES_MUTE_MASK0_FC_M 0x0000ffff 1041 #define AR_AES_MUTE_MASK0_FC_S 0 1042 #define AR_AES_MUTE_MASK0_QOS_M 0xffff0000 1043 #define AR_AES_MUTE_MASK0_QOS_S 16 1044 1045 /* Bits for AR_AES_MUTE_MASK1. */ 1046 #define AR_AES_MUTE_MASK1_SEQ_M 0x0000ffff 1047 #define AR_AES_MUTE_MASK1_SEQ_S 0 1048 #define AR_AES_MUTE_MASK1_FC_MGMT_M 0xffff0000 1049 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1050 #define AR_AES_MUTE_MASK1_FC0_MGMT_M 0x00ff0000 1051 #define AR_AES_MUTE_MASK1_FC0_MGMT_S 16 1052 #define AR_AES_MUTE_MASK1_FC1_MGMT_M 0xff000000 1053 #define AR_AES_MUTE_MASK1_FC1_MGMT_S 24 1054 1055 /* Bits for AR_GATED_CLKS. */ 1056 #define AR_GATED_CLKS_TX 0x00000002 1057 #define AR_GATED_CLKS_RX 0x00000004 1058 #define AR_GATED_CLKS_REG 0x00000008 1059 1060 /* Bits for AR_OBS_BUS_CTRL. */ 1061 #define AR_OBS_BUS_SEL_1 0x00040000 1062 #define AR_OBS_BUS_SEL_2 0x00080000 1063 #define AR_OBS_BUS_SEL_3 0x000c0000 1064 #define AR_OBS_BUS_SEL_4 0x08040000 1065 #define AR_OBS_BUS_SEL_5 0x08080000 1066 1067 /* Bits for AR_OBS_BUS_1. */ 1068 #define AR_OBS_BUS_1_PCU 0x00000001 1069 #define AR_OBS_BUS_1_RX_END 0x00000002 1070 #define AR_OBS_BUS_1_RX_WEP 0x00000004 1071 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1072 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1073 #define AR_OBS_BUS_1_TX_HCF 0x00000020 1074 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1075 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1076 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1077 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1078 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1079 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1080 #define AR_OBS_BUS_1_WEP_STATE_M 0x0003f000 1081 #define AR_OBS_BUS_1_WEP_STATE_S 12 1082 #define AR_OBS_BUS_1_RX_STATE_M 0x01f00000 1083 #define AR_OBS_BUS_1_RX_STATE_S 20 1084 #define AR_OBS_BUS_1_TX_STATE_M 0x7e000000 1085 #define AR_OBS_BUS_1_TX_STATE_S 25 1086 1087 /* Bits for AR_SLEEP1. */ 1088 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 1089 #define AR_SLEEP1_CAB_TIMEOUT_M 0xffe00000 1090 #define AR_SLEEP1_CAB_TIMEOUT_S 21 1091 /* Default value. */ 1092 #define AR_CAB_TIMEOUT_VAL 10 1093 1094 /* Bits for AR_SLEEP2. */ 1095 #define AR_SLEEP2_BEACON_TIMEOUT_M 0xffe00000 1096 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 1097 1098 /* Bits for AR_TPC. */ 1099 #define AR_TPC_ACK_M 0x0000003f 1100 #define AR_TPC_ACK_S 0 1101 #define AR_TPC_CTS_M 0x00003f00 1102 #define AR_TPC_CTS_S 8 1103 #define AR_TPC_CHIRP_M 0x003f0000 1104 #define AR_TPC_CHIRP_S 16 1105 1106 /* Bits for AR_QUIET1. */ 1107 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1108 #define AR_QUIET1_NEXT_QUIET_S 0 1109 #define AR_QUIET1_QUIET_ENABLE 0x00010000 1110 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1111 1112 /* Bits for AR_QUIET2. */ 1113 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1114 #define AR_QUIET2_QUIET_PERIOD_S 0 1115 #define AR_QUIET2_QUIET_DUR_M 0xffff0000 1116 #define AR_QUIET2_QUIET_DUR_S 16 1117 1118 /* Bits for AR_TSF_PARM. */ 1119 #define AR_TSF_INCREMENT_M 0x000000ff 1120 #define AR_TSF_INCREMENT_S 0 1121 1122 /* Bits for AR_QOS_NO_ACK. */ 1123 #define AR_QOS_NO_ACK_TWO_BIT_M 0x0000000f 1124 #define AR_QOS_NO_ACK_TWO_BIT_S 0 1125 #define AR_QOS_NO_ACK_BIT_OFF_M 0x0000007f 1126 #define AR_QOS_NO_ACK_BIT_OFF_S 4 1127 #define AR_QOS_NO_ACK_BYTE_OFF_M 0x00000180 1128 #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1129 1130 /* Bits for AR_PHY_ERR. */ 1131 #define AR_PHY_ERR_DCHIRP 0x00000008 1132 #define AR_PHY_ERR_RADAR 0x00000020 1133 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 1134 #define AR_PHY_ERR_CCK_TIMING 0x02000000 1135 1136 /* Bits for AR_PCU_MISC. */ 1137 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1138 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1139 #define AR_PCU_TX_ADD_TSF 0x00000008 1140 #define AR_PCU_CCK_SIFS_MODE 0x00000010 1141 #define AR_PCU_RX_ANT_UPDT 0x00000800 1142 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1143 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1144 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1145 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 1146 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1147 #define AR_PCU_TBTT_PROTECT 0x00200000 1148 #define AR_PCU_CLEAR_VMF 0x01000000 1149 #define AR_PCU_CLEAR_BA_VALID 0x04000000 1150 1151 /* Bits for AR_BT_COEX_MODE. */ 1152 #define AR_BT_TIME_EXTEND_M 0x000000ff 1153 #define AR_BT_TIME_EXTEND_S 0 1154 #define AR_BT_TXSTATE_EXTEND 0x00000100 1155 #define AR_BT_TX_FRAME_EXTEND 0x00000200 1156 #define AR_BT_MODE_M 0x00000c00 1157 #define AR_BT_MODE_S 10 1158 #define AR_BT_MODE_LEGACY 0 1159 #define AR_BT_MODE_UNSLOTTED 1 1160 #define AR_BT_MODE_SLOTTED 2 1161 #define AR_BT_MODE_DISABLED 3 1162 #define AR_BT_QUIET 0x00001000 1163 #define AR_BT_QCU_THRESH_M 0x0001e000 1164 #define AR_BT_QCU_THRESH_S 13 1165 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 1166 #define AR_BT_PRIORITY_TIME_M 0x00fc0000 1167 #define AR_BT_PRIORITY_TIME_S 18 1168 #define AR_BT_FIRST_SLOT_TIME_M 0xff000000 1169 #define AR_BT_FIRST_SLOT_TIME_S 24 1170 1171 /* Bits for AR_BT_COEX_WEIGHT. */ 1172 #define AR_BTCOEX_BT_WGHT_M 0x0000ffff 1173 #define AR_BTCOEX_BT_WGHT_S 0 1174 #define AR_STOMP_LOW_BT_WGHT 0xff55 1175 #define AR_BTCOEX_WL_WGHT_M 0xffff0000 1176 #define AR_BTCOEX_WL_WGHT_S 16 1177 #define AR_STOMP_LOW_WL_WGHT 0xaaa8 1178 1179 /* Bits for AR_BT_COEX_MODE2. */ 1180 #define AR_BT_BCN_MISS_THRESH_M 0x000000ff 1181 #define AR_BT_BCN_MISS_THRESH_S 0 1182 #define AR_BT_BCN_MISS_CNT_M 0x0000ff00 1183 #define AR_BT_BCN_MISS_CNT_S 8 1184 #define AR_BT_HOLD_RX_CLEAR 0x00010000 1185 #define AR_BT_DISABLE_BT_ANT 0x00100000 1186 1187 /* Bits for AR_PCU_TXBUF_CTRL. */ 1188 #define AR_PCU_TXBUF_CTRL_SIZE_M 0x000007ff 1189 #define AR_PCU_TXBUF_CTRL_SIZE_S 0 1190 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 1792 1191 #define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE (1792 / 2) 1192 1193 /* Bits for AR_PCU_MISC_MODE2. */ 1194 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1195 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1196 #define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX 0x00000008 1197 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1198 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1199 #define AR_PCU_MISC_MODE2_MGMT_QOS_M 0x0000ff00 1200 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1201 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR 0x00010000 1202 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1203 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1204 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1205 1206 /* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */ 1207 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1208 1209 /* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */ 1210 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1211 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1212 1213 /* Bits for AR_PHY_ERR_[123]. */ 1214 #define AR_PHY_ERR_COUNT_M 0x00ffffff 1215 #define AR_PHY_ERR_COUNT_S 0 1216 1217 /* Bits for AR_TSFOOR_THRESHOLD. */ 1218 #define AR_TSFOOR_THRESHOLD_VAL_M 0x0000ffff 1219 #define AR_TSFOOR_THRESHOLD_VAL_S 0 1220 1221 /* Bit for AR_TXSIFS. */ 1222 #define AR_TXSIFS_TIME_M 0x000000ff 1223 #define AR_TXSIFS_TIME_S 0 1224 #define AR_TXSIFS_TX_LATENCY_M 0x00000f00 1225 #define AR_TXSIFS_TX_LATENCY_S 8 1226 #define AR_TXSIFS_ACK_SHIFT_M 0x00007000 1227 #define AR_TXSIFS_ACK_SHIFT_S 12 1228 1229 /* Bits for AR_TXOP_X. */ 1230 #define AR_TXOP_X_VAL 0x000000ff 1231 1232 /* Bits for AR_TIMER_MODE. */ 1233 #define AR_TBTT_TIMER_EN 0x00000001 1234 #define AR_DBA_TIMER_EN 0x00000002 1235 #define AR_SWBA_TIMER_EN 0x00000004 1236 #define AR_HCF_TIMER_EN 0x00000008 1237 #define AR_TIM_TIMER_EN 0x00000010 1238 #define AR_DTIM_TIMER_EN 0x00000020 1239 #define AR_QUIET_TIMER_EN 0x00000040 1240 #define AR_NDP_TIMER_EN 0x00000080 1241 #define AR_TIMER_OVERFLOW_INDEX_M 0x00000700 1242 #define AR_TIMER_OVERFLOW_INDEX_S 8 1243 #define AR_TIMER_THRESH_M 0xfffff000 1244 #define AR_TIMER_THRESH_S 12 1245 1246 /* Bits for AR_SLP32_MODE. */ 1247 #define AR_SLP32_HALF_CLK_LATENCY_M 0x000fffff 1248 #define AR_SLP32_HALF_CLK_LATENCY_S 0 1249 #define AR_SLP32_ENA 0x00100000 1250 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1251 1252 /* Bits for AR_SLP32_WAKE. */ 1253 #define AR_SLP32_WAKE_XTL_TIME_M 0x0000ffff 1254 #define AR_SLP32_WAKE_XTL_TIME_S 0 1255 1256 /* Bits for AR_SLP_MIB_CTRL. */ 1257 #define AR_SLP_MIB_CLEAR 0x00000001 1258 #define AR_SLP_MIB_PENDING 0x00000002 1259 1260 /* Bits for AR_2040_MODE. */ 1261 #define AR_2040_JOINED_RX_CLEAR 0x00000001 1262 1263 /* Bits for AR_KEYTABLE_TYPE. */ 1264 #define AR_KEYTABLE_TYPE_M 0x00000007 1265 #define AR_KEYTABLE_TYPE_S 0 1266 #define AR_KEYTABLE_TYPE_40 0 1267 #define AR_KEYTABLE_TYPE_104 1 1268 #define AR_KEYTABLE_TYPE_128 3 1269 #define AR_KEYTABLE_TYPE_TKIP 4 1270 #define AR_KEYTABLE_TYPE_AES 5 1271 #define AR_KEYTABLE_TYPE_CCM 6 1272 #define AR_KEYTABLE_TYPE_CLR 7 1273 #define AR_KEYTABLE_ANT 0x00000008 1274 #define AR_KEYTABLE_VALID 0x00008000 1275 1276 /* 1277 * AR9271 specific registers. 1278 */ 1279 #define AR9271_RESET_POWER_DOWN_CONTROL 0x050044 1280 #define AR9271_FIRMWARE 0x501000 1281 #define AR9271_FIRMWARE_TEXT 0x903000 1282 #define AR7010_FIRMWARE_TEXT 0x906000 1283 1284 /* Bits for AR9271_RESET_POWER_DOWN_CONTROL. */ 1285 #define AR9271_RADIO_RF_RST 0x00000020 1286 #define AR9271_GATE_MAC_CTL 0x00004000 1287 1288 1289 #define AR_BASE_PHY_ACTIVE_DELAY 100 1290 1291 #define AR_CLOCK_RATE_CCK 22 1292 #define AR_CLOCK_RATE_5GHZ_OFDM 40 1293 #define AR_CLOCK_RATE_FAST_5GHZ_OFDM 44 1294 #define AR_CLOCK_RATE_2GHZ_OFDM 44 1295 1296 #define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */ 1297 #define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */ 1298 1299 #define AR_SLEEP_SLOP 3 /* TUs */ 1300 1301 #define AR_MIN_BEACON_TIMEOUT_VAL 1 1302 #define AR_FUDGE 2 1303 #define AR_BEACON_DMA_DELAY 2 1304 #define AR_SWBA_DELAY 10 1305 /* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */ 1306 #define AR_TSF_TO_TU(hi, lo) ((hi) << 22 | (lo) >> 10) 1307 1308 #define AR_KEY_CACHE_SIZE 128 1309 #define AR_RSVD_KEYTABLE_ENTRIES 4 1310 1311 #define AR_CAL_SAMPLES 64 /* XXX AR9280? */ 1312 #define AR_MAX_LOG_CAL 2 /* XXX AR9280? */ 1313 1314 /* Maximum number of chains supported by any chipset. */ 1315 #define AR_MAX_CHAINS 3 1316 1317 /* Default number of key cache entries. */ 1318 #define AR_KEYTABLE_SIZE 128 1319 1320 /* GPIO pins. */ 1321 #define AR_GPIO_WLANACTIVE_PIN 5 1322 #define AR_GPIO_BTACTIVE_PIN 6 1323 #define AR_GPIO_BTPRIORITY_PIN 7 1324 1325 #define AR_SREV_5416(sc) \ 1326 ((sc)->mac_ver == AR_SREV_VERSION_5416_PCI || \ 1327 (sc)->mac_ver == AR_SREV_VERSION_5416_PCIE) 1328 #define AR_SREV_5416_20_OR_LATER(sc) \ 1329 ((AR_SREV_5416(sc) && \ 1330 (sc)->mac_rev >= AR_SREV_REVISION_5416_20) || \ 1331 (sc)->mac_ver >= AR_SREV_VERSION_9100) 1332 #define AR_SREV_5416_22_OR_LATER(sc) \ 1333 ((AR_SREV_5416(sc) && \ 1334 (sc)->mac_rev >= AR_SREV_REVISION_5416_22) || \ 1335 (sc)->mac_ver >= AR_SREV_VERSION_9100) 1336 1337 #define AR_SREV_9160(sc) \ 1338 ((sc)->mac_ver == AR_SREV_VERSION_9160) 1339 #define AR_SREV_9160_10_OR_LATER(sc) \ 1340 ((sc)->mac_ver >= AR_SREV_VERSION_9160) 1341 #define AR_SREV_9160_11(sc) \ 1342 (AR_SREV_9160(sc) && \ 1343 (sc)->mac_rev == AR_SREV_REVISION_9160_11) 1344 1345 #define AR_SREV_9280(sc) \ 1346 ((sc)->mac_ver == AR_SREV_VERSION_9280) 1347 #define AR_SREV_9280_10_OR_LATER(sc) \ 1348 ((sc)->mac_ver >= AR_SREV_VERSION_9280) 1349 #define AR_SREV_9280_10(sc) \ 1350 (AR_SREV_9280(sc) && \ 1351 (sc)->mac_rev == AR_SREV_REVISION_9280_10) 1352 #define AR_SREV_9280_20(sc) \ 1353 (AR_SREV_9280(sc) && \ 1354 (sc)->mac_rev >= AR_SREV_REVISION_9280_20) 1355 #define AR_SREV_9280_20_OR_LATER(sc) \ 1356 ((sc)->mac_ver > AR_SREV_VERSION_9280 || \ 1357 (AR_SREV_9280(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9280_20)) 1358 1359 #define AR_SREV_9285(sc) \ 1360 ((sc)->mac_ver == AR_SREV_VERSION_9285) 1361 #define AR_SREV_9285_10_OR_LATER(sc) \ 1362 ((sc)->mac_ver >= AR_SREV_VERSION_9285) 1363 #define AR_SREV_9285_11(sc) \ 1364 (AR_SREV_9285(sc) && \ 1365 (sc)->mac_rev == AR_SREV_REVISION_9285_11) 1366 #define AR_SREV_9285_11_OR_LATER(sc) \ 1367 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 1368 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_11)) 1369 #define AR_SREV_9285_12(sc) \ 1370 (AR_SREV_9285(sc) && \ 1371 ((sc)->mac_rev == AR_SREV_REVISION_9285_12)) 1372 #define AR_SREV_9285_12_OR_LATER(sc) \ 1373 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 1374 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_12)) 1375 1376 #define AR_SREV_9271(sc) \ 1377 ((sc)->mac_ver == AR_SREV_VERSION_9271) 1378 #define AR_SREV_9271_10(sc) \ 1379 (AR_SREV_9271(sc) && \ 1380 (sc)->mac_rev == AR_SREV_REVISION_9271_10) 1381 1382 #define AR_SREV_9287(sc) \ 1383 ((sc)->mac_ver == AR_SREV_VERSION_9287) 1384 #define AR_SREV_9287_10_OR_LATER(sc) \ 1385 ((sc)->mac_ver >= AR_SREV_VERSION_9287) 1386 #define AR_SREV_9287_10(sc) \ 1387 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1388 (sc)->mac_rev == AR_SREV_REVISION_9287_10) 1389 #define AR_SREV_9287_11(sc) \ 1390 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1391 (sc)->mac_rev == AR_SREV_REVISION_9287_11) 1392 #define AR_SREV_9287_11_OR_LATER(sc) \ 1393 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1394 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_11)) 1395 #define AR_SREV_9287_12(sc) \ 1396 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1397 (sc)->mac_rev == AR_SREV_REVISION_9287_12) 1398 #define AR_SREV_9287_12_OR_LATER(sc) \ 1399 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1400 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_12)) 1401 #define AR_SREV_9287_13_OR_LATER(sc) \ 1402 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1403 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_13)) 1404 1405 #define AR_SREV_9380(sc) \ 1406 ((sc)->mac_ver == AR_SREV_VERSION_9380) 1407 #define AR_SREV_9380_10_OR_LATER(sc) \ 1408 ((sc)->mac_ver >= AR_SREV_VERSION_9380) 1409 #define AR_SREV_9380_20(sc) \ 1410 (AR_SREV_9380(sc) && \ 1411 (sc)->mac_rev == AR_SREV_REVISION_9380_20) 1412 #define AR_SREV_9380_20_OR_LATER(sc) \ 1413 ((sc)->mac_ver > AR_SREV_VERSION_9380 || \ 1414 (AR_SREV_9380(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9380_20)) 1415 1416 #define AR_SREV_9485(sc) \ 1417 ((sc)->mac_ver == AR_SREV_VERSION_9485) 1418 1419 #define AR_SINGLE_CHIP(sc) AR_SREV_9280_10_OR_LATER(sc) 1420 1421 #define AR_RADIO_SREV_MAJOR 0xf0 1422 #define AR_RAD5133_SREV_MAJOR 0xc0 1423 #define AR_RAD2133_SREV_MAJOR 0xd0 1424 #define AR_RAD5122_SREV_MAJOR 0xe0 1425 #define AR_RAD2122_SREV_MAJOR 0xf0 1426 1427 #define AR_BCHAN_UNUSED 0xff 1428 #define AR_PD_GAINS_IN_MASK 4 /* NB: Max for all chips. */ 1429 #define AR_MAX_RATE_POWER 63 1430 1431 #define AR_HT40_POWER_INC_FOR_PDADC 2 1432 #define AR_PWR_TABLE_OFFSET_DB (-5) 1433 #define AR9280_TX_GAIN_TABLE_SIZE 22 1434 #define AR9003_TX_GAIN_TABLE_SIZE 32 1435 #define AR9003_PAPRD_MEM_TAB_SIZE 24 1436 1437 #define AR_BASE_FREQ_2GHZ 2300 1438 #define AR_BASE_FREQ_5GHZ 4900 1439 1440 #define AR_SD_NO_CTL 0xe0 1441 #define AR_NO_CTL 0xff 1442 #define AR_CTL_MODE_M 0x07 1443 #define AR_CTL_MODE_S 0 1444 #define AR_CTL_11A 0 1445 #define AR_CTL_11B 1 1446 #define AR_CTL_11G 2 1447 #define AR_CTL_2GHT20 5 1448 #define AR_CTL_5GHT20 6 1449 #define AR_CTL_2GHT40 7 1450 #define AR_CTL_5GHT40 8 1451 1452 /* 1453 * Macros to access registers. 1454 */ 1455 #define AR_READ(sc, reg) \ 1456 (sc)->ops.read((sc), (reg)) 1457 1458 #define AR_WRITE(sc, reg, val) \ 1459 (sc)->ops.write((sc), (reg), (val)) 1460 1461 #define AR_WRITE_BARRIER(sc) \ 1462 (sc)->ops.write_barrier((sc)) 1463 1464 #define AR_SETBITS(sc, reg, mask) \ 1465 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask)) 1466 1467 #define AR_CLRBITS(sc, reg, mask) \ 1468 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask)) 1469 1470 /* 1471 * Macros to access subfields in registers. 1472 */ 1473 /* Mask and Shift (getter). */ 1474 #define MS(val, field) \ 1475 (((val) & field##_M) >> field##_S) 1476 1477 /* Shift and Mask (setter). */ 1478 #define SM(field, val) \ 1479 (((val) << field##_S) & field##_M) 1480 1481 /* Rewrite. */ 1482 #define RW(var, field, val) \ 1483 (((var) & ~field##_M) | SM(field, val)) 1484